vishay siliconix si8473edb document number: 65037 s09-1820-rev. a, 14-sep-09 www.vishay.com 1 p-channel 20-v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ? trenchfet ? power mosfet ? typical esd protection: 3000 v ? gate-source ovp ? compliant to rohs directive 2002/95/ec applications ? load switch ? battery switch ? charger switch ? gate-source over vo ltage protection (see page 3) notes: a. surface mounted on 1" x 1" fr4 board with full copper, t = 5 s. b. surface mounted on 1" x 1" fr4 board with minimum copper, t = 5 s. c. refer to ipc/jedec (j-std-020c), no manual or hand soldering. d. in this document, any reference to case represents t he body of the micro foot device and foot is the bump. e. based on t a = 25 c. product summary v ds (v) r ds(on) ( ) i d (a) a, e - 20 0.041 at v gs = - 4.5 v - 7.1 0.055 at v gs = - 2.5 v - 6.1 micro foot ? 32 41 s dd g b u mp side v ie w backside v ie w device markin g : 8 473e xxx = date/lot tracea b ility code 8 473e xxx orderin g information: si 8 473edb-t1-e1 (lead (p b )-free and halogen-free) p-channel mosfet s d r g absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds - 20 v gate-source voltage v gs 12 continuous drain current (t j = 150 c) t a = 25 c i d - 7.1 a a t a = 70 c - 5.7 a t a = 25 c - 4.5 b t a = 70 c - 3.6 b pulsed drain current i dm - 25 continuous source-drain diode current t a = 25 c i s - 2.3 a t a = 25 c - 0.92 b maximum power dissipation t a = 25 c p d 2.7 a w t a = 70 c 1.8 a t a = 25 c 1.1 b t a = 70 c 0.73 b operating junction and storage temperature range t j , t stg - 55 to 150 c package reflow conditions c vpr 260 ir/convection 260
www.vishay.com 2 document number: 65037 s09-1820-rev. a, 14-sep-09 vishay siliconix si8473edb notes: a. surface mounted on 1" x 1" fr4 board with full copper, t = 5 s. b. maximum under steady stat e conditions is 85 c/w. c. surface mounted on 1" x 1" fr4 board with minimum copper, t = 5 s. d. maximum under steady stat e conditions is 175 c/w. notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not s ubject to production testing. c. surface mounted on 1" x 1" fr4 board with full copper, t = 5 s. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a, b t = 5 s r thja 35 45 c/w maximum junction-to-ambient c, d t = 5 s r thja 85 110 specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = - 250 a - 20 v v ds temperature coefficient v ds /t j i d = - 250 a - 14 mv/c v gs(th) temperature coefficient v gs(th) /t j 3.4 gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 0.6 - 1.5 v gate-source leakage i gss v ds = 0 v, v gs = 4.5 v 5 a v ds = 0 v, v gs = 12 v 1 ma zero gate voltage drain current i dss v ds = - 20 v, v gs = 0 v - 1 a v ds = - 20 v, v gs = 0 v, t j = 70 c - 10 on-state drain current a i d(on) v ds - 5 v, v gs = - 4.5 v - 5 a drain-source on-state resistance a r ds(on) v gs = - 4.5 v, i d = - 1 a 0.034 0.041 v gs = - 2.5 v, i d = - 1 a 0.046 0.055 forward transconductance a g fs v ds = - 10 v, i d = - 1 a 11 s dynamic b gate resistance r g v gs = - 0.1 v, f = 1 mhz 3.6 k tu r n - o n d e l ay t i m e t d(on) v dd = - 10 v, r l = 10 i d ? - 1 a, v gen = - 4.5 v, r g = 1 15 25 s rise time t r 50 75 turn-off delay time t d(off) 55 85 fall time t f 100 150 tu r n - o n d e l ay t i m e t d(on) v dd = - 10 v, r l = 10 i d ? - 1 a, v gen = - 10 v, r g = 1 715 rise time t r 18 30 turn-off delay time t d(off) 155 235 fall time t f 110 165 drain-source body diode characteristics continuous source-drain diode current i s t a = 25 c - 2.3 c a pulse diode forward current i sm - 25 body diode voltage v sd i s = - 1 a, v gs = 0 v - 0.85 - 1.2 v body diode reverse recovery time t rr i f = - 1 a, di/dt = 100 a/s, t j = 25 c 30 60 ns body diode reverse recovery charge q rr 17 35 nc reverse recovery fall time t a 13 ns reverse recovery rise time t b 17
vishay siliconix si8473edb document number: 65037 s09-1820-rev. a, 14-sep-09 www.vishay.com 3 application circuit example gate-source protection from over-voltage in reverse polarity protection circuit si 8 473edb s d r g v i n v out g n d r1 > 50 k
www.vishay.com 4 document number: 65037 s09-1820-rev. a, 14-sep-09 vishay siliconix si8473edb typical characteristics 25 c, unless otherwise noted gate current vs. gate-source voltage output characteristics on-resistance vs. drain current 0 0.2 0.4 0.6 0. 8 1.0 0 3 6 9 12 15 1 8 v gs - gate-to-so u rce v oltage ( v ) i gss - gate c u rrent (ma) i gss at 25 c 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v ds - drain-to-so u rce v oltage ( v ) i d - drain c u rrent (a) v gs =5 v thr u 2.5 v v gs =2 v v gs =1.5 v 0.00 0.03 0.06 0.09 0.12 0 5 10 15 20 25 r ds(on) - on-resistance ( ) i d - drain c u rrent (a) v gs =2.5 v v gs =4.5 v gate current vs. gate-source voltage transfer characteristics on-resistance vs. junction temperature v gs - gate-to-so u rce v oltage ( v ) i gss - gate c u rrent (a) 0 3 6 9 12 15 1 8 10 -3 10 -4 10 -5 10 -6 10 -7 10 - 8 10 -9 t j = 25 c t j = 150 c 0 2 4 6 8 10 0.0 0.5 1.0 1.5 2.0 v gs - gate-to-so u rce v oltage ( v ) i d - drain c u rrent (a) t c = 25 c t c = 125 c t c = - 55 c 0. 8 0.9 1.0 1.1 1.2 1.3 1.4 - 50 - 25 0 25 50 75 100 125 150 t j - j u nction temperat u re (c) ( n ormalized) - on-resistance r ds(on) v gs =2.5 v ,4.5 v i d =1a
vishay siliconix si8473edb document number: 65037 s09-1820-rev. a, 14-sep-09 www.vishay.com 5 typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 0.1 1 10 100 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 1.4 t j = 150 c v sd - so u rce-to-drain v oltage ( v ) i s - so u rce c u rrent (a) t j = 25 c 0.5 0.6 0.7 0. 8 0.9 1.0 1.1 1.2 - 50 - 25 0 25 50 75 100 125 150 v ( v ) gs(th) t j - temperat u re (c) i d =250 a on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0.00 0.02 0.04 0.06 0.0 8 0.10 0.12 012345 - on-resistance ( ) r ds(on) v gs - gate-to-so u rce v oltage ( v ) t j =25 c t j = 125 c 0.001 0 40 8 0 60 110 time (s) 20 po w er ( w ) 0.01 0.1 100 600 safe operating area, junction-to-ambient v ds - drain-to-so u rce v oltage ( v ) * v gs > minim u m v gs at w hich r ds(on) is specified 100 1 0.1 1 10 100 0.01 10 i d - drain c u rrent (a) 0.1 t a =25 c single p u lse 10 ms 100 ms dc limited b yr ds(on) * b v dss limited 1ms 10 s 1s
www.vishay.com 6 document number: 65037 s09-1820-rev. a, 14-sep-09 vishay siliconix si8473edb typical characteristics 25 c, unless otherwise noted notes: when mounted on 1" x 1" fr4 with full copper. * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resistanc e, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to deter mine the current rating, when this rating falls below the package limit. current derating* 0 1 2 3 4 5 6 0 255075100125150 t a - am b ient temperat u re (c) i d - drain c u rrent (a) power derating 0.0 0.3 0.6 0.9 1.2 1.5 25 50 75 100 125 150 t a - am b ient temperat u re (c) po w er ( w )
vishay siliconix si8473edb document number: 65037 s09-1820-rev. a, 14-sep-09 www.vishay.com 7 typical characteristics 25 c, unless otherwise noted normalized thermal transient impedance, junction-to-ambient (1" x 1" fr4 board with full copper) 10 -3 10 -2 0 0 6 0 1 1 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1. d u ty cycle, d = 2. per unit base = r thja = 8 5 c/ w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm normalized thermal transient impedance, junction-to-ambient (1" x 1" fr4 board with minimum copper) 10 -3 10 -2 0 0 0 1 0 1 1 10 -1 10 -4 100 0.2 0.1 0.05 0.02 sq u are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1 0.1 0.01 d u ty cycle = 0.5 t 1 t 2 n otes: p dm 1. d u ty cycle, d = 2. per unit base = r thja = 175 c/ w 3. t jm - t a =p dm z thja (t) t 1 t 2 4. s u rface mo u nted single p u lse
www.vishay.com 8 document number: 65037 s09-1820-rev. a, 14-sep-09 vishay siliconix si8473edb package outline micro foot: 4-bump (2 x 2, 0.8 mm pitch) notes (unless otherwise specified): 1. laser mark on the silicon die back, coat ed with a thin metal. 2. bumps are eutectic solder 63/57 sn/pb. 3. non-solder mask defined copper landing pad. 4. the flat side of wafers is oriented at the bottom. notes: a. use millimeters as the primary measurement. vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?65037 . b u mp n ote 2 8 473e xxx recommended land mark on backside of die silicon 4 x ? 0.30 0.31 n ote 3 solder mask ? 0.40 b diamerter e e a a 2 a 1 e s d e s e dim. millimeters a inches min. max. min. max. a 0.600 0.650 0.0236 0.0256 a 1 0.260 0.290 0.0102 0.0114 a 2 0.340 0.360 0.0134 0.0142 b 0.370 0.410 0.0146 0.0161 d 1.520 1.600 0.0598 0.0630 e 1.520 1.600 0.0598 0.0630 e 0.750 0.850 0.0295 0.0335 s 0.370 0.380 0.0146 0.0150
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.
|
