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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet FEATURES: * Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8 * Single Voltage Read and Write Operations - 3.0-3.6V for SST39LF512/010/020/040 - 2.7-3.6V for SST39VF512/010/020/040 * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 10 mA (typical) - Standby Current: 10 A (typical) * Sector-Erase Capability - Uniform 4 KByte sectors * Fast Read Access Time: - 45 ns for SST39LF512/010 - 55 ns for SST39LF020/040 - 70 and 90 ns for SST39VF512/010/020/040 * Latched Address and Data * Fast Erase and Byte-Program: - Sector-Erase Time:18 ms typical - Chip-Erase Time: 70 ms typical - Byte-Program Time: 14 s typical - Chip Rewrite Time: 1 second typical for SST39LF/VF512 2 seconds typical for SST39LF/VF010 4 seconds typical for SST39LF/VF020 8 seconds typical for SST39LF/VF040 * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 32-Pin PLCC - 32-Pin TSOP (8mm x14mm)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PRODUCT DESCRIPTION The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 are 64K x8, 128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF512/010/020/040 devices write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF512/010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39LF512/010/020/040 and SST39VF512/010/020/ 040 devices provide a maximum Byte-Program time of 20 sec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, they are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications,
(c) 2000 Silicon Storage Technology, Inc. 395-2 8/00
they significantly improves performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/ Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet surface mount requirements, the SST39LF512/ 010/020/040 and SST39VF512/010/020/040 devices are offered in 32-pin TSOP and 32-pin PLCC packages. See Figures 1 and 2 for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 1
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39LF512/010/020/040 and SST39VF512/010/020/040 device is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Byte-Program Operation The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 are programmed on a byte-by-byte basis. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 s. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 14 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The SectorErase operation is initiated by executing a six-byte-command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse , while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 8 for timing waveforms. Any commands written during the Sector-Erase operation will be ignored. Chip-Erase Operation The SST39LF512/010/020/040 and SST39VF512/010/020/ 040 devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the "1's" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command sequence with ChipErase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for timing diagram, and Figure 17 for the flowchart. Any commands written during the Chip-Erase operation will be ignored. Write Operation Status Detection The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits : Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ7) When the SST39LF512/010/020/040 and SST39VF512/ 010/020/040 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 15 for a flowchart.
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0's and 1's, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing diagram and Figure 15 for a flowchart. Data Protection The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 provide the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six byte load sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command FUNCTIONAL BLOCK DIAGRAM
X-Decoder EEPROM Cell Array
codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC. Product Identification The Product Identification mode identifies the devices as the SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 and SST39LF/VF040 and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for these devices. Users may wish to use the Software Product Identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 10 for the Software ID Entry and Read timing diagram and Figure 16 for the Software ID entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION TABLE Address Manufacturer's ID Device ID SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 0000H 0001H 0001H 0001H 0001H Data BF H D4 H D5 H D6 H D7 H
395 PGM T1.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Product Identification Mode Exit/Reset In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 11 for timing waveform and Figure 16 for a flowchart.
Memory Address
Address Buffers & Latches Y-Decoder
CE# OE# WE# DQ7 - DQ0
395 ILL B1.0
Control Logic
I/O Buffers and Data Latches
16
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512 A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
395 ILL F01.0
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
Standard Pinout Top View Die Up
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM)
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
WE# WE# WE# WE#
VDD
A12
A15
A16
A18
VDD
A12
A15
A16
VDD
A12
A15
A16
NC
VDD
A12
A15
NC
NC
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512
NC
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
5 6 7 8 9 10 11 12 13
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512
4
3
2
1
32 31 30 29 28 27 26 25 24 23 22
NC
A17
NC
A17
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
32-Pin PLCC Top View
21 14 15 16 17 18 19 20
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
VSS
395 ILL F02b.1
DQ1
DQ2
VSS
DQ3
DQ4
DQ5 DQ5 DQ5
DQ1
DQ2
VSS
DQ3
DQ4
DQ1
DQ2
DQ3
DQ4
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLCC
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4
DQ6
VSS
DQ6
DQ6
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet TABLE 2: PIN DESCRIPTION Symbol Pin Name AMS-A0 Address Inputs DQ7-DQ0 Data Input/output Functions To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: 3.0-3.6V for SST39LF512/010/020/040 2.7-3.6V for SST39VF512/010/020/040 Unconnected Pins
395 PGM T2.0
1 2 3 4 5 6
CE# OE# WE# VDD Vss NC
Chip Enable Output Enable Write Enable Power Supply Ground No Connection
Note: AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
TABLE 3: OPERATION MODES SELECTION Mode CE# Read VIL Program VIL Erase VIL Standby Write Inhibit Product Identification Hardware Mode Software Mode VIH X X VIL VIL
7
OE# VIL VIH VIH X VIL X VIL VIL WE# VIH VIL VIL X X VIH VIH VIH A9 AIN AIN X X X X VH AIN DQ DOUT DIN X High Z High Z/DOUT High Z/DOUT Manufacturer's ID (BF) Device ID1 Address AIN AIN Sector address, XXh for Chip-Erase X X X AMS2 - A1 = VIL, A0 = VIL AMS2 - A1 = VIL, A0 = VIH See Table 4
395 PGM T3.1
8 9 10 11 12 13 14 15 16
Notes:1. Device ID = D4 for SST39LF/VF512, D5 for SST39LF/VF010, D6 for SST39LF/VF020 and D7 for SST39LF/VF040 2. AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE
Command Sequence 1st Bus Write Cycle Addr1 Data Byte-Program 5555H AAH Sector-Erase 5555H AAH Chip-Erase 5555H AAH Software ID Entry 5555H AAH Software ID Exit XXH F0H Software ID Exit 5555H AAH 2nd Bus Write Cycle Addr1 Data 2AAAH 55H 2AAAH 55H 2AAAH 55H 2AAAH 55H 2AAAH 55H 3rd Bus Write Cycle Addr1 Data 5555H A0H 5555H 80H 5555H 80H 5555H 90H 5555H F0H
395 PGM T4.0
4th Bus Write Cycle Addr1 Data BA3 Data 5555H AAH 5555H AAH
5th Bus Write Cycle Addr1 Data 2AAAH 55H 2AAAH 55H
6th Bus Write Cycle Addr1 Data SAx2 30H 5555H 10H
Notes: 1. Address format A14-A0 (Hex). Address A15 is "Don't Care" for the Command sequence for SST39LF/VF512. Address A15 and A16 are "Don't Care" for the Command sequence for SST39LF/VF010. Address A15, A16 and A17 are "Don't Care" for the Command sequence for SST39LF/VF020. Address A15, A16, A17 and A18 are "Don't Care" for the Command sequence for SST39LF/VF040. 2. SAx for Sector-Erase; uses AMS-A12 address lines AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 3. BA = Program Byte address 4. Both Software ID Exit operations are equivalent 5. With AMS -A1 =0; SST Manufacturer's ID = BFH, is read with A0 = 0, SST39LF/VF512 Device ID = D4H, is read with A0 = 1. SST39LF/VF010 Device ID = D5H, is read with A0 = 1. SST39LF/VF020 Device ID = D6H, is read with A0 = 1. SST39LF/VF040 Device ID = D7H, is read with A0 = 1. AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 6. The device does not remain in Software Product ID Mode if powered down.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................... -55C to +125C Storage Temperature ........................................................................................................................ -65C to +150C D. C. Voltage on Any Pin to Ground Potential .............................................................................. -0.5V to VDD+ 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential .......................................................... -1.0V to VDD+ 1.0V Voltage on A9 Pin to Ground Potential ................................................................................................. -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25C) ............................................................................................ 1.0W Through Hole Lead Soldering Temperature (10 Seconds) .................................................................................. 300C Surface Mount Lead Soldering Temperature (3 Seconds) .................................................................................. 240C Output Short Circuit Current1 .................................................................................................................................................................... 50 mA
Note: 1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE FOR SST39LF512/010/020/040 Range Ambient Temp VDD Commercial 0 C to +70 C 3.0-3.6V OPERATING RANGE FOR SST39VF512/010/020/040 Range Ambient Temp VDD Commercial 0 C to +70 C 2.7-3.6V Industrial -40 C to +85 C 2.7-3.6V
(c) 2000 Silicon Storage Technology, Inc.
AC CONDITIONS OF TEST Input Rise/Fall Time .................................. 5 ns Output Load .............................................. CL = 30 pF for SST39LF512/010/020/040 CL = 100 pF for SST39VF512/010/020/040 See Figures 12 and 13
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet TABLE 5: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST39LF512/010/020/040 AND 2.7-3.6V FOR SST39VF512/010/020/040 Limits Symbol Parameter Min Max Units Test Conditions IDD Power Supply Current Read Write Standby VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage Supervoltage for A9 pin Supervoltage Current for A9 pin 20 20 15 1 1 0.8 0.7 VDD VDD-0.3 0.2 VDD-0.2 11.4 12.6 200 mA mA A A A V V V V V V A CE#=OE#=VIL,WE#=VIH , all I/Os open, Address input = VIL/VIH, at f=1/TRC Min., VDD=VDD Max CE#=WE#=VIL, OE#=VIH, VDD =VDD Max. CE#=VIHC, VDD = VDD Max. VIN =GND to VDD, VDD = VDD Max. VOUT =GND to VDD, VDD = VDD Max. VDD = VDD Min. VDD = VDD Max. VDD = VDD Max. IOL = 100 A, VDD = VDD Min. IOH = -100A, VDD = VDD Min. CE# = OE# =VIL, WE# = VIH CE# = OE# = VIL, WE# = VIH, A9 = VH Max.
395 PGM T5.0
1 2 3 4 5 6 7 8
I SB I LI I LO VIL VIH VIHC VOL VOH VH IH
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ1 TPU-WRITE1 Power-up to Read Operation Power-up to Write Operation
Minimum 100 100
Units s s
395 PGM T6.0
9 10
TABLE 7: CAPACITANCE (Ta = 25 C, f=1 Mhz, other pins open) Parameter Description Test Condition CI/O1 CIN1 I/O Pin Capacitance Input Capacitance VI/O = 0V VIN = 0V
Maximum 12 pF 6 pF
395 PGM T7.0
11 12 13
Note: 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: RELIABILITY CHARACTERISTICS Symbol Parameter NEND1 TDR1 VZAP_HBM1 VZAP_MM1 ILTH1 Endurance Data Retention ESD Susceptibility Human Body Model ESD Susceptibility Machine Model Latch Up
Minimum Specification 10,000 100 2000 200 100 + IDD
Units Cycles Years Volts Volts mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
395 PGM T8.1
14 15 16
Note: 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V FOR SST39LF512/010/020/040 AND 2.7-3.6V FOR SST39VF512/010/020/040 SST39VF512-70 SST39VF010-70 SST39LF512-45 SST39LF020-55 SST39VF020-70 SST39LF010-45 SST39LF040-55 SST39VF040-70 Symbol Parameter Min Max Min Max Min Max TRC Read Cycle Time 45 55 70 TCE Chip Enable Access Time 45 55 70 TAA Address Access Time 45 55 70 TOE Output Enable Access Time 30 30 35 1 CE# Low to Active Output 0 0 0 TCLZ TOLZ1 OE# Low to Active Output 0 0 0 1 TCHZ CE# High to High-Z Output 15 15 25 1 TOHZ OE# High to High-Z Output 15 15 25 TOH1 Output Hold from Address 0 0 0 Change
SST39VF512-90 SST39VF010-90 SST39VF020-90 SST39VF040-90 Min Max Units 90 ns 90 ns 90 ns 45 ns 0 ns 0 ns 30 ns 30 ns 0 ns
395 PGM T9.1
Note: 1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter TBP Byte-Program Time TAS Address Setup Time TAH Address Hold Time TCS WE# and CE# Setup Time TCH WE# and CE# Hold Time TOES OE# High Setup Time TOEH OE# High Hold Time TCP CE# Pulse Width TWP WE# Pulse Width TWPH WE# Pulse Width High TCPH CE# Pulse Width High TDS Data Setup Time TDH Data Hold Time TIDA Software ID Access and Exit Time TSE Sector-Erase TSCE Chip-Erase
Min 0 30 0 0 0 10 40 40 30 30 40 0
Max 20
150 25 100
Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms
395 PGM T10.0
Note: 1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TRC ADDRESS AMS-0
TAA
1 2
CE#
TCE
3
OE# VIH WE# TOH DATA VALID AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 TCHZ HIGH-Z DATA VALID
395 ILL F03.0
TOE
TOLZ
TOHZ
4 5 6 7 8 9
DQ7-0
HIGH-Z
TCLZ
Note:
FIGURE 3: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 5555 TAH TWP WE# TAS OE# TCH CE# TCS DQ7-0 AA SW0 Note: 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA)
395 ILL F04.0
2AAA
5555
ADDR TDH
10 11 12 13 14 15 16
TWPH
TDS
AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc.
9
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 5555 TAH TCP CE# TAS OE# TCH WE# TCS DQ7-0 AA SW0 Note: 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) TCPH TDS 2AAA 5555 ADDR TDH
395 ILL F05.0
AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0 TCE CE# TOEH OE# TOE WE# TOES
DQ7 Note:
D
D#
D#
D
395 ILL F06.0
AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
FIGURE 6: DATA# POLLING TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc.
10
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
1
ADDRESS AMS-0 TCE CE# TOEH OE# TOE TOES
2 3 4
WE#
5
DQ6
TWO READ CYCLES WITH SAME OUTPUTS 395 ILL F07.0
6 7 8 9
Note:
AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA SAX
TSE
10 11 12
CE#
OE# TWP WE#
13
55 SW1 80 SW2 AA SW3 55 SW4 30 SW5
334 ILL F08.0
DQ7-0
AA SW0
14 15 16
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minmum timings are met. (See Table 10) SAX = Sector Address AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
FIGURE 8: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc. 395-2 8/00
11
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
10 SW5
334 ILL F17.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minmum timings are met. (See Table 10) AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
FIGURE 9: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
Three-byte sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
CE#
OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 90 SW2 TAA BF Device ID
395 ILL F09.1
TIDA
Note: Device ID = D4 for SST39LF/VF512, D5 for SST39LF/VF010, D6 for SST39LF/VF020 and D7 for SST39LF/VF040.
FIGURE 10: SOFTWARE ID ENTRY AND READ
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET
1 2
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
AA
55
F0 TIDA
3 4 5
CE#
OE# TWP WE# T WHP SW0 SW1 SW2
395 ILL F10.0
6 7
FIGURE 11: SOFTWARE ID EXIT AND RESET
8 9 10 11 12 13 14 15 16
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
395 ILL F12.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are at VIT (0.5 VDD) and VOT (0.5 VDD) Input rise and fall times (10% 90%) are <5 ns.
Note: VIT-VINPUT Test VOT-VOUTPUT Test VIHT-VINPUT HIGH Test VILT-VINPUT LOW Test
FIGURE 12: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT CL
395 ILL F11.1
FIGURE 13: A TEST LOAD EXAMPLE
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Start
1 2
Load data: AA Address: 5555
3 4 5
Load data: 55 Address: 2AAA
Load data: A0 Address: 5555
6 7 8 9 10 11
395 ILL F13.0
Load Byte Address/Byte Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
12 13 14 15 16
FIGURE 14: BYTE-PROGRAM ALGORITHM
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Internal Timer Byte-Program/ Erase Initiated
Toggle Bit Byte-Program/ Erase Initiated
Data# Polling Byte-Program/ Erase Initiated
Wait TBP, TSCE, or TSE
Read byte
Read DQ7
Program/Erase Completed
Read same byte
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes
Program/Erase Completed
Program/Erase Completed
395 ILL F14.0
FIGURE 15: WAIT OPTIONS
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
1
Software ID Entry Command Sequence Software ID Exit & Reset Command Sequence
2
Load data: AA Address: 5555 Load data: AA Address: 5555 Load data: F0 Address: XX
3 4
Load data: 55 Address: 2AAA
Load data: 55 Address: 2AAA
Wait TIDA
5
Load data: 90 Address: 5555 Load data: F0 Address: 5555 Return to normal operation
6 7
Wait TIDA
Wait TIDA
8
Read Software ID Return to normal operation
395 ILL F15.1
9 10 11
FIGURE 16: SOFTWARE ID COMMAND FLOWCHARTS
12 13 14 15 16
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Chip-Erase Command Sequence Load data: AA Address: 5555
Sector-Erase Command Sequence Load data: AA Address: 5555
Load data: 55 Address: 2AAA
Load data: 55 Address: 2AAA
Load data: 80 Address: 5555
Load data: 80 Address: 5555
Load data: AA Address: 5555
Load data: AA Address: 5555
Load data: 55 Address: 2AAA
Load data: 55 Address: 2AAA
Load data: 10 Address: 5555
Load data: 30 Address: SAX
Wait TSCE
Wait TSE
Chip erased to FFH
Sector erased to FFH
395 ILL F16.0
FIGURE 17: ERASE COMMAND SEQUENCE
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet Device SST39VFxxx Speed Suffix1 Suffix2 - XXX XX XX
1
Package Modifier H = 32 pins Numeric = Die modifier Package Type N = PLCC W = TSOP (die up) (8mm x 14mm) U = Unencapsulated die Temperature Range C = Commercial = 0 to 70C I = Industrial = -40 to 85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 45 = 45 ns 55 = 55 ns 70 = 70 ns 90 = 90 ns Device Density 512 = 512 Kilobit 010 = 1 Megabit 020 = 2 Megabit 040 = 4 Megabit Voltage L = 3.0-3.6V V = 2.7-3.6V
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(c) 2000 Silicon Storage Technology, Inc.
19
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet SST39LF512 Valid combinations SST39LF512-45-4C-WH SST39LF512-45-4C-NH SST39VF512 Valid combinations SST39VF512-70-4C-WH SST39VF512-70-4C-NH SST39VF512-90-4C-WH SST39VF512-90-4C-NH SST39VF512-90-4C-U4 SST39VF512-70-4I-WH SST39VF512-70-4I-NH SST39VF512-90-4I-WH SST39VF512-90-4I-NH SST39LF010 Valid combinations SST39LF010-45-4C-WH SST39LF010-45-4C-NH SST39VF010 Valid combinations SST39VF010-70-4C-WH SST39VF010-70-4C-NH SST39VF010-90-4C-WH SST39VF010-90-4C-NH SST39VF010-90-4C-U4 SST39VF010-70-4I-WH SST39VF010-70-4I-NH SST39VF010-90-4I-WH SST39VF010-90-4I-NH SST39LF020 Valid combinations SST39LF020-55-4C-WH SST39LF020-55-4C-NH SST39VF020 Valid combinations SST39VF020-70-4C-WH SST39VF020-70-4C-NH SST39VF020-90-4C-WH SST39VF020-90-4C-NH SST39VF020-90-4C-U4 SST39VF020-70-4I-WH SST39VF020-70-4I-NH SST39VF020-90-4I-WH SST39VF020-90-4I-NH SST39LF040 Valid combinations SST39LF040-55-4C-WH SST39LF040-55-4C-NH SST39VF040 Valid combinations SST39VF040-70-4C-WH SST39VF040-70-4C-NH SST39VF040-90-4C-WH SST39VF040-90-4C-NH SST39VF040-90-4C-U1 SST39VF040-70-4I-WH SST39VF040-70-4I-NH SST39VF040-90-4I-WH SST39VF040-90-4I-NH
Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c) 2000 Silicon Storage Technology, Inc.
20
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet PACKAGING DIAGRAMS
TOP VIEW SIDE VIEW BOTTOM VIEW
1 2
Optional Pin #1 Identifier
.485 .495 .447 .453 .042 .048
2 1 32
.106 .112 .020 R. MAX. .023 x 30 .029 .030 R. .040
3
.490 .530
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400 BSC
4 5
.050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032
6 7
32.PLCC.NH-ILL.1
Note:
1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
8 9 10 11 12 13 14 15 16
(c) 2000 Silicon Storage Technology, Inc.
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395-2 8/00
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
PIN # 1 IDENTIFIER 1.05 0.95 .50 BSC
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
Note:
1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm.
32.TSOP-WH-ILL.3
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE: WH
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com * Literature FaxBack 888-221-1178, International 732-544-2873
(c) 2000 Silicon Storage Technology, Inc.
22
395-2 8/00

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