View SMMS695A_1003922.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
D D D D D D D
description
The TM16EN64HPU is a 128M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of sixteen TMS465409, 16 777 216 x 4-bit 4K-refresh EDO dynamic random-access memories (DRAMs), each in a 400-mil, 32-pin plastic thin small-outline package (TSOP) (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895). The TM16EN64LPU is a 128M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS464409, 16 777 216 x 4-bit 8K-refresh EDO dynamic random-access memories (DRAMs), each in a 400-mil, 32-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895). The TM16EN72HPU is a 128M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS465409, 16 777 216 x 4-bit 4K-refresh EDO dynamic random-access memories (DRAMs), each in a 400-mil, 32-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895). The TM16EN72LPU is a 128M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS464409, 4 194 309 x 4-bit 8K-refresh EDO dynamic random-access memories (DRAMs), each in a 400-mil, 32-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895).
operation
The TM16EN64xPU operates as sixteen TMS46x409s that are connected as shown in the TM16EN64xPU functional block diagram. The TM16EN72xPU operates as eighteen TMS46x409s that are connected as shown in the TM16EN72xPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
1
PRODUCT PREVIEW
Organization - TM16EN64xPU-xx . . . 16 777216 x 64 Bits - TM16EN72xPU-xx . . . 16 777216 x 72 Bits Single 3.3-V Power Supply (10% Tolerance) JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket TM16EN64HPUxx -- Utilizes Sixteen 64M-Bit High-Speed (16M x 4-Bit) Dynamic RAMs TM16EN72HPUxx -- Utilizes Eighteen 64M-Bit High-Speed (16M x 4-Bit) Dynamic RAMs High-Speed, Low-Noise LVTTL Interface High-Reliability 32-Lead 300-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGC Suffix)
D D D D D D D
Long Refresh Periods: - TM16ENxxHPU: 64 ms (4 096 Cycles) - TM16ENxxLPU: 64 ms (8 192 Cycles) 3-State Output Extended-Data-Out (EDO) Operation With CAS-Before-RAS (CBR), RAS-Only, and Hidden Refresh Serial Presence-Detect (SPD) Using EEPROM Ambient Temperature Range 0C to 70C Gold-Plated Contacts Performance Ranges
ACCESS TIME tRAC (MAX) '16ENxxxPU-40 40 ns '16ENxxxPU-50 50 ns '16ENxxxPU-60 60 ns ACCESS ACCESS EDO TIME TIME CYCLE tCAC tAA tHPC (MAX) (MAX) (MIN) 11 ns 20 ns 16 ns 13 ns 25 ns 20 ns 15 ns 30 ns 25 ns
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM16EN64HPU TM16EN72HPU ( SIDE VIEW ) ( SIDE VIEW )
PIN NOMENCLATURE - TM16ENxxHPU A[0:11] A[0:11] DQ[0:63] CB[0:7] CAS[0:7] RAS0 and RAS2 WE0 and WE2 OE0 and OE2 SA[0:2] SDA SCL NC VDD VSS Row Address Inputs Column Address Inputs Data In / Data Out Check Bit In / Check Bit Out Column-Address Strobe Row-Address Strobe Write Enable Output Enable Serial Presence-Detect (SPD) Device Add Input SPD Address / Data SPD Clock No-Connect Pin 3.3-V Supply Ground
1
10 11
PRODUCT PREVIEW
PIN NOMENCLATURE - TM16ENxxLPU A[0:12] A[0:10] DQ[0:63] CB[0:7] CAS[0:7] RAS0 and RAS2 WE0 and WE2 OE0 and OE2 SA[0:2] SDA SCL NC VDD VSS Row Address Inputs Column Address Inputs Data In / Data Out Check Bit In / Check Bit Out Column-Address Strobe Row-Address Strobe Write Enable Output Enable Serial Presence-Detect (SPD) Device Add Input SPD Address / Data SPD Clock No-Connect Pin 3.3-V Supply Ground
40
41
84
2
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
Pin Assignments
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NAME VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE0 CAS0 CAS1 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 A12 VDD NC NC NO. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 PIN NAME VSS OE2 RAS2 CAS2 CAS3 WE2 VDD NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS NC NC NC SDA SCL VDD NO. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 PIN NAME VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD NC CAS4 CAS5 NC NC VSS A1 A3 A5 A7 A9 A11 NC VDD NC NC NO. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 PIN NAME VSS NC NC CAS6 CAS7 NC VDD NC NC CB6 CB7 VSS DQ48 DQ50 DQ51 VDD DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS NC NC SA0 SA1 SA2 VDD
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
3
PRODUCT PREVIEW
DQ49
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
dual-in-line memory module and components
The dual-in-line memory module and components include:
D D D
PC substrate: 1,27
" 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM16EN64xPU
RAS0 WE0 OE0 CAS0 DQ[0:3] CAS DQ[0:3] CAS DQ[4:7] DQ[0:3] CAS DQ[0:3] CAS DQ[12:15] CAS2 DQ[16:19] DQ[0:3] CAS DQ[0:3] CAS DQ[20:23] CAS3 DQ[24:27] DQ[0:3] CAS DQ[0:3] CAS DQ[28:31] TM16EN64HPU A[0:11] TM16EN64LPU A[0:12] LEGEND: CS = SPD = DQ[0:3] OE OE OE OE OE OE OE OE W U0 RAS RAS2 WE2 OE2 CAS4 DQ[32:35] RAS DQ[36:39] RAS CAS5 DQ[40:43] RAS DQ[44:47] RAS CAS6 DQ[48:51] RAS DQ[52:55] RAS CAS7 DQ[56:59] RAS DQ[60:63] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] OE OE OE OE OE OE OE OE W RAS
UB0
W U1
W
RAS
UB1
PRODUCT PREVIEW
CAS1 DQ[8:11]
W U2
W
RAS
UB2
W U3
W
RAS
UB3
W U4
W
RAS
UB4
W U5
W
RAS
UB5
W U6
W
RAS
UB6
W U7
W
RAS
UB7
SPD EEPROM A[0:11]: U[0:7], UB[0:7] SCL A[0:12]: U[0:7], UB[0:7] Chip select Serial Presence Detect SA0 SA1 SA2 A0 A1 A2 SDA
4
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
functional block diagram for the TM16EN72xPU
RAS0 WE0 OE0 CAS0 DQ[0:3] CAS DQ[0:3] CAS DQ[4:7] CAS1 DQ[8:11] DQ[0:3] CAS DQ[0:3] CAS DQ[12:15] CAS1 CB[0:3] CAS2 DQ[16:19] DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[20:23] CAS3 DQ[24:27] DQ[0:3] CAS DQ[0:3] CAS DQ[28:31] DQ[0:3] OE OE OE OE OE OE OE OE OE W U0 RAS RAS2 WE2 OE2 CAS4 DQ[32:35] RAS DQ[36:39] RAS CAS5 DQ[40:43] RAS DQ[44:47] RAS CAS5 CB[4:7] RAS CAS6 DQ[48:51] RAS DQ[52:55] RAS CAS7 DQ[56:59] RAS DQ[60:63] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] OE OE OE OE OE OE OE OE OE W RAS
UB0
W U1
W
RAS
UB1
W U2
W
RAS
UB2
W U3
W
RAS
UB3
U8
UB8
W U4
W
RAS
UB4
W U5
W
RAS
UB5
W U6
W
RAS
UB6
W U7
W
RAS
UB7
TM16EN72HPU A[0:11] TM16EN72LPU A[0:12]
SPD EEPROM A[0:11]: U[0:8], UB[0:8] A[0:12]: U[0:8], UB[0:8] SCL A0 A1 A2 SDA
SA0
SA1
SA2
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
5
PRODUCT PREVIEW
W
W
RAS
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM16EN64xPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W TM16EN72xPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VDD VSS Supply voltage Supply voltage 2 2 - 0.3 0 3 NOM 3.3 0 VDD + 0.3 5.5 0.8 70 MAX 3.6 UNIT V V V V V C
PRODUCT PREVIEW
VIH High-level input voltage VIH-SPD High-level input voltage for the SPD device VIL TA Low-level input voltage Ambient temperature
6
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted)
TM16EN64HPU
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '16EN64HPU-40 MIN 2.4 VDD - 0.2 0.4 0.2 20 MAX '16EN64HPU-50 MIN 2.4 VDD - 0.2 0.4 0.2 20 MAX '16EN64HPU-60 MIN 2.4 V VDD - 0.2 0.4 V 0.2 20 A MAX UNIT
VOH
VOL
II
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
IO
20
20
20
A
VDD = 3.6 V,
Minimum cycle
2560
2080
1760
mA
ICC2
Average g standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR)
16
16
16
mA
8
8
8
mA
ICC3
Average refresh current (RASx-only refresh or CBR) Average EDO current Average CBR refresh current
2560
2080
1760
mA
ICC4
VDD = 3.6 V, RASx low,
tHPC = MIN, CASx cycling
2400
1920
1600
mA
ICC5
VDD = 3.6 V, Minimum cycle, RASx low after CASx low
2560
2080
1760
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
7
PRODUCT PREVIEW
ICC1
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued)
TM16EN64LPU
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '16EN64LPU-40 MIN 2.4 VDD - 0.2 0.4 0.2 20 MAX '16EN64LPU-50 MIN 2.4 VDD - 0.2 0.4 0.2 20 MAX '16EN64LPU-60 MIN 2.4 V VDD - 0.2 0.4 V 0.2 20 A MAX UNIT
VOH
VOL
II
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
IO
20
20
20
A
PRODUCT PREVIEW
ICC1
VDD = 3.6 V,
Minimum cycle
2000
1600
1440
mA
ICC2
Average g standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR)
16
16
16
mA
8
8
8
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average EDO current Average CBR refresh current
2000
1600
1440
mA
ICC4
VDD = 3.6 V, RASx low,
tHPC = MIN, CASx cycling
2240
1760
1440
mA
ICC5
VDD = 3.6 V, Minimum cycle, RASx low after CASx low
2560
2080
1760
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
8
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued)
TM16EN72HPU
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '16EN72HPU-40 MIN 2.4 VDD - 0.2 0.4 0.2 20 MAX '16EN72HPU-50 MIN 2.4 VDD - 0.2 0.4 0.2 20 MAX '16EN72HPU-60 MIN 2.4 V VDD - 0.2 0.4 V 0.2 20 A MAX UNIT
VOH
VOL
II
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
IO
20
20
20
A
VDD = 3.6 V,
Minimum cycle
2880
2340
1980
mA
ICC2
Average g standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR)
18
18
36
mA
9
9
9
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average EDO current Average CBR refresh current
2880
2340
1980
mA
ICC4
VDD = 3.6 V, RASx low,
tHPC = MIN, CASx cycling
2700
2160
1800
mA
ICC5
VDD = 3.6 V, Minimum cycle, RASx low after CASx low
2880
2340
1980
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
9
PRODUCT PREVIEW
ICC1
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued)
TM16EN72LPU
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '16EN72LPU-40 MIN 2.4 VDD - 0.2 0.4 0.2 20 MAX '16EN72LPU-50 MIN 2.4 VDD - 0.2 0.4 0.2 20 MAX '16EN72LPU-60 MIN 2.4 V VDD - 0.2 0.4 V 0.2 20 A MAX UNIT
VOH
VOL
II
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
IO
20
20
20
A
PRODUCT PREVIEW
ICC1
VDD = 3.6 V,
Minimum cycle
2250
1800
1620
mA
ICC2
Average g standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR)
18
18
18
mA
9
9
9
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average EDO current Average CBR refresh current
2250
1800
1620
mA
ICC4
VDD = 3.6 V, RASx low,
tHPC = MIN, CASx cycling
2520
1980
1620
mA
ICC5
VDD = 3.6 V, Minimum cycle, RASx low after CASx low
2880
2340
1980
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
10
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETER Ci(A) Ci(OE) Ci(CAS) Ci(RAS) Ci(W) Co Input capacitance, A0 - A12 Input capacitance, OEx Input capacitance, CASx Input capacitance, RASx Input capacitance, WEx Output capacitance '16EN64xPU MIN MAX 82 58 16 58 58 8 '16EN72xPU MIN MAX 92 65 23 65 65 8 UNIT pF pF pF pF pF pF
NOTE 2: VDD = NOM supply voltage 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3)
PARAMETER tAA tCAC tCPA tRAC tOEA tCLZ tREZ tCEZ tOEZ tWEZ Access time from column address (see Note 4) Access time from CASx (see Note 4) Access time from CASx precharge (see Note 4) Access time from RASx (see Note 4) Access time from OEx (see Note 4) Delay time, CASx to output in low impedance Output buffer turn off delay from RASx (see Note 5) Output buffer turn off delay from CASx (see Note 5) Output buffer turn off delay from OEx (see Note 5) Output buffer turn off delay from WEx (see Note 5) 0 3 3 3 3 11 11 11 11 '16ENxxxPU-40 MIN MAX 20 11 22 40 11 0 3 3 3 3 13 13 13 13 '16ENxxxPU-50 MIN MAX 25 13 28 50 13 0 3 3 3 3 15 15 15 15 '16ENxxxPU-60 MIN MAX 30 15 35 60 15 UNIT ns ns ns ns ns ns ns ns ns ns
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 5. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the output is no longer driven. Data in should not be driven until one of the applicable maximum specs is satisfied.
EDO timing requirements
'16ENxxxPU-40 MIN tHPC tPRWC tCSH tCHO tDOH tCAS tWPE tOCH tCP tOEP Cycle time, EDO page mode, read-write Cycle time, EDO read-write Delay time, RASx active to CASx precharge Hold time, OEx from CASx Hold time, output from CASx Pulse duration, CASx active (see Note 6) Pulse duration, WEx active (output disable only) Setup time, OEx before CASx Pulse duration, CASx precharge Precharge time, OEx 16 47 32 5 5 6 5 5 6 5 10 000 MAX '16ENxxxPU-50 MIN 20 57 40 5 5 8 5 5 8 5 10 000 MAX '16ENxxxPU-60 MIN 25 68 48 5 5 10 5 5 10 5 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns
NOTE 6: In a read-write cycle, tCWD and tCWL must be observed.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
11
PRODUCT PREVIEW
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
ac timing requirements
'16ENxxxPU-40 MIN tRC tRWC tRASP tRAS tRP tWP tRASS tRPS tASC tASR tDS tRCS tCWL tRWL tWCS tWRP tWTS tCSR tCAH tDH tRAH tRCH tRRH tWCH tROH tWRH tWTH tCHR tOEH tCHS Cycle time, random read or write Cycle time, read-write Pulse duration, RASx active, fast page mode (see Note 7) Pulse duration, RASx active, non-page mode (see Note 7) Pulse duration, RASx precharge Pulse duration, write command Pulse duration, RASx active, self refresh (see Note 8) Pulse duration, RASx precharge after self refresh Setup time, column address Setup time, row address Setup time, data in (see Note 9) Setup time, read command Setup time, write command before CASx precharge Setup time, write command before RASx precharge Setup time, write command before CASx active (early-write only) Setup time, WEx high before RASx low (CBR refresh only) Setup time, WEx low before RASx low (test mode only) Setup time, CASx referenced to RASx ( CBR refresh only ) Hold time, column address Hold time, data in (see Note 9) Hold time, row address Hold time, read command referenced to CASx (see Note 10) Hold time, read command referenced to RASx (see Note 10) Hold time, write command during CASx active ( early-write only ) Hold time, RASx referenced to OEx Hold time, WEx high after RASx low (CBR refresh) Hold time, WEx low after RASx low (test mode only) Hold time, CASx referenced to RASx (CBR refresh only ) Hold time, OEx command Hold time, CASx active after RASx precharge (self-refresh) 69 92 40 40 25 6 100 70 0 0 0 0 6 6 0 5 5 5 6 6 6 0 0 6 6 6 6 6 11 -50 100 000 10 000 MAX '16ENxxxPU-50 MIN 84 111 50 50 30 8 100 90 0 0 0 0 8 8 0 5 5 5 8 8 8 0 0 8 8 8 8 8 13 -50 100 000 10 000 MAX '16ENxxxPU-60 MIN 104 135 60 60 40 10 100 110 0 0 0 0 10 10 0 5 5 5 10 10 10 0 0 10 10 10 10 10 15 -50 100 000 10 000 MAX UNIT ns ns ns ns ns ns
ms
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PRODUCT PREVIEW
tRHCP Hold time, RASx active from CASx precharge 22 28 35 ns NOTES: 7. In a read-write cycle, tRWD and tRWL must be observed. 8. During the period of 10 ms tRASS 100 ms, the device is in transition state from normal operation mode to self-refresh mode. 9. Referenced to the later of CASx or WEx in write operations 10. Either tRRH or tRCH must be satisfied for a read cycle.
12
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
ac timing requirements (continued)
'16ENxxxPU-40 MIN tAWD tCPW tCRP tCWD tOED tRAD tRAL tCAL tRCD tRPC tRSH tRWD tTAA tTCPA tTRAC tT tREF Delay time, column address to write command ( read-write only ) Delay time, WEx low after CASx precharge (read-write only) Delay time, CASx precharge to RASx Delay time, CASx to write command ( read-write only ) Delay time, OEx to data in Delay time, RASx to column address (see Note 11) Delay time, column address to RASx precharge Delay time, column address to CASx precharge Delay time, RASx to CASx ( see Note 11) Delay time, RASx precharge to CASx Delay time, CASx active to RASx precharge Delay time, RASx to write command (read-write only) Access time from address (test mode) Access time, from column precharge (test mode) Access time, from RASx (test mode) Transition time Refresh time interval 35 37 5 26 11 8 20 12 10 5 6 55 25 30 45 1 50 64 29 20 MAX '16ENxxxPU-50 MIN 42 45 5 30 13 10 25 15 12 5 8 67 30 35 55 1 50 64 37 25 MAX '16ENxxxPU-60 MIN 49 54 5 34 15 12 30 18 14 5 10 79 35 40 65 1 50 64 45 30 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns
ns ns ns ms
NOTE 11: The maximum value is specified only to ensure access time.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
13
PRODUCT PREVIEW
ns
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect
The serial-presence-detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through a IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Tables in this section list the SPD contents as follows: Table 1-TM16EN64HPU Table 3-TM16EN72HPU Table 2-TM16EN64LPU Table 4-TM16EN72LPU
Table 1. Serial-Presence-Detect Data for the TM16EN64HPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module DIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code LVTTL tRAC=40ns tCAC=11ns Non-parity 15.6 s x4 N/A Rev. 1 26 97h TBD TBD TBD '16EN64HPU-40 ITEM 128 bytes DATA 80h '16EN64HPU-50 ITEM 128 bytes DATA 80h '16EN64HPU-60 ITEM 128 bytes DATA 80h
PRODUCT PREVIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91
256 bytes EDO 12 12 1 bank 64 bits
08h 02h 0Ch 0Ch 01h 40h 00h 01h 28h 0Bh 00h 00h 04h 00h 01h 1Ah 9700...00h
256 bytes EDO 12 12 1 bank 64 bits
08h 02h 0Ch 0Ch 01h 40h 00h
256 bytes EDO 12 12 1 bank 64 bits
08h 02h 0Ch 0Ch 01h 40h 00h
LVTTL tRAC=50ns tCAC=13ns Non-parity 15.6 s x4 N/A Rev. 1 38 97h TBD TBD TBD
01h 32h 0Dh 00h 00h 04h 00h 01h 26h 9700...00h
LVTTL tRAC=60ns tCAC=15ns Non-parity 15.6 s x4 N/A Rev. 1 50 97h TBD TBD TBD
01h 3Ch 0Fh 00h 00h 04h 00h 01h 32h 9700...00h
TBD indicates values are determined at manufacturing time and are module dependent.
14
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 1. Serial Presence-Detect Data for the TM16EN64HPU (Continued)
BYTE NO. 95-98 92 93-94 99-125 126-127 128-166 FUNCTION DESCRIBED Assembly serial number PCB revision code Manufacturing date Manufacturer specific data Vendor specific data System integrator's specific data '16EN64HPU-40 ITEM TBD TBD TBD TBD TBD TBD DATA '16EN64HPU-50 ITEM TBD TBD TBD TBD TBD TBD DATA '16EN64HPU-60 ITEM TBD TBD TBD TBD TBD TBD DATA
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
15
PRODUCT PREVIEW
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 2. Serial-Presence-Detect Data for the TM16EN64LPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module DIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data LVTTL tRAC=40ns tCAC=11 ns Non-Parity 15.6 s x4 N/A Rev. 1 36 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD '16EN64LPU-40 ITEM 128 bytes DATA 80h '16EN64LPU-50 ITEM 128 bytes DATA 80h '16EN64LPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5
256 bytes EDO 13 11 1 bank 64 bits
08h 02h 0Dh 0Bh 01h 40h 00h 01h 28h 0Bh 00h 00h 04h 00h 01h 1Ah 9700...00h
256 bytes EDO 13 11 1 bank 64 bits
08h 02h 0Dh 0Bh 01h 40h 00h
256 bytes EDO 13 11 1 bank 64 bits
08h 02h 0Dh 0Bh 01h 40h 00h
PRODUCT PREVIEW
6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
LVTTL tRAC=50ns tCAC=13ns Non-Parity 15.6 s x4 N/A Rev. 1 38 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 32h 0Dh 00h 00h 04h 00h 01h 26h 9700...00h
LVTTL tRAC=60ns tCAC=15ns Non-parity 15.6 s x4 N/A Rev. 1 50 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h 00h 04h 00h 01h 32h 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
16
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 3. Serial-Presence-Detect Data for the TM16EN72HPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module DIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data LVTTL tRAC=40ns tCAC=11 ns ECC 15.6 s x4 x4 Rev. 1 40 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD '16EN72HPU-40 ITEM 128 bytes DATA 80h '16EN72HPU-50 ITEM 128 bytes DATA 80h '16EN72HPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
256 bytes EDO 12 12 1 bank 72 bits
08h 02h 0Ch 0Ch 01h 48h 00h 01h 28h 0Bh 02h 00h 04h 04h 01h 28h 9700...00h
256 bytes EDO 12 12 1 bank 72 bits
08h 02h 0Ch 0Ch 01h 48h 00h
256 bytes EDO 12 12 1 bank 72 bits
08h 02h 0Ch 0Ch 01h 48h 00h
LVTTL tRAC=50ns tCAC=13ns ECC 15.6 s x4 x4 Rev. 1 52 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 32h 0Dh 02h 00h 04h 04h 01h 34h 9700...00h
LVTTL tRAC=60ns tCAC=15ns ECC 15.6 s x4 x4 Rev. 1 64 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 02h 00h 04h 04h 01h 40h 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
17
PRODUCT PREVIEW
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 4. Serial-Presence-Detect Data for the TM16EN72LPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module DIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data LVTTL tRAC=40ns tCAC=11 ns ECC 15.6 s x4 x4 Rev. 1 40 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD '16EN72LPU-40 ITEM 128 bytes DATA 80h '16EN72LPU-50 ITEM 128 bytes DATA 80h '16EN72LPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5
256 bytes EDO 13 11 1 bank 72 bits
08h 02h 0Dh 0Bh 01h 48h 00h 01h 28h 0Bh 02h 00h 04h 04h 01h 28h 9700...00h
256 bytes EDO 13 11 1 bank 72 bits
08h 02h 0Dh 0Bh 01h 48h 00h
256 bytes EDO 13 11 1 bank 72 bits
08h 02h 0Dh 0Bh 01h 48h 00h
PRODUCT PREVIEW
6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
LVTTL tRAC=50ns tCAC=13ns ECC 15.6 s x4 x4 Rev. 1 52 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 32h 0Dh 02h 00h 04h 04h 01h 34h 9700...00h
LVTTL tRAC=60ns tCAC=15ns ECC 15.6 s x4 x4 Rev. 1 64 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 02h 00h 04h 04h 01h 40h 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
18
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
device symbolization (TM16EN64HPU illustrated)
TM16EN64HPU Unbuffered Key Position YY MM T -SS = = = =
-SS
YYMMT
3.3-V Voltage Key Position Year Code Month Code Assembly Site Code Speed Code
NOTE A: Location of symbolization may vary.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
19
PRODUCT PREVIEW
TM16EN64HPU, TM16EN64LPU 16777216 BY 64-BIT TM16EN72HPU, TM16EN72LPU 16777216 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS695A - AUGUST 1997 - REVISED NOVEMBER 1997
MECHANICAL DATA
BS (R-PDIM-N168)
5.255 (133,48) 5.245 (133,22) Notch 0.157 (4,00) x 0.122 (3,10) Deep 2 Places
DUAL IN-LINE MEMORY MODULE
(Note D) Notch 0.079 (2,00) x 0.122 (3,10) Deep 2 Places 0.054 (1,37) 0.046 (1,17)
0.039 (1,00) TYP
0.050 (1,27) 0.125 (3,18)
0.014 (0,35) MAX 0.118 (3,00) TYP 0.700 (17,78) TYP 1.130 (28,70) 1.120 (28,45) 0.106 (2,70) MAX 0.157 (4,00) MAX (For Double Sided DIMM Only) 4088181/A 06/97
PRODUCT PREVIEW
0.125 (3,18) 0.118 (3,00) DIA 2 Places
NOTES: A. B. C. D. E.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MO-161 Dimension includes De-panelization variations; applies between notch and tab edge. Outline may vary above notches to allow router/panelization irregularities.
20
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SMMS695A

	To Download SMMS695A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .