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19-2744; Rev 0; 1/03
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
General Description
The MAX9760-MAX9763 family combines a stereo or mono 3W bridge-tied load (BTL) audio power amplifier, stereo single-ended headphone amplifier, headphone sensing, and a 2:1 input multiplexer all in a tiny 28-pin thin QFN package. These devices operate from a single 4.5V to 5.5V supply and feature an industry-leading 100dB PSRR, allowing these devices to operate from noisy supplies without the addition of a linear regulator. An ultra-low 0.002% THD+N ensures clean, low-distortion amplification of the audio signal. Patented clickand-pop suppression eliminates audible transients on power and shutdown cycles. Power-saving features include low 4mV V OS (minimizes DC current drain through the speakers), low 13mA supply current, and a 10A shutdown mode. A MUTE function allows the outputs to be quickly enabled or disabled. A headphone sense input detects the presence of a headphone jack and automatically configures the amplifiers for either speaker or headphone mode. In speaker mode, the amplifiers can deliver up to 3W of continuous average power into a 3 load. In headphone mode, the amplifier can deliver up to 200mW of continuous average power into a 16 load. The gain of the amplifiers is externally set, allowing maximum flexibility in optimizing output levels for a given load. The amplifiers also feature a 2:1 input multiplexer, allowing multiple audio sources to be selected. The multiplexer can also be used to compensate for limitations in the frequency response of the loud speakers by selecting an external equalizer network. The various functions are controlled by either an I2C-compatible or simple parallel control interface. The MAX9760-MAX9763 are available in either a thermally efficient 28-pin thin QFN package (5mm 5mm 0.8mm) or a TSSOP-EP package. All devices have thermal overload protection (OVP) and are specified over the extended -40C to +85C temperature range. o PC99/01 Compliant o 3W BTL Stereo Speaker Amplifier o 200mW Stereo Headphone Amplifier o Low 0.002% THD+N o Patented Click-and-Pop Suppression o ESD-Protected Outputs o Low Quiescent Current: 13mA o Low-Power Shutdown Mode: 10A o MUTE Function o Headphone Sense Input o Stereo 2:1 Input Multiplexer o Optional 2-Wire, I2C-Compatible or Parallel Interface o Tiny 28-Pin Thin QFN (5mm 5mm 0.8mm) and TSSOP-EP Packages
Features
o Industry-Leading, Ultra-High 100dB PSRR
MAX9760-MAX9763
Ordering Information
PART MAX9760ETI MAX9760EUI TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 28 Thin QFN-EP* 28 TSSOP-EP*
*EP = Exposed paddle. Ordering Information continued at end of data sheet.
Simplified Block Diagram
SINGLE SUPPLY 4.5V TO 5.5V
Applications
Notebooks Portable DVD Players Tablet PCs PC Audio Peripherals Camcorders
LEFT IN1 LEFT IN2 SE/ BTL RIGHT IN1 RIGHT IN2
CONTROL
I2CCOMPATIBLE
Pin Configurations and Functional Diagrams appear at end of data sheet.
MAX9760
________________________________________________________________ Maxim Integrated Products
1
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................................+6V SVDD to GND .........................................................................+6V SVDD to VDD .........................................................................-0.3V PVDD to VDD .......................................................................0.3V PGND to GND.....................................................................0.3V All Other Pins to GND.................................-0.3V to (VDD + 0.3V) Continuous Input Current (into any pin except power-supply and output pins) ...............................................................20mA Continuous Power Dissipation 28-Pin Thin QFN (derate 20.8mW/C above +70C) ....1667mW 28-Pin TSSOP-EP (derate 23.8mW/C above +70C) ..1905mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = PVDD = 5.0V, GND = PGND = 0V, SHDN = 5V, CBIAS = 1F, RIN = RF = 15k, RL = . TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Supply Voltage Range Quiescent Supply Current (IVDD + IPVDD) Shutdown Current Switching Time Turn-On Time Thermal Shutdown Threshold Thermal Shutdown Hysteresis OUTPUT AMPLIFIERS (SPEAKER MODE, HPS = GND) Output Offset Voltage VOS OUT_+ - OUT_-, AV = 1V/V VDD = 4.5V to 5.5V Power-Supply Rejection Ratio PSRR (Note 2) f = 1kHz, VRIPPLE = 200mVP-P f = 20kHz, VRIPPLE = 200mVP-P Output Power Total Harmonic Distortion Plus Noise Signal-to-Noise Ratio Slew Rate Maximum Capacitive Load Drive Crosstalk POUT fIN = 1kHz, THD+N < 1%, TA = +25C fIN = 1kHz, BW = 22Hz to 22kHz RL = 8 RL = 4 RL = 3 POUT = 1W, RL = 8 POUT = 2W, RL = 4 1 75 4 100 82 70 1.4 2.6 3 0.005 0.01 95 1.6 No sustained oscillations fIN = 10kHz 1 73 % dB V/s nF dB W dB 32 mV SYMBOL VDD/PVDD IDD I SHDN tSW tON BTL mode, HPS = 0V SHDN = GND Gain or input switching CBIAS = 1F CBIAS = 0.1F CONDITIONS Inferred from PSRR test MAX9760/MAX9761 MAX9762/MAX9763 MIN 4.5 13 7 7 10 10 300 30 160 15 TYP MAX 5.5 32 18 18 50 A s ms
o o
UNITS V mA
Single-ended mode, HPS = VDD
C C
THD+N SNR SR CL
RL = 8, POUT = 1W, BW = 22Hz to 22kHz
2
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
ELECTRICAL CHARACTERISTICS (continued)
(VDD = PVDD = 5.0V, GND = PGND = 0V, SHDN = 5V, CBIAS = 1F, RIN = RF = 15k, RL = . TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS VDD = 4.5V to 5.5V Power-Supply Rejection Ratio PSRR (Note 2) f = 1kHz, VRIPPLE = 200mVP-P f = 20kHz, VRIPPLE = 200mVP-P Output Power POUT fIN = 1kHz, THD+N < RL = 32 1%, TA = +25C RL = 16 fIN = 1kHz, BW = 22Hz to 22kHz POUT = 60mW, RL = 32 POUT = 125mW, RL = 16 120 MIN 75 TYP 106 88 76 88 200 0.002 % 0.002 92 1.8 No sustained oscillations fIN = 10kHz VBIAS = 1.25V, VDD = 0V VBIAS = 2.5V, VDD = 5V 2.35 2.5 50 2 0.8 1 0.9 x VDD 0.7 x VDD 1 2 78 425 750 15 2.65 dB V/s nF dB mW dB MAX UNITS
MAX9760-MAX9763
OUTPUT AMPLIFIERS (HEADPHONE MODE, HPS = VDD)
Total Harmonic Distortion Plus Noise
THD+N
Signal-to-Noise Ratio Slew Rate Maximum Capacitive Load Drive Crosstalk STANDBY SUPPLY (SVDD) (Note 3) SVDD Current BIAS VOLTAGE (BIAS) BIAS Voltage Output Resistance Input Voltage High Input Voltage Low Input Leakage Current HEADPHONE SENSE INPUT (HPS) Input Voltage High Input Voltage Low Input Leakage Current
SNR SR CL
RL = 32, BW = 22Hz to 22kHz, VOUT = 1VRMS
ISVDD
A
VBIAS RBIAS VIH VIL IIN
V k V V A
1 DIGITAL INPUTS (MUTE, SHDN, HPS_EN, GAINA/B, IN1/2)
VIH VIL IIN
V V A
_______________________________________________________________________________________
3
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
ELECTRICAL CHARACTERISTICS (continued)
(VDD = PVDD = 5.0V, GND = PGND = 0V, SHDN = 5V, CBIAS = 1F, RIN = RF = 15k, RL = . TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Input Voltage High Input Voltage Low Input Hysteresis Input High Leakage Current Input Low Leakage Current Input Capacitance Output Voltage Low Output Current High Serial Clock Frequency Bus Free Time Between STOP and START Conditions START Condition Hold Time START Condition Setup Time Clock Period Low Clock Period High Data Setup Time Data Hold Time Receive SCL/SDA Rise Time Receive SCL/SDA Fall Time Transmit SDA Fall Time Pulse Width of Suppressed Spike IIH IIL CIN VOL IOH fSCL tBUF tHD:STA tSU:STA tLOW tHIGH tSU:DAT tHD:DAT tr tf tf tSP (Note 4) (Note 5) (Note 5) (Note 5) (Note 6) 1.3 0.6 0.6 1.3 0.6 100 0 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 50 0.9 300 300 250 IOL = 3mA VOH = 5V VIN = 5V VIN = 0V 10 0.4 1 400 SYMBOL VIH VIL 0.2 1 1 CONDITIONS MIN 2.6 0.8 TYP MAX UNITS V V V A A pF V A kHz s s s s s ns s ns ns ns ns 2-WIRE SERIAL INTERFACE (SCL, SDA, ADD, INT) (MAX9760/MAX9762)
TIMING CHARACTERISTICS (MAX9760/MAX9762)
Note 1: Note 2: Note 3: Note 4:
All devices are 100% production tested at +25C. All temperature limits are guaranteed by design. PSRR is specified with the amplifier inputs connected to GND through RIN and CIN. Refer to the SVDD section. A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL's falling edge. Note 5: CB = total capacitance of one of the bus lines in picofarads. Device tested with CB = 400pF. 1k pullup resistors connected from SDA/SCL to VDD. Note 6: Input filters on SDA, SCL, and ADD suppress noise spikes of less than 50ns.
4
_______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
Typical Operating Characteristics
(VDD = PVDD = 5V, TA = +25C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE)
MAX9760 toc01
MAX9760-MAX9763
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE)
MAX9760 toc02
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE)
RL = 4 AV = 2V/V
MAX9760 toc03
1 RL = 3 AV = 2V/V 0.1 THD+N (%)
1 RL = 3 AV = 4V/V
1
0.1 THD+N (%) POUT = 500mW POUT = 1W POUT = 500mW POUT = 1W THD+N (%)
0.1 POUT = 250mW P OUT = 500mW 0.01 POUT = 2W POUT = 2.5W POUT = 1W 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 10 100 1k FREQUENCY (Hz) 10k 100k POUT = 2W
0.01 POUT = 2W POUT = 2.5W
0.01
0.001 10 100 1k FREQUENCY (Hz) 10k 100k
0.001
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE)
MAX9760 toc04
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE)
MAX9760 toc05
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE)
RL = 8 AV = 4V/V
MAX9760 toc06
1 RL = 4 AV = 4V/V
1 RL = 8 AV = 2V/V
1
0.1 THD+N (%) THD+N (%) POUT = 250mW POUT = 500mW
0.1 THD+N (%)
0.1 POUT = 250mW 0.01 POUT = 1.2W POUT = 500mW
POUT = 250mW P OUT = 500mW 0.01
0.01 POUT = 1W 0.001 10 100 1k FREQUENCY (Hz) 10k 100k POUT = 2W
POUT = 1W POUT = 1.2W 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 10
POUT = 1W 100
1k FREQUENCY (Hz)
10k
100k
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE)
MAX9760 toc07
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE)
MAX9760 toc08
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE)
AV = 2V/V RL = 4 10
MAX9760 toc09
100 AV = 2V/V RL = 3 10
100 AV = 4V/V RL = 3 10
100
THD+N (%)
THD+N (%)
1 f = 10kHz f = 20Hz
1 f = 1kHz 0.1
THD+N (%)
f = 10kHz
1
0.1
0.1
f = 1kHz
f = 10kHz
0.01
f = 1kHz
0.01 f = 20Hz 0.001
0.01 f = 20Hz 0.001 0 1 2 OUTPUT POWER (W) 3 4 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT POWER (W)
0.001 0 1 2 OUTPUT POWER (W) 3 4
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, TA = +25C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE)
MAX9760 toc10
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE)
MAX9760 toc11
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE)
AV = 4V/V RL = 8 10
MAX9760 toc12
100 AV = 4V/V RL = 4 10 f = 10kHz f = 1kHz 0.1
100 AV = 2V/V RL = 8 10
100
THD+N (%)
THD+N (%)
1
1 f = 10kHz 0.1 f = 1kHz
THD+N (%)
1 f = 10kHz f = 1kHz
0.1
0.01 f = 20Hz 0.001 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT POWER (W)
0.01 f = 20Hz 0.001 0 0.5 1.0 OUTPUT POWER (W) 1.5 2.0
0.01 f = 20Hz 0.001 0 0.5 1.0 OUTPUT POWER (W) 1.5 2.0
OUTPUT POWER vs. TEMPERATURE (SPEAKER MODE)
MAX9760 toc13
OUTPUT POWER vs. TEMPERATURE (SPEAKER MODE)
MAX9760 toc14
OUTPUT POWER vs. TEMPERATURE (SPEAKER MODE)
THD+N = 10%
MAX9760 toc15
4 THD+N = 10% 3 THD+N = 1% 2
4
2.0
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
3
THD+N = 10%
1.5 THD+N = 1% 1.0
2
THD+N = 1%
1 f = 1kHz RL = 3 0 -40 -15 10 35 60 85 TEMPERATURE (C)
1 f = 1kHz RL = 4 0 -40 -15 10 35 60 85 TEMPERATURE (C)
0.5 f = 1kHz RL = 8 0 -40 -15 10 35 60 85 TEMPERATURE (C)
OUTPUT POWER vs. LOAD RESISTANCE (SPEAKER MODE)
MAX9760 toc16
POWER DISSIPATION vs. OUTPUT POWER (SPEAKER MODE)
1.4 POWER DISSIPATION (W) 1.2 1.0 0.8 0.6 0.4 0.2 RL = 4 f = 1kHz 0 0.5 1.0 1.5 2.0 2.5
MAX9760 toc17
5 f = 1kHz 4 OUTPUT POWER (W) THD+N = 10%
1.6
3 THD+N = 1% 2
1
0 1 10 100 1k 10k 100k LOAD RESISTANCE ()
0 OUTPUT POWER (W)
6
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, TA = +25C, unless otherwise noted.)
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (SPEAKER MODE)
MAX9760 toc18
MAX9760-MAX9763
CROSSTALK vs. FREQUENCY (SPEAKER MODE)
-50 -60 CROSSTALK (dB) VIN = 200mVP-P RL = 8
MAX9760 toc19
40 VRIPPLE = 200mVP-P 50 60 PSRR (dB) 70 80 90 100 10 100 1k FREQUENCY (Hz) 10k
-40
-70 -80 -90 -100 LEFT TO RIGHT -110 -120 RIGHT TO LEFT
100k
10
100
1k FREQUENCY (Hz)
10k
100k
ENTERING SHUTDOWN (SPEAKER MODE)
MAX9760 toc20
EXITING SHUTDOWN (SPEAKER MODE)
MAX9760 toc21
SHDN
2V/div
SHDN
2V/div
OUT_+ AND OUT_-
1V/div
OUT_+ AND OUT_-
1V/div
OUT_+ - OUT_100ms/div RL = 8 INPUT AC-COUPLED TO GND
200mV/div
OUT_+ - OUT_100ms/div RL = 8 INPUT AC-COUPLED TO GND
200mV/div
ENTERING POWER-DOWN (SPEAKER MODE)
MAX9760 toc22
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE)
RL = 16 AV = 1V/V 2V/div THD+N (%) 0.1
MAX9760 toc23
1
VDD
OUT_+ AND OUT_-
0.01
POUT = 25mW
POUT = 50mW
1V/div
0.001 OUT_+ - OUT_100ms/div 200mV/div 0.0001 RL = 8 INPUT AC-COUPLED TO GND 10
POUT = 100mW
POUT = 150mW
100
1k FREQUENCY (Hz)
10k
100k
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7
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, TA = +25C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE)
MAX9760 toc24
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE)
MAX9760 toc25
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE)
RL = 32 AV = 2V/V 0.1
MAX9760 toc26
1 RL = 16 AV = 2V/V
1 RL = 32 AV = 1V/V 0.1
1
0.1 POUT = 25mW 0.01
THD+N (%)
THD+N (%)
0.01
POUT = 25mW
POUT = 50mW
THD+N (%)
POUT = 50mW
POUT = 25mW 0.01
POUT = 50mW
0.001
POUT = 100mW
POUT = 150mW
0.001 POUT = 100mW POUT = 150mW
0.001
POUT = 150mW POUT = 100mW
0.0001 10 100 1k FREQUENCY (Hz) 10k 100k
0.0001 10 100 1k FREQUENCY (Hz) 10k 100k
0.0001 10 100 1k FREQUENCY (Hz) 10k 100k
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (HEADPHONE MODE)
MAX9760 toc27
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (HEADPHONE MODE)
MAX9760 toc28
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (HEADPHONE MODE)
AV = 1V/V RL = 32
MAX9760 toc29
100 10 1 THD+N (%) AV = 1V/V RL = 16
100 10 1 THD+N (%) AV = 2V/V RL = 16
100 10 1
f = 20Hz 0.1 0.01 0.001 f = 1kHz
f = 10kHz 0.1 0.01 0.001 f = 1kHz f = 20Hz
f = 10kHz
THD+N (%)
0.1 f = 20Hz 0.01 0.001 f = 1kHz
f = 10kHz
0.0001 0 50 100 150 200 250 300 OUTPUT POWER (mW)
0.0001 0 50 100 150 200 250 300 OUTPUT POWER (mW)
0.0001 0 25 50 75 100 125 OUTPUT POWER (mW)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (HEADPHONE MODE)
MAX9760 toc30
OUTPUT POWER vs. TEMPERATURE (HEADPHONE MODE)
THD+N = 10%
MAX9760 toc31
OUTPUT POWER vs. TEMPERATURE (HEADPHONE MODE)
MAX9760 toc332
100 10 1 THD+N (%) 0.1 0.01 0.001 0.0001 0 25 50 75 100 AV = 2V/V RL = 32 f = 1kHz f = 10kHz
300 250 OUTPUT POWER (mW) 200 150 100 50 0
150 125 OUTPUT POWER (mW) 100 THD+N = 1% 75 50 25 0 THD+N = 10%
THD+N = 1%
f = 20Hz
f = 1kHz RL = 16 -40 -15 10 35 60 85
f = 1kHz RL = 32 -40 -15 10 35 60 85
125
OUTPUT POWER (mW)
TEMPERATURE (C)
TEMPERATURE (C)
8
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, TA = +25C, unless otherwise noted.)
OUTPUT POWER vs. LOAD RESISTANCE (HEADPHONE MODE)
MAX9760 toc33
MAX9760-MAX9763
POWER DISSIPATION vs. OUTPUT POWER (HEADPHONE MODE)
MAX9760 toc34
POWER DISSIPATION vs. OUTPUT POWER (HEADPHONE MODE)
MAX9760 toc35
600 f = 1kHz 500 OUTPUT POWER (mW) 400 300 200 100 0 1 10 100 1k THD+N = 1% THD+N = 10%
120 100 POWER DISSIPATION (mW) 80 60 40 20 0
70 60 POWER DISSIPATION (mW) 50 40 30 20 10 0 RL = 32 f = 1kHz 0 20 40 60 80
RL = 16 f = 1kHz 0 50 100 150 200
10k
100
LOAD RESISTANCE ()
OUTPUT POWER (mW)
OUTPUT POWER (mW)
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (HEADPHONE MODE)
MAX9760 toc36
CROSSTALK vs. FREQUENCY (HEADPHONE MODE)
-50 -60 VIN = 200mVP-P RL = 16
MAX9760 toc37
EXITING SHUTDOWN (HEADPHONE MODE)
MAX9760 toc38
40 VRIPPLE = 200mVP-P 50 60 PSRR (dB) 70 80 90 100 10 100 1k FREQUENCY (Hz) 10k
-40
SHDN
2V/div
CROSSTALK (dB)
-70 -80 -90 -100 -110 -120 10 LEFT TO RIGHT 100 1k FREQUENCY (Hz) 10k 100k HP JACK 200mV/div RIGHT TO LEFT 1V/div OUT_+
100k
100ms/div RL = 16 INPUT AC-COUPLED TO GND
ENTERING SHUTDOWN (HEADPHONE MODE)
MAX9760 toc39
EXITING POWER-DOWN (HEADPHONE MODE)
MAX9760 toc40
2V/div SHDN 2V/div VDD 1V/div
OUT_+ 1V/div 200mV/div
OUT_+
HP JACK 100ms/div RL = 16 INPUT AC-COUPLED TO GND
HP JACK 100ms/div RL = 16 INPUT AC-COUPLED TO GND
200mV/div
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9
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, TA = +25C, unless otherwise noted.)
ENTERING POWER-DOWN (HEADPHONE MODE)
MAX9760 toc41
SUPPLY CURRENT vs. SUPPLY VOLTAGE (SPEAKER MODE)
TA = +85C SUPPLY CURRENT (mA)
MAX9760 toc42
25
VDD
2V/div
20
15
TA = +25C
OUT_+
1V/div
10 TA = -40C 5
HP JACK
200mV/div 0 RL = 16 INPUT AC-COUPLED TO GND 100ms/div 4.50 4.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (HEADPHONE MODE)
MAX9760 toc43
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX97960 toc44
12 10 SUPPLY CURRENT (mA) TA = +85C 8 6 TA = +25C 4 TA = -40C 2 0 4.50 4.75 5.00 5.25
20 TA = +85C SUPPLY CURRENT (A) 15 TA = +25C
10
5
TA = -40C
0 5.50 4.50 4.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
POWER DISSIPATION vs. OUTPUT POWER (SPEAKER MODE)
0.7 POWER DISSIPATION (W) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.25 0.50 0.75 1.00 1.25 1.50 OUTPUT POWER (W) RL = 8 f = 1kHz OUT_+ - OUT_OUT_+ AND OUT_MAX9760 toc45
EXITING POWER-DOWN (SPEAKER MODE)
MAX9760 toc46
0.8
VDD
2V/div
1V/div
200mV/div
100ms/div RL = 8 INPUT AC-COUPLED TO GND
10
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
Pin Description
PIN MAX9760 QFN 1 2 3 TSSOP 26 27 28 MAX9761 QFN -- -- 3 TSSOP -- -- 28 MAX9762 QFN 1 2 3 TSSOP 26 27 28 MAX9763 QFN -- -- 3 TSSOP -- -- 28 SDA INT VDD Bidirectional Serial Data I/O C Interrupt Output Power Supply Standby Power Supply. Connect to a standby power supply that is always on, or connect to VDD through a Schottky diode and bypass with 220F capacitor to GND. Short to VDD if clickless operation is not essential. Left-Channel Input 1 Left-Channel Input 2 Left-Channel Gain Set A Left-Channel Gain Set B Power Ground Left-Channel Bridged Amplifier Positive Output. OUTL+ also serves as the left-channel headphone amplifier output. Output Amplifier Power Supply Left-Channel Bridged Amplifier Negative Output Active-Low Shutdown. Connect SHDN to VDD for normal operation. Address Select. A logic high sets the address LSB to 1, a logic low sets the address LSB to zero. Headphone Sense Input. A logic high configures the device as a single-ended headphone amp. A logic low configures the device as a BTL speaker amp. DC Bias Bypass. See BIAS Capacitor Selection section for capacitor selection. Connect CBIAS from BIAS to GND. Ground NAME FUNCTION
MAX9760-MAX9763
4
1
4
1
4
1
4
1
SVDD
5 6 7 8 9, 13, 23, 27
2 3 4 5 6, 10, 20, 24
5 6 7 8 9, 13, 23, 27
2 3 4 5 6, 10, 20, 24
5 6 7 8 9, 23, 27
2 3 4 5 6, 20, 24
5 6 7 8 9, 23, 27
2 3 4 5 6, 20, 24
INL1 INL2 GAINLA GAINLB PGND
10
7
10
7
10
7
10
7
OUTL+
11, 25 12 14
8, 22 9 11
11, 25 12 14
8, 22 9 11
11, 25 -- 14
8, 22 -- 11
11, 25 -- 14
8, 22 -- 11
PVDD OUTLSHDN
15
12
--
--
15
12
--
--
ADD
16
13
16
13
16
13
16
13
HPS
17
14
17
14
17
14
17
14
BIAS
18
15
18
15
13
10
13
10
GND
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11
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
Pin Description (continued)
PIN MAX9760 QFN 19 20 21 22 TSSOP 16 17 18 19 MAX9761 QFN 19 20 21 22 TSSOP 16 17 18 19 MAX9762 QFN 19 20 21 22 TSSOP 16 17 18 19 MAX9763 QFN 19 20 21 22 TSSOP 16 17 18 19 INR1 INR2 GAINRA GAINRB Right-Channel Input 1 Right-Channel Input 2 Right-Channel Gain Set A Right-Channel Gain Set B Right-Channel Bridged Amplifier Positive Output. OUTR+ also serves as the right-channel headphone amplifier output. Right-Channel Bridged Amplifier Negative Output Serial Clock Line No Connection. Not internally connected. Mono Gain Set Active-High Mute Input Headphone Enable. A logic high enables HPS. A logic low disables HPS and the device is always configured as a BTL speaker amp. Gain Select. A logic low selects the gain set by GAIN_A. A logic high selects the gain set by GAIN_B. Input Select. A logic low selects amplifier input 1. A logic high selects amplifier input 2. NAME FUNCTION
24
21
24
21
24
21
24
21
OUTR+
26 28 -- -- --
23 25 -- -- --
26 -- -- -- 1
23 -- -- -- 26
26 28 12 18 --
23 25 9 15 --
26 -- 12 18 1
23 -- 9 15 26
OUTRSCL N.C. GAINM MUTE
--
--
2
27
--
--
2
27
HPS_EN
--
--
15
12
--
--
15
12
GAINA/B
--
--
28
25
--
--
28
25
IN1/2
Detailed Description
The MAX9760-MAX9763 feature 3W BTL speaker amplifiers, 200mW headphone amplifiers, input multiplexers, headphone sensing, and comprehensive clickand-pop suppression. The MAX9760/ MAX9761 are stereo BTL/headphone amplifiers. The MAX9762/ MAX9763 are mono BTL/stereo headphone amplifiers. The MAX9760/MAX9762 are controlled through an I2Ccompatible, 2-wire serial interface. The MAX9761/ MAX9763 are controlled through five logic inputs: MUTE, SHDN, HPS_EN, GAINA/B, and IN1/2 (see Selector Guide). The MAX9760-MAX9763 feature exceptional PSRR (100dB at 1kHz), allowing these
devices to operate from noisy digital supplies without the need for a linear regulator. The speaker amplifiers use a BTL configuration. The signal path is composed of an input amplifier and an output amplifier. Resistor RIN sets the input amplifier's gain, and resistor RF sets the output amplifier's gain. The output of these two amplifiers serves as the input to a slave amplifier configured as an inverting unity-gain follower. This results in two outputs, identical in magnitude, but 180 out of phase. The overall gain of the speaker amplifiers is twice the product of the two amplifier gains (see Gain-Setting Resistor section). A feature of this architecture is that there is no phase inversion from input to output.
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
Input Multiplexer
MAX9760 IN_1 AUDIO INPUT 30k IN_2
MAX9760-MAX9763
15k
Each amplifier features a 2:1 input multiplexer, allowing input selection between two stereo sources. Both multiplexers are controlled by bit 1 in the control register (MAX9760/MAX9762) or by the IN1/2 pin (MAX9761/ MAX9763). A logic low selects input IN_1 and a logic high selects input IN_2. The input multiplexer can also be used to further expand the number of gain options available from the MAX9760-MAX9763 family. Connecting the audio source to the device through two different input resistors (Figure 1) increases the number of gain options from two to four (MAX9760/MAX9761) and from three to six (MAX9762/MAX9763). Additionally, the input multiplexer allows a speaker equalization network to be switched into the speaker signal path. This is typically useful in optimizing acoustic response from speakers with small physical dimensions.
Figure 1. Using the Input Multiplexer for Gain Setting When configured as a headphone (single-ended) amplifier, the slave amplifier is disabled, muting the speaker and the main amplifier drives the headphone. The MAX9760-MAX9763 can deliver 3W of continuous average power into a 3 load with less than 1% THD+N in speaker mode, and 200mW of continuous average power into a 16 load with less than 1% THD+N in headphone mode. These devices also feature thermal overload protection.
Headphone Sense Enable
The HPS pin is enabled by HPS_EN (MAX9762/ MAX9763) or the HPSD bit (MAX9760/MAX9761). HPSD or HPS_EN determines whether the device is in automatic detection mode or fixed mode operation (see Tables 1a and 1b).
Mono Mode
The MAX9762/MAX9763 are 3W mono speaker amplifiers, 200mW stereo headphone amplifiers, and a mixer/attenuator (see the MAX9762/MAX9763 Functional Diagram). In speaker (mono) mode, the mixer/attenuator combines the two stereo inputs (INL_ and INR_) and attenuates the resultant signal by a factor of 2. This allows for full reproduction of a stereo signal through a single speaker, while maintaining optimum headroom. The resistor connected between GAINM and OUTR+, sets the gain of the devices in speaker mode (see the MAX9762 Functional Diagram). This allows the speaker amplifier to have a different gain and feedback network from the headphone amplifier.
Headphone Sense Input (HPS)
A voltage on HPS less than 0.7 VDD sets the device to speaker mode. A voltage greater than 0.9 VDD disables the inverting bridge amplifier (OUT_-), which mutes the speaker amplifier and sets the device into headphone mode. For automatic headphone detection, connect HPS to the control pin of a 3-wire headphone jack as shown in Figure 2. With no headphone present, the resistive voltage-divider created by R1 and R2 sets the voltage on HPS to be less than 0.7 VDD, setting the device to speaker mode and the gain setting defaults to GAINA (MAX9760/MAX9762). When a headphone plug is inserted into the jack, the control pin is disconnected from the tip contact, and HPS is pulled to VDD through R1, setting the device into headphone mode and the gain-setting defaults to GAINB (MAX9760/MAX9762) (see Gain Select section). Place a resistor in series with the control pin and HPS (R3) to prevent any audio signal from coupling into HPS when the device is in speaker mode.
BIAS
These devices operate from a single 5V supply, and feature an internally generated, power-supply independent, common-mode bias voltage of 2.5V referenced to GND. BIAS provides both click-and-pop suppression and sets the DC bias level for the audio outputs. BIAS is internally connected to the noninverting input of each speaker amplifier (see Typical Application Circuit/ Functional Diagram). Choose the value of the bypass capacitor as described in the BIAS Capacitor section. No external load should be applied to BIAS. Any load lowers the BIAS voltage, affecting the overall performance of the device.
Shutdown
The MAX9760-MAX9763 feature a 10A, low-power shutdown mode that reduces quiescent current consumption and extends battery life. The drive amplifiers and bias circuitry are disabled, the amplifier outputs (OUT_) go high impedance, and BIAS is driven to
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
GND. Driving SHDN low places the devices into shutdown mode, disables the interface, and resets the I2C registers to a default state. A logic high on SHDN enables the devices. MAX9760/MAX9762 Software Shutdown A logic high on bit 0 of the SHDN register places the MAX9760/MAX9762 in shutdown mode. A logic low enables the device. The digital section of the MAX9760/MAX9762 remains active when the device is shut down through the interface. All devices feature a logic low on the SHDN input.
VDD R1 680k
MAX9760- MAX9763 HPS OUTL+ OUTR+
R3 47k
R2 10k
MUTE
All devices feature a mute mode. When the device is muted, the input is disconnected from the amplifiers. MUTE does not shut down the device. MAX9760/MAX9762 MUTE The MAX9760/MAX9762 MUTE mode is selected by writing to the MUTE register (see the Command Byte Definitions section). The left and right channels can be independently muted. MAX9761/MAX9763 MUTE The MAX9761/MAX9763 feature an active-high MUTE input that mutes both channels.
Figure 2. HPS Configuration Circuit
Table 1a. HPS Setting (MAX9760/MAX9761)
INPUTS HPSD 0 0 1 1 HPS 0 1 X X SPKR/HP X X 0 1 MODE MAX9760 GAIN PATH* A B A or B A or B MAX9762 GAIN PATH* M B M A or B
BTL SE BTL SE
Click-and-Pop Suppression
The MAX9760-MAX9763 feature Maxim's patented comprehensive click-and-pop suppression. During startup and shutdown, the common-mode bias voltage of the amplifiers is slowly ramped to and from the DC bias point using an S-shaped waveform. In headphone mode, this waveform shapes the frequency spectrum, minimizing the amount of audible components present at the headphone. In speaker mode, the BTL amplifiers start up in the same fashion as in headphone mode. When entering shutdown, both amplifier outputs ramp to GND quickly and simultaneously. The MAX9760- MAX9763 can also be connected to a standby power source that ensures that the device undergoes its full shutdown cycle even after power has been removed. Standby Power Supply (SVDD) The MAX9760-MAX9763 feature a patented system that provides clickless power-down when power is inadvertently removed from the device. SV DD is an optional secondary supply that powers the device through its shutdown cycle when V DD is removed. During this cycle, the amplifier output DC level slowly ramps to GND, ensuring clickless power-down. If clickless power-down is required, connect SVDD to either a secondary power supply that is always on, or connect a reservoir capacitor from SVDD to GND. SVDD does not
14
*Note: A - GAINA path selected B - GAINB path selected M - GAINM path selected A or B - Gain path selected by GAINAB control bit in register 02h
Table 1b. HPS Setting (MAX9762/MAX9763)
INPUTS HPSEN 0 1 1 HPS X 0 1 BTL BTL SE A or B A or B A or B M M A or B MODE MAX9761 GAIN PATH* MAX9763 GAIN PATH*
*Note: A or B - Gain path selected by external GAINAB M - GAINM path selected
need to be connected to either a secondary power supply or reservoir capacitor for normal device operation. If click-and-pop suppression during power-down is not required, connect SVDD to VDD directly.
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tHD, STA tBUF tHD, STA tSP tSU, STO
Figure 3. 2-Wire Serial Interface Timing Diagram
The clickless power-down cycle only occurs when the device is in headphone mode. The speaker mode is inherently clickless, the differential architecture cancels the DC shift across the speaker. The MAX9760- MAX9763 BTL outputs are pulled to GND quickly and simultaneously, resulting in no audible components. If the MAX9760-MAX9763 are only used as speaker amplifiers, then reservoir capacitors or secondary supplies are not necessary. When using a reservoir capacitor, a 220F capacitor provides optimum charge storage for the shutdown cycle for all conditions. If a smaller reservoir capacitor is desired, decrease the size of CBIAS. A smaller CBIAS causes the output DC level to decay at a faster rate, increasing the audible content at the speaker, but reducing the duration of the shutdown cycle.
S
Sr
P
SCL
SDA
Figure 4. START/STOP Conditions
Digital Interface
The MAX9760/MAX9762 feature an I2C/SMBus-compatible 2-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX9760/MAX9762 and the master at clock rates up to 400kHz. Figure 3 shows the 2-wire interface timing diagram. The MAX9760/MAX9762 are transmit/receive slave-only devices, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the MAX9760/ MAX9762 by transmitting the proper address followed by a command and/or data words. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse.
The MAX9760/MAX9762 SDA and SCL amplifiers are open-drain outputs requiring a pullup resistor (500 or greater) to generate a logic high voltage. Series resistors in line with SDA and SCL are optional. These series resistors protect the input stages of the devices from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals (see START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. START and STOP Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-tolow transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 4). A START condition from the master signals the beginning of a transmission to the MAX9760/
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
SCL
SDA
STOP
START
LEGAL STOP CONDITION
SCL
Acknowledge Bit (ACK) The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data word. The receiving device always generates ACK. The MAX9760/MAX9762 generate an ACK when receiving an address or data by pulling SDA low during the night clock period. When transmitting data, the MAX9760/MAX9762 wait for the receiving device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. Slave Address The bus master initiates communication with a slave device by issuing a START condition followed by a 7-bit slave address (Figure 6). When idle, the MAX9760/ MAX9762 wait for a START condition followed by its slave address. The LSB of the address word is the Read/Write (R/W) bit. R/W indicates whether the master is writing to or reading from the MAX9760/MAX9762 (R/W = 0 selects the write condition, R/W = 1 selects the read condition). After receiving the proper address, the MAX9760/MAX9762 issue an ACK by pulling SDA low for one clock cycle.
A1 A0 R/W
SDA
START
ILLEGAL STOP
ILLEGAL EARLY STOP CONDITION
Figure 5. Early STOP Condition
S
A6
A5
A4
A3
A2
Figure 6. Slave Address Byte Definition
MAX9762. The master terminates transmission by issuing the STOP condition, this frees the bus. If a REPEATED START condition is generated instead of a STOP condition, the bus remains active. Early STOP Conditions The MAX9760/MAX9762 recognize a STOP condition at any point during the transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 5). This condition is not a legal I2C format, at least one clock pulse must separate any START and STOP conditions. REPEATED START Conditions A REPEATED START (S r ) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation. S r may also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX9760/ MAX9762 serial interface supports continuous write operations with or without an Sr condition separating them. Continuous read operations require Sr conditions because of the change in direction of data flow.
16
The MAX9760/MAX9762 have a factory-/user-programmed address. Address bits A6-A2 are preset, while A0 and A1 is set by ADD. Connect ADD to either VDD, GND, SCL, or SDA to change the last 2 bits of the slave address (Table 2). Write Data Format There are three registers that configure the MAX9760/MAX9762: the MUTE register, SHDN register, and control register. In write data mode (R/W = 0), the register address and data byte follow the device address (Figure 7). MUTE Register The MUTE register (01hex) is a read/write register that sets the MUTE status of the device. Bit 3 (MUTEL) of the MUTE register controls the left channel, bit 4 (MUTER) controls the right channel. A logic high mutes the respective channel, a logic low brings the channel out of mute. SHDN Register The SHDN register (02hex) is a read/write register that controls the power-up state of the device. A logic high in bit 0 of the SHDN register shuts down the device; a logic low turns on the device. A logic high is required in bits 2 to 7 to reset all registers to their default settings.
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
S ADDRESS 7 BITS I2C SLAVE ADDRESS. SELECTS DEVICE. WR ACK COMMAND 8 BITS REGISTER ADDRESS. SELECTS REGISTER TO BE WRITTEN TO. ACK DATA 8 BITS REGISTER DATA ACK P 1
S
ADDRESS 7 BITS
WR
ACK
COMMAND 8 BITS
ACK
S
ADDRESS 7 BITS
WR
ACK
DATA 8 BITS
P 1
I2C SLAVE ADDRESS. SELECTS DEVICE.
REGISTER ADDRESS. SELECTS REGISTER TO BE READ.
I2C SLAVE ADDRESS. SELECTS DEVICE.
DATA FROM SELECTED REGISTER
Figure 7. Write/Read Data Format Example
Table 2. I2C Slave Addresses
ADD CONNECTION GND VDD SDA SCL I C ADDRESS 100 1000 100 1001 100 1010 100 1011
2
Table 4. SHDN Register Format
REGISTER ADDRESS BIT 7 6 5 4 3 2 1 0 NAME RESET RESET RESET RESET RESET RESET X SHDN VALUE 0* 1 0* 1 0* 1 0* 1 0* 1 0* 1 Don't Care 0* 1 0000 0010 DESCRIPTION -- Reset device -- Reset device -- Reset device -- Reset device -- Reset device -- Reset device -- Normal operation Shutdown
Table 3. MUTE Register Format
REGISTER ADDRESS BIT 7 6 5 4 3 2 1 0 NAME X X X MUTER MUTEL X X X VALUE Don't Care Don't Care Don't Care 0* 1 0* 1 Don't Care Don't Care Don't Care 0000 0001 DESCRIPTION -- -- -- Unmute right channel Mute right channel Unmute left channel Mute left channel -- -- --
*Default state.
*Default state.
Control Register The control register (03hex) is a read/write register that determines the device configuration. Bit 1 (IN1/IN2) controls the input multiplexer, a logic high selects input 1, a logic low selects input 2. Bit 2 (HPS_D) controls the headphone sensing. A logic low configures the device
in automatic headphone detection mode. A logic high disables the HPS input. Bit 3 (GAINA/B) controls the gain-select multiplexer. A logic low selects GAINA. A logic high selects GAINB. GAINA/B is ignored when HPS_D = 0. Bit 4 (SPKR/HP) selects the amplifier operating mode when HPS_D = 1. A logic high selects speaker mode and a logic low selects headphone mode.
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17
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
Table 5. Control Register Format
REGISTER ADDRESS BIT 7 6 5 4 NAME X X X SPKR/HP VALUE Don't Care Don't Care Don't Care 0* 1 0* 1 0* 2 HPS_D 1 0* 1 Don't Care 0000 0011 DESCRIPTION -- -- -- Speaker mode selected Headphone mode selected Gain-setting A selected Gain-setting B selected Automatic headphone detection enabled Automatic headphone detection disabled (HPS ignored). Input 1 selected Input 2 selected --
-1 VOUT(P-P) 2 x VOUT(P-P) +1 VOUT(P-P)
3
GAINA/B
Figure 8. Bridge-Tied Load Configuration
Applications Information
BTL Speaker Amplifiers
The MAX9760-MAX9763 feature speaker amplifiers designed to drive a load differentially, a configuration referred to as bridge-tied load (BTL). The BTL configuration (Figure 8) offers advantages over the singleended configuration, where one side of the load is connected to ground. Driving the load differentially doubles the output voltage compared to a singleended amplifier under similar conditions. Thus, the devices' differential gain is twice the closed-loop gain of the input amplifier. The effective gain is given by: A VD = 2 x RF RIN
1 0
IN1/IN2 X
Read Data Format In read mode (R/W = 1), the MAX9760/MAX9762 write the contents of the selected register to the bus. The direction of the data flow reverses following the address acknowledge by the MAX9760/MAX9761. The master device reads the contents of all registers, including the read-only status register. Table 6 shows the status register format. Interrupt Output (INT) The MAX9760/MAX9762 include an interrupt output (INT) that can indicate to a master device that an event has occurred. INT is triggered when the state of HPS changes. During normal operation, INT idles high. If a headphone is inserted/removed from the jack and that action is detected by HPS, INT pulls the line low. INT remains low until a read data operation is executed. I2C Compatibility The MAX9760/MAX9762 are compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the ninth clock pulse. The communication protocol supports the standard I2C 8-bit communications. The general call address is ignored. The MAX9760/MAX9762 addresses are compatible with the 7-bit I2C addressing protocol only. No 10-bit formats are supported.
Substituting 2 x VOUT(P-P) for VOUT(P-P) into the following equations yields four times the output power due to doubling of the output voltage: VRMS = VOUT(P-P) 22
2 V POUT = RMS RL
Since the differential outputs are biased at midsupply, there is no net DC voltage across the load. This eliminates the need for DC-blocking capacitors required for single-ended amplifiers. These capacitors can be large, expensive, consume board space, and degrade low-frequency performance.
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
Table 6. Status Register Format
REGISTER ADDRESS BIT 7 6 5 4 3 2 1 0 NAME THRM AMPRAMPR+ AMPLAMPL+ HPSTS X X VALUE 0 1 0 1 0 1 0 1 0 1 0 1 Don't Care Don't Care 0000 0000 DESCRIPTION Device temperature below thermal limit Device temperature exceeding thermal limit OUTR- current below current limit OUTR- current exceeding current limit OUTR+ current below current limit OUTR+ current exceeding current limit OUTL- current below current limit OUTL- current exceeding current limit OUTL+ current below current limit OUTL+ current exceeding current limit Device in speaker mode Device in headphone mode -- --
When the MAX9760/MAX9762 are configured to automatically detect the presence of a headphone jack, the device defaults to gain setting A when the device is in speaker mode. When the MAX9762/MAX9763 are configured as speaker amplifiers, the gain setting defaults to the mono setting (GAINM).
where TJ(MAX) is +150C, TA is the ambient temperature, and JA is the reciprocal of the derating factor in C/W as specified in the Absolute Maximum Ratings section. For example, JA of the QFN package is +42C/W. The increase in power delivered by the BTL configuration directly results in an increase in internal power dissipation over the single-ended configuration. The maximum power dissipation for a given VDD and load is given by the following equation: PDISS(MAX) = 2VDD2 2RL
Single-Ended Headphone Amplifier
The MAX9760-MAX9763 can be configured as singleended headphone amplifiers through software or by sensing the presence of a headphone plug (HPS). In headphone mode, the inverting output of the BTL amplifier is disabled, muting the speaker. The gain is 1/2 that of the device in speaker mode, and the output power is reduced by a factor of 4. In headphone mode, the load must be capacitively coupled to the device, blocking the DC bias voltage from the load (see Typical Application Circuit).
Power Dissipation and Heat Sinking
Under normal operating conditions, the MAX9760- MAX9763 can dissipate a significant amount of power. The maximum power dissipation for each package is given in the Absolute Maximum Ratings section under Continuous Power Dissipation or can be calculated by the following equation: PDISSPKG(MAX) = TJ(MAX) - TA JA
If the power dissipation for a given application exceeds the maximum allowed for a given package, either reduce VDD, increase load impedance, decrease the ambient temperature, or add heat sinking to the device. Large output, supply, and ground PC board traces improve the maximum power dissipation in the package. Thermal overload protection limits total power dissipation in these devices. When the junction temperature exceeds +160C, the thermal protection circuitry disables the amplifier output stage. The amplifiers are enabled once the junction temperature cools by 15C. This results in a pulsing output under continuous thermal-overload conditions as the device heats and cools.
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
Component Selection
Gain-Setting Resistors External feedback components set the gain of the MAX9760-MAX9763. Resistor RIN sets the gain of the input amplifier (AVIN) and resistor RF sets the gain of the second stage amplifier (AVOUT): 10k RF A VIN = - , A VOUT = - 10k RIN Combining AVIN and AVOUT, RIN and RF set the singleended gain of the device as follows: RF 10k RF A V = A VIN x A VOUT = - x - 10k = + R IN RIN As shown, the two-stage amplifier architecture results in a noninverting gain configuration, preserving absolute phase through the MAX9760-MAX9763. The gain of the device in BTL mode is twice that of the single-ended mode. Choose RIN between 10k and 15k and RF between 15k and 100k. Input Filter The input capacitor (CIN), in conjunction with RIN, forms a highpass filter that removes the DC bias from an incoming signal. The AC-coupling capacitor allows the amplifier to bias the signal to an optimum DC level. Assuming zero-source impedance, the -3dB point of the highpass filter is given by: f-3dB = 1 2RINCIN Output-Coupling Capacitor The MAX9760/MAX9763 require output-coupling capacitors to operate in single-ended (headphone) mode. The output-coupling capacitor blocks the DC component of the amplifier output, preventing DC current from flowing to the load. The output capacitor and the load impedance form a highpass filter with a -3dB point determined by: f-3dB = 1 2RLCOUT
As with the input capacitor, choose COUT such that f-3dB is well below the lowest frequency of interest. Setting f-3dB too high affects the amplifier`s low-frequency response. Load impedance is a concern when choosing COUT. Load impedance can vary, changing the -3dB point of the output filter. A lower impedance increases the corner frequency, degrading low-frequency response. Select COUT such that the worst-case load/COUT combination yields an adequate response. Select capacitors with low ESR to minimize resistive losses and optimize power transfer to the load. BIAS Capacitor BIAS is the output of the internally generated 2.5VDC bias voltage. The BIAS bypass capacitor, C BIAS , improves PSRR and THD+N by reducing power supply and other noise sources at the common-mode bias node, and also generates the clickless/popless, startup/shutdown DC bias waveforms for the speaker amplifiers. Bypass BIAS with a 1F capacitor to GND. Supply Bypassing Proper power-supply bypassing ensures low-noise, low-distortion performance. Place a 0.1F ceramic capacitor from V DD to GND. Add additional bulk capacitance as required by the application, typically 100F. Bypass PVDD with a 100F capacitor to GND. Locate bypass capacitors as close to the device as possible.
Choose RIN according to the Gain-Setting Resistors section. Choose the CIN such that f-3dB is well below the lowest frequency of interest. Setting f-3dB too high affects the amplifier's low-frequency response. Use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with high-voltage coefficients, such as ceramics, may result in an increased distortion at low frequencies. Other considerations when designing the input filter include the constraints of the overall system, the actual frequency band of interest, and click-andpop suppression.
Gain Select
The MAX9760-MAX9763 feature multiple gain settings on each channel, making available different gain and feedback configurations. The gain-setting resistor (RF) is connected between the amplifier output (OUT_+) and the gain setpoint (GAIN_). An internal multiplexer switches between the different feedback resistors
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
CF RF2 RF1 RIN
GAIN RF1 RIN
RF1 RF2 RIN FREQUENCY 1 2 RF2 CF
VBIAS
Figure 9. Bass Boost Circuit
Figure 10. Bass Boost Response
depending on the status of the gain control input. The stereo MAX9760/MAX9761 feature two gain options per channel. The mono MAX9762/MAX9763 feature two gain options per single-ended channel, and a single gain option for the mono speaker amplifier (see Tables 1a and 1b for the gain-setting options). The MAX9762 defaults to GAINM in speaker mode and can switch between GAINA and GAINB in headphone mode. Bass Boost Circuit Headphones typically have a poor low-frequency response due to speaker and enclosure size limitations. A bass boost circuit compensates the poor low-frequency response (Figure 9). At low frequencies, the capacitor CF is an open circuit, and the effective impedance in the feedback loop (RF(EFF)) is RF(EFF) = RF1. At the frequency: 1 2RF2CF where the impedance, CF, begins to decrease, and at high frequencies, the CF is a short circuit. Here the impedance of the feedback loop is: R x RF2 RF(EFF) = F1 RF1 + RF2
Assuming RF1 = RF2, then RF(EFF) at low frequencies is twice that of RF(EFF) at high frequencies (Figure 10). Thus, the amplifier has more gain at lower frequencies, boosting the system's bass response. Set the gain rolloff frequency based upon the response of the speaker and enclosure.
Layout and Grounding
Good PC board layout is essential for optimizing performance. Use large traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance, as well as route heat away from the device. Good grounding improves audio performance, minimizes crosstalk between channels, and prevents any digital switching noise from coupling into the audio signal. If digital signal lines must cross over or under audio signal lines, ensure that they cross perpendicular to each other. The MAX9760-MAX9763 QFN and TSSOP-EP packages feature exposed thermal pads on their undersides. This pad lowers the package's thermal resistance by providing a direct heat conduction path from the die to the printed circuit board. Connect the pad to signal ground by using a large pad, or multiple vias to the ground plane.
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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
Typical Application Circuit
VDD
0.1F VDD BIAS SVDD 1F GAINLB 15k GAINLA 15k AUX_IN OUT BIAS HPF 0.68F 0.68F 15k INL2 OUTLINL1 OUTL+ PVDD 0.047F 27.4k 33.2k 220F 10k
MAX4060
IN+ IN-
CODEC 0.68F 15k INR1
MAX9760
0.68F HPF VDD
OUTR15k INR2 OUTR+ 15k GAINRA 33.2k 220F VDD 10k 680k
1k
1k
10k SCL SDA
GAINRB 27.4k 0.047F HPS
47k
MICROCONTROLLER
ADD INT SHDN
22
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
Functional Diagrams
VDD
MAX9760-MAX9763
PVDD VDD 10k AUDIO INPUT AUDIO INPUT INL1 INL2 2:1 INPUT MUX
SVDD GAIN SET MUX 10k OUTL+ GAINLB GAINLA
BIAS
10k BIAS 10k OUTL-
10k AUDIO INPUT AUDIO INPUT INR1 INR2 2:1 INPUT MUX
GAIN SET MUX 10k
GAINRB GAINRA
OUTR+
10k SHDN SCL SDA ADD INT 10k LOGIC HPS MAX9760 GND OUTRHPS
______________________________________________________________________________________
23
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
Functional Diagrams (continued)
PVDD VDD 10k INL1 INL2 2:1 INPUT MUX
SVDD GAIN SET MUX 10k OUTL+ GAINLB GAINLA
BIAS
10k BIAS 10k OUTL-
10k INR1 INR2 2:1 INPUT MUX
GAIN SET MUX 10k
GAINRB GAINRA
OUTR+
10k SHDN MUTE HP_EN GAINA/B IN1/IN2 10k OUTRLOGIC HPS MAX9761 HPS
GND
24
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
Functional Diagrams (continued)
MAX9760-MAX9763
PVDD VDD
SVDD 10k GAIN SET MUX 10k
GAINRB GAINRA GAINM
INR1 INR2
2:1 INPUT MUX
MIXER
OUTR+
BIAS
BIAS 10k
10k
OUTR-
10k INL1 INL2 SHDN SCL SDA ADD INT 2:1 INPUT MUX
GAIN SET MUX 10k
GAINLB GAINLA
OUTL
LOGIC
HPS
HPS
MAX9762
GND
______________________________________________________________________________________
25
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
Functional Diagrams (continued)
PVDD VDD
SVDD 10k GAIN SET MUX 10k
GAINRB GAINRA GAINM
INR1 INR2
2:1 INPUT MUX
MIXER
OUTR+
BIAS
10k BIAS 10k OUTR-
10k INL1 INL2 SHDN HP_EN MUTE IN1/IN2 GAINA/B 2:1 INPUT MUX
GAIN SET MUX 10k
GAINLB GAINLA
OUTL
LOGIC
HPS
HPS
MAX9763
GND
26
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
Pin Configurations
MAX9760-MAX9763
GAINRB
OUTR+
OUTR-
PGND
PGND
PGND
PVDD
SCL
28
27
26
25
PVDD
24
23
PGND
IN1/2
TOP VIEW
OUTR-
OUTR+
TOP VIEW
28
27
26
25
24
23
22
22
GAINRB
SDA INT VDD SVDD INL1 INL2 GAINLA
1 2 3 4 5 6 7 10 11 12 13 14 8 9
21 20 19
GAINRA INR2 INR1 GND BIAS HPS ADD
MUTE HPS_EN VDD SVDD INL1 INL2 GAINLA
1 2 3 4 5 6 7 10 11 12 13 14 8 9
21 20 19
GAINRA INR2 INR1 GND BIAS HPS GAINA/B
MAX9760
18 17 16 15
MAX9761
18 17 16 15
GAINLB
OUTL+
OUTL-
PGND
GAINLB
OUTL+
PGND
OUTL-
PGND
SHDN
THIN QFN
THIN QFN
SVDD 1 INL1 2 INL2 3 GAINLA 4 GAINLB 5 PGND 6 OUTL+ 7 PVDD 8 OUTL- 9 PGND 10 SHDN 11 ADD 12 HPS 13 BIAS 14
28 VDD 27 INT 26 SDA 25 SCL 24 PGND
SVDD 1 INL1 2 INL2 3 GAINLA 4 GAINLB 5 PGND 6 OUTL+ 7 PVDD 8 OUTL- 9 PGND 10 SHDN 11 GAIN/AVB 12 HPS 13 BIAS 14
MAX9760
MAX9761
23 OUTR22 PVDD 21 OUTR+ 20 PGND 19 GAINRB 18 GAINRA 17 INR2 16 INR1 15 GND
TSSOP
TSSOP
______________________________________________________________________________________
PGND
28 VDD 27 HPS_EN 26 MUTE 25 IN/1V2 24 PGND 23 OUTR22 PVDD 21 OUTR+ 20 PGND 19 GAINRB 18 GAINRA 17 INR2 16 INR1 15 GND
SHDN
PVDD
PVDD
27
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
Pin Configurations (continued)
GAINRB OUTR+ OUTR+ OUTR-
OUTR-
PGND
PGND
PGND
28
27
26
25
24
23
22
28
27
26
25
PVDD
24
23
PGND
PVDD
IN1/2
SCL
TOP VIEW
TOP VIEW
SDA INT VDD SVDD INL1 INL2 GAINLA
1 2 3 4 5 6 7 10 11 12 13 14 8 9
21 20 19
GAINRA INR2 INR1 GAINM BIAS HPS ADD
22
GAINRB
MUTE HPS_EN VDD SVDD INL1 INL2 GAINLA
1 2 3 4 5 6 7 10 11 12 13 14 8 9
21 20 19
GAINRA INR2 INR1 GAINM BIAS HPS GAINA/B
MAX9762
18 17 16 15
MAX9763
18 17 16 15
GAINLB
OUTL+
PGND
N.C.
SHDN
PVDD
GND
GAINLB
OUTL+
PGND
N.C.
THIN QFN
THIN QFN
SVDD 1 INL1 2 INL2 3 GAINLA 4 GAINLB 5 PGND 6 OUTL+ 7 PVDD 8 N.C. 9 GND 10 SHDN 11 ADD 12 HPS 13 BIAS 14
28 VDD 27 INT 26 SDA 25 SCL 24 PGND
SVDD 1 INL1 2 INL2 3 GAINLA 4 GAINLB 5 PGND 6 OUTL+ 7 PVDD 8 N.C. 9 GND 10 SHDN 11 GAINA/B 12 HPS 13 BIAS 14
28 VDD 27 HPS_EN 26 MUTE 25 IN1/2 24 PGND
MAX9762
23 OUTR22 PVDD 21 OUTR+ 20 PGND 19 GAINRB 18 GAINRA 17 INR2 16 INR1 15 GAINM
MAX9763
23 OUTR22 PVDD 21 OUTR+ 20 PGND 19 GAINRB 18 GAINRA 17 INR2 16 INR1 15 GAINM
TSSOP
TSSOP
28
______________________________________________________________________________________
SHDN
PVDD
GND
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
Ordering Information (continued)
PART MAX9761ETI MAX9761EUI MAX9762ETI MAX9762EUI MAX9763ETI MAX9763EUI TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 28 Thin QFN-EP* 28 TSSOP-EP* 28 Thin QFN-EP* 28 TSSOP-EP* 28 Thin QFN-EP* 28 TSSOP-EP*
Chip Information
MAX9760 TRANSISTOR COUNT: 5256 MAX9761 TRANSISTOR COUNT: 2715 MAX9762 TRANSISTOR COUNT: 5046 MAX9763 TRANSISTOR COUNT: 2505 PROCESS: BiCMOS
MAX9760-MAX9763
*EP = Exposed paddle.
Selector Guide
PART MAX9760 MAX9761 MAX9762 MAX9763
2
CONTROL INTERFACE I2C Compatible Parallel I C Compatible Parallel
SPEAKER AMPLIFIER Stereo Stereo Mono Mono
HEADPHONE AMPLIFIER Stereo Stereo Stereo Stereo
INPUT MUX Yes Yes Yes Yes
______________________________________________________________________________________
29
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux MAX9760-MAX9763
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
L
REV.
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
C L
C L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO.
21-0140
C
1 2
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
2 2
30
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP, 4.0,EXP PADS.EPS
MAX9760-MAX9763
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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