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AV3168/69 VIDEO PERFORMANCE
Item 1 Attenuation of Luminance Signal
Specification 0 - 5 Mhz 6 Mhz 9 Mhz +/- 0.1 dB > 3dB > 35 dB < 1dB 5 dB > 25 dB < 2dB > 20dB < 3 dB > 38 dB > 82 dB AM PM > 64 dB > 60 dB < 0.5% < 1 degree +/- 2 nsec. +/- 2% < 0.7 IRE < 4 degree
2
Attenuation of NTSC Color Difference Signal
0.4 MHz 1 MHz 2 MHz
3
Attenuation of PAL Color Difference Signal Attenuation of Component Color Difference Signal Luma SNR Chroma SNR
1.3 MHz 3.6 MHz 2 MHz 5 MHz
4
5 6
7 8 9 10 11 12
Differential Gain Differential Phase Y/C Delay Y/C Gain inequality Y/C Intermodulation SCH
3-24
January 4, 2001
AV3168 Detailed Block Diagram
VSYN HSYN MSTR PDEN CPNT
70
69
68
43
42
EAV
Video Timing Generation
CONT
FMT
AV3168
BRTN CMOD[1:0]
MONO
MUX Y
2
5 MHz
Contrast
Pedestal
Y
10
PD<7:0>
DEMUX
Cb Cr
CVBS
D/A
39
CVBS, B, Cr
4
LPF
Modulation & Gain
C
10
FSEL[1:0]
f sc
SDA SCL
D/A
PALMN
36
Y, R, Y
I 2C Serial I/F
MacroVision Anti-Tapping
Gen
CK27
K[1:0]
Color Space Conv.
R, Cb G,Y B, Cr
10
D/A
36
C, G, Cb
CLOCK
ACK GCK
70 69 69 68
GEN.
CCC
Close Caption
XOUT
XIN
GOUT0
GOUT1
RST
Figure 1
AV3168/69
PIN DESCRIPTIONS
COMP
VDDA
IREF
BIAS
CVBS
VDDA
VSS
C
Y
VSS 30
VREF VSS VSS GOUT0 GOUT1 XOUT XIN MSTR VSS VDD RST
40 41 42 43 44 1 2 3 4 5 6
39
38
37
36
35
34
33
32
31
29
28 27 26 25 24 23 22 21 20 19 18
VDDA
PDEN CPNT VSS ACK SCL SDA VDD HSYN VSYN PD7 PD6
CK27
GCK
VDD
10
11
12
13
14
15
16 PD5
VSS
5-24
VSS
PD0
PD1
PD2
PD3
PD4
17
7
8
9
January 4, 2001
AV3168/69
PIN DESCRIPTIONS
Pin Name Pin # Type Description
DIGITAL VIDEO INPUT PD<7 -0> HSYN VSYN 11-16 18-19 21 20 I I/O I/O Multiplexed Cb, Y, and Cr digital video input bus. In Slave Mode (MSTR pin is low) Horizontal Synch input. In Master Mode (MSTR pin is high) Horizontal Synch output. In slave mode (MSTR pin is low) Vertical Sync input. In master mode Vertical Sync output.
VIDEO CONTROL SIGNALS MSTR 3 I Master Mode; If this pin is high, the chip outputs horizontal and vertical sync signals. Otherwise it receives both horizontal and vertical sync signals. Select either component or composite video output. 0: Simultaneous Composite and S-Video output. 1: Component video output either RGB or YCbCr determined by the register CR0[5:4]. Pedestal enable pins. When this pin is high 7.5 IRE is added for the NTSC composite analog output.
CPNT
27
I
PDEN
28
1
VIDEO ANALOG OUTPUT, REFERENCE AND COMPENSATION CVBS 35 O Analog video output Determined by the state of CPNT pin and CR0[5:4] CPNT CR0[5] CR0 [4] --- 0 ---- X------ X: ---Composite video output --- 1----- X------ 0: --- Cr output in YCbCr component mode --- 1 ---0 0------X: --- 1111111111- :: --- 1------1------ 1: ----Blue color output in RGB mode Analog video output Determined by the state of CPNT pin and CR0[5:4] CPNT CR0[5] CR0 [4] --- 0 ----- X----- X: ---S-Video Y output. --i 1------ X---- - 0: ---Y output in YCbCr component mode --- 1 ---0 0------X: -- 1111111111- :: - i 1 ----- 1--- -- 1: - -R color output in RGB mode
Y
31
O
6-24
January 4, 2001
AV3168/69 PIN DESCRIPTIONS (Continued)
Pin Name C Pin # 33 Type O Description Analog video output Determined by the state of CPNT pin and CR0[5:4] CPNT CR0[5] CR0 [4] --- 0 ------ X------X: --S-Video C output. ---- 1 ------ X-----0:---Cb output in YCbCr component mode --1 1 ------ 0 ---- X:1111111- :: --1 1 ------ 1------1:--Green color output in RGB mode Voltage reference. It has an internal voltage reference circuit, but may be overridden by an external voltage reference input. A 0.1 uF ceramic capacitor is required between this pin and GND. A resistor should be connected between this pin and GND to control the DAC output current. The recommended value is 198 (382) ohm 1% metal film resistor for double (single) end 75 ohm termination. Compensation capacitor for the DAC internal reference amplifier. A 0.1 uF ceramic capacitor is required between this pin and VDDA. DAC bias voltage. A 0.1 uf ceramic capacitor must be used to decouple this pin to VDDA.
VREF
40
I/O
IREF
39
I
COMP BIAS
38 37
I I/O
SERIALCONTRL BUS SCL SDA 24 23 I I/0 Serial bus clock Serial bus address and data input and output pin. Open drain output.
CLOCK SIGNALS GCK 7 O General Purpose Clock. Clock frequency is determined by the state of GOUT[1:0] when RST pin is low. 00 : 40.5 MHz clock output. 0 1: 54.0 MHz clock output. 1 0: 67.5 Mhz clock output. 1 1: 81.0 MHz CK27 ACK 9 25 O I/O 27 MHz clock output pin. 384*fs Audio clock output pin. Controlled by CR2[1:0] 0 0: 384 * 48.0 KHz (18.432MHz) clock output. 0 1: 384 * 44.1 KHz (16.934MHz) clock output. 1 0. 384 * 96.0 KHz (36.864MHz) clock output. 1 1: 384 * 88.2 KHz (33.868MHz) clock output.
7-24
January 4, 2001
AV3168/69 PIN DESCRIPTIONS (Continued)
Pin Name XIN XOUT Pin # 2 1 Type I O 27 Mhz oscillator input 27 Mhz oscillator output Description
MISCELLANEOUS SIGNALS RST GOUT1 6 44 I I/O Active low chip reset input. Chip is in the power down mode when the RST is low. Dual function pin. GCK frequency select pin when RST is low. General purpose output pin when RST is high Dual function pin. GCK frequency select pin when RST is low. General purpose output pin when RST is high
GOUT0
43
I/O
POWER AND GROUND VDD VSS 10, 22, 5 8, 17, 26, 30, 34, 41, 42, 4 29, 32, 36. +5V GND Digital power supply. Digital ground
VDDA
+5V
Analog video power supply.
8-24
January 4, 2001
AV3168/69 VIDEO TIMING GENERATION
The video encoder can operate as a master or a slave in the timing generation. In the master mode, the video encoder outputs SYNC signals. In the slave mode, the internal timing is lock to the external SYNC signals.
MASTER MODE
If the MSTR pin is high, the video encoder operates in the master mode. It uses the internal counters to generate the video timing and outputs HSYN and VSYN. The HSYNs are asserted for 64 pixel times. The negative transition of the HSYNs occur in the Cb slot. The VSYNs are asserted for 3 line times for NTSC and 2.5 for PAL. The co-incident negative transitions of HSYN and VSYN indicate the beginning of an odd field. The negative transition of the VSYN while the HSYN is high indicates the beginning of an even field.
SLAVE MODE
In the slave mode operation, the decoder automatically detects the input format and locks the internal timing counters to the external synchronization signals. It support 2 types of synch inputs: (a) HSYN / VSYNC, or (b) CCIR656 EAV data. If EAV is present, the video encoder synchronized to the EAV packets according to CCIR656 specifications to generate the video timing. HSYN and VSYN signals are ignored. If EAV is not present, the Video Encoder uses the signals presented on HSYN and VSYN for line and field counter increment. If register CR0[3] is low the encoder assumes the negative transition of the HSYN should be co-incited with the Cb0 datum. If CR0[3] is high it assume the transition co-incited with Y0 datum.
NTSC VERTICAL INTERVAL TIMING
Blanked
524
525
1
2
3
4
5
6
7
8
9
10 - 20
VSYN
Field One
Blanked
262
263
264
265
266
267
268
269
270
271
272
273 - 280
VSYN
Field Two
9-24
January 4, 2001
AV3168/69
PAL VERTICAL INTERVAL TIMING
Blanked
Field 1 & 5
621 622 623 624 625 1 2 3 4 5 6 7 - 20
VSYN
Field 2 &6
309 310 311 312 313 314 315
Blanked
316
317
318
319
320 - 333
VSYN
Blanked
Field 3 & 7
621 622 623 624 625 1 2 3
4
5
6
7 - 20
VSYN
Blanked
Field 4 & 8
309 310 311 312 313 314 315 316 317 318 319 320 - 333
VSYN
10-24
January 4, 2001
AV3168/69 LUMINANCE PROCESSING
The luminance, Y, are interpolated to 27 Mhz sampling rate through a multi-tap linear poly-phase filter. The filter frequency response is flat from 0 to 5 MHz. Contrast and Brightness control are provided for minor adjustment only.
Contrast Control
Item 1 2 3 4 . CREG1<1:0> 00 01 10 11 Contrast Normal Less Contrast Least Contrast High Contrast
Brightness Control
Item 1 2 3 4 CREG1<3:2> 00 01 10 11 Contrast Normal Modest Brightness High Brightness Less Brightness
LUMINANCE FILTER
luminance Filter Frequency Response 0 -10 Attenuation (dB) -20 -30 -40 -50 0 2 4 6 8 Frequency (Mhz) 10 12
11-24
January 4, 2001
AV3168/69 CHROMINANCE PROCESSING
The Cb and Cr signals are filtered and interpolated to 27 Mhz. The filter has 3 bandwidth: 0.675, 1.3 or 2 MHz. The filter bandwidth can be either auto select or user select via control register CREG<7:6>.
Chroma Filter Bandwidth Control
Item 1 2 3 4 CREG2<7:6> 00 01 10 11 Chroma Bandwidth auto-select 0.675 Mhz 1.375 MHz. 2.0 MHz
CHROMINANCE FILTER Chrominance Filter Frequency Response 0
Component
Attenuation (dB)
-10
NTSC PAL
-20 -30 -40 -50 0
1
2 3 4 Frequency (MHz)
5
6
12-24
January 4, 2001
AV3168/69 CLOCK FREQUENCY CONTROL
The system clock, GCK, output frequency is determined by the state of two general purpose output pins (GOUT0 and GOUT1) while the RST pin is low. The output frequencies are.
System Clock
Item 1 2 3 4 GOUT<1:0> 00 01 10 11 Frequency (MHz) 40.5 54.0 67.5 81.0
The ACK outputs 384 times 40.5, 48 or 96 KHz audio clock. The clock frequency is selected via Control Register. CR2 <1:0> .
Audio Clock
Item 1 2 3 4 CR2<1:0> 00 01 10 11 Audio Sampling Frequency (KHz) 48.0 44.1 96.0 88.2 Clock Frequency (MHz) 18.432 16.934 36.864 33.869
13-24
January 4, 2001
AV3168/69 CONTROL and CLOSED CAPTION REGISTER DESCRIPTION
The AV3168 contains three 8-bit registers for timing generation, luma and chroma processing control, clock generation and power management. Additionally it contains 4 Closed Caption Data Registers. These registers are programmed via the 7-bit address I2C bus. I2C Address = 0X65. (I2C bus Address = 0x64 for AV3169). The protocol is 7- bit chip address followed by 8- bit register address and 8-bit register data.
Control Register 0, CR0 (Address: 0x0, Default Value: 0x00)
Item 1 Register Bits CR0[7:6] Mnemonic FSEL[1:0] #bits 2 Description Chroma Filter Selection 00: Automatic bandwidth assignment based on the output format selection (default) 01: 0.675 MHz bandwidth 10: 1.36 MHz bandwidth 11: 2 MHz bandwidth 2 CR0[5:4] CMOD[1:0] 2 Component Output Selection. Valid only If pin 27 CPNT pin is `1'. 00: Sony Betacam (Default) 01: Mashushita M-II 10: SMPTE 11: RGB 3 CR0[3] SDLY 1 Input Hsyn negative transition position 0: The Negative HSYNC transition coincided with Cb0 datum (Default) 1: The Negative HSYNC transition co-incited with Y0 datum. 4 CR0[2] SCH 1 Subcarrier horizontal sync phase control (SCH) 0: Subcarrier reset every 4 fields for NTSC and every 8 field for PAL (Default), SCH =0 according CCIR 624 Spec. 1: Subcarrier free running. 5 CR0[1] PALMN 1 Enable South American PALM and PALN 0: Non-South American Mode, PAL(BDGHI), or NTSC (Default). 1: South American Mode (Pal-M, Pal-N) Used in master mode only to select either 525 or 625 line system timing. 0: 525-line M system (Default) 1: 626-line system.
6
CR0[0]
FMT0
1
14-24
January 4, 2001
AV3168/69
Control Register 1, CR1 (Address: 0x01, Default Value: 0x00)
Item 1 Register Bits CR1[7] Mnemonic VBIOFF #bits 1 Description Vertical Blanking Interval disable. 1: Vertical interval (VBI) is not blanked 0: VBI Blanked (Default) For M system line 1-21, 262-284, 525 are blanked. For 625 line system line 1-22, 311-335, 624 - 625 are blanked. Close Caption enable 00: Disable Closed Caption Data (Default) 10: Enable Closed Caption Data on odd field only. 01: Enable Closed Caption Data on even field only. 11: Enable Closed Caption Data on all fields Luma Delay Control 0: Luma output not delayed (Default) 1: Luma output delayed by 74ns Brightness Control 00: Brightness Control Off (Default) 01: Moderate Brightness Gain 10: Most Brightness Gain 11: Least Brightness Gain Contrast Control 00: Contrast Control Off (Default) 01: 15/16 * Luma Gain 10: 14/16 * Luma Gain 11: 17/16 * Luma Gain
2
CR1[6:5]
CCC
2
3
CR1[4]
YDLY
1
4
CR1[3:2]
BGT
2
5
CR1[1:0]
CON
2
Control Register 2, CR2 (Address: 0x02, Default Value: 0x00)
Item 1 Register Bits CR2[7] Mnemonic BW #bits 1 Description Monochrome Display 0: Color Display (Default) 1: Monochrome Display Composite DAC Power Down control. 0: Enable CVBS DAC (Default) 1: Power Down CVBS DAC S-video DACs Power Down control. 0: S-video DAC On (Default) 1: S-video DAC Power Down
2
CR2[6]
PWDCV
1
3
CR2[5]
PWDYC
1
15-24
January 4, 2001
AV3168/69 Control Register 2, CR2 (Address: 0x02, Default Value: 0x00)
Item 4 Register Bits CR2[4] Mnemonic GOUTEN #bits 1 Description General purpose register GOUT<1:0> Output Enable. 0: Pin 44 and 43 in high impedance state. 1: Gout<1:0> are output to pin 44 and 43. General purpose output registers. These registers connected to pin 44 and 43 respectively. Audio clock, ACK, output frequency select 00: 48 * 384 KHz 01: 44.1 * 384 KHz 10: 96.0 * 384 KHz 11: 88.2 * 384 KHz
5 6
CR2[3:2] CR2[1:0]
GOUT[1:0] K[1:0]
2 2
Extended Closed Caption Register 0 (Address: 0x03, Default Value: 0x00)
Register ECC[15:8] Mnemonic ECC[15:8] #bits 8 Description Extended Closed Caption Data (Upper byte)
Extended Closed Caption Register 1 (Address: 0x04, Default Value: 0x00)
Register ECC[7:0] Mnemonic ECC[7:0] #bits 8 Description Extended Closed Caption Data (Lower byte)
Closed Caption Register 0 (Address: 0x05, Default Value: 0x00)
Register CC[15:8] Mnemonic CC[15:8] #bits 8 Description Closed Caption Data (Upper byte)
Closed Caption Register 1 (Address: 0x06, Default Value: 0x00)
Register CC[7:0] Mnemonic CC[7:0] #bits 8 Description Closed Caption Data (Lower byte)
16-24
January 4, 2001
I2C Bus Control Register write example:
I2C Bus Control Register write example:
Start
CA6
CA0 R/W ACK A7
A0
ACK D7
D0 ACK
Stop
SDA
1
1
1
SDA
Start
CA6
1
1 1
CA0 R/W ACK A7
A0
ACK D7
D0 ACK
Stop
1
1
SCL
SCL
Chip adrress: CA<6:0> = 65H Register address: A<7:0> = 00H DATA: D<7:0> = 30H
Chip adrress: CA<6:0> = 65H Register address: A<7:0> = 00H DATA: D<7:0> = 30H
AV3168/69 APPLICATION CIRCUIT
De-coupling and Analog Connections
+5V Connector
47 uF
5
FERRITE-BEAD
C10
47uF
C1 C7
10 BIAS VDDA 29,32,36
VDD
C8
22
AV3168
C3
COMP
C4
C5
C2
35 31 33 VLPF
C9
CSVB Y
Video
27.0000 MHz
12~22pF XIN
C
75 ohm
XOUT
IREF 196 ohm VREF
+5 V
12~22pF
1.5 K
IC
2
C6
SDL SDA
100 ohm GCK Selection
GOUT1 GOUT0
C1 -C10 are 0.1 uF Capacitors
+5 V
Reconstruction Filter (VLPF) for The Double End 75 Ohm Termination
22 pF 1.8 uH
Video Output 75 ohm
TV
75 ohm
180 pF
180 pF
18-24
January 4, 2001
AV3168/69 DIGITAL VIDEO INPUT PORT TIMING DIAGRAM
.
tck27L
CK27
tck27H
tpdsu
PD<7:0>
tpdhd
Figure 1: Pixel Bus
.
CK27
tsysu
HSYN VSYN
tsyhd
Figure 2: Horizontal Sync and Vertical Sync Signals
tBUF
tSU;STA
SDA
tSU;DAT tSU;STO tHIGH
tHD;STA
SCL
P
S
tLOW tR tF tHD;DAT
Sr
P
Figure 3: I 2C Serial Port Timing
19-24
January 4, 2001
AV3168/69 ABSOLUTE MAXIMUM RATINGS
Symbol VDD Vi Ai Vo Ao TDsc TASC Ta Tstg Tj Tsol Tvsol Tstor Notes: 1. Absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. 2. Applied voltage must be current limited to specified range, and measured with respect to VSS. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device. Characteristics Power Supply Voltage (Measured to GND) Digital Input Applied Voltage2 Digital Input Forced Current
3,4
Min -0.5 GND-0.5 -100 GND-0.5 -100
Max +7.0
Units V V
100 VDD+0.5 100 1 infinite
mA V mA Sec Sec
o o o o
Digital Output Applied Voltage2 Digital Output Forced Current
3,4
Digital Short Circuit Duration (single output high state to Vss)
Analog Short Circuit Duration (single output to VSS1) Ambient Operating Temperature Range Storage Temperature Range Junction Temperature (Plastic Package) Lead Soldering Temperature (10 sec., 1/4" from pin) Vapor Phase Soldering (1 minute) Storage Temperature -65 -25 -65 -65
+125 +150 +150 300 220 +150
C C C
C oC oC
20-24
January 4, 2001
AV3168/69 RECOMMENDED OPERATING CONDITIONS
Symbol VDD Vref Iref RL Ta Characteristics Power supply voltage Reference voltage
Reference current
Min 4.35
Typical 5 1.235 3.15 37.5
Max 5.25
Units V V mA
Analog output load Ambient operating temperature range 0
70 70
o
C
ELECTRICAL CHRACTERISTICS
Symbol Supply IDD IDDQ Total Power Supply Current, Analog + Digital Total Power Supply Current, DAC Power Down 130 37 TBD TBD mA mA Characteristics Min Typ Max Units
Digital Characteristics VIH VIL IIH IIL CIN VOH VOL IOZH IOZL CI CO Digital Input Voltage, Logic HIGH, TTL Compatible Inputs. Digital Input Voltage, Logic LOW, TTL Compatible Inputs Digital Input Current, Logic HIGH, (VIN=4.0V) Digital Input Current, Logic LOW, (VIN=0.4V) Digital Input Capacitance (f=1Mhz, VIN=2.4V) Digital Output Voltage, Logic HIGH, CMOS Compatible Outputs (IOH= -1mA) Digital Output Voltage, Logic LOW, CMOS Compatible Outputs (IOL=4.0 mA) Hi-Z Leakage Current, HIGH, VDD=Max, VIN=VDD) Hi-Z Leakage Current, LOW, VDD=Max, VIN=VSS) Digital Input Capacitance (TA=25oC, f=1Mhz) Digital Output Capacitance (TA=25oC, f=1Mhz) 3.7 VSS 2.0 VSS VDD 0.8 10 -10 7 VDD 0.4 10 -10 8 10 V V
A A
pF V V
A A
pF pF
Video Clock and Oscillator Signal
FX
Crystal Oscillator Input Frequency 27 Mhz Clock,CK27, Frequency CK27 Pulse Width, HIGH
-30 ppm
27.0000 27.0000
+30 ppm
Mhz Mhz ns
F27
tck27H
10
18.5
21-24
January 4, 2001
AV3168/69
Symbol Characteristics CK27 Pulse Width, LOW Min 14.5 Typ 18.5 Max Units ns
tck27L tpdsu tpdhd tsysu tsyhd tpdsu tpdhd tsysu tsyhd
tpwd
Video Bus Master Mode Timing Digital Pixel Data P<7:0> Input Setup Time Digital Pixel Data P<7:0> Input Hold Time HSYN and VSYN Output Setup Time HSYN and VSYN Output Setup Time 8 3 10 6 ns ns ns ns
Video Bus Slave Mode Timing Digital Pixel Data P<7:0> Input Setup Time Digital Pixel Data P<7:0> Input Hold Time HSYN and VSYN Input Setup Time HSYN and VSYN Input Setup Time 8 3 8 3 ns ns ns ns
s
Miscellaneous Digital Signals RST, active low reset time 1
Serial Port Timing
fsc tsu;sta thd;sta tsu;sto tLOW tHIGH tr tf tsu;DAT thd;DAT tvd;DAT tBUF
RES PSRR
SCL Clock Frequency Start condition set up time Start condition hold time Stop condition set up time SCL Low time SCL High time SCL & SDA rise time SCL & SDA fall time Data set-up time Data hold time SCL LOW to data out valid Bus Free time 4.7 250 0 4.7 4.0 4.0 4.7 4.0
100
kHz us us us us us
1.0 0.3
us us ns ns
3.4
us us
Analog Video (DAC) Outputs DAC Resolution Power Supply Rejection Ratio (Full Scale Output) COMP=0.1 F, f=DC to 1 Mhz, VRIP= 100 mV p-p.) Voltage Reference (VREF) Output Voltage Reference Output Impedance DAC Gain Factor TBD 10 bits dB
VRO ZR KDAC
1.112 10 10.31
1.235
1.359
V K
10.85
11.39
22-24
January 4, 2001
AV3168/69
Symbol KIMBAC IREF RREF VBLANK VOC COUT RL TDOV Characteristics KDAC Imbalance Between DACs DAC Reference Current (IREF=Nominal) Reference Resistor (VRO=Nominal) Blanking Level Output Voltage (NTSC and PAL Modes) Video Output Compliance Voltage Video Output Capacitance (Iout=0 mA, f=1Mhz) Total Output Load Resistance Analog Output Delay -0.3 20 37.5 20 Min -1 3.15 196 0.300 1.6 Typ Max +1 Units % mA
V V pF
ns
23-24
January 4, 2001
AV3168/69 PACKAGING INFORMATION
A B
44-Pin Plastic Leaded Chip Carrier (PLCC)
29 28
39 40
44
1
45
6 7 18 17
C
D
a b fg d e
Dimensions
max A B C D 1.22 0.81 17.65 16.66 0.736 17.526 16.612 2.15 1.27 1.07 norm min unit mm. mm. mm. mm. mm. mm. max norm 0.406 15.748 0.51 3.04 4.57 2.565 4.368 min 0.33 unit mm. mm. mm. mm. mm.
h
d e f g h
0.53 16.00
a b
24-24
January 4, 2001

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