Description |
Programmable lor='#FF0000'>logic , 160 macrocells, 10 lor='#FF0000'>logic array blocks, 64 I/O pins, 20ns Programmable lor='#FF0000'>logic , 64 macrocells, 4 lor='#FF0000'>logic array blocks, 36 I/O pins, 6ns Programmable lor='#FF0000'>logic , 128 macrocells, 8 lor='#FF0000'>logic array blocks, 84 I/O pins, 6ns Programmable lor='#FF0000'>logic , 32 macrocells, 2 lor='#FF0000'>logic array blocks, 36 I/O pins, 12ns Programmable lor='#FF0000'>logic , 96 macrocells, 6 lor='#FF0000'>logic array blocks, 52 I/O pins, 15ns Programmable lor='#FF0000'>logic , 128 macrocells, 8 lor='#FF0000'>logic array blocks, 100 I/O pins, 7ns Programmable lor='#FF0000'>logic , 128 macrocells, 8 lor='#FF0000'>logic array blocks, 84 I/O pins, 7ns Programmable lor='#FF0000'>logic , 32 macrocells, 2 lor='#FF0000'>logic array blocks, 36 I/O pins, 7ns Programmable lor='#FF0000'>logic , 256 macrocells, 16 lor='#FF0000'>logic array blocks, 164 I/O pins, 12ns Programmable lor='#FF0000'>logic , 192 macrocells, 12 lor='#FF0000'>logic array blocks, 124 I/O pins, 12ns Programmable lor='#FF0000'>logic , 64 macrocells, 4 lor='#FF0000'>logic array blocks, 36 I/O pins, 7ns Programmable lor='#FF0000'>logic , 64 macrocells, 4 lor='#FF0000'>logic array blocks, 68 I/O pins, 15ns Programmable lor='#FF0000'>logic , 160 macrocells, 10 lor='#FF0000'>logic array blocks, 84 I/O pins, 10ns Programmable lor='#FF0000'>logic , 160 macrocells, 10 lor='#FF0000'>logic array blocks, 104 I/O pins, 10ns Programmable lor='#FF0000'>logic Device Family 可编程逻辑器件系列 Programmable lor='#FF0000'>logic , 160 macrocells, 10 lor='#FF0000'>logic array blocks, 64 I/O pins, 10ns Programmable lor='#FF0000'>logic , 160 macrocells, 10 lor='#FF0000'>logic array blocks, 64 I/O pins, 6ns Programmable lor='#FF0000'>logic , 256 macrocells, 16 lor='#FF0000'>logic array blocks, 164 I/O pins, 20ns Programmable lor='#FF0000'>logic , 32 macrocells, 2 lor='#FF0000'>logic array blocks, 36 I/O pins, 15ns Programmable lor='#FF0000'>logic , 192 macrocells, 12 lor='#FF0000'>logic array blocks, 124 I/O pins, 15ns Programmable lor='#FF0000'>logic , 192 macrocells, 12 lor='#FF0000'>logic array blocks, 124 I/O pins, 20ns Programmable lor='#FF0000'>logic , 256 macrocells, 16 lor='#FF0000'>logic array blocks, 164 I/O pins, 15ns Programmable lor='#FF0000'>logic , 64 macrocells, 4 lor='#FF0000'>logic array blocks, 36 I/O pins, 15ns Programmable lor='#FF0000'>logic , 64 macrocells, 4 lor='#FF0000'>logic array blocks, 68 I/O pins, 7ns Programmable lor='#FF0000'>logic , 96 macrocells, 6 lor='#FF0000'>logic array blocks, 64 I/O pins, 15ns Programmable lor='#FF0000'>logic , 32 macrocells, 2 lor='#FF0000'>logic array blocks, 36 I/O pins, 6ns Programmable lor='#FF0000'>logic , 64 macrocells, 4 lor='#FF0000'>logic array blocks, 68 I/O pins, 6ns Programmable lor='#FF0000'>logic , 128 macrocells, 8 lor='#FF0000'>logic array blocks, 68 I/O pins, 6ns Programmable lor='#FF0000'>logic , 64 macrocells, 4 lor='#FF0000'>logic array blocks, 68 I/O pins, 10ns Programmable lor='#FF0000'>logic , 96 macrocells, 6 lor='#FF0000'>logic array blocks, 76 I/O pins, 7ns Programmable lor='#FF0000'>logic , 32 macrocells, 2 lor='#FF0000'>logic array blocks, 36 I/O pins, 10ns
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