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DX3N60 TC174 X4043 A3188ELT EL5261 L7805AB ALH80M48 95HQ015
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    Integrated Device Technology, Inc.
Part No. IDT723663
OCR Text ...synchronous interface. all data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. the clocks for each port are independent of one another and can be asynchronous or coincident. the enables f...
Description 4K x 36 SyncFIFO, 5.0V

File Size 294.36K  /  29 Page

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    Integrated Device Technology, Inc.
Part No. IDT723644
OCR Text ...synchronous interface. all data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. the clocks for each port are independent of one another and can be asynchronous or coincident. the enables f...
Description 256 x 36 x 2 SyncBiFIFO, 5.0V

File Size 518.41K  /  35 Page

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    ST16C55005 ST16C550IQ48 ST16C550 ST16C550CJ44 ST16C550CP40 ST16C550CQ48 ST16C550IJ44 ST16C550IP40

EXAR[Exar Corporation]
Part No. ST16C55005 ST16C550IQ48 ST16C550 ST16C550CJ44 ST16C550CP40 ST16C550CQ48 ST16C550IJ44 ST16C550IP40
OCR Text ... strobe). A logic 0 on this pin transfers the contents of the ST16C550 data bus to the CPU. Connect to logic 1 when using IOR. Write data strobe (active low strobe). A logic 0 on this pin transfers the contents of the CPU data bus to the ad...
Description UART WITH 16-BYTE FIFO’s

File Size 237.98K  /  35 Page

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    Integrated Device Technology, Inc.
Part No. IDT723643
OCR Text ...synchronous interface. all data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. the clocks for each port are independent of one another and can be asynchronous or coincident. the enables f...
Description 256 x 36 SyncFIFO, 5.0V

File Size 455.09K  /  28 Page

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    INTEGRATED DEVICE TECHNOLOGY INC
Part No. IDT723634L12PF
OCR Text ...synchronous interface. all data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. the clocks for each port are independent of one another and can be asynchronous or coincident. the enables f...
Description 512 X 36 BI-DIRECTIONAL FIFO, 8 ns, PQFP128

File Size 405.88K  /  35 Page

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    TCN75-3.3MOA TCN75-5.0MOA TCN75-5.0MUA TCN75-3.3MUA TCN75

MICROCHIP[Microchip Technology]
Part No. TCN75-3.3MOA TCN75-5.0MOA TCN75-5.0MUA TCN75-3.3MUA TCN75
OCR Text ...ch controls the bus: initiating transfers (Start), generating the clock, and terminating transfers (Stop). The device addressed by the master. A unique condition signaling the beginning of a transfer indicated by SDA falling (High - Low) wh...
Description 2-Wire Serial Temperature Sensor and Thermal Monitor

File Size 392.97K  /  20 Page

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    NANYA TECHNOLOGY CORP
Part No. NT5DS64M8AF-6K
OCR Text ...ata rate architecture: two data transfers per clock cycle  bidirectional data strobe (dqs) is transmitted and received with data, to be used in capturing data at the receiver  dqs is edge-aligned with data for reads and is center- ali...
Description 64M X 8 DDR DRAM, 0.7 ns, PBGA60

File Size 2,293.16K  /  76 Page

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