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For resetting Found Datasheets File :: 3463    Search Time::0.922ms    
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    IMP16C554 IMP16C554-CJ68 IMP16C554-LJ68

IMP[IMP, Inc]
IMP Inc
IMP INC.
Part No. IMP16C554 IMP16C554-CJ68 IMP16C554-LJ68
OCR Text ...MODE OPERATION When FCR BIT-0=1;resetting IER BIT 3-0 to zero puts the IMP16C554 in the FIFO polled mode of operation. Since the receiver and 6 408-432-9100/www.impweb.com (c) 2002 IMP, Inc. IMP16C554 transmitter are controlled...
Description Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs
SWITCH, NO, RA, PCB MOUNT
SW,PB,1 FORM A,PC,MOM,RTANG

File Size 495.38K  /  20 Page

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    MC145010DW MC145010P MC145011DW MC145011P MC145012 MC145012P MC145013DW MC145013P MC145017P MC145018P MC14468P MC14578P

MOTOROLA[Motorola Inc]
MOTOROLA[Motorola, Inc]
Part No. MC145010DW MC145010P MC145011DW MC145011P MC145012 MC145012P MC145013DW MC145013P MC145017P MC145018P MC14468P MC14578P MC1455P1D MC14470P MC1455BP1D MC14467P1 MC1455BP1 MC1455P1
OCR Text ... are provided for triggering or resetting if desired. Multipliers Linear Four-Quadrant Multipliers Multipliers are designed for use where the output voltage is a linear product of two input voltages. Typical applications include: multi...
Description Photoelectric Smoke Detector with I/O
Micro-Power Comparator plus Voltage Follower
Photoelectic Smoke Detector IC with I/O and Temporal Pattern Horn Driver
Ionization Smoke Detector with I/O For Line-Powered Applications
Timing Circuits
Other Analog Circuits

File Size 52.47K  /  4 Page

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    MN662724RPE

PANASONIC[Panasonic Semiconductor]
Part No. MN662724RPE
OCR Text ...tion, FLAG6 output, that is the resetting signal for the address of RAM used to de-interleave error correction data. "L" level: address reset. During command execution, RESY output, that is the frame resynchronization signal. "H" level: syn...
Description Signal Processing LSI for CD Players

File Size 41.83K  /  7 Page

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    MN662747RPH

Panasonic, Corp.
PANASONIC[Panasonic Semiconductor]
Part No. MN662747RPH
OCR Text ...level, FLAG6 output, signal for resetting address of RAM for error correction de-interleave. "L" level: address reset. When IOSEL is "H" level, RESY output, frame resynchronization signal. "H" level: synchronized. "L" level: out of sync. ...
Description Signal Processing LSI for CD Players SPECIALTY CONSUMER CIRCUIT, PQFP80

File Size 52.31K  /  7 Page

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    MT8924-1 MT8924AE MT8924AS

MITEL[Mitel Networks Corporation]
Part No. MT8924-1 MT8924AE MT8924AS
OCR Text ...zation takes two frame periods. resetting the device disables the output drivers of the microprocessor interface and DSTo. Overflow Signalling (Output). When OS is Low, a conference is in the overflow condition. This signal is delayed by ha...
Description PCM Conference Circuit (PCC) Preliminary Information

File Size 101.82K  /  18 Page

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    MT8950 MT8950AC

Mitel Semiconductor
MITEL[Mitel Networks Corporation]
Part No. MT8950 MT8950AC
OCR Text ...in the Violation word, and, the resetting of Data Activity (DA) and Scan Point output (SPo) are controlled by this register. The contents of the register are updated once every ST-BUS frame when the interface is enabled. Data ST-BUS In (TTL...
Description ISO-CMOS ST-BUS⑩ FAMILY Data Codec
ISO-CMOS ST-BUS FAMILY Data Codec
ISO-CMOS ST-BUS?/a> FAMILY Data Codec

File Size 222.80K  /  16 Page

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    MT8952B-1 MT8952BE MT8952BP MT8952BS

Mitel Semiconductor
MITEL[Mitel Networks Corporation]
Part No. MT8952B-1 MT8952BE MT8952BP MT8952BS
OCR Text ...tive LOW Schmitt Trigger input, resetting all the registers including the transmit and receive FIFOs and the watchdog timer. Supply (5 Volts). 24 25 TEOP CKi 26 F0i 27 28 RST VDD Address Bits A3 0 0 0 0 0 0 0 0 1 1 A2 0...
Description ISO-CMOS ST-BUS FAMILY HDLC Protocol Controller
ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller

File Size 169.67K  /  27 Page

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    MT8952 MT8952B MT8952BC MT8952BS MT8952BE MT8952BP

Mitel Semiconductor
MITEL[Mitel Networks Corporation]
Part No. MT8952 MT8952B MT8952BC MT8952BS MT8952BE MT8952BP
OCR Text ...tive LOW Schmitt Trigger input, resetting all the registers including the transmit and receive FIFOs and the watchdog timer. Supply (5 Volts). 24 25 TEOP CKi 26 F0i 27 28 RST VDD Address Bits A3 0 0 0 0 0 0 0 0 1 1 A2 0...
Description ISO-CMOS ST-BUS FAMILY HDLC Protocol Controller
ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller

File Size 160.74K  /  22 Page

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