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NANYA TECHNOLOGY CORP
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| Part No. |
NT5DS16M16BW-6K
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| OCR Text |
...ycle at the i/o pins. a single read or write access for the 256mb ddr sdram effectively consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half-clock-cycle d... |
| Description |
16M X 16 DDR DRAM, 0.7 ns, PBGA60
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| File Size |
1,341.90K /
80 Page |
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it Online |
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| Part No. |
MT18LD1672AG-6X
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| OCR Text |
...and execut- ing any ras# cycle (read, write) or ras# refresh cycle (ras#-only, cbr or hidden) so that all combi- nations of ras# addresses (a0-a10/a11) are executed at least every t ref, regardless of sequence. the cbr re- fresh cycle will... |
| Description |
16M X 72 EDO DRAM MODULE, 60 ns, DMA168
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| File Size |
621.95K /
27 Page |
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it Online |
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DENSITRON INTERNATIONAL
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| Part No. |
LM4229
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| OCR Text |
...ta write rd="l"?c/d="h": status read c/d="l": data read 5 rd i data read active low 6 wr i data write active low 7 db0 i/o bi-directional data bus line 0 8 db1 i/o bi-directional data bus line 1 9 db2 i/o bi-directional ... |
| Description |
240 X 128 GRAPHICS LCD MODULE
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| File Size |
109.93K /
8 Page |
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it Online |
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IDT
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| Part No. |
IDT71P71104 IDT71P71204
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| OCR Text |
... 2mx9, 1mx18, 512kx36) u common read and write data port u dual echo clock output u 2-word burst on all sram accesses u multiplexed address bus - one read or one write request per clock cycle u ddr (double data rate) data bus ... |
| Description |
1.8V 2M x 9 DDR II Pipelined SRAM
1.8V 2M x 8 DDR II Pipelined SRAM
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| File Size |
612.62K /
24 Page |
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it Online |
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MAXIM INTEGRATED PRODUCTS INC
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| Part No. |
DS1250YL-70-IND
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| OCR Text |
...e cycles low-power cmos read and write access times as fast as 70ns lithium energy source is electrically disconnected to retain freshness until power is applied for the first time full 10% v cc operating range (ds1250... |
| Description |
512K X 8 NON-VOLATILE SRAM MODULE, 70 ns, DMA34
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| File Size |
294.88K /
14 Page |
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it Online |
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