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Atmel Corp.
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| Part No. |
ATF1500
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| OCR Text |
...O macrocells, each containing a flipflop, the ATF1500 can easily integrate several TTL, SSI, MSI and simple PLDs. In terms of logic density, the ATF1500 p r o v i de s a n i nt e r m e di a t e s ol u t i o n b et w e e n A tm e l ' s 2 4 -... |
| Description |
44-pin Complex PLD(44脚复杂可编程逻辑器件)
44-pin Complex PLD(44??????缂???昏??ㄤ欢)
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| File Size |
179.52K /
10 Page |
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MAXIM - Dallas Semiconductor
MAXIM[Maxim Integrated Products]
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| Part No. |
MAX9381
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| OCR Text |
...tial data, differential clock D flipflop is pin compatible with the ON Semiconductor MC100EP52, with the added benefit of a wider supplyvoltage range from 2.25V to 5.5V and 25% lower supply current. Data enters the master part of the flip-f... |
| Description |
Lowest Power 3.0GHz ECL/PECL Differential Data and Clock D Flip-Flop
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| File Size |
185.97K /
7 Page |
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it Online |
Download Datasheet |
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LATTICE[Lattice Semiconductor]
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| Part No. |
MACH445-12 MACH445-15 MACH445-15YC MACH445-12YC MACH445-20YC
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| OCR Text |
... configured with or without the flipflop, and whether or not the macrocell drives an I/O cell. The flip-flop clock depends on the mode selected for the macrocell. In synchronous mode, any of the PAL block clocks generated by the Clock Gener... |
| Description |
High-Density EE CMOS Programmable Logic
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| File Size |
206.54K /
28 Page |
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it Online |
Download Datasheet |
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FAIRCHILD[Fairchild Semiconductor]
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| Part No. |
74VHCT574A 74VHCT574ASJ 74VHCT574AN 74VHCT574AMTC 74VHCT574AM 74VHCT574ASJX 74VHCT574N
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| OCR Text |
... dissipation. This 8-bit D-type flipflop is controlled by a clock input (CP) and an Output Enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. Protection circuits ensure that 0V to 7V can be applie... |
| Description |
ACTIVE HIGH P-P WITH WDI, MR, -40C to 125C, 5-SOT-23, T/R
Octal D-Type Flip-Flop with 3-STATE Outputs
Active low P-P with WDI, MR, -40C to 125C, 5-SOT-23, T/R
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| File Size |
92.66K /
7 Page |
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it Online |
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IDT
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| Part No. |
IDT74LVCH32501A IDT74LVCH32501ABF IDT74LVCH32501ABF8
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| OCR Text |
...bus data is stored in the latch/flipflop on the LOW-to-HIGH transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B port to A port is similar but requires using OEBA, LEBA and CLKBA. Flow-through organi... |
| Description |
3.3V CMOS 36-Bit Registered Transceiver with 5.0V Tolerant I/O, and Bus-Hold
3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5V TOLERANT I/O, AND BUS-HOLD
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| File Size |
145.57K /
7 Page |
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it Online |
Download Datasheet |
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Price and Availability
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