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GSI Technology, Inc.
http://
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| Part No. |
GS881Z36T-100I GS881Z36T-11I GS881Z36T-66T
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| OCR Text |
...nd flow through mode ? nbt (no bus turn around) functionality allows zero wait ? read-write-read bus utilization ? fully pin - compatibl...self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off... |
| Description |
256K X 36 ZBT SRAM, 18 ns, PQFP100 TQFP-100
8Mb Pipelined and Flow Through Synchronous NBT SRAMs
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| File Size |
527.70K /
34 Page |
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Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
CYPRESS[Cypress Semiconductor]
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| Part No. |
CY7C1352B-133AC CY7C1352B-80AC CY7C1352B CY7C1352B-100AC CY7C1352B-143AC CY7C1352B-150AC CY7C1352B-166AC
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| OCR Text |
...MT55L256L18P * Supports 166-MHz bus operations with zero wait states -- Data is transferred on every clock * Internally self-timed output buffer control to eliminate the need to use OE * Fully registered (inputs and outputs) for pipelined o... |
| Description |
256K x 18 Pipilined SRAm with NoBL Architecture 256K X 18 ZBT SRAM, 3.8 ns, PQFP100
256K x 18 Pipilined SRAm with NoBL Architecture 256K X 18 ZBT SRAM, 4 ns, PQFP100
256K x 18 Pipilined SRAm with NoBL Architecture 256K X 18 ZBT SRAM, 4.2 ns, PQFP100
256K x 18 Pipilined SRAm with NoBL Architecture 256K X 18 ZBT SRAM, 5 ns, PQFP100
256K x 18 Pipilined SRAm with NoBL Architecture 256K X 18 ZBT SRAM, 7 ns, PQFP100
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| File Size |
187.09K /
12 Page |
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it Online |
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PHILIPS[Philips Semiconductors]
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| Part No. |
ISP1123 ISP1123NB ISP1123BD ISP1123D
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| OCR Text |
bus compound hub
Rev. 01 -- 5 October 1999 Preliminary specification
1. General description
The ISP1123 is a compound Universal Serial ...self-powered or hybrid-powered. When it is hybrid-powered the hub functions are powered by the upstr... |
| Description |
Universal Serial bus compound hub
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| File Size |
270.94K /
49 Page |
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it Online |
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MITSUBISHI[Mitsubishi Electric Semiconductor]
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| Part No. |
MH32D72AKLA-10 MH32D72AKLA-75
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| OCR Text |
...nput
Data Input/Output: Data bus Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in writ...self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. I... |
| Description |
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
2 /415 /919 /104-BIT (33 /554 /432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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| File Size |
324.12K /
38 Page |
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it Online |
Download Datasheet |
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MITSUBISHI[Mitsubishi Electric Semiconductor]
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| Part No. |
MH32D72AKLB-10 MH32D72AKLB-75
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| OCR Text |
...nput
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in wri...self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. I... |
| Description |
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
2 /415 /919 /104-BIT (33 /554 /432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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| File Size |
354.77K /
40 Page |
View
it Online |
Download Datasheet |
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