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  zdb fanout Datasheet PDF File

For zdb fanout Found Datasheets File :: 44    Search Time::1.75ms    
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    Silicon Laboratories, Inc.
HIROSE ELECTRIC Co., Ltd.
Part No. SL23EP08SC-2T SL23EP08SC-2H
OCR Text ... 220 mhz zero dela y buffer ( zdb ) key features ? 10 to 220 mhz operating frequency range ? low output clock skew: 70ps-typ ? l...fanout buffer. high and low-drive product options the sl23ep08 is offered with high drive ?-1...
Description 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 0.150 INCH, ROHS COMPLIANT,SOIC-16

File Size 239.03K  /  18 Page

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    ICS9DB803DI ICS9DB803DFILFT ICS9DB803DGILFT

Integrated Device Technology
Part No. ICS9DB803DI ICS9DB803DFILFT ICS9DB803DGILFT
OCR Text ... select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 23 sclk in clock pin of smbus circuitry, 5v tolerant. 24 sdata i/o data pin for smbus circuitry, 5v tolerant. idt tm /ics tm eight output differential buffer for p...
Description Eight Output Differential Buffer for PCIe Gen 2

File Size 250.48K  /  21 Page

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    9DB403DGILF 9DB403DGLF 9DB403DGLFT 9DB403DGILFT ICS9DB403D 9DB403DFILFT 9DB403DFLF 9DB403DFLFT

Integrated Device Technology
Part No. 9DB403DGILF 9DB403DGLF 9DB403DGLFT 9DB403DGILFT ICS9DB403D 9DB403DFILFT 9DB403DFLF 9DB403DFLFT
OCR Text ... select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 13 sclk in clock pin of smbus circuitry, 5v tolerant. 14 sdata i/o data pin for smbus circuitry, 3.3v tolerant. 15 pd# in asynchronous active low input pin used to po...
Description Four Output Differential Buffer for PCIe Gen 1 and Gen 2

File Size 274.09K  /  19 Page

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    9FG1201HFLF 9FG1201HGLFT 9FG1201HFLFT ICS9FG1201H11

Integrated Device Technology
Part No. 9FG1201HFLF 9FG1201HGLFT 9FG1201HFLFT ICS9FG1201H11
OCR Text ...rates as a zero-delay buffer (zdb) with the pll operating. 0 = fanout mode (pll bypassed), 1 = zdb mode (pll u sed) 31 oe6# in active low input for enabling dif pair 6. 1 = tri-state outputs, 0 = enable outputs 32 dif_6# out 0.7v differ...
Description Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

File Size 241.48K  /  23 Page

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    ICS9DB401CGLFT ICS9DB401CFLFT

Integrated Device Technology
Part No. ICS9DB401CGLFT ICS9DB401CFLFT
OCR Text ... select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 13 sclk in clock pin of smbus circuitry, 5v tolerant. 14 sdata i/o data pin for smbus circuitry, 5v tolerant. 15 pd# in asynchronous active low input pin used to powe...
Description Four Output Differential Buffer for PCI Express

File Size 239.76K  /  17 Page

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    9DB1933AKLF 9DB1933AKLFT

Integrated Device Technology
Part No. 9DB1933AKLF 9DB1933AKLFT
OCR Text ...erates as a zer o-delay buffer (zdb) with the pll operating. 0 = fanout mode (pll bypassed), 1 = zdb mode (pll u sed) idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 5 1...
Description Nineteen Output Differential Buffer for PCIe Gen3

File Size 183.51K  /  17 Page

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    Integrated Device Technology, Inc.
Part No. ICS9DB801CFLFT
OCR Text ... select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 23 sclk input clock pin of smbus circuitry, 5v tolerant. 24 sdata i/o data pin for smbus circuitry, 5v tolerant. idt tm /ics tm eight output differential buffer f...
Description Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48

File Size 207.52K  /  19 Page

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    9DB1904BKLF 9DB1904BKLFT

Integrated Device Technology
Part No. 9DB1904BKLF 9DB1904BKLFT
OCR Text ...perates as a zero-delay buffer (zdb) with the pll operating. 0 = fanout mode (pll bypassed), 1 = zdb mode (pll used) idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for p...
Description 19 Output Differential Buffer for PCIe Gen2 and QPI

File Size 180.96K  /  18 Page

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    9DB1200CGLF 9DB1200CGLFT

Integrated Device Technology
Part No. 9DB1200CGLF 9DB1200CGLFT
OCR Text ... select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 36 vttpwrgd#/pd in vttpwrgd# is an active low input used to sample latched inputs and allow the device to power up. pd is an asynchronous active high input pin used t...
Description Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM

File Size 155.36K  /  14 Page

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For zdb fanout Found Datasheets File :: 44    Search Time::1.75ms    
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