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ILX551A
2048-pixel CCD Linear Sensor (B/W)
Description The ILX551A is a reduction type CCD linear sensor designed for facsimile, image scanner and OCR use. This sensor reads B4 size documents at a density of 200DPI (Dot Per Inch). A built-in timing generator and clock-drivers ensure direct drive at 5V logic for easy use. Features * Number of effective pixels: 2048 pixels * Pixel size: 14m x 14m (14m pitch) * Built-in timing generator and clock-drivers * Ultra low lag * Maximum clock frequency: 5MHz Absolute Maximum Ratings * Supply voltage VDD1 11 VDD2 6 * Operating temperature -10 to +55 * Storage temperature -30 to +80 Pin Configuration (Top View)
NC 15 S2
22 pin DIP (Cer-DIP)
Block Diagram
NC
10
Read out gate pulse generator
12
Read out gate
CCD analog shift register
NC
14
Clock-drivers
Mode selector
NC
16
1 2 3 4 5 6 7 8 9 10 11 2048 1
Clock pulse generator Sample-and-hold pulse generator
GND
NC SHSW CLK NC NC VDD2 VDD2 NC ROG
20 VDD1 19 GND 18 NC 17 GND 16 NC 15 NC 14 NC 13 NC 12 GND
VDD1
20
VDD2
22
NC
18
Output amplifier Sample-and-hold circuit
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
VOUT
1
E00439-PS
NC
2
NC
3
NC
6
NC
7
VDD2
8
CLK
NC
21 VDD2
17
5
D33
D15
D14
S1
VOUT
22 VDD2
GND
19
VDD2
21
SHSW
NC
13
4
S2048
S2047
D36
D35
D34
V V C C
GND
ROG
11
VDD2
9 D39 D38 D37
ILX551A
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 Symbol VOUT NC NC SHSW CLK NC NC VDD2 VDD2 NC ROG Description Signal output NC NC Switch { with S/HS/H GND without VDD2 Pin No. 12 13 14 15 16 17 18 19 20 21 22 Symbol GND NC NC NC NC GND NC GND VDD1 VDD2 VDD2 GND NC NC NC NC GND NC GND 9V power supply 5V power supply 5V power supply Description
Clock pulse NC NC 5V power supply 5V power supply NC Clock pulse
Recommended Supply Voltage Item VDD1 VDD2 Min. 8.5 4.75 Typ. 9.0 5.0 Max. 9.5 5.25 Unit V V
Note) Rules for raising and lowering power supply voltage To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V). Mode Description Mode in use S/H Yes No Pin condition Pin 4 SHSW GND VDD2
Input Capacity of Pins Item Input capacity of CLK pin Input capacity of ROG pin Symbol CCLK CROG Min. -- -- Typ. 10 10 Max. -- -- Unit pF pF
Recommended Input Pulse Voltage Item Input clock high level Input clock low level Min. 4.5 0.0 Typ. 5.0 -- -2- Max. 5.5 0.5 Unit V V
ILX551A
Electrooptical Characteristics (Ta = 25C, VDD1 = 9V, VDD2 = 5V, Clock frequency = 1MHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm)) Item Secsitivity Sensitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure 9V supply current 5V supply current Total transfer efficiency Output impedance Offset level Symbol R PRNU VSAT VDRK DSNU IL DR SE IVDD1 IVDD2 TTE ZO VOS Min. 30 -- 1.5 -- -- -- -- -- -- -- 92.0 -- -- Typ. 40 2.0 1.8 0.3 0.5 0.02 6000 0.045 4.0 1.8 97.0 600 4.0 Max. 50 8.0 -- 2.0 3.0 -- -- -- 8.0 5.0 -- -- -- Unit V/(lx * s) % V mV mV % -- lx * s mA mA % V Remarks Note 1 Note 2 -- Note 3 Note 3 Note 4 Note 5 Note 6 -- -- -- -- Note 7
Notes) 1. For the sensitivity test light is applied with a uniform intensity of illumination. 2. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1. PRNU = (VMAX - VMIN)/2 VAVE x 100 [%]
The maximum output is set to VMAX, the minimum output to VMIN and the average output to VAVE. 3. Integration time is 10ms. 4. VOUT = 500mV 5. DR = VSAT VDRK
When optical accumulated time is shorter, the dynamic range gets wider because dark voltage is in proportion to optical accumulated time. 6. SE = VSAT R
7. Vos is defined as indicated below.
D31 OS
GND
,
D32 D33 S1 VOS
-3-
Fig. 1. Clock Timing Diagram (without S/H mode)
5
ROG
0
2 3 4
2087
1
5
CLK
0
1
D2 D3 D4
D5 D6
D11 D12 D13 D14 D15
D31 D32 D33 S1 S2 S3 S4
VOUT
Optical black (18 pixels)
Dummy signal (33 pixels)
Effective picture elements signal (2048 pixels)
1-line output period (2087 pixels)
S2045 S2046 S2047 S2048 D34 D35 D36 S37 S38 D39
Dummy signal (6 pixels)
2
-4-
ILX551A
ILX551A
Fig. 2. CLK, VOUT Timing
t1 t2
CLK t3 t4
, , , ,,
t5 VOUT t6
Item CLK pulse rise/fall time CLK pulse duty 1 CLK - VOUT 1 CLK - VOUT 2 1 100 x t3/(t3 + t4)
Symbol t1, t2 -- t5 t6
Min. 0 40 50 30
Typ. 10 50 80 75
Max. -- 60 110 120
Unit ns % ns ns
Fig. 3. ROG, CLK Timing
ROG
t8
t9
t10
CLK t7 t11
Item ROG, CLK pulse timing ROG pulse rise/fall time ROG pulse period
Symbol t7, t11 t8, t10 t9
Min. 500 0 500
Typ. 1000 10 1000 -5-
Max. -- -- --
Unit ns ns ns
ILX551A
Example of Representative Characteristics
Spectral sensitivity characteristics (Standard characteristics)
1.0 0.9 0.8 Relative sensitivity 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 Wavelength [nm] 800 900 1000 Ta = 25C
Dark signal voltage rate vs. Ambient temperature (Standard characteristics)
VDD1, VDD2 supply current vs. Clock frequency (Standard characteristics)
IVDD1 IVDD2
10
10
1
IVDD1, IVDD2 - VDD1, VDD2 supply current [mA] 0 10 20 30 40 50 60
5
5
Dark signal voltage rate
1
0.5
0.5
0.1 Ta - Ambient temperature [C]
0.1 0.1M
1M Clock frequency [Hz]
5M
-6-
Application Circuit
1
5V
9V 22 NC NC NC NC VDD2 (D) VDD1 (A) GND (A) VDD2 (D) GND (A) NC GND (D) ROG 9 10 NC 11 21 20 19 18 17 16 15 14 13 12
VOUT
NC
NC
SHSW
CLK
NC
NC
VDD2 (D)
1
2
3
4
5
6
7
8
0.01
10/16V 3k CLK 2SA1175 ROG
VDD2 (D)
-7-
0.01
22/10V
Output signal
ILX551A
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
ILX551A
Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm
Upper ceramic layer 39N 29N 29N
, ,
0.9Nm Lower ceramic layer Low-melting glass (1) (2) (3) (4)
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered.
3) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. -8-
ILX551A
4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
-9-
Package Outline
Unit: mm
22pin DIP (400mil)
41.6 0.5 12
22
5.0 0.5
1
11
4.0 0.5
0.3
PACKAGE STRUCTURE
PACKAGE MATERIAL
Cer-DIP
LEAD TREATMENT
TIN PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
5.20g
Sony Corporation
DRAWING NUMBER
LS-A18-01(E)
4.35 0.5
2.54
M
0.51
3.65
- 10 -
1. The height from the bottom to the sensor surface is 2.45 0.3mm. 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5.
0.25
H
No.1 Pixel
10.0 0.5
V
0 to 9
7.35 0.5
28.672 (14m X 2048Pixels)
ILX551A

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