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conceptual up6019 1 up6019-ds-c3101, oct. 2017 www.upi-semi.com rebmunredr oe pytegakca pk ramer ymqp9106p ul 62-4x4nfq w high performance, single synchronous step-up converter ?? ?? ? portable charging devices ?? ?? ? quick charge power bank ?? ?? ? i/o supplies ?? ?? ? system power supplies general description applications ordering information features pin configuration the up6019 is a high-efficiency, single synchronous boost converter in power bank and e-cigarette. the proprietary rcot tm technology provides fast transient response and high noise immunity. it supports ceramic output capacitors. this combination is ideal for building modern low duty ratio, untra-fast load step response dc-dc converters. the output voltage ranges from 4v to 15v, and the conversion input voltage ranges is from 3v to 5.5v. the switching frequency is fixed 450khz. it is available in a space saving wqfn4x4- 26l package. ?? ?? ? wide input voltage range: 3v to 5.5v ?? ?? ? output voltage range: 4v to 15v ?? ?? ? built-in 1% 1v reference ?? ?? ? built-in ldo linear voltage regulator ?? ?? ? rcot tm (robust constant on-time) control architecture ?? ?? ? 450khz switching frequency ?? ?? ? 4000ppm/ o c r ds(on) current sensing ?? ?? ? 8ms soft start ?? ?? ? built-in ovp/uvp/ocp/otp ?? ?? ? wqfn4x4-26l package ?? ?? ? rohs compliant and halogen free note: (1) please check the sample/production availability with upi representatives. (2) upi products are compatible with the current ipc/jedec j-std-020 requirement. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suitable for use in snpb or pb-free soldering processes. fb vout comp vdd en 5 25 23 26 vout vreg mode vouit agnd lgrip pgnd 22 1 2 nc vin ocp 21 20 14 1615 6 pgnd pgnd pgnd pgnd pgnd lx lx lx vout lx_c boot 24 4 27 exposed pad i (lx) 28 exposed pad ii (vout) 1312 11 10 9 7 8 wqfn4x4-26l 31 7 1918 upi confidential
conceptual up6019 2 up6019-ds-c3101, oct. 2017 www.upi-semi.com typical application circuit v in =3v~4.5v vin 2.2uf vout 22uf 22uf 22uf v out =5v/9v/12v boot 5.1 0.1uf vreg 10uf lx_c lx 1uh 22uf 22uf pgnd lgrip fb 75k 100pf 1nf 56k (5v) 226k 56k (9v) agnd vdd 2.2uf en ocp 49k comp 4.7k 2.2nf mode 0 psm fccm disable enable 75k (12v) 22uf mcu mcu 100pf upi confidential
conceptual up6019 3 up6019-ds-c3101, oct. 2017 www.upi-semi.com functional pin description .onni pe manni pn oitcnufnip 1p moc .noitasnepmocretrevnoctsoob otkrowtennoitasnepmocatcennoc .dnuorg 2e dom .noitidnocdaolthgilniecivedehtrofnipnoitcelesedom noitarepo piks-eslupniskrowecivedeht,dnuorgotdetcennocsinipsi htnehw .edom mccecrofniskrowecivedeht,hgihdellupsinipsihtnehw.ed om 82,91-71, 3t uov .sniptuptuoretrevnoc 3xfu22muminim ahtiwegatlovtuptuossapyb .roticapaccimarec 4d dv .tupniylppusrewopretrevnoc ciehtrofegatlovsaibsedivorpnipsiht d natuov otnipsihttcennoc.srotalugerraenilv5lanretniehtsrewo pdna .retlifc/r nahtiwtissapyb 5d nga .dnuorglangis 31-9, 6d ngp .nip dngrewopretrevnoc 7g erv .tupniegatlovylppusevirdetag dnatuptuo odlv5 8p irgl .noitcejnielppirrevirdetagedis wol mrofcrseiresatcennoc .poollortnocehtetasnepmocotbfdnadngotpirgl 72,61-4 1x l .tuptuosehctiwslanretni .rotcudnituptuoehtotnipsihttcennoc 0 2c _xl .tuptuosehctiwslanretni croticapacpartstoobehttcennoc toob ot .niptoob 1 2t oob .revirdetag tefsomreppugnitaolfehtrofylppuspartstoob croticapacpartstoobehttcennoc toob c_xlehtdnaniptoobneewteb ehtsedivorproticapacpartstoobeht.tiucricpartstoobam rofotnip ctahterusne.tefsomreppuehtnonrutotegrahc toob ehtraendecalpsi .ci 2 2c n .detcennocyllanretniton 3 2n iv .tupniylppusrewop tuptuoehtottnerrucseilppustahtegatlovtupni .egatlov 4 2p co .gnittesnoitcetorptnerrucrevo dngotnipsihtmorfrotsiseratcennoc .levelnoitcetorptnerrucrevoehttesot 5 2n e .elbanepihc .ecivedehtelbasidotdngottrohs 6 2b f .tupnikcabdeef a.reifilpmarorreehtottupnignitrevniehtsinipsiht .egatlovrotalugertesotdesusidngottuptuomorfredividr otsiser upi confidential
conceptual up6019 4 up6019-ds-c3101, oct. 2017 www.upi-semi.com functional block diagram x(-1/8) psm/fccm switch on-time calculator ramp 1v en / ss control 16.8v 0.3v control logic t on one-shot xcon en uv ov ea pwm fb ocp ocp zc boot pgnd mode voutlx vdd linear regulator vreg agnd lx_c 10ua lgrip vin comp upi confidential
conceptual up6019 5 up6019-ds-c3101, oct. 2017 www.upi-semi.com the up6019 implements a unique rcot tm control topology for the synchronous boost. the rcot tm supports extremely low esr output capacitors and makes the design easier and robust. the output voltage ranges from 4v to 15v. the conversion input voltage ranges from 3v up to 5.5v. adaptive on-time control tracks the preset switching frequency over a wide input and output voltage range while allowing the switching frequency to increase at the step- up of the load. the up6019 has a mode pin to select between force ccm and pulse-skip modes for light load conditions. the strong gate drivers allow low r ds(on) fets for high-current applications. enable and soft start when the en pin voltage rises above the enable threshold voltage (typically 1.8v), the converter enters its start-up sequence. the internal ldo regulator starts immediately and regulates to 5v at the vreg pin. in the second phase, an internal dac starts ramping up the reference voltage from 0v to 1v. smooth and constant ramp-up of the output voltage is maintained during start-up regardless of load current. on-time control and frequency the up6019 does not have a dedicated oscillator that determines switching frequency. however, the device runs with pseudo-constant frequency by feed-forwarding the input and output voltages into its on-time one-shot timer. the rcot tm control adjusts the on-time to be inversely proportional to the input voltage and proportional to the output voltage. this makes the switching freuquency fairly constant in steady state conditions over wide input voltage range. the off-time is modulated by a pwm comparator. the fb node voltage (the mid-point of resistor divider) is compared to the internal 1v reference voltage added with a ramp signal. when both signals match, the pwm comparator asserts a set signal to terminate the off-time (turn off the low-side mosfet and turn on high-side mosfet). the set signal is valid if the inductor current level is below the ocp threshold, otherwise the off-time is extended until the current level falls below the threshold. light load condition in pulse-skip operation while the mode pin is pulled low, the up6019 operates in synchronous and automatically reduces the switching frequency at light load conditions to maintain high efficiency. this reduction of the frequency is achieved smoothly and without increasing vout ripples or load regulation. as the load current is further decreased, it takes longer time to discharge the output capacitor to the level than requires the next on cycle. functional description the transition pin from discontinuous to continuous conduction mode can be calculated as: ) v v ( v v l f i out in out in out osc out = 1 2 1 2 over current limit the up6019 monitors the inductor peak current by low side mosfet r ds(on) when it turns on. the over current limit is triggered once the sensing current level is higher than v ocset . when triggered, the over current limit will keep low side mosfet off even the voltage loop commands it to turn on. the output voltage will decrease if the load continuously demands more current than current limit level and consequently causes v out to decrease faster until uvp occurs and shuts down the up6019. the peak current limit threshold is set by connecting a resistor from ocp to gnd. the ocp pin will source a 10ua current and create a voltage drop across r ocp as the v ocset . v ocset = 10ua x r ocp. when the voltage drop across the low side mosfet equals the voltage across the setting resistor, the peak current limit will be activated. the voltage across lx and gnd pins is compared with v ocset for current limit. the peak current limit level is calculated as: 2 8 ripple ) on ( ds ocset lim _ peak i r v i + = where i ripple is the peak-to-peak inductor ripple current at steady state. over voltage/under voltage protection the up6019 monitors output voltage to detect over voltage and under voltage. when the output voltage becomes higher than 16.8v, the ovp is triggered, low side mosfet is off and the high side mosfet is on. when the feedback voltage is lower than 0.3v, the uvp is triggered, then high side mosfet and low side mosfet are latched. this function is enabled after 5ms following en has become high. uvlo protection the up6019 uses vin under voltage lockout protection (uvlo). when the vin voltage is lower than the uvlo threshold voltage, the switch mode power supply shuts off. this is non-latch protection. over temperature protection the up6019 monitors the temperature of itself. if the temperature exceeds typical 130 o c, the up6019 will be turned off. this is the non-latch protection. it will be recovered once temperature is lower than 100 o c. upi confidential
conceptual up6019 6 up6019-ds-c3101, oct. 2017 www.upi-semi.com (note 1) supply voltage, vout and vdd ----------------------------------------------------------------------------------------------------- -0.3v to +26v lx pin voltage to gnd --------------------------------------------------------------------------------------------------- -0.3v to (vout+ -0.3v) boot pin voltage ---------------------------------------------------------------------------------------------------------------------- -v lx -0.3v to v lx +6v vin and vreg pin voltage ----------------------------------------------------------------------------------------------------------- -0.3v to +6v other pins to gnd ------------------------------------------------------------------------------------------------------------------------- -0.3 v to +6v storage temperature range ------------------------------------------------------------------------------------------------------------- -55 o c to +150 o c lead temperature (soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260 o c esd rating (note 2) hbm (human body mode) --------------------------------------------------------------------------------------------------------------------- 2kv mm (machine mode) ----------------------------------------------------------------------------------------------------------------------------- 200v (note 4) input voltage, v in ----------------------------------------------------------------------------------------------------------------------------- --- 3v to 5.5v output voltage, v out --------------------------------------------------------------------------------------------------------------------------- 4 v to 13v output load, p outmax ----------------------------------------------------------------------------------------------------------------------------------- 20w operating junction temperature ra nge ------------------------------------------------------------------------------------------ -40 o c to +125 o c operating ambient temperature ra nge ------------------------------------------------------------------------------------------ -40 o c to +85 o c note 1. stresses listed as the above absolute maximum ratings may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 o c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions. absolute maximum rating thermal information recommended operation conditions package thermal resistance (note 3) wqfn4x4-26l ja, controller and hs -------------------------------------------------------------------------------------------------------- tbd wqfn4x4-26l ja, ls ------------------------------------------------------------------------------------------------------------------------ tbd wqfn4x4-26l jc, controller and hs ------------------------------------------------------------------------------------------------------- tbd wqfn4x4-26l jc, ls ------------------------------------------------------------------------------------------------------------------------ tbd power dissipation, p d @ t a = 25 c wqfn4x4-26l p d, controller and hs --------------------------------------------------------------------------------------------------------- tbd wqfn4x4-26l p d, ls -------------------------------------------------------------------------------------------------------------------------- tb d upi confidential
conceptual up6019 7 up6019-ds-c3101, oct. 2017 www.upi-semi.com (v dd = 5v, t a =25 o c, unless otherwise specified) electrical characteristics retemara pl obmy ss noitidnoctse tn i mp y tx a ms tinu ylppusrewop dlohserht olvu ni vv nivolvu gnisi r3 8. 29 . 27 9. 2v siseretsy h5 1. 02 . 05 2. 0v tnerrucylppus ni vi niv v ne v,v5= bf i,v1.1= tuo daolon =- -0 6 3- -a u tnerrucylppus dd vi ddv v ne v,v5= bf i,v1.1= tuo daolon =- -6 . 01a m tnerrucnwodtuhs ni vi ds_niv v ne i,v0= tuo daolon =- -- -0 1a u tnerrucnwodtuhs dd vi ds_ddv v ne i,v0= tuo daolon =- -- -1a u egatlovecnereferlanretni egatlovkcabdee fv bf t,noitidnocmcc a 52= o c9 9. 011 0. 1v tnerructupnibf vi bf v bf t,v1= a 52= o c- -1 0. 02 . 0a u egrahcsidtuovfobf vv sid_bf egrahcsidtuo v- -1 . 1- - v siseretsy h- -5 0. 0- - sehctiwsrewop ecnatsiserhctiwsrepp ur nosd,gu - -9- -m ? ecnatsiserhctiwsrewo lr nosd,gl - -6- -m ? lortnocycneuqerfdnaytud emi-ffo mumini mt nim_ffo v ni v,v6.3= tuo v5 =- -0 0 7- -s n emit-no mumini mt nim_no v ni v6.3 =- -0 4 2- -s n ycneuqer ff ws v ni v,v7.3= tuo mcc @ v9 =- -0 5 4- -z hk tratstfos emittratstfo st ss %59=tuovothgihnev mor f- -8- -s m dlohserhtcigol egatlovdlohserhtnip n ev ne elban e8 . 1- -- - v elbasi d- -- -5 .0 emit-n ot no r tr = ,nep of xl zhk054= v ni v,v7.3= tuo i,v9= tuo daolon= - -8 03. 1- -s u tnerructupnin ei ne v5=ne v- -- -1a u esnestnerruc:noitcetorp tnerrucecruos pc oi sc v pco v1 =9 0 11 1a u feocpme t- -0 00 4- -/ mpp o c upi confidential
conceptual up6019 8 up6019-ds-c3101, oct. 2017 www.upi-semi.com electrical characteristics retemara pl obmy ss noitidnoctse tn i mp y tx a ms tinu pvo dnapvu:noitcetorp egatlovdlohserhtpv ov pvo gnisi r3 .5 18 .6 13 .8 1v egatlovdlohserhtpv uv pvu v bf - -3 . 0- -v emityalednoitagaporp pv ut ledpvu - -3 . 3- -s m emityaled pvutuptu ot nepvu elbakrow pvuotelbane mor f- -5 .3 1- -s m egatlov odl gerv egatlovtuptuo od lv ger 526. 40 . 55 73. 5v tnerructuptuo od li ger - -- -0 5a m egatlovtuo pord od lv pord ,v5.4= dd vi ger am02 =- -0 0 3- -v m nwodtuhslamreht dlohserhtnwodtuhslamreh tt nds erutarepmetnwodtuh s- -0 3 1- - o c siseretsy h- -0 3- - o c upi confidential
conceptual up6019 9 up6019-ds-c3101, oct. 2017 www.upi-semi.com typical operation characteristics this page is intentionally left blank and will be updated when data is available. upi confidential
conceptual up6019 10 up6019-ds-c3101, oct. 2017 www.upi-semi.com application information setting output voltage the output voltage is set by an external resistor divider. with the given feedback voltage, vfb, and feedback bias current, ifb, the voltage divider can be calculated as: vout r2 r1 i fb v fb ? ? ? ? ? ? + = 2 1 1 r r v v fb out the internal vref is 1v with 1% accuracy. component selection external component selection begins with inductor value selection based on the considerations of the output voltage, output current, and the maximum/minimum input voltages. inductor selection inductor selection should consider the inductor value, rated current, dcr, size, core material, and cost. the inductor value is selected based on the consideration of inductor ripple current and the inductor rated saturation current should be higher than the peak current at maximum load. the inductor should have low core loss at 450khz and low dcr for better efficiency. depending on the application, the inductor values 1uh is recommended. input capacitor selection for better input voltage filtering, the low esr of capacitor is highly recommended. the vin pin is the power supply for the up6019. a 2.2uf ceramic bypass capacitor is recommended as close as possible to the vin pin of the ic. the vreg pin is the output of the internal ldo. a ceramic capacitor of more than 1uf is required at the vreg pin to get a stable operation of the ldo. for the power stage, because of the inductor current ripple, the input voltage changes if there is parasitic inductance and resistance between the power supply and the inductor. it is needed to have large input capacitance to make the input voltage ripple less. it is recommended to use three 22uf x5r or x7r type ceramic capacitors for most applications. output capacitor selection for small output voltage ripple, it is recommends a low- esr ceramic capacitor. to use three 22uf ceramic output capacitors work for most applications is recommended. larger capacitor values can be used to improve the load transient response. take care when evaluating a capacitors de-rating under dc bias. the bias can significantly reduce capacitance. ceramic capacitors can lose most of their capacitance at rated voltage. therefore, reserve margin on the voltage rating to ensure adequate effective capacitance. from the required output voltage ripple, the output ripple voltage can be calculated as: ? ? ? ? ? ? ? ? + ? = ? out sw l out c f esr i v 8 1 where f sw = switching frequency, c out = output capacitance and ? i l = inductor ripple current, esr = equivalent series resistance of the used output capacitor. upi confidential
conceptual up6019 11 up6019-ds-c3101, oct. 2017 www.upi-semi.com application information application circuit with true output short protection with external n-mosfet control *fb pin reserve a 0402 mlcc cap to agnd, default nc. v in =3v~4.5v vin 2.2uf vout 22uf 22uf 22uf v out =5v/9v/12v boot 5.1 0.1uf vreg 10uf lx_c lx 1uh 22uf 22uf pgnd lgrip fb 75k 100pf 1nf 56k (5v) 227k 56k (9v) agnd vdd 2.2uf en ocp 49k comp 4.7k 2.2nf mode 0 psm fccm disable enable 75k (12v) 22uf mcu mcu 1uf mcu 1m vbus d+ d- gnd usb 100pf *nc 100pf upi confidential
conceptual up6019 12 up6019-ds-c3101, oct. 2017 www.upi-semi.com application information layout consideration for best performance of the up6019, the following guidelines are recommended. 1. input and output capacitors should be placed close to the ic and connected to ground plane to reduce noise coupling. 2. the gnd should be connected to a strong ground plane for heat sinking and noise protection. 3. keep the main current traces as short and wide as possible. 4. lx node of dc-dc converter is with high frequency voltage swing. to prevent radiation of high frequency noise, the inductor should be placed close to the ic. 5. please keep vin, fb, lgrip and ocp trace away from the noise source such as lx node and place cvin close to the ic and connected to ground plane to reduce supply ripple. 6. place the feedback components as close as possible to the ic and keep away from the noise source. 7. since the up6019 is high performance converter and also running high currents, the layout should be consideration of the thermal as well. a thermal pad improves the thermal capabilities of the package, please soldered exposed pad to the large plate. 8. the exposed pad ii(vout) have the most heating of the ic (shown as figure1), please increase vout copper plane as wide as possible to get better thermal performance. gnd vout gnd gnd gnd c in inductor c out vin c vdd via for vin via for gnd via for vout via for lgrip_r via for vdd c comp r comp c feedforward fb vout comp vdd en 5 25 23 26 vout vreg mode vout agnd lgrip pgnd 22 1 2 nc vin ocp 21 20 14 1615 6 pgnd pgnd pgnd pgnd pgnd lx lx lx vout lx_c boot 24 4 27 exposed pad i (lx) 28 exposed pad ii (vout) 1312 11 10 9 7 8 wqfn4x4-26l 31 7 1918 via for lgrip_r c lgrip_gnd c lgrip_fb figure 1. layout reference of wqfn4x4-26wl upi confidential
conceptual up6019 13 up6019-ds-c3101, oct. 2017 www.upi-semi.com package information note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. wqfn4x4 - 26l 3.90 - 4.10 pin 1 mark bottom view - exposed pad 3.20 - 3.40 0.15 - 0.25 0.225 bsc 3.90 - 4.10 0.00 - 0.05 0.20 ref 0.70 - 0.80 0.15 - 0.25 0.55bsc 3.25 - 3.45 0.25 - 0.45 0.50 bsc 0.15 - 0.25 0.517bsc 0.10 - 0.20 0.55 bsc 0.10 - 0.20 0.10 - 0.20 0.325bsc 0.45 bsc 0.875 bsc 0.25bsc 0.25bsc 0.30bsc 0.15 - 0.25 1.225 - 1.425 1.225 - 1.425 1.35 bsc 0.45 bsc 0.25 bsc 0.958 - 1.158 0. 55 bsc 0.45 bsc 0.45 bsc 1.30bsc 0.45bsc upi confidential
conceptual up6019 14 up6019-ds-c3101, oct. 2017 www.upi-semi.com important notice upi and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. upi products are sold subject to the taerms and conditions of sale supplied at the time of order acknowledgment. however, no responsibility is assumed by upi or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. no upi components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. no license is granted by implication or otherwise under any patent or patent rights of upi or its subsidiaries. copyright ( c ) 2017, upi semiconductor corp. upi semiconductor corp. headquarter 9f.,no.5, taiyuan 1st st. zhubei city, hsinchu taiwan, r.o.c. tel : 886.3.560.1666 fax : 886.3.560.1888 upi semiconductor corp. sales branch office 12f-5, no. 408, ruiguang rd. neihu district, taipei taiwan, r.o.c. tel : 886.2.8751.2062 fax : 886.2.8751.5064 upi confidential

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