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quasi -r esonant control lers with integrated power mosfet str- y6700 series str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 1 j un . 09 , 2 01 6 general descriptions the str - y6700 series are power ics for switching power supplies, incorporating a mosfet and a quasi - resonant controller ic. including an auto standby function in the controller, the product achieves the low standby power by the automatic switching between the pwm operation in normal operation , one bottom - skip operation under m edium to light load conditions and the burst - oscillation under light load conditions. the product achieves high cost - performance p ower supply systems with few external components. features ? multi - mode control t he optimum operation depending on load conditions is changed automatically and is achieved high efficiency operation across the full range of loads . operation mode normal load ------------------------- quasi - resonant mode medium to light load ------------- one b ottom - skip mode light load -------------------------- burst oscillation mode (auto standby function) ? no load power consumption p in < 30 mw (100v ac ) p in < 50 mw (230v ac ) ? leading edge blanking function ? bias assist function ? built - in startup circuit reduces ? protections overcurrent protection 1 ( ocp 1): pulse - by - pulse, with input compensation function overcurrent protection 2 ( ocp 2) (1) : l atched shutdown overload protection ( olp ): l atched shutdown overvoltage protection ( ovp ): l atched shutdown thermal shutdown protection ( tsd ): l atched shutdown (1) products with the l ast letter "a " don t have the ocp2 function. typical application nf gndfb/olp s/ocp vcc d/st 2 1 7 542 3 str-y6700 6 bd vac c1 d2 r2 c3 t1 d51 c51 r51 r52 u51 r54r56 c52 d p s pc1 pc1 c4 r ocp c y br1 r53 r55 l51 c53 c5 r bd2 r bd1 dz bd c bd r3 u1 vout(+) vout(-) package to220f -7l not to scale lineup ? electrical characteristics products v dss (min.) r ds(on) (max.) str C y6735 str C y6735a 500 v 0.8 str C y6753 650 v 1.9 str C y6754 1.4 str C y6766 str C y6766a 800 v 1.7 str C y6765 2.2 str C y6763 str C y6763a 3.5 ? output power, p out (2) products p out (open frame) 380 vdc 85~265v ac str C y6735 str C y6735a 120 w(100v ac ) C str C y6753 100 w 60 w s tr C y6754 120 w 67 w str C y6766 str C y6766a 140 w 80 w str C y6765 120 w 70 w str C y6763 str C y6763a 80 w 50 w (2) the output power is actual continues power that is measure d at 50 c ambient. the peak output power can be 120 to 140 % of the value stated here. core size, on duty, and thermal design affect the output power. it may be less than the value stated here. applications ? white goods ? office automation equipment ? industrial equipment http://www.sanken - ele.co.jp/en/ downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 2 j un . 09 , 2 01 6 contents general descriptions ------------------------------------------------------------------------------------------ 1 1. absolute maximum ratings ----------------------------------------------------------------------------- 3 2. electrical characterist ics -------------------------------------------------------------------------------- 4 3. performance curves -------------------------------------------------------------------------------------- 6 3.1 derating curves ------------------------------------------------------------------------------------ 6 3.2 ambient temperature versus power dissipation curves ---------------------------------- 6 3.3 mosfet safe operating area curves ------------------------------------------------------- 8 3.4 transient thermal resistance curves --------------------------------------------------------- 9 4. block diagram ------------------------------------------------------------------------------------------- 10 5. pin configuration definitions ------------------------------------------------------------------------- 10 6. typical application ------------------------------------------------------------------------------------- 11 7. physical dimensions ------------------------------------------------------------------------------------ 12 8. marking diagram --------------------------------------------------------------------------------------- 12 9. operational description ------------------------------------------------------------------------------- 13 9.1 startup operation ------------------------------------------------------------------------------- 13 9.2 undervoltage lockout (uvlo) --------------------------------------------------------------- 13 9.3 bias assist func tion ----------------------------------------------------------------------------- 13 9.4 soft start function ------------------------------------------------------------------------------ 14 9.5 constant output voltage control ------------------------------------------------------------ 15 9.6 leading edge blanking function ------------------------------------------------------------- 15 9.7 quasi - resonant operation and bottom - on timing setup ------------------------------ 15 9.7.1 quasi - resonant operation ------------------------------------------------------------ 15 9.7.2 bottom - on timing setup ------------------------------------------------------------- 16 9.8 bd pin blanking time -------------------------------------------------------------------------- 17 9.9 multi - mode control ----------------------------------------------------------------------------- 18 9.9.1 one bottom - skip quasi - resonant operation ------------------------------------- 18 9.9.2 automatic standby mode function ------------------------------------------------- 19 9.10 maximum on - time limitation function --------------------------------------------------- 19 9.11 overcurrent protection (ocp) ---------------------------------------------------------------- 20 9.11.1 overcurrent protection 1 (ocp1) --------------------------------------------------- 20 9.11.2 overcurrent protection 2 (ocp2) --------------------------------------------------- 20 9.11.3 ocp1 input compensation function ----------------------------------------------- 20 9.11.4 when overcurrent input compensation is not required ---------------------- 23 9.12 overload protection (olp) -------------------------------------------------------------------- 23 9.13 overvoltage protection (ovp) ---------------------------------------------------------------- 24 9.14 thermal shutdown (tsd) ---------------------------------------------------------------------- 24 10. design notes ---------------------------------------------------------------------------------------------- 25 10.1 external components --------------------------------------------------------------------------- 25 10.2 transformer design ----------------------------------------------------------------------------- 27 10.3 pcb trace layout and component placement -------------------------------------------- 28 11. pattern layout example ------------------------------------------------------------------------------- 30 12. reference design of power supply ------------------------------------------------------------------ 31 important not es ------------------------------------------------------------------------------------- 33 downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 3 j un . 09 , 2 01 6 1. absolute maximum ratings ? c urrent polarities are defined as follows: a current flow going into the ic (sinking) is positive current (+); and a current flo w coming out of the ic (sourcing) is negative current ( ? ). ? unless otherwise specified t a = 25 c parameter symbol test conditions pins rating units notes drain peak current (1) i dpeak single pulse 1 C 2 6.7 a str C y6763 / 63a 8.9 str C y6765 9.2 str C y6753 10.5 str C y6766 / 66a 11.0 str C y675 4 14.6 str C y6735 / 35a maximum switching current (2) i dmax single pulse ta= ? 20 to 125c 1 C 2 6.7 a str C y6763 / 63a 8.9 str C y6765 9.2 str C y6753 10.5 str C y6766 / 66a 11.0 str C y6754 14.6 str C y6735 / 35a avalanche energy (3)(4) e as i lpeak =2.3a 1 C 2 60 mj str C y6763 / 63a i lpeak =2.6a 77 str C y6765 i lpeak =2.9a 99 str C y6753 i lpeak =3.2a 116 str C y6766 / 66a i lpeak =4.1a 198 str C y6754 i lpeak =3.5a 152 str C y6735 / 35a d/st pin voltage v startup 1 ? 4 ? 1.0 to v dss v s/ocp pin voltage v ocp 2 C 4 ? 2.0 to 6.0 v vcc pin voltage v cc 3 C 4 35 v fb/olp pin voltage v fb 5 C 4 ? 0.3 to 7.0 v fb/olp pin sink current i fb 5 C 4 10.0 ma bd pin voltage v bd 6 C 4 ? 6.0 to 6.0 v power dissipation ( 5) p d1 with infinite heatsink 1 C 2 19.9 w str C y6763 / 63a 21.8 str C y6765 20.2 str C y6753 23.6 str C y6766 / 66a 21.5 str C y6735 / 35a str C y6754 without heatsink 1 C 2 1.8 w control part power dissipation p d2 v cc i cc 3 C 4 0.8 w internal fr ame temperature in operation t f ? ? 20 to 115 c operating ambient temperature t op ? ? 20 to 115 c storage temperature t stg ? ? 40 to 125 c junction temperature t ch ? 150 c (1) refer to 3.3 mosfet safe operating area curves (2) the maximum switching current is the d rain current determined by the drive voltage of the ic and threshold voltage (v th ) of the mosfet. (3) refer to figure 3-2 avalanche energy derating coefficient curve (4) single pulse, v dd = 99 v, l = 20 mh (5) refe r to 3.2 t a -p d1 curves. downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 4 j un . 09 , 2 01 6 2. electrical characteristics ? the polarity value for current specifies a sink as "+," and a source as " ? ," referencing the ic. ? unless otherwise specified, t a = 25 c, v cc = 20 v parameter symbol test conditions pins min. typ. max. units notes power supply startup operation operation start voltage v cc(on) 3 ? 4 13.8 15.1 17.3 v operation stop vol tage (1) v cc(off) 3 ? 4 8.4 9.4 10.7 v circuit current in operation i cc(on) 3 ? 4 ? 1.3 3.7 ma circuit current in non - operation i cc(off) v cc = 13 v 3 ? 4 ? 4.5 50 a startup circuit operation voltage v start(on) 1 ? 4 42 57 72 v startup current i cc(startup) v cc = 13 v 3 ? 4 ? 4.5 ? 3.1 ? 1.0 ma startup current biasing threshold voltage v cc(bias) 3 ? 4 9.5 11.0 12.5 v pwm switching frequency f osc 1 ? 4 18.4 21.0 24.4 khz soft start operation duration t ss 1 ? 4 ? 6.05 ? ms normal operation bottom - skip operation threshold voltage 1 v ocp(bs1) 2 ? 4 0.487 0.572 0.665 v bottom - skip operation threshold voltage 2 v ocp(bs2) 2 ? 4 0.200 0.289 0.380 v quasi - resonant operation threshold voltage 1 v bd(th1) 6 ? 4 0.14 0.24 0.34 v quas i- resonant operation threshold voltage 2 (2) v bd(th2) 6 ? 4 0.07 0.17 0.27 v maximum feedback current i fb(max) 5 ? 4 ? 320 ? 205 ? 120 a standby operation standby operation threshold voltage v fb(stbop) 5 ? 4 0.45 0.80 1.15 v protected operat ion maximum on - time t on(max) 1 ? 4 30.0 40.0 50.0 s leading edge blanking time t on(leb) 1 ? 4 ? 455 ? ns str C y67 35 / 35 a/ 65 / 66 / 54 ? 470 ? str C y6763 / 63a/ 53 overcurrent detection 1 threshold voltage in input compensation operation v ocp(l) v bd = C 3v 2 ? 4 0.560 0.660 0.760 v overcurrent detection 1 threshold voltage in normal operation v ocp(h) v bd = 0v 2 ? 4 0.820 0.910 1.000 v overcurrent detection 2 threshold voltage v ocp(la.off) 2 ? 4 1.65 1.83 2.01 v products without the l as t letter "a" (1) v cc(off) < v cc(bias) always. (2) v bd(th2) < v bd(th1) always. downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 5 j un . 09 , 2 01 6 parameter symbol test conditions pins min. typ. max. units notes bd pin source current i bd(o) 6 ? 4 ? 250 ? 83 ? 30 a olp bias current i fb(olp) 5 ? 4 ? 15 ? 10 ? 5 a olp threshold voltage v fb(olp) 5 ? 4 5.50 5.96 6.40 v fb pin maximum voltage in feedback operation v fb(max) 5 ? 4 3.70 4.05 4.40 v ovp threshold voltage v cc(ovp) 3? 4 28.5 31.5 34.0 v thermal shutdown operating temperature t j(tsd) ? 135 ? ? c mosfet drain - to - source breakdown voltage v dss i ds =300a 1 C 2 500 ? ? v str - y6735 / 35a 650 ? ? str - y6753 / 54 80 0 ? ? str - y6763 / 63a / 65 /66 /66a drain leakage current i dss v ds =v dss 1 C 2 ? ? 300 a on resistance r ds(on) 1 C 2 ? ? 0.8 str - y6735 / 35a ? ? 1.4 str C y6754 1.7 str C y6766 / 66a 1.9 str C y6753 2.2 str C y6765 ? ? 3.5 str C y6763 / 63a switching time t f 1 C 2 ? ? 250 ns str C y6753 / 63 / 63a ? ? 300 ns str - y6735 / 35a / 54 / 66 / 66a / 65 thermal resistance channel to frame thermal resistance ( 3) ch -f ? ? 2.4 2.7 c/w str - y6735 / 35a / 54 ? 1.9 2. 2 str C y6766 / 66a ? 2.7 3.1 str C y6753 ? 2.3 2.6 str C y6765 ? 2.8 3.2 str C y6763 / 63a channel to case thermal resistance ( 4) ch -c ? ? 5.1 5.9 c/w str - y6735 / 35a / 54 ? 4.6 5.3 str C y6766 / 66a ? 5.4 6.2 str C y6753 ? 5.0 5.8 str C y6765 ? 5.5 6.3 str C y6763 / 63a (3) ch -f is thermal resist ance between channel and internal frame. (4) ch -c is thermal resist ance between channel and case. case temperature is measured at the backside surface . downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 6 j un . 09 , 2 01 6 3. performance curves 3.1 derating curves figure 3-1 soa temperature derating coefficient curve figure 3-2 aval anche energy derating coefficient curve 3.2 ambient temperature versus power dissipation curves ? str C y6735 str C y6735a ? str C y6753 0 20 40 60 80 100 0 25 50 75 100 125 safe operating area temperature derating coefficient (%) internal frame temperature, t f ( c) 0 20 40 60 80 100 25 50 75 100 125 150 e as temperature derating coefficient (%) channel temperature, t ch ( c) 0 5 10 15 20 25 30 0 25 50 75 100 125 150 power dissipation, p d1 (w) ambient temperature, t a ( c ) 1.8 21.5 115 with infinite heatsink without heatsink 0 5 10 15 20 25 30 0 25 50 75 100 125 150 power dissipation, p d1 (w) ambient temperature, t a ( c ) 1.8 20.2 115 with infinite heatsink without heatsink 115 downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 7 j un . 09 , 2 01 6 ? str C y6754 ? str C y6763 str C y6763a ? str C y6765 ? str C y6766 str C y6766a 0 5 10 15 20 25 30 0 25 50 75 100 125 150 power dissipation, p d1 (w) ambient temperature, t a ( c ) with infinite heatsink without heatsink 1.8 21.5 115 0 5 10 15 20 25 30 0 25 50 75 100 125 150 power dissipation, p d1 (w) ambient temperature, t a ( c ) 1.8 19.9 115 with infinite heatsink without heatsink 0 5 10 15 20 25 30 0 25 50 75 100 125 150 power dissipation, p d1 (w) ambient temperature, t a ( c ) 1.8 21.8 115 with infinite heatsink without heatsink 0 5 10 15 20 25 30 0 25 50 75 100 125 150 power dissipation, p d1 (w) ambient temperature, t a ( c ) 1.8 23.6 115 with infinite heatsink without heatsink downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 8 j un . 09 , 2 01 6 3.3 mosfet safe operating area curves ? when the ic is used, the safe operating area curve should be multiplied by t he temperature derating c oefficient derived from figure 3-1. ? the broken line in the safe operating area curve is the drain current curve limited by on - resistance. ? unless otherwise specified, t a = 25 c, single pulse ? str C y6735 , str C y6735a ? str C y6753 ? str C y6754 ? str C y6763 , str C y6763a ? str C y6765 ? str C y6766 , str C y6766a 0.1 1 10 100 10 100 1000 drain current, i d (a) drain - to - source voltage (v) 0.01 0.1 1 10 100 10 100 1000 drain current, i d (a) drain - to - source voltage (v) 0.1 1 10 100 10 100 1000 drain current, i d (a) drain - to - source voltage (v) 0.01 0.1 1 10 10 100 1000 drain current, i d (a) drain - to - source voltage (v) 0.01 0.1 1 10 10 100 1000 drain current, i d (a) drain - to - source voltage (v) 0.1 1 10 100 10 100 1000 drain current, i d (a) drain - to - source voltage (v) 0.1ms 1ms 0.1ms 1ms 0.1ms 1ms 0.1ms 1ms 0.1ms 1ms 0.1ms 1ms downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 9 j un . 09 , 2 01 6 3.4 transient thermal resistance curves ? str C y6735 , str C y6735a , st rC y6754 , str C y6765 ? str C y6753 , str C y6763 , str C y6763a ? str C y6766 , str C y6766a 0.001 0.01 0.1 1 10 transient thermal resistance ch - c ( c/w) time (s) 0.001 0.01 0.1 1 10 transient thermal resistance ch - c ( c/w) time (s) 0.001 0.01 0.1 1 10 transient thermal resistance ch - c ( c/w) time (s) 1 10 100 1m 10m 100m 1 10 100 1m 10m 100m 1 10 100 1m 10m 100 m downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 10 j un . 09 , 2 01 6 4. block diagram uvlo reg / i const startup vcc gnd d/sts/ocp bd 12 6 4 3 bd_str-y6700_r1 fb/olp 5 nf 7 latch logic osc bd fb/stb olp ocp/bs drv 5. pin configuration definitions 1 5 d/sts/ocp vcc gnd fb/olp bd (lf3051) 24 6 7 nf 3 pin name descriptions 1 d/st mosfet drain and startup c urrent input 2 s/ocp mosfet source and overcurrent protection (ocp) signal input 3 vcc power supply voltage input for control part and overvoltage protection (ovp) signal input 4 gnd ground 5 fb /olp constant voltage control signal input and over lo ad protection (olp) signal input 6 bd bottom detection signal input, input compensation detection signal input 7 nf* (non - function) * for stable operation, nf pin should be connected to gnd pin, using the shortest possible path . downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 11 j un . 09 , 2 01 6 6. typical application ? the pcb traces d/st pins should be as wide as possible, in order to enhance th ermal dissipation. ? in applications having a power supply specified such that d/st pin has larg e transient surge voltages, a clamp snubber circuit of a capacitor - resistor - diode (crd) combination should be added on the primary winding p, or a damper snubber circuit of a capacitor (c) or a resistor - capacitor (rc) combination should be added between the d/st pin and the s/ocp pin. ? for stable operation, nf pin should be connected to gnd pin, using the shortest possible path. nf gnd fb/olp s/ocp vcc d/st 2 1 7 54 2 3 str-y6700 6 bd vac c1 d2 r2 c3 t1 d51 c51 r51 r52 u51 r54r56 c52 d p s pc1 pc1 c4 r ocp c y br1 r53 r55 l51 c53 c v c5 r bd2 r bd1 dz bd c bd r3 u1 vout(+) vout(-) c2 r1 d1 crd clamp snubber c(rc)damper snubber figure 6-1 typical application downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 12 j un . 09 , 2 01 6 7. physical dimensions ? to220f -7l 0.5 0.5 0.5 0.5 0.45 +0.2 -0.1 r-end r-end 2.6 0.1 2.6 4.2 3.2 +0.2 2.8 0.15 2 10.4 0.5 15 10 1 2 3 4 5 6 7 0.2 1.1 0.2 0.2 5p1.170.15 5.850.15 0.3 0.2 5.6 gate burr measured at pin base measured at pin base measured at pin tip 2.540.6 measured at pin tip 5.080.6 50.5 50.5 0.15 7-0.62 -0.1 +0.2 7-0.55 measured at pin base front view side view notes : 1) dimension is in millimeters . 2) leadform: lf no. 3051 3) gate burr indicates protrusion of 0.3 mm (max .). 4) pin treatment pb - free. device composition compliant with the rohs directive. 8. marking diagram 2 1 7 part number str y 6 7 y m d d x lot number: y is the last digit of the year of manufacture (0 to 9) m is the month of the year (1 to 9, o, n or d ) dd is the day of the month (01 to 31) x is the control number 2 downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 13 j un . 09 , 2 01 6 9. operational description ? all of the parameter values used in these descriptions are typical values, unless they are specified as minimum or maximum. ? with regard to current direction, "+" indicates sink current (toward the ic) and " C " indicates source current (from the ic). 9.1 startup operation figure 9 -1 shows the circuit around ic. figure 9-2 shows the start up operation. vac c1 d2 r2 c3 t1 d p br1 vcc gnd d/st 1 4 3 u1 v d figure 9-1 vcc pin peripheral circuit v cc(on) vcc pin voltage drain current, i d t start figure 9-2 startup operation the ic incorporates the startup circuit. the circuit is connected to d/st pin. when d/st pin voltage reaches to startup circuit operation voltage v start(on) = 57 v, the startup circuit starts operation. during the startup process, the constant current, i cc(startup) = ? 3.1 ma, charges c3 at vcc pin. when vcc pin voltage increases to v cc(on) = 15.1 v, the control circuit starts operation. during the ic operation, the voltage rectified the auxiliary winding voltage, v d , of figure 9 -1 becomes a power source to the vcc pin. after switching operation begins, the startup circuit turns off automatically so that its current consumption becomes zero. the approximate value of auxiliary winding voltage is about 20 v, taking account of the winding turns of d winding so that vcc pin voltage becomes equation (1) within the specification of input and output voltage variation of power supply. .) (min v v .) (max v ) ovp (cc cc )bias(cc < < ? 12.5 (v) < < cc v 28 .5 (v) (1) the startup time of ic is determined by c3 capacitor value. the approximate startup time t start (shown in figure 9-2 ) is calculated as follows: ) stratup (cc )int(cc ) on (cc start i v v c3 t = (2) where, t start : startup time of ic (s) v cc(int) : initial voltage on vcc pin (v) 9.2 undervoltage lockout (uvlo) figure 9-3 shows the relationship of vcc pin voltage and circuit current i cc . when vcc pin vol tage decreases to v cc(off) = 9.4 v, the control circuit stops operation by undervoltage lockout ( uvlo ) circuit, and reverts to the state before startup. circuit current, i cc v cc off v cc on vcc pin voltage start stop figure 9-3 relationship between vcc pin voltage and i cc 9.3 bias assist function by the bias assist f unction , the startup failure is prevented and the latched state is kept. the bias assist function is activated , when the vcc voltage decreases to the startup current biasing threshold voltage , v cc(bias) = 11.0 v , in either of following condition: the fb pin voltage is the standby operation threshold voltage, v fb(stbop) = 0.80 v o r less or the ic is in the latched state due to activating the protection function. downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 14 j un . 09 , 2 01 6 when t he bias assist f unction is activated , the vcc pin voltage is kept almost constant voltage, v cc(bias) by providing the startup current, i startup , from the startup circuit. thus, the vcc pin voltage is kept more than v cc(off) . since the startup failure is prevented by the bias assist f unction , the value of c3 connected to vcc pin can be small . thus, the startup time and the response time of the ovp become shorter. the o peration of t he bias assist f unction in startup is as follows. it is necessary to check and adjust the startup process based on actual operation in the application, so that poor starting conditions may be avoided. figure 9 -4 shows vcc pin voltage behavior during the startup period. after vcc pin voltage increases to v cc(on) = 15.1 v at startup, the ic starts the operation. then circuit current increases and vcc pin voltage decrease s. at the same time, the auxiliary winding voltage v d increases in proportion to output voltage. these are all balanced to produce vcc pin voltage. when vcc pin voltage is decrease to v cc(off) = 9.4 v in startup operation , the ic stops switching operation and a startup failure occurs . when the output load is light at startup, the output voltage may become more than the target voltage due to the delay of feedback circuit. in this case, the fb pin voltage is decreased by the feedback control. when t he fb pin voltage decreases to the standby operation threshold voltage , v fb(stbop) = 0.80 v , or less, the ic stops switching operation and vcc pin voltage decreases. when vcc pin voltage decrea ses to v cc(bias) , t he bias assist function is activated and the startup failure is prevented . ic starts operation vcc pin voltage v cc(on) v cc(bias) v cc(off) startup failure startup success target operating voltage time bias assist period increase with rising of output voltage figure 9-4 vcc pin voltage during startup period 9.4 soft start function figure 9-5 shows the behavior of vcc pin voltage, drain current and bd pin voltage during the startup period. the ic activates the soft start circuitry during the startup period. soft start is fixed to t ss = 6.05 ms . during the soft start period, over current threshold is increased step - wisely ( 4 steps). this function reduces the voltage and the current stress of mosfet and secondary side rectifier diode. during the soft start operation period, the oper ation is in pwm operation, at an internally set operation frequency, f osc = 21.0 khz . until bd pin voltage becomes the following condition after the soft start time, the switching operation is pwm control of f osc = 21.0 khz. when bd pin voltage , v bd , becomes the following condition, the ic starts quasi - resonant operation. quasi - resonant operation starting condition ? v bd v bd(th1) = 0.24 v ? the effective pu lse width of quasi - resonant signal is 1.0 s or more (refer to figure 9- 12 ) after the soft start period, d/st pin current, i d , is limited by the overcurrent protection (ocp), until the output voltage increases to the target operating voltage. this period is given as t lim . when t lim is longer than the olp delay time, t olp , the output power is limited by the olp operation (olp). thus, the t olp must be set longer than t lim ( refer to section 9.13 ). v cc(on) v cc(off) time vcc pin voltage normal operation d/st pin current, i d t ss time v bd(th1) time bd pin voltage pwm operation quasi-resonant operation startup of smps startup of ic t start t lim the effective pulse width is 1.0s or more pwm operation quasi-resonant operation enlarged waveform figure 9-5 v cc and i d and v bd behavior during startup downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 15 j un . 09 , 2 01 6 9.5 constant output voltage control the ic achieves the constant voltage control of the power supply o utput by using the current - mode control method, which enhances the response speed and provides the stable operation. the ic compares the voltage, v rocp , of a current detection resistor with the target voltage, v sc , by the internal fb comparator, and contro ls the peak value of v rocp so that it gets close to v sc , as shown in figure 9-6 and figure 9-7 . v sc is generated by the fb/olp pin voltage. ? light load conditions when load conditio ns become lighter, the output voltage, v out , increases. thus, the feedback current from the error amplifier on the secondary - side also increases. the feedback current is sunk at the fb/olp pin, transferred through a photo - coupler, pc1, and the fb/olp pin v oltage decreases. thus, v sc decreases, and the peak value of v rocp is controlled to be low, and the peak drain current of i d decreases. this control prevents the output voltage from increasing. ? heavy load conditions when load conditions become greater, th e ic performs the inverse operation to that described above. thus, v sc increases and the peak drain current of i d increases. this control prevents the output voltage from decreasing. pc1 c5 r ocp 2 4 5 s/ocp fb/olp gnd u1 i fb v rocp c4 r3 figure 9-6 fb/olp pin peripheral circuit v sc fb comparator drain current, i d + - voltage on both sides of r ocp v rocp target voltage figure 9-7 drain current, i d , and fb comparator operation in steady operation 9.6 leading edge blanking function the ic uses the peak - curr ent - mode control method for the constant voltage control of output. in peak - current - mode control method, there is a case that the power mosfet turns off due to unexpected response of fb comparator or overcurrent protection circuit (ocp) to the steep surge current in turning on a power mosfet. in order to prevent this response to the surge voltage in turning - on the power mosfet, the leading edge blanking, t on(leb) is built - in. during t on(leb) , the ocp threshold voltage becomes v ocp(la.off) = 1.83 v in order not to respond to the turn - on drain current surge (refer to section 9.12 ). 9.7 quasi- resonant operation and bottom - on timing set up 9.7.1 quasi-resonant operation using quasi - resonant operation, switching loss and switching noise are reduced and it is possible to obtain converters with high efficiency and low noise. this ic performs quasi - resonant operation during one bottom - skip operation. figure 9-8 shows the circuit of a flyback converter. the meaning of symbol s in figure 9-8 is shown in table 9-1. a flyback converter is a system that transfers the energy stored in the transformer to the secondary side when the primary side power mosfet is turned off. after the energy is completely transferred to the secondary, when the power mosfet keeps turning off, the v ds begins free oscillation based on the l p and c v . the qu asi - resonant operation is the bottom - on operation that the power mosfet turns - on at the bottom point of free oscillation of v ds . figure 9-9 shows an ideal v ds waveform during bottom - on operation. the delay time, t o ndly , is the time from starting free oscillation of v ds to power mosfet turn - on . the t ondly of an ideal bottom - on operation is half cycle of the free oscillation, and is calculated using equation (3) . v p ondly c l t P (3) t1 s v in n p n s l p c v v fly i d i off v o c51 v f c1 d51 p u1 figure 9-8 basic flyback converter circuit downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 16 j un . 09 , 2 01 6 table 9-1 the meaning of symbol s in figure 9-8 symbol descriptions v in input voltage v fly flyback voltage ( ) f o s p fly v v n n v + = v ds the voltage between drain and source of power mosfet n p primary side number of turns n s secondary side number of turns v o output voltage v f forward voltage drop of the secondary side rectifier i d drain current of power mosfet i off current which flows through the secondary side rectifier when power mosfet is off c v voltage resonant capacitor l p primary side inductance v ds 0 i off 0 i d 0 t on v in v fly t ondly bottom point figure 9-9 ideal bottom - on operation waveform 9.7.2 bottom - on timing set up bd pin detects the signal of bottom - on timing and input compensation of ocp1 ( refer to section 9.12.3 ). figure 9- 10 shows the bd pin peripheral circuit, figure 9- 11 shows the waveform of auxiliary winding voltage. the quasi - resonant signal, v rev2 , is proportional to auxiliary winding voltage, v d and is calculated as follows: ( ) f 1 rev 2bd 1bd 2bd 2 rev v v r r r v ? + = (4) where, v rev1 : flyback voltage of auxiliary winding d v f : forward voltage drop of z bd the bd pin detects the bottom point usi ng the v rev2 . t he t hreshold voltage of q uasi -r esonant o peration has a hysteresis . v bd(th1) is quasi - resonant operation threshold voltage 1, v bd(th2) is quasi - resonant operation threshold voltage 2. when the bd pin voltage, v rev2 , increases to v bd(th1) = 0.24 v or more at the power mosfet turns - off, the power mosfet keeps the off - state. after that, the v ds decreases by the free oscillation. when the v ds decreases to v bd(th2) = 0.17 v, the power mosfet turns - on and the threshold voltage goes up to v bd(th1) automatically to prevent malfunction of the bd pin from noise interference. 1 s/ocp vcc d/st bd 6 3 c1 d2 r2 c3 t1 d p r ocp c v r bd1 dz bd v in v fly v in flyback voltage forward voltage 2 c bd r bd2 u1 v rev2 v rev1 gnd 4 v fw1 figure 9- 10 bd pin peripheral cir cuit 0 v fw1 v rev1 t on auxiliary winding voltage, v d v bd(th1) v bd(th2) 0 quasi-resonant signal, v rev2 3.0 v recommended,but less than 6.0 v acceptable figure 9- 11 the waveform of auxiliary winding voltage ? r bd1 and r bd2 s etup r bd1 and r bd2 should be set so that v rev2 becomes the following range : under the lowest condition of vcc pin voltage in power supply specification, v rev2 v bd(th1) = 0.34 v(max.). under the highest condition of vcc pin voltage in downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 17 j un . 09 , 2 01 6 power supply specification, v rev2 < 6.0 v (a bsolute maximum rating of the bd pin ) and t he effective pulse width of quasi - resonant signal is 1.0 s or more (refer to figure 9- 12 ). the value of v rev2 is recommended about 3.0 v . quasi-resonant signal, v rev2 0.34v effective pulse width (1.0 s or more) 3.0 v recommended,but less than 6.0 v acceptable 0.27v figure 9- 12 the effective pulse width of quasi - resonant signal ? c bd setup the delay time, t ondly , until which the power mosfet turns on, is adjusted by the value of c bd , so that the power mosfet turns on at the bottom - on of v ds (refer to figure 9-9). the initial value of c bd is set about 1000 pf. c bd is adjusted while observing the actual operation waveforms of v ds and i d under the maximum input voltage and the maximum output power (if a voltage probe is connected to bd pin, the bottom point may misalign ). if the turn - on point precedes the bottom of the v ds signal (see figure 9- 13 ), after confirming the initial turn - on point, delay the turn - on point by increasing the c bd va lue gradually, so that the turn - on will match the bottom point of v ds . v ds 0 i off 0 auxiliary winding voltage bottom point early turn-on point on i d 0 v bd 0 v d 0 v bd(th1) v bd(th2) figure 9- 13 when the turn - on of a v ds waveform occurs before a bottom point in the converse situation, if th e turn - on point lags behind the v ds bottom point ( figure 9- 14 ) , a fter confirming the initial turn - on point, advance the turn - on point by decreasing the c bd value gradually, so that the turn - on wil l match the bottom point of v ds . on v ds 0 i off 0 i d 0 v bd 0 v d 0 v bd(th2) v bd(th1) delayed turn-on point bottom point auxiliary winding voltage figure 9- 14 when the turn - on of a v ds waveform occurs after a bottom point 9.8 bd pin blanking time since the auxiliary winding voltage is input to the bd pin , bd pin v oltage may be affected from the surge voltage ringing when the power mosfet turns off. if the ic detects the surge voltage as quasi - resonant signal, the ic may repeatedly turn the power mosfet on and off at high frequency. this result in an increase of the mosfet power dissipation and temperature, and it can be damaged. the bd pin has a blanking period of 250 ns (max.) to avoid detecting voltage during this period . the poor coupling (the high leakage inductance) tends to happen in a low output voltage trans former design with high n p / n s turns ratio (n p and n s indicate the number of turns of the primary winding and s econdary winding, respectively) , and the surge voltage ringing of bd pin occurs easily ( see figure 9- 15 ). if the surge voltage continues longer than bd pin blanking period and the high frequency operation of power mosfet occurs, the following adjustments are required so that the surge period of bd pin is less than 250 ns. in addition, the bd pin waveform during operation should be measured by connecting test probes as short to the bd pin and the gnd pin as possible, in order to measure any surge voltage correctly. downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 18 j un . 09 , 2 01 6 ? c bd must be connected near the bd pin and the gnd pin. ? the circuit trace loop between the bd p in and the gnd pin must be separated from any traces carrying high current ? the coupling of the primary winding and the auxiliary winding must be good ? the clamping snubber circuit (refer to figure 6-1 ) must be adjusted properly. v rev2 v rev2 (a) normal bd pin waveform (good coupling) v bd(th1) v bd(th2) bd pin blanking time 250ns max. v bd(th1) v bd(th2) (b) inappropriate bd pin waveform (poor coupling) figure 9- 15 the difference of bd pin voltage, v rev2 , waveform by the coupling condition of the transformer 9.9 multi -mode control when the output power decreases, the us ual quasi - resonant control increases the switching frequency and the switching loss . thus, the ic has the multi - mode control to achieve high efficiency operation across the full range of loads. the automatic multi - mode control changes among the following three operational modes according to the output loading state: normal quasi - resonant operation in heavy load, one bottom - skip quasi - resonant operation in medium to light load , and burst oscillation operation (auto standby function) in light load. 9.9.1 one botto m- skip quasi -resonant operation the one bottom - skip function limits the rise of the power mosfet operation frequency in medium to light load in order to reduce the switching loss. figure 9- 17 shows the operation st ate transition diagram of the output load from light load to heavy load. figure 9- 18 shows the state transition diagram from heavy load to light load. as shown in figure 9-16 , in the process of the increase and decrease of load current, hysteresis is imposed at the time of each operational mode change. for this reason, the switching waveform does not become unstable near the threshold voltage of a change, and this enables the ic to switch in a stable operation. before the one bottom - skip point changed from heavy to light load, or after that done from light to heavy load, the switching frequency of the normal quasi - resonant operation becomes higher and the switching loss of po wer mosfet increases. thus, the temperature of the power mosfet should be checked at higher switching frequency of the operation changing point in maximum ac input voltage. one bottom-skip quasi-resonant normal quasi-resonant v ocp(bs2) v ocp(bs1) v ocp(h) load current figure 9- 16 hysteresis at the operational mode change ? the mode is changed from one bottom - skip quasi - resonant operation to normal quasi - resonant operation (light load to heavy load). when load is increased from one bottom - skip operation, the mosfet peak drain cu rrent value will increase, and the positive pulse width will widen. also, the peak value of the s/ocp pin voltage increases. when the load is increased further and the s/ocp pin voltage rises to v ocp(bs1) , the mode is changed to normal quasi - resonant opera tion (see figure 9- 17 ). v ocp(bs1) one bottom-skip quasi-resonant normal quasi-resonant light load heavy load v ocp(h) v ds s/ocp pin voltage figure 9- 17 operation state transition diagram from light load to heavy load conditions ? the mode is changed from normal quasi - resonant operation to one bottom - skip quasi - resonant operation (heavy load to light load). when load is decreased from normal quasi - resonant operation, the mosfet peak drain current value will decrease, and the positive pulse width will narro w. also, the peak value of the s/ocp pin voltage decreases. when load is reduced further and the s/ocp pin voltage falls to v ocp(bs2) , the mode is downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 19 j un . 09 , 2 01 6 changed to one bottom - skip quasi - resonant operation (see figure 9- 18 ). v ocp(bs2) one bottom-skip quasi-resonant normal quasi-resonant light load heavy load v ocp(h) v ds s/ocp pin voltage figure 9- 18 operation state transition diagram from heavy load to light load conditions figure 9- 19 shows the effective pulse width o f normal quasi - resonant signal, and figure 9- 20 shows the effective pulse width of one bottom - skip quasi - resonant signal. in order to perform stable normal quasi - resonant operation and one bottom - skip operation, it is necessary to ensure that the pulse width of the quasi - resonant signal is 1 s or more under the conditions of minimum input voltage and minimum output power. the pulse width of the quasi - resonant signal, v rev2 , is defined as the period from the maximum specification of v bd(th1) , 0.34 v, on the rising edge, to the maximum specification of v bd(th2) , 0.27 v on the falling edge of the pulse. quasi-resonant signal, v rev2 0.34v 0.27v s/ocp pin voltage effective pulse width 1.0s or more figure 9- 19 the effective pulse width of normal quasi - resonant signal s/ocp pin voltage 0.34v 0.27v effective pulse width 1.0s or more quasi-resonant signal, v rev2 figure 9- 20 the effective pulse width of one bottom - skip quasi - resonant signal 9.9.2 automatic standby mode function the s/ocp pin circuit monitors i d . automatic standby mode is activated automatically when i d reduces under light load conditions at which the s/ocp pin voltage falls to the standby state threshold voltage (about 9% compared to v ocp(h) = 0.910 v). during standby mode, when the fb/olp pin voltage falls below v fb(stbop) , the ic stops switching operation, and the burst oscillation mode will begin, as shown in figure 9 - 21 . burst oscillation mode reduces switching losses and improves power supply efficiency because of periodic non - switching intervals. generally, to improve efficiency under light load conditions, the frequency of the burst oscillation mode becomes just a few kilohertz. because the ic suppresses the peak drain current well during burst oscillation mode, audible noises can be reduced. if the vcc pin voltage decreases to v cc(bias) = 11.0 v during the transition to the burst oscillation mode, the bias assist function is activated and stabilizes the standby mode operation, because i cc(startup) is provided to the vcc pin so that the vcc pin voltage does not decrease to v cc(off) . however, if the bias assist function is always activated during steady -s tate operation including standby mode, the power loss increases. therefore, the vcc pin voltage should be more than v cc(bias) , for example, by adjusting the turns ratio of the auxiliary winding and secondary winding and/or reducing the value of r2 in figure 10 -2 (refer to section 10.1 peripheral components for a detail of r2). normal operation standby operation normal operation burst oscillation output current, i out drain current , i d below several khz figure 9- 21 auto st andby mode timing 9.10 maximum on - time limitation function when the input voltage is low or in a transient state such that the input voltage turns on or off, the on - time of the incorporated power mosfet is limited to the maximum on - time, t on(max) = 40.0 s in order to prevent the decreasing of switching frequency . t hus, the peak drain current is limited, and the audible noise of the transformer is suppressed. in designing a power supply, the on - time must be less downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 20 j un . 09 , 2 01 6 than t on(max) (see figure 9- 22 ). if such a transformer is used that the on - time is t on(max) or more, under the condition with the minimum input voltage and the maximum output power, the output power would become low. in that case, the transformer should be redesigned taking into consideration the following: ? inductance, l p , of the transformer should be lowered in order to raise the operation frequency. ? lower the primary and the secondary turns ratio, n p / n s , to lower the duty cy cle. v ds i d on-time timetime figure 9- 22 confirmation of maximum on - time 9.11 overcurrent protection ( ocp ) the ic has an overcurrent protection 1 ( ocp1 ) and an overcurrent protection 2 ( ocp2 ). ocp1 function : pulse - by - pulse , with input compen - sation function . the ocp2 function: in case output winding is short ed etc. , the ic stops switching operation at the latched state. the products with the last letter "a" don t have the ocp2 function. 9.11.1 overcurrent protection 1 (ocp1) ocp1 detects each drain peak current level of a power mosfet on pulse - by - pulse basis, and limits the output power when the current level reaches to ocp threshold voltage. during leading edge blanking time (t bw ), ocp1 is disabled. when power mosfe t turns on, the surge voltage width of s/ocp pin should be less than t on(leb) , as shown in figure 9- 23 . in order to prevent surge voltage, pay extra attention to r ocp trace layout (refer to section 10.3 ). surge at mosfet turn on t on(leb) v ocp(h) figure 9- 23 s/ocp pin voltage in addition, if a c (rc) damper snubber of figure 9- 24 is used, reduce the capacitor value of damper snubber . if the turn - on timing is nt fitted to a v ds bottom point, adjustments are required (refer to section 9.7.2 ). c1 t1 d51 r ocp c cr damper snubber u1 c51 c cr damper snubber 1 d/st s/ocp 2 figure 9- 24 damper snubber circuit 9.11.2 overcurrent protection 2 (ocp2) the products with the last letter "a" do n t have the ocp2 function. as the protection for an abnormal state, such as an output winding being shorted or the withstand voltage of se condary rectifier being out of specification, when the s/ocp pin voltage reaches v ocp(la.off) = 1.83 v, the ic stops switching operation immediately, in latch mode. this overcurrent protection also operates during the l eading edge blanking. releasing the latched state is done by turning off the input voltage and by dropping the vcc pin voltage below v cc(off) . 9.11.3 ocp1 input compensation function the usual control ics have some propagation delay time. the steeper the slope of the actual drain current at a high ac input voltage is, the larger the detection voltage of actual drain peak current is, compared to overcurrent detection threshold voltage. thus, the peak current has some variation depending on the ac input voltage in o cp1 state. when using a quasi - resonant converter with universal input (85 to 265 vac), if the output power is set constant, then because higher input voltages have higher frequency, the on - time is reduced. thus, the peak current in ocp 1 state tends to be a ffected by propagation delay in the high er input voltage . if the ic does not have input compensation function, the output current at ocp1 point in the maximum input voltage, i out(ocp) , becomes about double of i out ( figure 9- 25 without input compensation). i out is the target output current consider ed with maximum output power in the minimum input voltage . downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 21 j un . 09 , 2 01 6 in order to suppress this variability , this ic has the overcurrent input compensation function. without input compensation with optimal input compensation with excessiveinput compensation i out output current at ocp1 i out(ocp) a 85v 265v ac input voltage v target output current figure 9- 25 ocp1 input compensation figure 9- 26 shows the ocp1 input compensation circuit. the value of input compensation is set by bd pin peripheral c ircuit. by ocp1 input compensation function, overcurrent detection 1 threshold voltage in normal operation , v ocp(h) = 0.910 v, is compensated depend ing on an ac input voltage. t he forward voltage of auxiliary winding d, v fw1 , is proportional to ac input voltage . as shown in figure 9- 26 , the voltage obtained by subtracting zener voltage, v z , of dz bd from v fw1 is biased by either end of r bd1 and r bd2 , and thus the bd pin voltage is p rovided the voltage on r db2 divided by the divider of r bd1 and r bd2 . 6 gnd v cc bd s/ocp 4 3 2 d2 r2 c3 t1 d r ocp r bd2 r bd1 dz bd c bd v fw2 flyback voltage, v rev1 forward voltagev fw1 v dzbd figure 9- 26 ocp input compensation circuit figure 9- 27 shows the eac h voltage waveform for the input voltage in normal quasi - resonant operation. when v dzbd v fw1 (point a), no input compensation required, v fw2 remains zero, and the detection voltage for an overcurrent event is the overcurrent 1 detection threshold voltage in n ormal o peration , v ocp(h) . when v dzbd < v fw 1 (point b through point d), the input vo ltage is increased and v fw1 exceeds the zener voltage, v z , of dz bd . v fw2 will be produced as a negative voltage to compensate v ocp(h) . the value of v fw2 should be adjusted so that the difference between i out and i out(ocp) is minimized as shown in figure 9- 25 with optimal input compen - sation. if the excessive input compensation, i out(ocp) may become less than i out ( figure 9- 25 with excessive input compensation ). thus, value of v fw2 must be adjusted so that i out(ocp) remains more than i out , across the input voltage range. v rev1 v fw1 v dzbd v fw2 at the input voltage where v fw1 reaches v z or more, v fw2 goes negative. a b d auxiliary winding voltage 0 vac 100 230 00 c v z 0 figure 9- 27 each voltage waveform for the input voltage in normal quasi - reson ant operation setup of bd pin peripheral components (dz bd , r bd1 and r bd2 ) is as follow s: 1) v in(ac)c setup v in(ac)c is t he ac input voltage that starts input compensation. in general specification, v in(ac)c is set 120 vac to 170 vac. 2) v z setup v in(ac)c is adju sted by the zener voltage, v z , of dz bd . the v fw1 at v in(ac)c is calculated by using equation (5) . v z is set from th e result. z c) ac (in p d 1 fw v 2 v n n v = = (5 ) where, n p : primary side number of turns n d : secondary side number of turns downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 22 j un . 09 , 2 01 6 3) r bd1 and r bd2 setup. the recommended value of r bd2 is 1.0 k . in general specification, r bd1 is set by using result of equation (6) so that v fw2 = ?3.0 v at maximum ac input volt age. 2 fw 2bd 1bd v r r = ? ?? ? ? ?? ? ? ? 2 fw z max ) ac (in p d v v 2 v n n (6 ) where, v fw2 : bd pin voltage (?3.0 v) n p : primary side winding number of turns n d : auxiliary winding number of turns v in(ac)max : maximum ac input voltage v z : zener voltage of dz bd 4) v ocp(h) ' is the overcurrent threshold voltage after input compensation. figure 9- 28 shows a relationship of v ocp(h) ' and bd pin voltage,v fw2 . v fw2 at maximum ac input voltage is calculated by using equation (7) . v ocp(h) ' and this variation are gotten by using the result from figure 9- 28 . when v ocp(h) ' including variation becomes the bottom - skip operation threshold voltage 1, v ocp(bs1) = 0.572 v, or less, the operation of ic is one bottom - skip only and the output current may be less than target output current, i out . ( ) z 1 fw 2bd 1bd 2bd 2 fw v v r r r v ? + = ? ?? ? ? ?? ? ? + = z max ) ac (in p d 2bd 1bd 2bd v 2 v n n r r r (7 ) figure 9- 28 overcurrent threshold voltage after input compensation, v ocp(h) ' (reference for design target values) 5) v rev2 is calculated by using equation (8) and is checked t o be the quasi - resonant operation threshold voltage 1, v bd(th1) = 0.34 v (max.), or more (refer to figure 9- 11 ). ( ) f 1 rev 2bd 1bd 2bd 2 rev v v r r r v ? + = 0.34 v (8) where, v rev1 : f lyback voltage of auxiliary wining v f : forward voltage drop of dz bd 6) t he bd pin voltage, which includes surge voltage, must be observed within the absolute maximum rat ing of the bd pin voltage ( C 6.0 to 6.0 v) in the actual operation at the maximum input voltage. < bd pin peripheral components value selection reference example > setting value : input voltage: v in(ac) = 85v ac to 265v ac , ac input voltage that starts input compensation: v in(ac)c = 120 v ac, primary side winding number of turns: n p = 40 t, auxiliary winding number of turns: n d = 5 t forward voltage of auxiliary winding: v fw1 = 20 v v fw1 is calculated by using equation (5) as follows: 2 v n n v c) ac (in p d 1 fw = v2.12 2 201 40 5 = = thus, zener voltage of dz bd is chosen to be 22 v of the e series. when v fw2 = ?3.0 v at maximum input voltage, 265v ac , r bd1 is calculated by using equation (6) as follows: ? ?? ? ? ?? ? ? = 2 fw z max ) ac (in p d 2 fw 2bd 1bd v v 2 v n n v r r k28.7 3 22 2 265 40 5 3 k1 = ?? ? ?? ? ?? ? ? = thus, r bd1 is chosen to be 7.5 k of the e series. 0 0.2 0.4 0.6 0.8 1 -6 -5 -4 -3 -2 -1 0 bd pin voltage v fw2 (v) 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 v ocp (h) ' (v) m ax. t yp. m in. v ocp(h) downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 23 j un . 09 , 2 01 6 when r bd2 = 1.0 k, |v fw2 | value at 265 vac is calculated by using equation (7) as foll ows: ( ) z 1 fw 2bd 1bd 2bd 2 fw v v r r r v ? + = v 92.2 22 2 265 40 5 1k 7.5k 1k = ?? ? ?? ? ? + = referring to figure 9- 28 , when v fw2 is compensated to C 2.92 v, the overcurrent threshold voltage after input compensation, v ocp(h) ', is set to about 0.66 v (t yp). when setting r bd2 = 1.0 k, r bd1 = 7.5 k, v f = 0.7 v, and v rev1 = 20 v, v rev2 is calculated by using equation (8) as follows: ( ) f 1 rev 2bd 1bd 2bd 2 rev v v r r r v ? + = ( ) v 27.2 7.0 20 k5.7 k1 k1 = ? + = v rev2 is v bd(th1) = 0.34 v (max.) or more. 9.11.4 when overcurrent input compensation is not required when the input voltage is narrow range, or provided from pfc circuit, the variation of the input voltage is small. thus, the variation of ocp point may become less than that of the universal input voltage specification. when overcurrent input compensation is not required, the input compensation function can be disabled by substituting a high - speed diode for the zener diode, dz bd , and by keeping bd pin voltage from being minus vo ltage. in addition, equation (9) shows the reverse voltage of a high - speed diode. the peak reverse voltage of high - speed diode selection should take account of its derating. 2 v n n v max ) ac (in p d fw1 = (9 ) where, v fw1 : forward voltage of auxiliary wining n p : primary side number of turns n d : secondary side number of turns v in(ac)max : maximum ac input voltage 9.12 overload protection (olp) figure 9- 29 shows the fb/o lp pin peripheral circuit, figure 9- 29 shows each waveform for overload protection (olp) operation. when the peak drain current of i d is limited by overcurrent protection 1 operation, the output voltage, v out , decreases and the feedback current from the secondary photo - coupler becomes zero. thus, the feedback current, i fb , charges c4 connected to the fb/olp pin and the fb/olp pin voltage , v fb/olp , increases. when v fb/olp increases to the fb pin maximum voltage in f eedback operation, v fb(max) = 4.05 v, or more , c4 is charged by i fb(olp) = ? 10 a. when v fb/olp increases to the olp threshold voltage, v fb(olp) = 5.96 v, the olp function is activated, the ic stops switching operation in the latched state . in order to keep the latched state, when vcc pin volt age decreases to v cc(bias) , the bias assist function is activated and vcc pin voltage is kept to over the v cc(off) . releasing the latched state is done by turning off the input voltage and by dropping the vcc pin voltage below v cc(off) . 4 5 fb / olp gnd c4 c5 r3 pc 1 i fb figure 9- 29 fb/olp pin peripheral circuit vcc pin voltage fb/olp pin voltage, v fb/olp v fb(olp) v fb(max) charged by i fb(olp) v cc(bias) drain current, i d t dly ac input voltage off latch release v cc(off) figure 9- 30 olp operation waveforms the time of the fb/olp pin voltage from v fb (max) to v fb(olp) is defined as the olp d elay t ime, t dly . because the capacitor c 5 for phase compensation is small compared to c4, t he approximate value of t dly is calculated by equation ( 10 ). when c4 = 4.7 f, the value of t dly would be approximately 0.9 s. the recommended value of r3 is 47 k. downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 24 j un . 09 , 2 01 6 ( ) ) olp ( fb ) max ( fb ) olp ( fb dly i 4c v v t ? P ( ) ? ? 10 4c v05.4 v96.5 t dly P ( 10 ) to enable the overload protection function to initiate an automatic restart, 220 k is connected b etween the fb/olp pin and ground, as a bypass path for i fb(olp) , as shown in figure 9- 31 . thus, the fb/olp pin is kept under v fb(olp) in olp state. in olp state as an output shorted, the output voltage and vcc pin voltage decrease. during the operation, bias assist function is disabled. thus, vcc pin voltage decreases to v cc(off) , the control circuit stops operation. after that, the ic reverts to the initial state by uvlo circuit, and the ic starts operation when vc c pin voltage increases to v cc(on) by startup current. thus the intermittent operation by uvlo is repeated in olp state without latched operation as shown in figure 9- 32 . the intermittent oscillation is determined by the cycle of the charge and discharge of the capacitor c3 connected to the vcc pin. in this case, the charge time is determined by the startup current from the startup circuit, while the discharge time is determined by the current supply to the internal circuits of the ic. 4 5 fb / olp gnd c5 220k pc 1 i fb figure 9- 31 fb/olp pin peripheral circuit (without latched operation) vcc pin voltage fb/olp pin voltage v fb(olp) v cc(off) v cc(on) drain current, i d figure 9- 32 olp operation waveform at output shorted (without latched operation) 9.13 overvoltage protection ( ovp ) when a voltage between vcc pin and gnd pin increases to v cc(ovp) = 31.5 v or more, overvoltage protection (ovp) is activa ted, the ic stops switching operation at the latched state. in order to keep the latched state, when vcc pin voltage decreases to v cc(bias) , the bias assist function is activated and vcc pin voltage is kept to over the v cc(off) . releasing the latched state is done by turning off the input voltage and by dropping the vcc pin voltage below v cc(off) . when the vcc pin voltage is provided by using auxiliary winding of transformer, the overvoltage conditions such as output voltage detection circuit open can be detected because the vcc pin voltage is proportional to output voltage. the approximate value of output voltage v out(ovp) in ovp condition is calculated by using equation (11) . = ) normal (cc ) normal ( out out(ovp) v v v 31.5 (v) ( 11 ) where, v out(normal) : output voltage in normal operation v cc(normal) : vcc pin voltage in normal operation 9.14 thermal shutdown (tsd) when the temperature of control circuit increases to t j(tsd) = 135 c (min.) or more, thermal shutdown (tsd) is activated, the ic stops switching operation at the latched state. in order to keep the latched state, when vcc pin voltage decreases to v cc(bias) , the bias assist function is activated and vcc pin voltage is kept to over the v cc(off) . downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 25 j un . 09 , 2 01 6 10. design notes 10.1 external components take care to use properly rated, including derating as necessary and proper type of components. nf gndfb/olp s/ocpvcc d/st 2 1 7 54 2 3 6 bd vac c1 d2 r2 c3 t1 d p pc1 c4 r ocp br1 c v c5 r bd2 r bd1 dz bd c bd r3 u1 c2 r1 d1 crd clamp snubber c(rc) damper snubber figure 10 -1 the ic peripheral circuit ? input and output electrolytic capacitor apply proper derating to ripple current, voltage, and temperature rise. use of high ripple current and low impedance types, designed for switch mode power supplies, is reco mmended. ? s/ocp pin peripheral circuit in figure 10 -1 , r ocp is the resistor for the current detection. a high frequency switching current flows to r ocp , and may cause poor operation if a high inductance resistor is used. choose a low inductance and high surge - tolerant type. ? vcc pin peripheral circuit the value of c 3 in figure 10 -1 is generally recommended to be 10 to 47f (refer to section 9.1 startup operation , because the startup time is determined by the value of c 3 ). in actual power supply circuits, there are cases in which the vcc pin voltage fluctuates in proportion to the output current, i out (see figure 10 -2 ), and the overvoltage protection function (ovp) on the vcc pin may be activated. this happens because c 3 is charged to a peak voltage on the auxiliary winding d, which is caused by the transient surge voltage coupled from the pr imary winding when the power mosfet turns off. for alleviating c 3 peak charging, it is effective to add some value r2, of several tenths of ohms to several ohms, in series with d2 (see figure 10 -1 ). the optimal val ue of r2 should be determined using a transformer matching what will be used in the actual application, because the variation of the auxiliary winding voltage is affected by the transformer structural design. without r2 with r2 vcc pin voltage output current, i out figure 10 -2 variation of vcc pin voltage and power ? fb/olp pin peripheral circuit c 5 is for high frequency noise reduction and phase compensation, and should be connected close to these pins. the value of c 5 is recommended to b e about 470 pf to 0.01f, and should be selected based on actual operation in the application. c4 is for the olp delay time, t dly , setting (refer to section 9.13 ). the recommended value of r3 is 47 k. ? bd pin peripheral circuit since bd pin detects the signal of bottom -on timing and input compensation of ocp1, the value s of bd pin peripheral components (dz bd , r bd1 , r bd2 and c bd ) are considered about both functions and should be adjusted. refer to section 9.7.2 and section 9.12.3 . ? nf pin for stable operation, nf pin should be connected to gnd pin, using the shortest possible path. ? snubber circuit when the surge voltage of v ds is large, the circuit should be added as follows (see figure 10 -1 ); ? a clamp snubber circuit of a capacitor - resistor - diode (crd) combination should be added on the primary winding p. ? a damper snubb er circuit of a capacitor (c) or a resistor - capacitor (rc) combination should be added between the d/st pin and the s/ocp pin. when the damper snubber circuit is added, this components should be connected near d/st pin and s/ocp pin. ? peripheral c ircuit of s econdary s ide s hunt r egulator figure 10 -3 shows the secondary side detection circuit with the standard shunt regulator ic (u51). downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 26 j un . 09 , 2 01 6 c52 and r53 are for phase compensation. the value of c52 and r53 are recommended to be around 0.047 f to 0.47 f and 4.7 k to 470 k, respectively. they should be selected based on actual operation in the application. d51 c51 r51 r52 u51 r54r56 c52 s pc1 r53 r55 l51 c53 vout (-) t1 (+) figure 10 -3 peripheral circuit of secondary side shunt regulator (u51) ? transformer apply proper design margin to core temperature rise by core loss and copper loss. because the switching currents contain high frequency currents, the skin effect may become a consideration. choose a suitable wire g auge in consideration of the rms current and a current density of 4 to 6 a/mm 2 . if measures to further reduce temperature are still necessary, the following should be considered to increase the total surface area of the wiring: ? increase the number of wires in parallel. ? use litz wires. ? thicken the wire gauge. in the following cases, the surge of vcc pin voltage becomes high. ? the surge voltage of primary main winding, p, is high (low output voltage and high output current power supply designs) ? the winding structure of auxiliary winding, d, is susceptible to the noise of winding p. when the surge voltage of winding d is high, the vcc pin voltage increases and the overvoltage protection function (ovp) may be activated. in transformer design, the following shou ld be considered; ? the coupling of the winding p and the secondary output winding s should be maximized to reduce the leakage inductance. ? the coupling of the winding d and the winding s should be maximized. ? the coupling of the winding d and the winding p sh ould be minimized. in the case of multi - output power supply, the coupling of the secondary - side stabilized output winding, s1, and the others (s2, s3) should be maximized to improve the line - regulation of those outputs. figure 10 -4 shows the winding structural examples of two outputs. winding structural example (a): s1 is sandwiched between p1 and p2 to maximize the coupling of them for surge reduction of p1 and p2. d is placed far from p1 and p2 to minimize the coupling to the primary for the surge reduction of d. winding structural example (b) p1 and p2 are placed close to s1 to maximize the coupling of s1 for surge reduction of p1 and p2. d and s2 are sandwiched by s1 to maximize the coupling of d and s1, and that of s1 and s2. this structure reduces the surge of d, and improves the line - regulation of outputs. margin tapemargin tape margin tapemargin tape p1 s1 p2 s2 d p1 s1 d s2 s1 p2 winding structural example (a) winding structural example (b) bobbin bobbin figure 10 -4 winding structural examples downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 27 j un . 09 , 2 01 6 10.2 transformer design the design of th e transformer is fundamentally the same as the power transformer of a ringing choke converter (rcc) system: a self - excitation type flyback converter. however, because the duty cycle will change due to the quasi - resonant operations delaying the turn - on, the duty cycle needs to be compensated. figure 10 -5 shows the quasi - resonant circuit. t1 s v in n p n s l p c v v fly i d i off v o c51 v f c1 d51 p u1 figure 10 -5 quasi - resonant circuit the flyback voltage , v fly is calculated as follows: ( ) f o s p fly v v n n v + = ( 12 ) where, n p : primary side number of turns n s : secondary side number of turns v o : output voltage v f : forward voltage drop of d51 the on duty, d on , at the minimum ac input voltage is calculated as follows: fly )min(in fly on v v v d + = ( 13 ) where, v in(min) : c1 voltage at the minimum ac input voltage v fly : flyback voltage. the inductance, l p ' on the primary side, taking into consideration the delay time, is calculated using equation ( 14 ). ( ) 2 v min on )min(in 1 min o 2 on )min(in p c f d v f 2p d v 'l ? ?? ? ? ?? ? + = ( 14 ) where, v in(min) : c1 voltage at the minimum ac input voltage d on : on - duty at the minimum input voltage p o : maximum output power f min : minimum operation frequency 1 : transformer efficiency c v : the voltage resonance capacitor connected between the drain and source of the power mosfet each parameter, such as the peak drain current, i dp , is calculated by the following formulas: v p ondly c'l t = ( 15 ) ( ) ondly min on on t f1 d ' d ? = ( 16 ) in(min) 2 o in v 1 p i = ( 17 ) ' d i 2 i on in dp = ( 18 ) value al 'l n p p \ = ( 19 ) ( ) fly f o p s v v v n n + = ( 20 ) where, t ondly : d elay time of quasi -r esonant operation i in : average input current 2 : conversion efficiency of the power supply i dp : peak drain current d on : on - duty after compensation v o : secondary side output voltage the minimum operation frequency, f min , can be calculated by the equation ( 22 ): ( ) 2 on )min(in v p v 2 on )min(in 1 o 1 o min d v c 2 'l c d v 4 2p 2p f ? ? ? ? ? ?? ? ? ? ? ? ? ?? ? + + ? = ( 21 ) figure 10 -6 shows the example of ni - limit versus al - value characteristics. cho ose the ferrite core that does not saturate and provides a design margin in consideration of temperature effects and other variations to ni - limit versus al - value characteristics . downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 28 j un . 09 , 2 01 6 al - value is calculated by using l p and n p . ni is calculated by using equation ( 22 ). it is recommended that al - value and ni provide the design margin of 30 % or more for saturation curve of core. dp p i n ni = (at) ( 22 ) where, n p : primary side number of turns i dp : peak switching current ni-limit (at) al-value (nh/t 2 ) margin : about 30% saturation curve ni l p /n p 2 figure 10 -6 example of ni - limit versus al - value characteristics 10.3 pcb trace layout and c omponent placement since the pcb circuit trace design and the component layout significantly affects operation, emi noise, and power dissipation, the high frequency pcb trace should be low impedance with small loop and wide trace. in addition, the ground t races affect radiated emi noise, and wide, short traces should be taken into account. figure 10 -7 shows the circuit design example. (1) main circuit trace layout this is the main trace containing switching currents, an d thus it should be as wide trace and small loop as possible. if c1 and the ic are distant from each other, placing a capacitor such as film capacitor (about 0.1 f and with proper voltage rating) close to the transformer or the ic is recommended to reduce impedance of the high frequency current loop. (2) control ground trace layout since the operation of ic may be affected from the large current of the main trace that flows in control ground trace, the control ground trace should be separated from main trace and connected at a single point grounding of point a in figure 10-7 as close to the r ocp pin as possible. (3) vcc trace layout this is the trace for supplying power to the ic, and thus it should be as small loop as possible. if c3 and the ic are distant from each other, placing a capacitor such as film capacitor c f (about 0.1 f to 1.0 f) close to the vcc pin and the gnd pin is recommended. (4) r ocp trace layout r ocp should be placed as close as possible to the s/ocp pin. t he connection between the power ground of the main trace and the ic ground should be at a single point ground (point a in figure 10-7 ) which is close to the base of r ocp . (5) peripheral components of the ic the compone nts for control connected to the ic should be placed as close as possible to the ic, and should be connected as short as possible to the each pin. (6) secondary rectifier smoothing circuit trace layout: this is the trace of the rectifier smoothing loop, carry ing the switching current, and thus it should be as wide trace and small loop as possible. if this trace is thin and long, inductance resulting from the loop may increase surge voltage at turning off the power mosfet. proper rectifier smoothing trace layou t helps to increase margin against the power mosfet breakdown voltage, and reduces stress on the clamp snubber circuit and losses in it. (7) thermal considerations because the power mosfet has a positive thermal coefficient of r ds(on) , consider it in thermal d esign. since the copper area under the ic and the d/st pin trace act as a heatsink, its traces should be as wide as possible. downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 29 j un . 09 , 2 01 6 nf gnd fb/olp s/ocpvcc d/st 2 1 7 54 2 3 6 bd c1 d2 r2 c3 t1 d51 c51 d p s pc1 c4 r ocp c y c v a r3 dz bd r bd1 c5 r bd2 c bd u1 c2 r1 d1 (1) main trace should be wide trace and small loop (6) main trace of secondary side should be wide trace and small loop (7)trace of d/st pin should be wide for heat release (2) control gnd trace should be connected at a single point as close to the r ocp as possible (5)the components connected to the ic should be as close to the ic as possible, and should be connected as short as possible (3) loop of the power supply should be small (4)r ocp should be as close to s/ocp pin as possible. figure 10 -7 peripheral circuit example around t he ic downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 30 j un . 09 , 2 01 6 11. pattern layout example the following show the four outputs pcb pattern layout example and the schematic of circuit using str - y6700 series. the pcb pattern layout example is made usable to other ics in common . t he parts in figure 11 -2 are only used. figure 11 -1 pcb circuit trace layout example 3 cn1 c6 t1 d51 r52 d55 d p1 s2 pc1 8 l51 c62 r54 f1 2 1 c1 th2 l1 7 2 c12 c9 c7 c11 c5 c13 rc1 d6 d5 r10 r2 r7 d54 c54 c57 r50 r57 r59 r51 r55 r56 pc1 c51 c52 c4 out2(+) out3(-) c3c2 tk1 c8 d3 s4 1 2 d50 c53 c58 c50 cn52 s5 c59 6 d53 c56 s1 out4(+) out5(+) out1(+) out4(-) out5(-) out1(-) tk50 th1 j2 r8 r9 bd gnd fb/olp s/ocp vcc d/st 2 1 6 542 3 str-y6700 ic1 7 nf f2 r1 r3 c10 d7 r12 r11 d2 q1 r5 d4 d1 d10 r6 r4 r53 r58 j54 j53 j56 l50 j55 c65 c63 c61 9 s3 5 d52 c55 out3(+) c64 4 c60 out2(-) j52 j50 j51 j57 figure 11 -2 circuit schematic for pcb circuit trace layout downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 31 j un . 09 , 2 01 6 12. reference design of power supply ? power supply specification ic str - y6754 input voltage 85 v ac to 265 v ac maximum output power 40.4 w output 1 14 v / 2.6a output 2 8 v / 0.5 a ? circuit schematic c2 t1 d52 r52 u51 d p1 s1 pc1 c55 r53 f1 c1 l1 c3 c7 c6 c5 c4 c9 d1 d5 d6 r3 r2 c54 r51 r54 r56 pc1 c52 out2(+) d51 c53 c51 s2 out1(+) r1 bd gndfb/olp s/ocpvcc d/st 2 1 6 542 3 str-y6700 u1 7 nf r4 c8 dz1 r6 r5 r55 out(-) s3 s4 p2 14v/2.6a 8v/0.5a d2 d4 d3 ? bill of materials symbol part type ratings (1) recommended sanken parts symbol part type ratings (1) recommended sanken parts c1 (2) film, x2 0.1 f, 275 v d52 schottky 90 v, 1.5 a ek 19 c2 electrolytic 220 f, 400 v dz1 zener 22v c3 ceramic 22 00 pf, 630 v f1 fuse 250 v ac , 3 a c4 ceramic 100 pf, 2 kv l1 (2) cm inductor 3.3 mh c5 electrolytic 22 f, 50v pc1 photo - coupler pc123 or equiv c6 ceramic 4.7 f, 16 v r1 (3) metal oxide 150 k, 1 w c7 (2) ceramic 4700 p f, 50v r2 (2) general 0.56 , 1 w c8 (2) ceramic 47 0 pf, 50v r3 (2) general 15 c9 ceramic, y1 2200 pf, 250 v r4 general 4 7 k c51 ceramic 2200 pf, 1 kv r5 (2) general 6.8 k c52 ceramic open r6 general 1 k c53 electrolytic 1000 f, 50 v r51 general 820 c54 electrolytic 47 0 f, 16 v r52 general 1.5 k c55 ceramic 0.1 f r53 (2) general 22 k d1 ge neral 600v, 1a em01a r54 (2) general 6.8 k d2 general 600v, 1a em01a r55 general, 1% 39 k d3 general 600v, 1a em01a r56 general, 1% 10 k d4 general 600v, 1a em01a t1 transformer see the specification d5 fast recovery 1000 v, 0.5 a eg01c u1 ic str - y6754 d6 fast recovery 200 v, 1 a al01z u51 shunt regulator v ref = 2.5 v tl431 or equiv d51 schottky 15 0 v, 10 a fmen - 210b (1) unless otherwise specified, the voltage rating of capacitor is 50 v or less and the power rating of resistor is 1/8 w or less. (2) it is necessary to be adjusted based on actual operation in the a pplication. (3) resistors applied high dc voltage and of high resistance are rec ommended to select resistors designed against electromigr atio n or use combinations of resistors i n series for that to reduce each applied voltage, according to the requ irement of the application. downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 32 j un . 09 , 2 01 6 ? transformer specification ? primary inductance, l p : 0.95 mh ? core size: eer28l ? al - value : 18 3 nh/n 2 (center gap of about 0.8 mm) ? winding specification winding symbol number of turns (t) wire diameter (mm) construction primary winding 1 p1 43 1euw C 0.30 two - layer, solenoid winding primary winding 2 p2 29 1euw C 0.30 single - layer, solenoid winding auxiliary winding d 12 tex C 0.23 2 single - layer, spac e winding output winding 1 s1 5 0.32 2 single - layer, solenoid winding output winding 2 s2 3 0.32 2 single - layer, solenoid winding output winding 3 s3 5 0.32 2 single - layer, solenoid winding output winding 4 s4 3 0.32 2 single - layer, sol enoid winding : start at this pin cross-section view bobbin d p1 vdc d/st vcc gnd 14v s2 p2 d p2 8v p1 s4 out1(+)out2(+) out(-) s1 s3 s1 s2s3 s4 downloaded from: http:///
str - y6700 s eries str - y6700 - ds rev. 4. 1 sanken electric co.,ltd. 33 j un . 09 , 2 01 6 important notes all data, illustrations, graphs , tables and any other information included in this document as to sanken s products listed herein (the sanken products) are current as of the date this docu ment is issued . all contents in this document are subject to any change without notice due to improvement of the sanken products , etc. please make sure to confirm with a sanken sales representative that the contents set forth in this document reflect the l atest revisions before use. the sanken products are intended for use as components of general purpose electroni c equipment or apparatus (such as home appliances, office equipment, telecommunication equipment, measuring equipment, e tc.). prior to use of the sanken products, please put your signature, or affix your name and seal, on the specification document s of the sanken products and return them to sanken. when considering use of the sanken products for any applications that require high er reliability (such as transportation equipment and its control systems, traffic signal control systems or equipment , disaster/crime alarm systems, various safety devices, etc.), you must contact a sanken sales representative to discuss the suitability of suc h use and put your signature, or affix your name and seal, on the specification documents of the sanken products and retur n them to sanken, prior to the use of the sanken products. the sanken products are not intended for use in any applications that require ex tremely hi gh reliability such as: aerospace equipment; nuclear power control systems; and medical equipment or syst ems, whose failure or malfunction may result in death or serious injury to people, i.e., medical devices in class iii or a highe r class as defined by r elevant laws of japan (collectively, the specific applications). sanken assumes no liabilit y or responsibility whatsoever for any and all damages and losses that may be suffered by you, users or any third party, resulting from the use of the sanken produ cts in the specific applications or in manner not in compliance with the instructions set forth herei n. in the event of using the sanken p roducts by either (i) combining other products or materials therewith or (ii) p hysically, chemically or otherwise proc essing or treating the same , you must duly consider all possible risks that may result from all such uses in advance and proceed therewith at your own responsibility. although sanken is making efforts to enhance the quality and reliability of its products, it is impossible to completely avoid the occurrence of any failure or defect in semiconductor products at a certain rate. you must take, at your own responsibility , preventative measures including using a sufficient safety design and confirming safety of any equipment or systems in/for which the sanken products are used, upon due consideration of a failure occurrence rate or derating, etc., in order not to cause any human injury or death, fire accident or social harm which may result from any failure or ma lfunction of the sanken products. please refer to the relevant specification documents and sanken s official website in relation to derating. no a nti - radioactive ray design ha s been adopted for the sanken p roducts. no contents in this document can be trans cribed or copied without sankens prior written consent. the c ircuit constant , operation examples, circuit examples, pattern layout examples, design examples , recommended examples, all information and evaluation result s based thereon, etc., described in th is document are presented for the sole purpose of reference of use of the sanken products and sanken assume s no responsibility whatsoever for any and all damages and losses that may be suffered by you, users or any third party, or any possible infringement of any and all property rights including intellectual property rights and any other rights of you, u sers or any third party , result ing from the foregoing . all technical information described in this document (the technical informati on) is presen ted for the sole purpose of reference of use of the sanken products and no license, express, implied or otherwise, i s granted hereby under any intellectual property rights or any other rights of sanken. unless otherwise agreed in writing between sanken and you, sa nken makes no warranty of any kind, whether express or implied, including, without limitation, any warranty (i) as to the quality or perform ance of the sanken products (such as implied warr anty of merchantability, or implied warranty of fitness for a parti cular purpose or special environment), (ii) that any sanken product is delivered free of claims of third parties by way of infringement or the li ke, (iii) that may arise from course of performance , course of dealing or usage of trade, and (iv) as to any information contained in this document (including its accuracy, usefulness, or reliability). in the event of using the sanken products, you must use the same after carefully examining all applicable environmental laws and regulations that regul ate the inclusion or use of any particular controlled substances, including , but not limi ted to , the eu rohs directive , so as to be in strict compliance with such applicable laws and regulations . you must not use the sanken products or the technical information for the purpose of any military applications or use, including but not limited to the development of weapons of mass destruction. in the event of exporting the sanken products or the technical information, or providing them for non - residents, you mus t comply with all applicable export control laws and regulations in each country including the u.s. export administration regulations (ear) and the foreign exchange and foreign trade act of japan , and follow the procedures required by such applicable laws and regulations. sanken assumes no responsibility for any troubles, which may occur during the transportation of the sanken products including the falling thereof, out of sankens distribution network. although sanken has prepared this document with its du e care to pursue the accuracy thereof, sanken does not warrant that it is error free and sanken assumes no liability whatsoever for any and all damages and losses which may be suffered by you resulting from any possible errors or omissions in connection with the contents included herein . please refer to the relevant specification documents in relation to particular precautions when using the sanken products, and refer to our official website in relation to general instructions and directions for using the s anken products. dsgn - cez - 16001 downloaded from: http:///

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