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product structure silicon monolithic integrated circuit this product has not designed prot ection against radioactive rays . 1/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 tsz22111 ? 14 ? 001 www.rohm.com led drivers for lcd backlights 1ch boost up type white led driver for large lcd BD9486F 1.1 general description BD9486F is a high efficiency driver for white leds and is designed for large lcds. BD9486F has a boost dcdc converter that employs an a rray of leds as the light source. BD9486F has some protect functions against fault conditions, such as over-voltage protection (ovp), over current limit protection of dcdc (ocp), led ocp protection, and over boost protection (fbmax). therefore it is available for the fail-safe design over a wide range output voltage. features ? dcdc converter with current mode ? vout discharge function at shutdown ? led protection circuit (over boost protection, led ocp protection) ? over-voltage protection (ovp) for the output voltage vout ? adjustable soft start ? adjustable oscillation frequency of dcdc ? wide range of analog dimming 0.2v to 3.0v ? uvlo detection for the input voltage of the power stage applications ? tv, computer display, lcd backlighting key specifications ? operating power supply voltage range:9.0v to 18.0v ? oscillator frequency of dcdc: 150khz (rt=100k ? ) ? operating current: 2.6ma(typ.) ? operating temperature range: -40c to +85c 1.2 package(s) w(typ) x d(typ) x h(max) sop16 10.00mm x 6.20mm x 1.71mm pin pitch 1.27mm figure 1. sop16 1.3 typical appli cation circuit(s) figure 2. typical application circuit datashee t downloaded from: http:///
datasheet d a t a s h e e t 2/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 1.4 absolute maximum ratings (ta=25c) parameter symbol ratings unit power supply voltage vccmax 20 v stb, ovp, uvlo, pwm, adim terminal voltage stb, ovp, uvlo, pwm, adim 20 v ss, rt, isense, fb, cs, cp, reg50 terminal voltage ss, rt, isense, fb, cs, cp, reg50 7 v dimout, gate terminal voltage dimout, gate vcc v power dissipation pd 625 (note 1) mw operating temperature range topr -40 to +85 c junction temperature tjmax 150 c storage temperature range tstg -55 to +150 c (note 1) in the case of mounting 1 laye r glass epoxy base-plate of 70mm70mm1.6mm, derate by 5.0mw/c when operating above ta=25c. 1.5 operating ratings parameter symbol range unit power supply voltage vcc 9.0 to 18.0 v dc/dc oscillation frequency fsw 50 to 800 khz effective range of adim signal vadim 0.2 to 3.0 v pwm input frequency fpwm 90 to 2000 hz 1.6 external components recommended range parameter symbol range unit reg50 connection capacitance c reg50 0.5 to 10 (note 2) f ss connection capacitance c ss 0.001 to 2.2 (note 2) f rt connection resistance r rt 15 to 300 k ? gate drive capacitance c gate to 1000 pf (note 2) please set connection capacitance above min value of recommended range according to temperature characteristic and dc bias characteristic. 1.7 pin configuration 1.8 physical dimension and marking diagram figure 3. pin configuration figure4. physical dimens ion and marking diagram of sop16 downloaded from: http:///
datasheet d a t a s h e e t 3/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 1.9 electrical characteristics (unless otherwise specified, ta=25c vcc=12v) parameter symbol limit unit condition min. typ. max. total current consumption circuit current icc 2.6 5.2 ma vstb=3.0v, pwm=3.0v, gate=l,ireg50=0ma circuit current (standby) ist 40 80 a vstb=0v uvlo block operation voltage vcc vuvlo_vcc 6.5 7.5 8.5 v vcc=sweep up hysteresis voltage vcc vuhys_vcc 150 300 600 mv vcc=sweep down uvlo release voltage vuvlo 2. 88 3.00 3.12 v vuvlo=sweep up uvlo hysteresis voltage vuhys 250 300 350 mv vuvlo=sweep down uvlo pin leak current uvlo_lk -2 0 2 a vuvlo=4.0v dc/dc block isense threshold voltage 1 vled1 0.225 0.233 0.242 v vadim=0.7v isense threshold voltage 2 vled2 0.656 0.667 0.677 v vadim=2.0v isense threshold voltage 3 vled3 0.988 1.000 1.012 v vadim=3.0v isense clamp voltage vled4 0.989 1.015 1.040 v vadim=3.3v (at masked analog dimming) oscillation frequency fct 142.5 150 157.5 khz rt=100k ? rt short protection range rt_det -0.3 - vrt 90% v rt=sweep down rt terminal voltage vrt 1.6 2.0 2.4 v rt=100k ? rt pin on resistance at off rrt_l - 2.0 4.0 k ? at latch off gate pin max duty output max_duty 90 95 99 % rt=100k ? gate pin on resistance (as source) ronso 2.5 5.0 10.0 ? gate pin on resistance (as sink) ronsi 2.0 4.0 8.0 ? ss pin source current i ssso -3.75 -3.0 -2.25 a vss=2.0v ss pin on resistance at off rss_l - 3.0 5.0 k ? soft start ended voltage vss_end 3.52 3.70 3.88 v ss=sweep up fb source current ifbso -115 -100 -85 a visense=0.2v, vadim=3.0v, vfb=1.0v fb sink current ifbsi 85 100 115 a visense=2.0v, vadim=3.0v, vfb=1.0v ocp detect voltage vcs 360 400 440 mv cs=sweep up ocp latch off detect voltage vcs 0.85 1.00 1.15 v cs=sweep up dc/dc protection block ovp detect voltage vovp 2.88 3.00 3.12 v vovp sweep up ovp detect hysteresis vovp_hys 150 200 250 mv vovp sweep down ovp pin leak current ovp_lk -2 0 2 a vovp=4.0v, vstb=3.0v downloaded from: http:///
datasheet d a t a s h e e t 4/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 1.9 electrical characteristics (unless otherwise specified, ta=25c vcc=12v) parameter symbol limit unit condition min. typ. max. led protection block led ocp detect voltage vledocp 2.88 3.0 3.12 v visense=sweep up over boost detection voltage vfbh 3.84 4.00 4.16 v vfb=sweep up dimming block adim pin leak current iladim -2 0 2 a vadim=2.0v isense pin leak current il_isense -2 0 2 a visense=4.0v dimout source on resistance ronso 5.0 10 20 ? dimout sink on resistance ronsi 4.0 8.0 16 ? reg50 block reg50 output voltage 1 reg50 _1 4.95 5.00 5.05 v io=0ma reg50 output voltage 2 reg 50_2 4.925 5.00 5.075 v io=-5ma reg50 available current | ireg50 | 5 - - ma reg50_uvlo detect voltag e reg50_th 2.0 2.3 2.6 v vreg50=sweep down vstb=0v reg50 discharge current reg50_dis 3.0 5.0 7.0 a stb=on->off, reg50=4.0v, pwm=l k stb block k stb pin high voltage stbh 2.0 - 18 v stb pin low voltage stbl -0.3 - 0.8 v stb pull down resistance rstb 600 1000 1400 k ? vstb=3.0v k pwm block k pwm pin high voltage pwm_h 1.5 - 18 v pwm pin low voltage pwm_l -0.3 - 0.8 v pwm pin pull down resistance rpwm 600 1000 1400 k ? vpwm=3.0v k fail block k cp detect voltage vcp 2.85 3.0 3.15 v vcp=sweep up cp charge current icp 2.7 3.0 3.3 a downloaded from: http:///
datasheet d a t a s h e e t 5/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 2.1 pin function no. pin name in/out function rating [v] 1 reg50 out 5.0v output voltage pin and shutdown timer pin -0.3 to 7 2 stb in ic on/off pin -0.3 to 20 3 ovp in over voltage protection detection pin -0.3 to 20 4 uvlo in under voltage lock out detection pin -0.3 to 20 5 ss out slow start setting pin -0.3 to 7 6 pwm in external pwm dimming signal input pin -0.3 to 20 7 cp out charge timer for abnormal state -0.3 to 7 8 adim in adim signal input pin -0.3 to 20 9 rt out dc/dc switching frequency setting pin -0.3 to 7 10 fb out error amplifier output pin -0.3 to 7 11 isense in led current detection input pin -0.3 to 7 12 gnd - - 13 dimout out dimming signal output for nmos -0.3 to vcc 14 gate out dc/dc switchi ng output pin -0.3 to vcc 15 cs in dc/dc output current detect pin, ocp input pin -0.3 to 7 16 vcc in power supply pin -0.3 to 20 downloaded from: http:///
datasheet d a t a s h e e t 6/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 2.2 pin esd type ovp uvlo ss rt reg50 cp adim fb dimout / vcc i i gate / vcc / cs pwm / stb isense figure 5. pin esd type downloaded from: http:///
datasheet d a t a s h e e t 7/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 2.3 block diagram figure 6. block diagram downloaded from: http:///
datasheet d a t a s h e e t 8/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 2.4 typical performance curves (reference data) figure 7. circuit current (active) figure 8. fsw vs rt characteristic figure 9. fb sink current vs fb voltage characteristic figure 10. fb source current vs fb voltage characteristic figure 11. isense feedback voltage vs adim voltage characteristic downloaded from: http:///
datasheet d a t a s h e e t 9/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 2.5 pin description pin 1: reg50 this is the 5.0v(typ.) output pin. available current is 5ma (min). and this terminal is also used as timer for discharging dcdc output capacitor. please refer to section 3.2.2 shutdown method and reg50 capacitance setting, for detailed explanation. pin 2: stb this is the on/off setting terminal of the ic. input reset-signal to this terminal to reset ic from latch-off. at startup, internal bias starts at high level, a nd then pwm dcdc boost starts after pwm rise edge inputs. note: ic status (ic on/off) transits depending on the voltage inputted to stb terminal. avoid the use of intermediate level (from 0.8v to 2.0v). in order to discharge output voltag e while stb=l and reg50uvlo=h, dimo ut can assert high, depending on pwm logic. about discharge behavior at end, please refer to secti on 3.5.3 timing chart or section 3.2.2 shutdown method and reg50 capacitance setting. pin 3: ovp the ovp terminal is the input for over-voltage protection. if ovp is more than 3.0v(typ ), the over-voltage protection (ovp) will work. at the moment of thes e detections, it sets gate=l, dimout=l and starts to count up the abnormal interval. if ovp detection continued to count four gate clocks, ic reaches latch off. (please refer to 3.5.5 timing chart) the ovp pin is high impedance, because the internal resistance is not connected to a certain bias. even if ovp function is not used, pin bias is still required because the open connection of this pin is not a fixed potential. the setting example is separately described in the section 3.2.7 ovp setting. as pwm=l interval, ic operates to keep the ovp pin voltage therefore the output voltage. please refer the section tbd the retaining function of the output voltage. pin 4: uvlo under voltage lock out pin is the input voltage of the power st age. , ic starts the boost operat ion if uvlo is more than 3.0v(typ) and stops if lower than 2.7v(typ). the uvlo pin is high impedance, because the inter nal resistance is not connected to a certain bias. even if uvlo function is not used, pin bias is still required because the open connection of this pin is not a fixed potential. the setting example is separately described in the section 3.2.6 uvlo setting pin 5: ss this is the pin which sets the soft start interval of dc/ dc converter. it performs the c onstant current charge of 3.0 a to external capacitance css. the switching duty of gate out put will be limited during 0v to 3.7v of the ss voltage. so the soft start interval tss can be expressed as follows tss = 1.23*10 6 *css css: the external capacitance of the ss pin . the logic of ss pin asserts low is defined as the latch-off state or pwm is not input high level after stb reset release. when ss capacitance is under 1nf, take note if the in-rush curr ent during startup is too large, or if over boost detection (fbmaxi) mask timing is too short. please refer to soft start behavior in the section 3.5.4 timing chart . pin 6: pwm this is the pwm dimming signal input terminal. the high / low level of pwm pins are the following. state pwm input voltage pwm=h pwm=1.5v to 18.0v pwm=l pwm= \ 0.3v to 0.8v pin 7: cp timer pin for counting the abnormal state of the over boost protection (fbmax). if the abnormal state is detected, the cp pin starts charging the external capacitance by 3 a. as the cp voltage reaches 3.0v, ic will be latched off. (gate=l, dimout=l). please refer to section 3.2.8 interval until latch off setting, for detailed explanation. pin 8: adim this is the input pin for analog dimming signal. the isense feedb ack point is set as 1/3 of this pin bias. if more than 3.0v is input, isense feedback voltage is clamped to limit to flow led large current. in this condition, the input current is caused. please refer to terminal explanation. downloaded from: http:///
datasheet d a t a s h e e t 10/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F pin 9: rt this is the dc/dc switching frequency setting pin. dcdc frequency is decided by connected resistor. the relationship between the frequency and rt resistance value (ideal) the oscillation setting ranges from 50khz to 800khz. the setting example is separately described in the section 3.2.5 dcdc oscillation frequency setting the fail logic indicating the abnormal state can be obtained by using the right circuit example. the gate capacitor is limited to 200pf. we recommend re1c001vn for m1.the rt pin output the 2.0v(typ.) in the normal state and drops to 0v in the latch off state. w hen reg50 reaches to 0v,there is a point that fail output voltage is uns table, if this is a problem, please add c1 capacitor. please refer to section 2.7 behavior list of the protect functions or 3.5 timing chart. pin 10: fb this is the output terminal of error amplifier. fb pin rises with the same slope as the ss pin during the soft-start period. after soft -start completion (ss>3.7v), it operates as follows. when pwm=h, it detects isense terminal voltage and outputs error signal compared to analog dimming signal (adim). it detects over boost (fbmax) over fb=4.0v(typ). after the ss completion, if fb>4.0v and pwm=h continues 4clk gate, the cp charge starts. after that, only the fb>4.0v is monitored, if cp charge continues to the cp=3.0v, ic will be latched off. (please refer to section 3.5.6 timing chart.) the loop compensation setting is described in section "3.4 loop compensation". pin 11: isense this is the input terminal for the current detection. error amplifier compares the lower one among 1/3 of the voltage terminal adim analog dimming and 1.0v(typ). and it detects abnormal led overcurrent at isense=3.0v(typ) over. if gate terminal continues during four clks (equivalent to 40 s at fosc = 100khz), it becomes latch-off. (please refer to section 3.5.7 timing chart.) i[] = [] figure 13. relationship of the feedback voltage and adim figure 14. isense terminal circuit example pin 12: gnd this is the gnd pin of the ic. ] k[ ] khz [ f r sw rt ? ? 15000 figure 12. rt terminal circuit example ch1: stb ch2: reg50 ch3: fail downloaded from: http:///
datasheet d a t a s h e e t 11/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F pin 13: dimout this is the output pin for external dimming nmos. the table below shows the rough output logic of each operation state, and the output h level is vcc. please refer to 3.5 timing chart for detailed explanations, because dimout logic has an exceptional behavior. please insert the resistor r dim between the dimming mos gate to improv e the over shoot of led current, as pwm turns from low to high. status dimout output normal same logic to pwm abnormal gnd level pin 14: gate this is the output terminal for driving t he gate of the boost mosfet. the high level is vcc. frequency can be set by the resistor connected to rt. refer to pin description for the frequency setting. pin 15: cs the cs pin has two functions. 1. dc / dc current mode feedback terminal the inductor current is converted to t he cs pin voltage by the sense resistor r cs. this voltage compared to the voltage set by error amplifier controls the output pulse. 2. inductor current limit (ocp) terminal the cs terminal also has an over curre nt protection (ocp). if the voltage is more than 0.4v(typ.), the switching operation will be stopped compulsorily. and the next boost pulse will be restarted to normal frequency. in addition, the cs voltage is more than 1.0v(typ.) during four gate clocks, ic will be latch off. as above ocp operation, if the current continues to flow nevertheless gate=l because of the de struction of the boost mos, ic will stops the operation completely. both of the above functions are enabled after 300ns (typ) when gate pin asserts high, because the leading edge blanking function (leb) is included into this ic to prevent the effect of noise. please refer to section 3.3.1 ocp setting / calculation me thod for the current rating of dcdc parts, for detailed explanation. if the capacitance cs in the right figure is increased to a micro order, please be careful that the limited value of nmos drain current id is more than the simple calculation. because the current id flows not only through rcs but also through cs, as the cs pin voltage moves according to id. pin 16: vcc this is the power supply pin of the ic. input range is from 9v to 18v. the operation starts at more than 7.5v(typ) and shuts down at less than 7.2v(typ) figure 15. dimout terminal circuit example figure 16. cs terminal circuit example downloaded from: http:///
datasheet d a t a s h e e t 12/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 2.6 detection condition list of the protect functions (typ condition) protect function detection pin detect condition release condition timer operation protection type detection condition pwm ss fbmax fb fb > 4.0v h(4clk) ss>3.7v fb < 4.0v cp charge latch off led ocp isense isense > 3.0v - - isense < 3.0v 4clk latch off rt gnd short rt rt3.0v no restart by release reg50uvlo reg50 reg50<2.3v - - reg50>2.6v no restart by release vcc uvlo vcc vcc<7.2v - - vcc>7.5v no restart by release ovp ovp ovp>3.0v - - ovp<2.8v 4clk latch off ocp cs cs>0.4v - - - no pulse by pulse ocp latch cs cs>1.0v - - cs<1.0v 4clk latch off to reset the latch type protection, please set stb logic to l once. otherwise the detection of vccuvlo, reg50uvlo is required. the clock number of timer operation corresponds to the boost pulse clock. 2.7 behavior list of the protect function protect function operation of the protect function dc/dc gate output dimming transistor (dimout) logic ss pin rt pin (failb logic) fbmax stops after latch l after latch discharge after latch l after latch led ocp stops immediately h immediately, l after latch discharge after latch l after latch rt gnd short stops immediately immediately l not discharge - stb stops immediately l after reg50uvlo detects discharge immediately l after reg50uvlo detects uvlo stops immediately immediately l discharge immediately h (2.0v) reg50uvlo stops immediately immediately l discharge immediately h (2.0v) vcc uvlo stops immediately immediately l discharge immediately h (2.0v) ovp stops immediately immediately l discharge after latch l after latch ocp stops immediately normal operation not discharge h (2.0v) ocp latch stops after latch l after latch discharge after latch l after latch please refer to section 3.5 timing chart for details. downloaded from: http:///
datasheet d a t a s h e e t 13/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.1 application circuit example introduce an example application using the BD9486F. 3.1.1 basic application example figure 17. basic application example ? 3.1.2 analog dimming or pwm dimming examples figure 18. example circuit for analog dimming figure 19. example circuit for pwm dimming i i i i i i i i i i i i downloaded from: http:///
datasheet d a t a s h e e t 14/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.2 external components selection 3.2.1 start up operation and soft start external capacitance setting the below explanation is the start up sequence of this ic figure 20. startup waveform figure 21. circuit behavior at startup explanation of start up sequence 1. reference voltage ref50 starts by stb=h. 2. ss starts to charge at the time of first pwm=h. at th is moment, the ss voltage of slow-start starts to equal fb voltage,and the circuit becomes fb=ss regardless of pwm logic. 3. when fb=ss reaches the lower point of internal sawtooth waveform, gate terminal outputs pulse and starts to boost vout. 4. it boosts vout and vout reaches the voltage to be able to flow led current. 5. if led current flows over decided level, fb=ss circuit disconnects and startup behavior completes. 6. then it works normal operation by feedback of isense terminal. if led current doesn't flow when ss becomes over 3.7v, ss=ff circuit completes forcibly and fbmax protection starts. method of setting ss external capacitance according to the sequence described above, start time tss that startup completes with fb=ss condition is the time that fb voltage reaches the feedback point. the capacitance of ss terminal is defined as css and the feedback voltage of fb terminal is defined as vfb. the equality on t fb is as follows. if css is set to a very small value, rush cu rrent flows into the inductor at startup. on the contrary, if css is enlarged t oo much, led will light up gradually. since css differs in the constant set up with the characteristic searched for and differs also by factors, such as a voltage rise ratio, an output capacitance, dcdc frequency, and led current, please confirm with the system. setting example when css=0.1 f,iss=3 a,and startup completes at vfb=3.7v, ss setting time is as follows. [sec] ]a [3 ]v[ vfb ]f [ c t ss ss ? ? [sec] 123 .0 ]a[ 10 3 ]v[7.3]f[ 10 1.0 t 6 6 ss ? ? ? ? ? ? ? i _ _ = i i i downloaded from: http:///
datasheet d a t a s h e e t 15/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.2.2 shutdown method and reg50 capacitance setting when this ic shuts down, vout discharge function works. indicated below is the sequence. figure 22. the waveform and diagram at shutdown sequence explanation of shutdown 1. when stb=l, gate and reg50 stop. 2. while stb=l and reg50uvlo=h, di mout asserts the same logic of pwm. and vout is discharged until reg50=5.0v reaches 2.3v by -5 a(typ.). 3. when vout is discharged enough by iled, iled doesnt get to flow. 4. when reg50 voltage reaches under 2. 3v(typ), whole system is shutdown. setting method of reg50 capacitance when reg50 terminal capacitance is defined as c reg , shutdown time t off is decided by the following equation. when discharge function is used, pwm signal mu st be continuously inputted after stb=l. vout discharge time is longest when pwm is set on mininum duty. please set c reg capacitance value with margin so that the system is shutdown after vout is discharged enough. please refer 1.6external components recommended range when setting c reg capacitance. 3.2.3 vcc series resistance setting here are the following effects of inse rting series resistor rvcc into vcc line. (i) in order to drop the voltage vcc, it is possible to suppress the heat generation of the ic. (ii) it can limit the inflow current to vcc line. however, if resistance rvcc is set bigger, vcc voltage becomes under minimum operation voltage (vcc<9v). rvcc must be set to an appropriate series resistance. especially, after stb is set to high, ireg may become large and vcc may fall greatly in the section charged to the capacitor of reg50 terminal depending on the external circuit of a vcc terminal. even in such a case, please set up to be set to vcc>9v in an operating condition. ics inflow current line i_in has the following inflow lines. ? ics circuit current icc ? current of rreg connected to reg50 ireg ? current to drive fets gate i_gate these decide the voltage v at rvcc. vcc terminal voltage at that time can be expressed as follows. here, judgement is the 9v minimum operation voltage. please consider a sufficient margin when setting the series resistor of vcc. ?? ]v[9 ] ? [ rvcc ]a[ ireg ]a[ idcdc ]a[ icc ]v[ vin [v] vcc ? ? ? ? ? ? figure 23. vcc series resistance circuit example [sec] ] [5 ][)3.2 0.5( ] [ a v f c t reg off ? ? ? ? ? downloaded from: http:///
datasheet d a t a s h e e t 16/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F setting example above equation is translated as follows. when vin=12v, icc=2.0ma, ireg =50ma and idcdc=2ma, rvccs value is calculated as follows. (icc is 2.6ma(typ.)) . please set each values with tolerance and margin. 3.2.4 led current setting led current can be adjusted by setting the resistance r s [ ? ] which connects to isense pin and adim[v]. relationship between r s and i led current with dc dimming (adim<3.0v) without dc dimming (adim>3.0v) setting example if i led current is 200ma and adim is 2.0v, we can calculate r isense as below. 3.2.5 dcdc oscillation frequency setting r rt which connects to rt pin sets the oscillation frequency f sw of dcdc. relationship between frequency f sw and rt resistance (ideal) setting example when dcdc frequency fsw is set to 200khz, r rt is as follows. ] ? [33.3 ]a[2.0 ]v[0.2 3 1 ]a[ i ]v[ adim 3 1 r led isense ? ? ? ? ] ? [ ]a[ i ]v[ adim 3 1 r led isense ? ? ]a[ ireg ]a[ idcdc ]a[ icc ]v[9 ]v[ vin ] ? [ rvcc ? ? ? ? ] ? [ ]a[ i ]v[ 015 .1 r led isense ? figure 24. led current setting example figure 25. rt terminal setting example ] k[ ] khz [ f 15000 r sw rt ? ? ] k[ ] khz [ ] khz [f r sw rt ? ? ? ? 75 200 15000 15000 ][ [a] ]a [ . ] a [ . ]v[ ] v[ ][ rvcc ? ? ? ? ? ? ? 56 0.050 002 0 002 0 9 12 downloaded from: http:///
datasheet d a t a s h e e t 17/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.2.6 uvlo setting under voltage lock out pin is the input voltage of the power stage. ic starts boost operation if uvlo is more than 3.0v(typ.) and stops if lower than 2.7v(typ.). the uvlo pin is high impedance, because the inter nal resistance is not connected to a certain bias. so, the bias by the external components is required, becau se the open connection of this pin is not a fixed potential. detection voltage is set by dividing resistors r1 and r2. the resistor values can be calculated by the formula below. uvlo detection equation as vin decreases, r1 and r2 values are set in the following formula by the vin det that uvlo detects. uvlo release equation r1 and r2 setting is decided by the equation above. the equation of uvlo release voltage is as follows. setting example if the normal input voltage, vin is 24v, t he detect voltage of uvlo is 18v, r2 is 30k ? , r1 is calculated as follows. by using these r1 and r2, the release voltage of uvlo, vin can , can be calculated too as follows. ]v[ ] ? k[2r ]) ? k[2r ] ? k[1r( v0.3 vin can ? ? ? ] ? k[ ]v[7.2 ])v[7.2 ]v[ vin ( ] ? k[2r 1r det ? ? ? ]k[ . ]v[. ])v[. ]v[( ]k[ ]v[. ])v[. ]v[ vin ( ]k[r r det ? ? ? ? ? ? ? ? ? ? 0 170 72 72 18 30 72 72 2 1 ]v[ . ]v[ ]k[ ]k[ ]k[ ]v[. ]k[r ]) k[r ]k[r( ]v[. vin can 0 20 30 30 170 03 2 2 1 03 ? ? ? ? ? ? ? ? ? ? ? ? ? figure 26. uvlo setting example downloaded from: http:///
datasheet d a t a s h e e t 18/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.2.7 ovp setting the ovp terminal is the input for over-v oltage protection of output voltage. the ovp pin is high impedance, because the internal resistance is not connected to a certain bias. detection voltage of vout is set by dividing resistors r1 and r2. the resistor values can be calculated by the formula below. ovp detection equation if vout is boosted abnormally, vovp det, the detect voltage of ovp, r1, r2 can be expressed by the following formula. ovp release equation by using r1 and r2 in the above equation, the release voltage of ovp, vovp can can be expressed as follows. setting example if the normal output voltage, vout is 40v, the detect voltage of ovp is 48v, r2 is 10k ohm, r1 is calculated as follows. by using these r1 and r2, the release voltage of ovp, vovp can can be calculated as follows. 3.2.8 interval until latch off setting about over boost protection (fbmax), t he capacitance value of cp terminal can set the time of latch-off. about the behavior from abnormal detection to latch-off, pl ease refer to the section 3.5.6 timing chart. the condition fb>4.0v(typ.) and pwm=h cont inues more than four gate clocks, t he cp terminal charge is started by 3 a. after that, only the fb voltage is monitored. as the cp voltage reaches to 3.0v(typ.), ic will be latched off. the time latch time to reach to latch-off is set by cp terminal capacitance as follows. setting example if the capacitor of cp pin is 0.47 f, the timer latch interval is as follows. figure 27. ovp setting example ]k[ ]v[. ])v[. ]v[ vovp ( ]k[r r det ? ? ? ? ? 03 03 2 1 ]v[ ] k[r ]) k[r ] k[r( v. vovp can ? ? ? ? ? ? 2 2 1 82 ] k[ ]v[ ])v[ ]v[ ( ] k[ ]v[. ])v[. ]v[ vovp ( ] k[r r det ? ? ? ? ? ? ? ? ? ? 150 3 3 48 10 03 03 2 1 ]v[. ]v[ ] k[ ] k[ ] k[ ]v[. ] k[ r ]) k[ r ] k[r( ]v[. vovp can 8 44 10 150 10 82 2 2 1 82 ? ? ? ? ? ? ? ? ? ? ? ? ? [sec] ]a [. ]v[. ]f[ c latch cp time ? ? ? ? 03 03 sec] m[ ]a [. ]v[. ]f[ . latch time 470 03 03 47 0 ? ? ? ? ? downloaded from: http:///
datasheet d a t a s h e e t 19/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.3 dcdc parts selection 3.3.1. ocp setting / calculation method for the current rating of dcdc parts ocp detection stops the switching when the cs pin voltage is more than 0.4v . the resistor value of cs pin, r cs needs to be considered by the coil l current. and the current rating of dcdc external parts is required more than the peak current of the coil. shown below are the calculation method of the coil peak curr ent, the selection method of r cs (the resistor value of cs pin) and the current rating of the external dcdc parts at continuous current mode. the calculation method of the coil peak current, ipeak at continuous current mode at first, since the ripple voltage at cs pin depends on the application condition of dcdc, the following variables are used. vout voltage=vout[v] led total current=iout[a] dcdc input voltage of the power stage =vin[v] efficiency of dcdc = [%] and then, the average input current iin is calculated by the following equation. and the ripple current of the inductor l ( il[a]) can be calculated by using dcdc the switching frequency, fsw, as follows. on the other hand, the peak current of the inducto r ipeak can be expressed as follows. (1) therefore, the bottom of t he ripple current imin is or 0 if imin>0, the operation mode is ccm (continuous current mode), otherwise the mode is dcm (di scontinuous current mode). (the selection method of rcs at continuous current mode) ipeak flows into rcs and that causes the voltage signal to cs pin. (please refer to the timing chart at the right) peak voltage vcspeak is as follows. as this vcspeak reaches 0.4v, the dcdc output stops the switching. therefore, rcs value is necessar y to meet the condition below. (the current rating of the external dcdc parts) the peak current as the cs voltage reaches ocp level (0.4v) is defined as ipeak_det. (2) the relationship among ipeak (equation (1)), ipeak_det (equation (2)) and the current rating of parts is required to meet the following please make the selection of the external parts such as fet, inductor, diode meet the above condition. ]a[ [%] ]v[v ]a[ i]v[ v i in out out in ?? ? ? ]a[ ]hz[ f]v[ v ]h[l ]v[v ])v[v ]v[ v( il sw out in in out ? ? ? ? ? ]a[ ]a[il ]a[i ipeak in 2 ? ? ? ]v[ ipeak rcs vcs peak ? ? ?? ?? det_ peak peak i i 2 ]a[il ]a[i in im in ? ? ? ]v[. ]v[ ipeak rcs 40 ? ? ? ]a[ ][ rcs ]v[. i det_ peak ? ? 40 the current rating of parts figure 28. coil current waveform [] i[] [] downloaded from: http:///
datasheet d a t a s h e e t 20/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F [setting example] output voltage = vout [v] = 40v led total current = iout [a] = 0.48v dcdc input voltage of the power stage = vin [v] = 24v efficiency of dcdc = [%] = 90% averaged input current iin is calculated as follows. if the switching frequency, f sw = 200khz, and the inductor, l=100 h, the ripple current of the inductor l ( il[a]) can be calculated as follows. therefore the inductor peak current, ipeak is if rcs is assumed to be 0.3 ? rcs value confirmation the above condition is met. and ipeak_det, the current ocp works, is if the current rating of the used parts is 2a, this inequality meets the above relationship. the parts selection is proper. and i min , the bottom of the il ripple current, can be calculated as follows. this inequality implies that the operat ion is continuous current mode. ]a[ . [%] ]v[ ]a[. ]v[ [%] ]v[v ]a[ i]v[ v ]a[i in out out in 89 0 90 24 48 0 40 ? ? ? ? ?? ? ? ]a[ . ]hz[ ]v[ ]h[ ]v[ ])v[ ]v[ ( ]hz[ f]v[ v ]h[l ]v[v ])v[v ]v[ v( il sw out in in out 48 0 10 200 40 10 100 24 24 40 3 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ]a[ . ]a[ . ]a[ . ]a[ ]a[il ]a[i ipeak in 13 1 2 48 0 89 0 2 ? ? ? ? ? ? 0 65 0 48 0 13 1 2 ?? ? ? ? ? ? ? ]a[ . ]a[ . ]a[ . ]a[ ]a[il ]a[i i in min ?? ?? det_ peak peak i i calculation result of the peak current v . ]v[ . ]a[ . ][. ipeak rcs vcs peak 40 339 0 13 1 30 ? ? ? ? ? ? ? ? ]a[ . ][. ]v[. i det_ peak 33 1 30 40 ? ? ? ]a[. ]a[ . ]a[ . 02 33 1 13 1 ? ? ? ? ? the current rating current rating confirmation of dcdc parts downloaded from: http:///
datasheet d a t a s h e e t 21/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.3.2. inductor selection the inductor value affects the input ripple current. as shown in section 3.3.1, where l: coil inductance [h] v out : dcdc output voltage [v] v in : input voltage [v] i out : output load current (the summation of led current) [a] i in : input current [a] f sw : oscillation frequency [hz] in continuous current mode, S il is set to 30% to 50% of the out put load current in many cases. in using smaller inductor, the boost is operated by the disc ontinuous current mode in which the coil current returns to zero at every period. *the current exceeding the rated current va lue of inductor flown through the coil c auses magnetic saturation, results in decreasing in efficiency. inductor needs to be selected to have such adequate margin that peak current does not exceed the rated current value of the inductor. *to reduce inductor loss and improve efficiency, inductor with low resistance components (dcr, acr) needs to be selected 3.3.3. output capaci tance cout selection output capacitor needs to be selected in co nsideration of equivalent series resistance required to even the stable area of output volt age or ripple voltage. be aware that set led current may not be flown due to decrease in led terminal voltage if output ripple component is high. output ripple voltage v out is determined by equation (4): (4) ]v[ r il vout esr ????? ? ? when the coil current is charged to the out put capacitor as mos turns off, much output ripple is caused. much ripple voltage of the output capacitor may cause the led current ripple. * rating of capacitor needs to be selected to have adequate margin against output voltage. *to use an electrolytic capacitor, adequate margin against a llowable current is also necessary. be aware that the led current is larger than the set value transitionally in case that led is provided with pwm dimming especially. 3.3.4. mosfet selection there is no problem if the absolute maximum rating is larger than the rated current of the induc tor l, or is larger than the sum of the tolerance voltage of c out and the rectifying diode v f . the product with small gate capacitance (injected charge) needs to be selected to achieve high-speed switching. * one with over current protection setting or higher is recommended. * the selection of one with small on resistance results in high efficiency. 3.3.5. rectifying diode selection a schottky barrier diode which has current ability higher than the rated current of l, reve rse voltage larger than the tolerance voltage of c out , and low forward voltage vf especially needs to be selected. ]a[ ] hz[ f]v[ v ]h[l ]v[ v ])v[ v ]v[ v( il sw out in in out ? ? ? ? ? ]a[ ]a[il ]a[i ipeak in 2 ? ? ? ]a[ [%] ]v[ v ]a[ i]v[ v i in out out in ?? ? ? figure 29. inductor current waveform and diagram figure 30. output capacitor diagram i v out v in c out r cs l r esr i l downloaded from: http:///
datasheet d a t a s h e e t 22/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.4.loop compensation a current mode dcdc converter has each one pole (phase lag) f p due to cr filter composed of the output capacitor and the output resistance (= led current) and zero (phase lead) f z by the output capacitor and the esr of the capacitor. moreover, a step-up dcdc converter has rhp zero (right-half plane zero point) f zrhp which is unique with the boost converter. this zero may cause the unstable feedback. to avoid this by rhp zero, the loop compensation that the cross-over frequency f c, set as follows, is suggested. fc = f zrhp /5 (f zrhp : rhp zero frequency) considering the response speed, the calc ulated constant below is not always optimized completely. it needs to be adequately verified with an actual device. figure 31. output stage and error amplifier diagram i. calculate the pole frequency fp and the rhp zero frequency f zrhp of dc/dc converter where i led = the summation of led current, (continuous current mode) ii. calculate the phase compensa tion of the error amp output (f c = f zrhp /5) above equation is described for lighting led without the oscillation. the value may cause much error if the quick response for the abrupt change of dimming signal is required. to improve the transient response, r fb1 needs to be increased, and c fb1 needs to be decreased. it needs to be adequately verified with an actual device in consideration of variation from parts to parts since phase margin is decreased. ]hz[ i l )d ( v f led out zrhp ? ?? ? ? ? 2 1 2 ][ )d ( v gm f i r f r out p led cs rhzp fb ? ? ? ? ? ? ? ? ? 1 5 1 ] hz[ c v i f out out led p ? ?? ? 2 out in out v v v d ? ? ]s[ . gm 4 10 04 ? ? ? ]f[ zrhp f 1 fb r 2 5 c f 1 fb r 2 1 1 fb c ? ? ? ? ? ? downloaded from: http:///
datasheet d a t a s h e e t 23/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.5.timing chart 3.5.1 pwm start up 1 (input pwm signal after input stb signal) y y figure 32. pwm start up 1 (input pwm signal after input stb signal) (*1)reg50 starts up when stb is changed from low to high. in the state where the pwm signal is not inputted, ss terminal is not charged and dcdc doesnt start to boost, either. (*2)when reg50 is more than 2.6v, the reset signal is released. (*3)the charge of the pin ss starts at the positive edge of pwm= l to h, and the soft start starts. the gate pulse outputs only during the corresponding pwm=h. and while the ss is less t han 0.4v, the pulse does not output. the pin ss continues charging in spite of the assert ion of pwm or ovp level. (*4)the soft start interval will end if the voltage of t he pin ss, vss reaches 3.7v. by this time, it boosts v out to the voltage where the set led current flows. the abnormal detection of fbmax starts to be monitored. (*5)as stb=l, the boost operation is st opped instantaneously. (discharge operation continues in the state of stb=l and reguvlo=l. please refer to section 3.5.3) (*6)in this diagram, before t he charge period is completed, stb is chan ged to high again. as stb=h again, the boost operation restarts the next pwm=h. it is the same operation as the timing of (*2). (for capacitance setting of ss terminal, please refer to section 3.2.1. downloaded from: http:///
datasheet d a t a s h e e t 24/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.5.2 pwm start up 2 (input stb signal after inputted pwm signal) figure 33. pwm start up 2 (input stb signal after inputted pwm signal) (*1)reg50 starts up when stb=h. (*2)when reg50uvlo releases or pwm is inputted to the edge of pwm=l h, ss charge starts and soft start period is started. the gate pulse outputs only during the correspo nding pwm=h. and while the ss is less than 0.4v, the pulse does not output. the pin ss continues charging in sp ite of the assertion of pwm or ovp level. (*3)the soft start interval will end if the voltage of t he pin ss, vss reaches 3.7v. by this time, it boosts v out to the point where the set led current flows. the abnormal dete ction of fbmax starts to be monitored. (*4)as stb=l, the boost operation is st opped instantaneously (gate=l, ss=l). (di scharge operation works in the state of stb=l and reg50uvlo=h. please refer to section 3.5.3) (*5)in this diagram, before the discharge per iod is completed, stb is changed to high again. as stb=h again, operation will be the same as the timing of (*1). downloaded from: http:///
datasheet d a t a s h e e t 25/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.5.3 turn off i figure 34. turn off (*1)as stb=h l boost operation stops and reg50 starts to discharge. (*2)while stb=l, reg50uvlo=h, dimout becomes same as pwm. reg50=5.0v is discharged by -5 a until reg50=2.3v,and then ic becomes off stat e. reg50 is discharged rapidly and rt becomes 0v at the same time. v out is discharged completely until this time. it should be set to avoid a sudden brightness. about capacitance value setting of reg50, please refer to the section 3.2.2. downloaded from: http:///
datasheet d a t a s h e e t 26/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.5.4 soft start function figure 35. soft start function (*1)the ss pin charge does not start by just stb=h. pwm=h is required to start the soft start. in the low ss voltage, the gate pin duty depends on the ss voltage. and while the ss is less than 0.4v, the pulse does not output. (*2)by the time stb=l, the ss pin is discharged immediately. as reg50uvlo=h, rt is still high. (*3)as the stb recovered to stb=h, the ss charge star ts immediately by the logic pwm=h in this chart. (*4)the ss pin is discharged immediately by the uvlo=l. (*5)the ss pin is discharged immediately by the vccuvlo=l. (*6)the ss pin is discharged immediately by the reg50uvlo=l. (*7)the ss pin is not discharged by the abnormal detecti on of the latch off type such as ovp until the latch off. downloaded from: http:///
datasheet d a t a s h e e t 27/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.5.5 ovp detection figure 36. ovp detection (*1)as ovp is detected, the output gate=l, dimout=l, and the abnormal counter starts. (*2)if ovp is released within 4 clocks of abnormal counter of the gate pin frequency, the boost operation restarts. (*3)as the ovp is detected again, the boost operation is stopped. (*4)as the ovp detection continues up to 4 count by the abnormal counter, ic will be latched off. (*5) once ic is latched off, the boost operation doesn't restart even if ovp is released. (*6)the stb=l input can make ic reset. (*7)it normally starts as stb turns low to high. (*8)the operation of the ovp detection is not related to the logic of pwm. downloaded from: http:///
datasheet d a t a s h e e t 28/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.5.6 fbmax detection y y ????? ????? figure 37. fbmax detection (*2) during the soft start, it is not judged to t he abnormal state even if the fb=h(fb>4.0v). (*3) when the pwm=h and fb=h, the abnormal counter doesnt start immediately. (*4) the cp charge will start if the pwm=h and the fb=h detecti on continues up to 4 clocks of the gate frequency. once the count starts, only fb level is monitored. (*5) when the fbmax detection continues till the cp charge reaches 3.0v, ic will be latched off. the latch off interval can be calculated by the external capacitance of cp pin. (please refer to section 3.2.8.) (*6) the latch off state can be reset by the stb=l. (*7) it is normally started by pwm=l to h, in this figure. downloaded from: http:///
datasheet d a t a s h e e t 29/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F 3.5.7 led ocp detection i i figure 38. led ocp detection (*1)if isense>3.0v, ledocp is detecte d, and gate becomes l. to detect le docp continuously, the dimout is compulsorily high, regardless of the pwm dimming signal. (*2)when the ledocp releases within 4 counts of the gate frequency, the boost operation restarts. (*3) as the ledocp is detected again, the boost operation is stopped. (*4)if the ledocp detection continues up to 4 counts of gate frequency. ic will be latched off. (*5)once ic is latched off, the boost operation doesn't restart even if the ledocp releases. (*6)the latch off state can be reset by the stb=l. (*7)it normally starts by stb=l to h. (*8)the operation of the ledocp detection is not related to the logic of the pwm. downloaded from: http:///
datasheet d a t a s h e e t 30/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F operational notes 1. reverse connection of power supply connecting the power supply in reverse polarity can damage the ic. take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the ics power supply terminals. 2. power supply lines design the pcb layout pattern to provide low impedance supply lines. separate the ground and supply lines of the digital and analog blocks to prevent noise in the ground and supply lines of the digital bloc k from affecting the analog block. furthermore, connect a capacitor to ground at all po wer supply pins. consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. ground voltage ensure that no pins are at a voltage below that of t he ground pin at any time, even during transient condition. 4. ground wiring pattern when using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the refe rence point of the application board to avoid fluctuations in the small-signal ground caused by large currents. also ensure that the ground trac es of external components do not cause variations on the ground voltage. the ground lines must be as short and thick as possible to reduce line impedance. 5. thermal consideration should by any chance the power dissipation rating be exceed ed the rise in temperature of the chip may result in deterioration of the properties of the ch ip. the absolute maximum rating of the pd stated in this specification is when the ic is mounted on a 70mm x 70mm x 1.6mm glass epoxy b oard. in case of exceeding this absolute maximum rating, increase the board size and copper area to prevent exceeding the pd rating. 6. recommended operating conditions these conditions represent a range within which the expect ed characteristics of the ic can be approximately obtained. the electrical characteristics are guaranteed under the conditions of each parameter. 7. rush current when power is first supplied to the ic, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the ic has more than one power supply. therefore, give s pecial consideration to power coupling capacitance, power wiring, width of ground wiri ng, and routing of connections. 8. testing on application boards when testing the ic on an application board, connecting a capacitor directly to a low-impedance output pin may subject the ic to stress. always dischar ge capacitors completely after each process or step. the ics power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. to prevent damage from static discharge, ground the ic during assemb ly and use similar precautions during transport and storage. 9. inter-pin short and mounting errors ensure that the direction and position are correct when mounting the ic on the pc b. incorrect mounting may result in damaging the ic. avoid nearby pins being shorted to each other especially to ground, power supply and output pin. inter-pin shorts could be due to many reasons such as me tal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. downloaded from: http:///
datasheet d a t a s h e e t 31/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F operational notes C continued 10. unused input terminals input terminals of an ic are often con nected to the gate of a mo s transistor. the gate has extremely high impedance and extremely low capacitance. if left unconnected, the electric fi eld from the outside can easily charge it. the small charge acquired in this way is enough to produce a signifi cant effect on the conduction through the transistor and cause unexpected operation of the ic. so unless otherwise specified, unused input terminals should be connected to the power supply or ground line. 11. regarding the input pin of the ic this monolithic ic contains p+ isolat ion and p substrate layers between adjac ent elements in order to keep them isolated. p-n junctions are formed at the intersection of t he p layers with the n layers of other elements, creating a parasitic diode or transistor. for example (refer to figure below): when gnd > pin a and gnd > pin b, the p-n junction operates as a parasitic diode. when gnd > pin b, the p-n junction operates as a parasitic transistor. parasitic diodes inevitably occur in the structure of the ic. the operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical dam age. therefore, conditions that cause these diodes to operate, such as applying a voltage lower than the gnd voltage to an input pin (a nd thus to the p substrate) should be avoided. figure 39. example of monolithic ic structure 12. ceramic capacitor when using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with temperature and the decrease in nominal capacitance due to dc bias and others. 13. area of safe operation (aso) operate the ic such that th e output voltage, output current, and power dissipation are all within the area of safe operation (aso). 14. thermal shutdown circuit(tsd) this ic has a built-in thermal shutdown circuit that pr events heat damage to the ic. normal operation should always be within the ics power dissipation rating. if however th e rating is exceeded for a continued period, the junction temperature (tj) will rise which will activate the tsd circui t that will turn off all output pins. when the tj falls below the tsd threshold, the circuits are autom atically restored to normal operation. note that the tsd circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no circumstances, should the tsd circuit be used in a set desi gn or for any purpose other t han protecting the ic from heat damage. 15. over current protection circuit (ocp) this ic incorporates an integrated over current protection circuit that is acti vated when the load is shorted. this protection circuit is effective in pr eventing damage due to sudden and unexpecte d incidents. however, the ic should not be used in applications characterized by continuous operation or transitioning of the protection circuit. downloaded from: http:///
datasheet d a t a s h e e t 32/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F ordering information b d 9 4 8 6 f - e 2 part number package f:sop16 packaging and forming specification e2: embossed tape and reel marking diagrams sop16 (top view) BD9486F part number marking lot number 1pin mark downloaded from: http:///
datasheet d a t a s h e e t 33/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F physical dimension, tape and reel information package name sop16 ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tapequantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () direction of feed reel 1pin (unit : mm) pkg : sop16 drawing no. : ex114-5001 (max 10.35 (include.burr)) downloaded from: http:///
datasheet d a t a s h e e t 34/34 tsz02201-0f1f0c100240-1-2 ? 2013 rohm co., ltd. all rights reserved. 15.feb.2016 rev.006 www.rohm.com tsz22111 ? 15 ? 001 BD9486F revision history date revision changes 12.jul.2013 001 new release 09.sep.2013 002 p.4 delete reg50_uvlo_hysteresis item p.4 modify reg50 discharge current limits min. 4.95ua -> 3.0ua typ. 5.00ua -> 5.0ua max. 5.05ua -> 7.0ua 19.nev.2013 003 p.3 circuit current (icc) add condition gate=l,ireg50=0ma p.6 2.2 pin esd type add reg50 schemat ic (pwm sch. is moved to stb sch.) p.10 pin description pin11 isense sentence adim analog dimming and 3.0v(typ) adim analog dimming and 1.0v(typ) figure.13 modify schematic (add adim=3.3v) 13.feb.2014 004 p.11 modify dimout explanation to the output h level is vcc. modify gate explanation to the high level is vcc. modify the figure.15 of dimout terminal circuit example. 01.sep.2014 005 p.15 3.2.3 vcc series resistance setting add explanation p.16 modify equation 15.feb.2016 006 p.2 add 1.6 external components recommended range pin configuration 1.6 1.7 physical dimension and marking diagram 1.7 1.8 p.3 electrical characteristics 1.8 1.9 p.4 electrical characteristics 1.8 1.9 p.15 add reg50 capacitance setting downloaded from: http:///
notice-p ga -e rev.003 ? 201 5 rohm co., ltd. all rights reserved. notice precaution on using rohm products 1. our products are designed and manufactured for application in ordinary electronic equipments (such as av equipment, oa equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). if you intend to use our products in devices requiring extremely h igh reliability (such as medical equipment (note 1) , transport equipment, traffic equipment, aircraft/spacecraft, nuclear powe r controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property ( specific applications ), please consult with the rohm sales representative in adv ance. unless otherwise agreed in writing by rohm in advance, rohm s hall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arisin g from the use of any rohm s products for specific applications. (note1) medical equipment classification of the specific appl ications japan usa eu china class class class b class class ? class 2. rohm designs and manufactures its products subject to stri ct quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsibilities, adequ ate safety measures including but not limited to fail-safe desig n against the physical injury, damage to any property, whic h a failure or malfunction of our products may cause. the followi ng are examples of safety measures: [a] installation of protection circuits or other protective devic es to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. our products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditions, as exemplified be low. accordingly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from th e use of any rohms products under any special or extraordinary environments or conditions. if yo u intend to use our products under any special or extraordinary environments or conditions (as exemplified belo w), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be n ecessary: [a] use of our products in any types of liquid, including water, oils, chemicals, and organi c solvents [b] use of our products outdoors or in places where the products are exposed to direct sunlight or dust [c] use of our products in places where the products are e xposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the products are exposed t o static electricity or electromagnetic waves [e] use of our products in proximity to heat-producing component s, plastic cords, or other flammable items [f] sealing or coating our products with resin or other coating materials [g] use of our products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] use of the products in places subject to dew condensation 4. the products are not subject to radiation-proof design. 5. please verify and confirm characteristics of the final or mou nted products in using the products. 6 . in particular, if a transient load (a large amount of load appl ied in a short period of time, such as pulse. is applied, confirmation of performance characteristics after on-board mou nting is strongly recommended. avoid applying power exceeding normal rated power; exceeding the power rating u nder steady-state loading condition may negatively affec t product performance and reliability. 7 . de -rate power dissipation depending on ambient temperature. wh en used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8 . confirm that operation temperature is within the specified range desc ribed in the product specification. 9 . rohm shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. precaution for mounting / circuit board design 1. when a highly active halogenous (chlorine, bromine, etc .) flux is used, the residue of flux may negatively affect prod uct performance and reliability. 2. in principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method mus t be used on a through hole mount products. i f the flow soldering method is preferred on a surface-mount p roducts , please consult with the rohm representative in advance. for details, please refer to rohm mounting specification downloaded from: http:///
notice-p ga -e rev.003 ? 201 5 rohm co., ltd. all rights reserved. precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, p lease allow a sufficient margin considering variations o f the characteristics of the products and external components, inc luding transient characteristics, as well as static characteristics. 2. you agree that application notes, reference designs, and a ssociated data and information contained in this docum ent are presented only as guidance for products use. therefore, i n case you use such information, you are solely responsible for it and you must exercise your own independ ent verification and judgment in the use of such information contained in this document. rohm shall not be in any way respon sible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such informat ion. precaution for electrostatic this product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. please take pr oper caution in your manufacturing process and storage so t hat voltage exceeding the products maximum rating will not be applied to products. please take special care under dry co ndition (e.g. grounding of human body / equipment / solder iro n, isolation from charged objects, setting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriorate i f the products are stored in the places where: [a] the products are exposed to sea winds or corrosive gases, in cluding cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to direct sunshine or condensation [d] the products are exposed to high electrostatic 2. even under rohm recommended storage condition, solderabil ity of products out of recommended storage time period may be degraded. it is strongly recommended to confirm so lderability before using products of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the correct direction, which is indi cated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a c arton. 4. use products within the specified time after opening a humi dity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage tim e period. precaution for product label a two-dimensional barcode printed on rohm products label is f or rohm s internal use only. precaution for disposition when disposing products please dispose them properly usi ng an authorized industry waste company. precaution for foreign exchange and foreign trade act since concerned goods might be fallen under listed items of export control prescribed by foreign exchange and foreign trade act, please consult with rohm in case of export. precaution regarding intellectual property rights 1. all information and data including but not limited to appl ication example contained in this document is for reference only. rohm does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. rohm shall not have any obligations where the claims, a ctions or demands arising from the combination of the products with other articles such as components, circuits, systems or ex ternal equipment (including software). 3. no license, expressly or implied, is granted hereby under any inte llectual property rights or other rights of rohm or any third parties with respect to the products or the information contai ned in this document. provided, however, that rohm will not assert it s intellectual property rights or other rights against you or you r customers to the extent necessary to manufacture or sell products containing the products, subject to th e terms and conditions herein. other precaution 1. this document may not be reprinted or reproduced, in whole or in part, without prior written consent of rohm. 2. the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 3. in no event shall you use in any way whatsoever the pr oducts and the related technical information contained in the products or this document for any military purposes, includi ng but not limited to, the development of mass-destruction weapons. 4. the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties. downloaded from: http:///
datasheet datasheet notice ? we rev.001 ? 2015 rohm co., ltd. all rights reserved. general precaution 1. before you use our pro ducts, you are requested to care fully read this document and fully understand its contents. rohm shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny rohms products against warning, caution or note contained in this document. 2. all information contained in this docume nt is current as of the issuing date and subj ec t to change without any prior notice. before purchasing or using rohms products, please confirm the la test information with a rohm sale s representative. 3. the information contained in this doc ument is provi ded on an as is basis and rohm does not warrant that all information contained in this document is accurate an d/or error-free. rohm shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. downloaded from: http:///

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