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1 for more information www.analog.com typical application features description 65 v , 3.5 a synchronous step - down silent switcher with 2.5 a quiescent current the lt ? 8641 step - down regulator features silent switcher architecture designed to minimize emi emissions while delivering high efficiency at frequencies up to 3 mhz . as - sembled in a 3 mm 4 mm qfn , the monolithic construc - tion with integrated power switches and inclusion of all necessary circuitry yields a solution with a minimal pcb footprint . an ultralow 2.5 a quiescent current with the output in full regulation enables applications requiring highest efficiency at very small load currents . transient response remains excellent and output voltage ripple is below 10 mv p - p at any load , from zero to full current . the lt 8641 allows high v in to low v out conversion at high frequency with a fast minimum top switch on - time of 35 ns . operation is safe in overload even with a saturated inductor . essential features are included and easy to use : an open - drain pg pin signals when the output is in regula - tion . the sync / mode pin selects between burst mode , pulse - skipping , or spread spectrum mode , and also al - lows synchronization to an external clock . soft - start and tracking functionality is accessed via the tr / ss pin . an accurate enable threshold can be set using the en / uv pin and a resistor at the rt pin programs switch frequency . 5 v 3.5 a step - down converter 12 v in to 5 v out efficiency applications n silent switcher ? architecture n ultralow emi emissions n spread spectrum frequency modulation n high effciency at high frequency n up to 95% effciency at 1mhz, 12v in to 5v out n up to 94% effciency at 2mhz, 12v in to 5v out n wide input voltage range: 3v to 65v n 3.5a maximum continuous output, 5a peak transient output n ultralow quiescent current burst mode ? operation n 2.5a i q regulating 12v in to 3.3v out n output ripple < 10mv p-p n fast minimum switch on-time: 35ns n low dropout under all conditions: 130mv at 1a n safely tolerates inductor saturation in overload n adjustable and synchronizable: 200khz to 3mhz n peak current mode operation n output soft-start and tracking n small 18-lead 3mm 4mm qfn n automotive and industrial supplies n general purpose step-down n gsm power supplies all registered trademarks and trademarks are the property of their respective owners . protected by u . s . patents , including 8823345. a r a r a document feedback LT8641 rev a 1.5 2 2.5 3 3.5 60 65 70 75 80 efficiency 85 90 95 100 0 0.325 0.650 0.975 1.300 1.625 power loss 1.950 2.275 2.600 efficiency (%) power loss (w) 8641 ta01b 1mhz, l = 3.3 h 2mhz, l = 2.2 h 3mhz, l = 1.5 h load current (a) 0.5 1
2 for more information www.analog.com pin configuration absolute maximum ratings v in , en / uv ................................................................ 65 v pg ............................................................................. 42 v bias .......................................................................... 25 v fb , tr / ss . ................................................................. 4 v sync / mode voltage . ................................................ 6 v operating junction temperature range ( note 2) lt 8641 e ............................................. C40 c to 125 c lt 8641 i .............................................. C40 c to 125 c lt 8641 h ............................................ C40 c to 150 c storage temperature range .................. C65 c to 150 c ( note 1) electrical characteristics the l denotes the specifications which apply over the full operating temperature range , otherwise specifications are at t a = 25 c . order information lead free finish tape and reel part marking * package description temperature range lt 8641 eudc # pbf lt 8641 eudc # trpbf lgsn 18- lead (3 mm 4 mm ) plastic qfn C40 c to 125 c lt 8641 iudc # pbf lt 8641 iudc # trpbf lgsn 18- lead (3 mm 4 mm ) plastic qfn C40 c to 125 c lt 8641 hudc # pbf lt 8641 hudc # trpbf lgsn 18- lead (3 mm 4 mm ) plastic qfn C40 c to 150 c consult adi marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . for more information on lead free part marking , go to : http :// www . linear . com / leadfree / for more information on tape and reel specifications , go to : http :// www . linear . com / tapeandreel / . some packages are available in 500 unit reels through designated sales channels with # trmpbf suffix . parameter conditions min typ max units minimum input voltage l 2.6 3.0 v v in quiescent current v en / uv = 0 v l 0.75 0.75 3 10 a a v en / uv = 2 v , not switching , v sync = 0 v l 1.7 1.7 4 10 a a v en / uv = 2 v , not switching , v sync = 2 v 0.3 0.5 ma v in current in regulation v out = 0.8 v , v in = 6 v , output load = 100 a v out = 0.8 v , v in = 6 v , output load = 1 ma l l 17 200 50 350 a a feedback reference voltage v in = 6 v , i load = 0.5 a v in = 6 v , i load = 0.5 a l 0.804 0.79 0.81 0.81 0.816 0.822 v v feedback voltage line regulation v in = 4.0 v to 42 v , i load = 0.5 a l 0.004 0.03 %/ v aa a a a a a ar r a ar r ra not a a aa a r r http :// www . linear . com / product / lt 8641 # orderinfo LT8641 rev a
3 for more information www.analog.com electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device . exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime . note 2: the lt 8641 e is guaranteed to meet performance specifications from 0 c to 125 c junction temperature . specifications over the C40 c to 125 c operating junction temperature range are assured by design , characterization , and correlation with statistical process controls . the lt 8641 i is guaranteed over the full C40 c to 125 c operating junction temperature range . the lt 8641 h is guaranteed over the full C 40 c to 150 c operating junction temperature range . high junction temperatures degrade operating lifetimes . operating lifetime is derated at junction temperatures greater than 125 c . the l denotes the specifications which apply over the full operating temperature range , otherwise specifications are at t a = 25 c . parameter conditions min typ max units feedback pin input current v fb = 1 v C20 20 na bias pin current consumption v bias = 3.3 v , i load = 1 a , 2 mhz 9 ma minimum on - time i load = 1.5 a , sync = 0 v i load = 1.5 a , sync = 2 v l l 35 35 50 50 ns ns minimum off - time 80 110 ns oscillator frequency r t = 221 k , i load = 1 a r t = 60.4 k , i load = 1 a r t = 18.2 k , i load = 1 a l l l 180 665 1.85 210 700 2.00 240 735 2.15 khz khz mhz top power nmos on - resistance i sw = 1 a 105 m top power nmos current limit l 6.2 8.2 9.9 a bottom power nmos on - resistance v intvcc = 3.4 v , i sw = 1 a 55 m bottom power nmos current limit v intvcc = 3.4 v 4.8 5.8 7.25 a sw leakage current v in = 42 v , v sw = 0 v , 42 v C15 15 a en / uv pin threshold en / uv rising l 0.95 1.01 1.07 v en / uv pin hysteresis 45 mv en / uv pin current v en / uv = 2 v C20 20 na pg upper threshold offset from v fb v fb falling l 5 7.5 10.25 % pg lower threshold offset from v fb v fb rising l C5.25 C8 C10.75 % pg hysteresis 0.4 % pg leakage v pg = 3.3 v C40 40 na pg pull - down resistance v pg = 0.1 v l 750 2000 sync / mode threshold sync / mode dc and clock low level voltage sync / mode clock high level voltage sync / mode dc high level voltage 0.7 2.3 0.9 1.2 2.6 1.4 2.9 v v v spread spectrum modulation frequency ? range r t = 60.4 k , v sync = 3.3 v 22 % spread spectrum modulation frequency v sync = 3.3 v 2.5 khz tr / ss source current l 1.2 1.9 2.6 a tr / ss pull - down resistance fault condition , tr / ss = 0.1 v 220 the junction temperature ( t j , in c ) is calculated from the ambient temperature ( t a in c ) and power dissipation ( pd , in watts ) according to the formula : t j = t a + ( pd ? ja ) where ja ( in c / w ) is the package thermal impedance . note 3: values determined per jedec 51-7, 51-12. see applications information section for information on improving the thermal resistance and for actual temperature measurements of a demo board in typical operating conditions . note 4: this ic includes overtemperature protection that is intended to protect the device during overload conditions . junction temperature will exceed 150 c when overtemperature protection is active . continuous operation above the specified maximum operating junction temperature will reduce lifetime . LT8641 rev a
4 for more information www.analog.com typical performance characteristics reference voltage LT8641 rev a 1.5 85 90 95 100 0 0.3 0.5 0.8 1.0 1.3 2 1.5 1.8 2.0 2.3 2.5 efficiency (%) power loss (w) ef?ciency at 5v out 8641 g03 f sw = 1mhz 2.5 l = we?lhmi7050, 2.2h efficiency power loss v in = 12v v in = 24v v in = 36v v in = 48v load current (a) 0 0.5 3 1 1.5 2 2.5 3 3.5 50 55 60 65 3.5 70 75 80 85 90 95 100 0 0.3 0.5 60 0.8 1.0 1.3 1.5 1.8 2.0 2.3 2.5 efficiency (%) power loss (w) 65 ef?ciency at 3.3v out 8641 g04 f sw = 1mhz l = we?lhmi7050, 4.7h v in = 12v v in = 24v v in = 36v v in = 48v load current (ma) 0.01 70 0.1 1 10 100 1000 20 30 40 50 60 75 70 80 90 100 efficiency (%) ef?ciency at 5v out 8641 g05 load current (ma) 0.01 0.1 80 1 10 100 1000 20 30 40 50 60 70 efficiency 85 80 90 100 efficiency (%) ef?ciency at 3.3v out 8641 g06 f sw = 1mhz l = we?lhmi7050, 4.7h v in = 12v v 90 = 24v v in = 36v v in = 48v v out = 3.3v i load = 1.5a l = we?lhmi7050, 4.7h v in = 12v v in = 24v switching frequency (mhz) 0.5 95 1.0 1.5 2.0 2.5 3.0 80 82 84 86 88 100 90 92 94 96 efficiency (%) ef?ciency vs frequency 8641 g07 v out = 5v i load = 10ma l = we?lhmi7050 0 v in = 12v v in = 24v inductor value (h) 1 2 3 4 5 6 7 0.3 8 9 10 65 70 75 80 85 90 95 0.7 100 efficiency (%) vs inductor value burst mode operation ef?ciency 8641 g08 temperature (c) ?50 ?25 0 25 1.0 50 75 100 125 150 801 803 805 807 809 1.3 811 813 815 817 819 reference voltage (mv) reference voltage 8641 g09 1.6 power loss 1.9 2.3 2.6 efficiency (%) power loss (w) vs frequency 12v in to 5v out ef?ciency 8641 g01 l = we?lhmi7050 efficiency 1mhz, l = 3.3h power loss l = we?lhmi7050 1mhz, l = 2.2h 2mhz, l = 1.5h 3mhz, l = 1h load current (a) 0.5 1 1.5 2 2mhz, l = 2.2h 2.5 3 3.5 60 65 70 75 80 85 90 3mhz, l = 1.5h 95 100 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 load current (a) 2.4 efficiency (%) power loss (w) vs frequency 12v in to 3.3v out ef?ciency 8641 g02 f sw = 1mhz l = we?lhmi7050, 4.7h efficiency power loss 0.5 v in = 12v v in = 24v v in = 36v v in = 48v load current (a) 0 0.5 1 1.5 2 1 2.5 3 3.5 50 55 60 65 70 75 80
5 for more information www.analog.com typical performance characteristics top fet current limit en pin thresholds minimum on - time LT8641 rev a 2.5 switch drop (mv) switch drop 8641 g16 top switch bottom switch switch current (a) 0 0.5 1 1.5 3 2 2.5 3 3.5 0 50 100 150 200 250 3.5 300 350 400 450 500 switch drop (mv) switch drop 8641 g17 en rising en falling ?0.15 temperature (c) ?50 ?25 0 25 50 75 100 125 150 ?0.10 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 en threshold (v) ?0.05 en pin thresholds 8641 g10 5% dc temperature (c) ?50 ?25 0 25 50 75 0 100 125 150 6 7 8 9 10 current limit (a) top fet current limit 0.05 8641 g15 i load = 2a v sync = 0 v sync = float temperature (c) ?50 ?25 0 25 50 0.10 75 100 125 25 28 31 34 37 40 43 0.15 minimum on-time (ns) 8641 g18 v out = 5v change in v out (%) load regulation 8641 g11 v out = 5v i load = 1a input voltage (v) 5 15 25 35 v in = 12v 45 55 65 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 load current (a) change in v out (%) line regulation 8641 g12 v out = 3.3v l = 4.7h in-regulation input voltage (v) 0 10 20 0 30 40 50 60 1.0 1.5 2.0 2.5 3.0 3.5 0.5 4.0 4.5 input current (a) no-load supply current 8641 g13 duty cycle 0.1 0.3 0.5 0.7 1 0.9 5.5 6.0 6.5 7.0 7.5 8.0 8.5 current limit (a) top fet current limit vs duty cycle 1.5 8641 g14 top switch bottom switch switch current = 1a temperature (c) ?50 ?25 0 25 50 2 75 100 125 150 0 50 100 150 200 250
6 for more information www.analog.com typical performance characteristics switching frequency frequency foldback soft - start current pg high thresholds pg low thresholds fb voltage (v) 0 switching frequency (khz) 300 400 500 0.6 1 8641 g23 200 100 0 0.2 0.4 0.8 600 700 800 v out = 3.3v v in = 12v v sync = 0v r t = 60.4k LT8641 rev a 2 720 730 740 switching frequency (khz) switching frequency 8641 g20 v ss = 0.5v temperature (c) ?50 ?25 2.5 0 25 50 75 100 125 150 1.4 1.5 1.6 3 1.7 1.8 1.9 2.0 2.1 2.2 ss pin current (a) soft?start current 8641 g25 fb rising 3.5 fb falling temperature (c) ?50 ?25 0 25 50 75 100 125 0 150 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 100 pg threshold offset from v ref (%) pg high thresholds 8641 g26 fb rising fb falling temperature (c) ?50 ?25 0 25 200 50 75 100 125 150 ?10.0 ?9.5 ?9.0 ?8.5 ?8.0 300 ?7.5 ?7.0 ?6.5 ?6.0 pg threshold offset from v ref (%) pg low thresholds 8641 g27 400 500 v in = 5v 600 dropout voltage (mv) dropout voltage 8641 g19 front page application v in = 12v v out = 5v load current (ma) 0 200 v out set to regulate at 5v 400 600 800 0 200 400 600 800 1000 1200 l = we?lhmi7050, 1h switching frequency (khz) burst frequency 8641 g21 front page application v out = 5v f sw = 1mhz input voltage (v) 5 15 25 load current (a) 35 45 55 65 0 20 40 60 80 100 0 120 140 load current (ma) (pulse-skipping mode) minimum load to full frequency 8641 g22 tr/ss voltage (v) 0 0.2 0.4 0.5 0.6 0.8 1.0 1.2 0 0.2 0.4 0.6 0.8 1.0 1 fb voltage (v) soft-start tracking 8641 g24 r t = 60.4k temperature (c) ?50 ?25 0 25 50 1.5 75 100 125 150 660 670 680 690 700 710
7 for more information www.analog.com typical performance characteristics rt programmed switching frequency v in uvlo switching frequency (mhz) 0.2 rt pin resistor (k) 150 200 250 1.8 8641 g28 100 50 125 175 225 75 25 0 0.6 1 1.4 2.2 2.6 3 case temperature rise case temperature rise vs 5 a pulsed load front page application 12v in to 5v out at 1a front page application 12v in to 5v out at 10ma v sync = 0v front page application 48v in to 5v out at 1a LT8641 rev a 35 3 3.5 0 10 20 30 40 50 60 case temperature rise (c) 45 case temperature rise 8641 g32 dc2373a demo board v in = 12v v out = 5v f sw = 2mhz standby load = 0.25a 1khz pulsed load = 5a duty cycle of 5a load 0 55 0.2 0.4 0.6 0.8 0 10 20 30 40 50 65 60 70 80 90 case temperature rise (c) pulsed load 8641 g33 4.5 5.0 5.5 6.0 6.5 7.0 v bias = 5v 7.5 bias pin current (ma) bias pin current 8641 g30 v bias = 5v v out = 5v v in = 12v i load = 1a switching frequency (mhz) 0.2 v out = 5v 0.6 1.0 1.4 1.8 2.2 2.6 3.0 0 5 10 i load = 1a 15 20 bias pin current (ma) bias pin current 8641 g31 frequency continuous operation switching waveforms, full 500ns/div v sw 5v/div f sw = 1mhz i l 1a/div 8641 g34 mode operation switching waveforms, burst 10s/div v sw 5v/div i l 500ma/div input voltage (v) 8641 g35 switching waveforms 500ns/div v sw 20v/div i l 1a/div 8641 g36 temperature (c) ?50 5 ?25 0 25 50 75 100 125 150 2.0 2.2 15 2.4 2.6 2.8 3.0 3.2 input voltage (v) minimum input voltage 8641 g29 dc2373a demo board v in = 12v, f sw = 1mhz 25 v in = 24v, f sw = 1mhz v in = 12v, f sw = 2mhz v in = 24v, f sw = 2mhz load current (a) 0 0.5 1 1.5 2 2.5
8 for more information www.analog.com typical performance characteristics start - up dropout performance start - up dropout performance transient response ; load current stepped from 1 a to 2 a transient response ; load current stepped from 300 ma ( burst mode operation ) to 1.3 a v in 2v/div v out 2v/div 100ms/div 2.5 load (2a in regulation) 8641 g39 v in v out v in 2v/div v out 2v/div 100ms/div 20 load (250ma in regulation) 8641 g40 v in v out conducted emi performance amplitude (dbv) 40 50 60 30 20 10 0 ?10 ?20 ?40 ?30 frequency (mhz) 0 27 3 6 9 15 12 18 21 24 30 spread spectrum mode fixed frequency mode 8641 g41 dc2373a demo board (with emi filter installed) 14v input to 5v output at 3.5a, f sw = 2mhz LT8641 rev a 100ma/div 8641 g37 front page application 300ma (burst mode operation) to 1.3a transient 12v in , 5v out c out = 47f 50s/div i load 1a/div front page application v out 200ma/div 8641 g38 1a to 2a transient 12v in , 5v out c out = 47f 50s/div i load 1a/div v out
9 for more information www.analog.com radiated emi performance ( cispr 25 radiated emission test with class 5 peak limits ) typical performance characteristics amplitude (dbv/m) 40 45 50 35 30 25 20 15 10 -5 0 5 frequency (mhz) 0 900 100 200 300 500 400 600 700 800 1000 amplitude (dbv/m) 40 45 50 35 30 25 20 15 10 ?5 0 5 frequency (mhz) 0 900 100 200 300 500 400 600 700 800 1000 dc2373a demo board (with emi filter installed) 14v input to 5v output at 3.5a, f sw = 2mhz 8641 g42 class 5 peak limit fixed frequency mode spread spectrum mode horizontal polarization peak detector class 5 peak limit fixed frequency mode spread spectrum mode vertical polarization peak detector LT8641 rev a
10 for more information www.analog.com pin functions bias ( pin 1): the internal regulator will draw current from bias instead of v in when bias is tied to a voltage higher than 3.1 v . for output voltages of 3.3 v to 25 v this pin should be tied to v out . if this pin is tied to a supply other than v out use a 1 f local bypass capacitor on this pin . if no supply is available , tie to gnd . intv cc ( pin 2): internal 3.4 v regulator bypass pin . the internal power drivers and control circuits are powered from this voltage . intv cc maximum output current is 20 ma . do not load the intv cc pin with external circuitry . intv cc current will be supplied from bias if bias > 3.1 v , otherwise current will be drawn from v in . voltage on intv cc will vary between 2.8 v and 3.4 v when bias is between 3.0 v and 3.6 v . decouple this pin to power ground with at least a 1 f low esr ceramic capacitor placed close to the ic . bst ( pin 3): this pin is used to provide a drive voltage , higher than the input voltage , to the topside power switch . place a 0.1 f boost capacitor as close as possible to the ic . v in 1 ( pin 4): the lt 8641 requires two 1 f small input bypass capacitors . one 1 f capacitor should be placed between v in 1 and gnd 1. a second 1 f capacitor should be placed between v in 2 and gnd 2. these capacitors must be placed as close as possible to the lt 8641 . a third larger capacitor of 2.2 f or more should be placed close to the lt 8641 with the positive terminal connected to v in 1 and v in 2 , and the negative terminal connected to ground . see applications section for sample layout . gnd 1 (6, 7): power switch ground . these pins are the return path of the internal bottom side power switch and must be tied together . place the negative terminal of the input capacitor as close to the gnd 1 pins as possible . also be sure to tie gnd 1 to the ground plane . see the applica - tions information section for sample layout . sw ( pins 8, 9): the sw pins are the outputs of the internal power switches . tie these pins together and connect them to the inductor and boost capacitor . this node should be kept small on the pcb for good performance and low emi . gnd 2 (10, 11): power switch ground . these pins are the return path of the internal bottom side power switch and must be tied together . place the negative terminal of the input capacitor as close to the gnd 2 pins as possible . also be sure to tie gnd 2 to the ground plane . see the applica - tions information section for sample layout . v in 2 ( pin 13): the lt 8641 requires two 1 f small input bypass capacitors . one 1 f capacitor should be placed between v in 1 and gnd 1. a second 1 f capacitor should be placed between v in 2 and gnd 2. these capacitors must be placed as close as possible to the lt 8641 . a third larger capacitor of 2.2 f or more should be placed close to the lt 8641 with the positive terminal connected to v in 1 and v in 2 , and the negative terminal connected to ground . see the applications information section for sample layout . en / uv ( pin 14): the lt 8641 is shut down when this pin is low and active when this pin is high . the hysteretic threshold voltage is 1.00 v going up and 0.96 v going down . tie to v in if the shutdown feature is not used . an external resistor divider from v in can be used to program a v in threshold below which the lt 8641 will shut down . rt ( pin 15): a resistor is tied between rt and ground to set the switching frequency . tr / ss ( pin 16): output tracking and soft - start pin . this pin allows user control of output voltage ramp rate during start - up . a tr / ss voltage below 0.8 v forces the lt 8641 to regulate the fb pin to equal the tr / ss pin voltage . when tr / ss is above 0.8 v , the tracking function is disabled and the internal reference resumes control of the error amplifier . an internal 1.9 a pull - up current from intv cc on this pin allows a capacitor to program output voltage slew rate . this pin is pulled to ground with an internal 200 mosfet during shutdown and fault conditions ; use a series resistor if driving from a low impedance output . this pin may be left floating if the tracking function is not needed . LT8641 rev a
11 for more information www.analog.com pin functions sync / mode ( pin 17): this pin programs four different operating modes : 1) burst mode . tie this pin to ground for burst mode operation at low output loads this will result in ultralow quiescent current . 2) pulse - skipping mode . float this pin for pulse - skipping mode . this mode offers full frequency operation down to low output loads before pulse skipping occurs . when floating , pin leakage currents should be <1 a . 3) spread spectrum mode . tie this pin high to intv cc (~3.4 v ) or an external supply of 3 v to 4 v . for pulse - skipping mode with spread spectrum modulation . 4) synchronization mode . drive this pin with a clock source to synchronize to an external frequency . during synchronization the part will operate in pulse - skipping mode . gnd ( pins 18): lt 8641 ground pin . connect this pin to system ground and to the ground plane . pg ( pin 19): the pg pin is the open - drain output of an internal comparator . pg remains low until the fb pin is within 8% of the final regulation voltage , and there are no fault conditions . pg is valid when v in is above 3.4 v , regardless of en / uv pin state . fb ( pin 20): the lt 8641 regulates the fb pin to 0.8 v . connect the feedback resistor divider tap to this pin . also , connect a phase lead capacitor between fb and v out . typically , this capacitor is 4.7 pf to 22 pf . sw ( exposed pad pins 21, 22): the exposed pads should be connected and soldered to the sw trace for good thermal performance . if necessary due to manufacturing limita - tions pins 21 and 22 may be left disconnected , however thermal performance will be degraded . block diagram + + ? + ? slope comp internal 0.8v ref oscillator 200khz to 3mhz burst detect 3.4v reg m1 m2 600k 60k c bst c out v out 8641 bd sw l bst 8, 9, 21, 22 switch logic and anti- shoot through error amp shdn 8% v c intv cc shdn thermal shdn intv cc uvlo v in uvlo shdn thermal shdn v in uvlo en/uv 1v + ? 14 4 3 18 gnd intv cc 2 bias 1 v in2 13 gnd1 6, 7 gnd2 10, 11 pg 19 fb r1 c1 r3 opt r4 opt r2 r t c ss opt v out 20 tr/ss 1.9a 16 rt 15 sync/mode 17 v in1 v in c in1 c in3 c vcc c in2 LT8641 rev a
12 for more information www.analog.com operation the lt 8641 is a monolithic , constant frequency , current mode step - down dc / dc converter . an oscillator , with frequency set using a resistor on the rt pin , turns on the internal top power switch at the beginning of each clock cycle . current in the inductor then increases until the top switch current comparator trips and turns off the top power switch . the peak inductor current at which the top switch turns off is controlled by the voltage on the internal vc node . the error amplifier servos the vc node by comparing the voltage on the v fb pin with an internal 0.8 v reference . when the load current increases it causes a reduction in the feedback voltage relative to the reference leading the error amplifier to raise the vc voltage until the average inductor current matches the new load current . when the top power switch turns off , the synchronous power switch turns on until the next clock cycle begins or inductor current falls to zero . if overload conditions result in more than 5.5 a flowing through the bottom switch , the next clock cycle will be delayed until switch current returns to a safe level . if the en / uv pin is low , the lt 8641 is shut down and draws 1 a from the input . when the en / uv pin is above 1 v , the switching regulator will become active . to optimize efficiency at light loads , the lt 8641 operates in burst mode operation in light load situations . between bursts , all circuitry associated with controlling the output switch is shut down , reducing the input supply current to 1.7 a . in a typical application , 2.5 a will be consumed from the input supply when regulating with no load . the sync / mode pin is tied low to use burst mode operation and can be floated to use pulse - skipping mode . if a clock is applied to the sync / mode pin the part will synchronize to an external clock frequency and operate in pulse - skipping mode . while in pulse - skipping mode the oscillator operates continuously and positive sw transitions are aligned to the clock . during light loads , switch pulses are skipped to regulate the output and the quiescent current will be several hundred a . the sync / mode pin may be tied high for pulse - skipping mode with spread spectrum modulation . to improve emi the lt 8641 can operate in spread spec - trum mode . this feature varies the clock with a triangu - lar frequency modulation of +20%. for example , if the lt 8641 s frequency is programmed to switch at 2 mhz , spread spectrum mode will modulate the oscillator between 2 mhz and 2.4 mhz . to improve efficiency across all loads , supply current to internal circuitry can be sourced from the bias pin when biased at 3.3 v or above . else , the internal circuitry will draw current from v in . the bias pin should be connected to v out if the lt 8641 output is programmed at 3.3 v to 25 v . comparators monitoring the fb pin voltage will pull the pg pin low if the output voltage varies more than 8% ( typical ) from the set point , or if a fault condition is present . the oscillator reduces the lt 8641 s operating frequency when the voltage at the fb pin is low . this frequency foldback helps to control the inductor current when the output voltage is lower than the programmed value which occurs during start - up or overcurrent conditions . when a clock is applied to the sync / mode pin , the sync / mode pin is floated , or held dc high , the frequency foldback is disabled and the switching frequency will slow down only during overcurrent conditions . LT8641 rev a
13 for more information www.analog.com applications information low emi pcb layout the lt 8641 is specifically designed to minimize emi emis - sions and also to maximize efficiency when switching at high frequencies . for optimal performance the lt 8641 requires the use of multiple v in bypass capacitors . tw o small 1 f capacitors should be placed as close as possible to the lt 8641 : one capacitor should be tied to v in 1 / gnd 1; a second capacitor should be tied to v in 2 / gnd 2. a third capacitor with a larger value , 2.2 f or higher , should be placed near v in 1 or v in 2 . see figure 1 for a recommended pcb layout . for more detail and pcb design files refer to the demo board guide for the lt 8641 . note that large , switched currents flow in the lt 8641 v in 1 , v in 2 , gnd 1, and gnd 2 pins and the input capacitors ( c in 1 , c in 2 ). the loops formed by the input capacitors should be as small as possible by placing the capacitors adjacent to the v in 1/2 and gnd 1/2 pins . capacitors with small case size such as 0603 are optimal due to lowest parasitic inductance . the input capacitors , along with the inductor and output capacitors , should be placed on the same side of the circuit board , and their connections should be made on that layer . place a local , unbroken ground plane under the application circuit on the layer closest to the surface layer . the sw and boost nodes should be as small as possible . finally , keep the fb and rt nodes small so that the ground traces will shield them from the sw and boost nodes . the exposed pad on the bottom of the package should be soldered to sw to reduce thermal resistance to ambient . to keep thermal resistance low , extend the ground plane from gnd 1 and gnd 2 as much as possible , and add thermal vias to additional ground planes within the circuit board and on the bottom side . figure 1. recommended pcb layout for the lt 8641 v v v v v v 1 6 11 16 ground plane on layer 2 20 r1 r2 c vcc c bst c in1 c in2 c in3 c out l r t c ss c1 r pg 17 7 10 22 21 ground via v in via v out via other signal vias 8641 f01 v LT8641 rev a
14 for more information www.analog.com applications information achieving ultralow quiescent current to enhance efficiency at light loads , the lt 8641 operates in low ripple burst mode operation , which keeps the out - put capacitor charged to the desired output voltage while minimizing the input quiescent current and minimizing output voltage ripple . in burst mode operation the lt 8641 delivers single small pulses of current to the output capaci - tor followed by sleep periods where the output power is supplied by the output capacitor . while in sleep mode the lt 8641 consumes 1.7 a . as the output load decreases , the frequency of single cur - rent pulses decreases ( see figure 2 a ) and the percentage of time the lt 8641 is in sleep mode increases , resulting in much higher light load efficiency than for typical convert - ers . by maximizing the time between pulses , the converter quiescent current approaches 2.5 a for a typical application when there is no output load . therefore , to optimize the quiescent current performance at light loads , the current in the feedback resistor divider must be minimized as it appears to the output as load current . in order to achieve higher light load efficiency , more energy must be delivered to the output during the single small pulses in burst mode operation such that the lt 8641 can stay in sleep mode longer between each pulse . this can be achieved by using a larger value inductor ( i . e ., 4.7 h ), and should be considered independent of switching frequency when choosing an inductor . for example , while a lower inductor value would typically be used for a high switch - ing frequency application , if high light load efficiency is desired , a higher inductor value should be chosen . see curve in typical performance characteristics . while in burst mode operation the current limit of the top switch is approximately 950 ma ( as shown in figure 3 ), resulting in low output voltage ripple . increasing the output capacitance will decrease output ripple proportionally . as load ramps upward from zero the switching frequency will increase but only up to the switching frequency pro - grammed by the resistor at the rt pin as shown in figure 2 a . the output load at which the lt 8641 reaches the programmed frequency varies based on input voltage , output voltage , and inductor choice . figure 2. sw frequency vs load information in burst mode operation (2 a ) and pulse - skipping mode (2 b ) (2 a ) (2 b ) figure 3. burst mode operation front page application 12v in to 5v out at 10ma v sync = 0v LT8641 rev a 800 0 200 400 600 800 1000 1200 switching frequency (khz) burst frequency front page application 8641 f02a front page application v out = 5v f sw = 1mhz input voltage (v) 5 15 25 35 45 v in = 12v 55 65 0 20 40 60 80 100 120 140 v out = 5v load current (ma) (pulse-skipping mode) minimum load to full frequency 8641 f02b mode operation switching waveforms, burst 10s/div v sw 5v/div i l load current (ma) 500ma/div 8641 f03 0 200 400 600
15 for more information www.analog.com applications information for some applications it is desirable for the lt 8641 to oper - ate in pulse - skipping mode , offering two major differences from burst mode operation . first is the clock stays awake at all times and all switching cycles are aligned to the clock . in this mode much of the internal circuitry is awake at all times , increasing quiescent current to several hundred a . second is that full switching frequency is reached at lower output load than in burst mode operation ( see figure 2 b ). to enable pulse - skipping mode , float the sync / mode pin . when a clock is applied to the sync / mode pin the lt 8641 will also operate in pulse - skipping mode . fb resistor network the output voltage is programmed with a resistor divider between the output and the fb pin . choose the resistor values according to : r 1 = r 2 v o u t 0 . 8 1 v C 1 ? ? ? ? ? ? ( 1 ) reference designators refer to the block diagram . 1% resistors are recommended to maintain output voltage accuracy . if low input quiescent current and good light - load efficiency are desired , use large resistor values for the fb resistor divider . the current flowing in the divider acts as a load current , and will increase the no - load input current to the converter , which is approximately : i q = 1 . 7 a + v o u t r 1 + r 2 ? ? ? ? ? ? v o u t v i n ? ? ? ? ? ? 1 n ? ? ? ? ? ? ( 2 ) where 1.7 a is the quiescent current of the lt 8641 and the second term is the current in the feedback divider reflected to the input of the buck operating at its light load efficiency n . for a 3.3 v application with r 1 = 1 m and r 2 = 324 k , the feedback divider draws 2.5 a . with v in = 12 v and n = 85%, this adds 0.8 a to the 1.7 a quiescent current resulting in 2.5 a no - load current from the 12 v supply . note that this equation implies that the no - load current is a function of v in ; this is plotted in the typical performance characteristics section . when using large fb resistors , a 4.7 pf to 22 pf phase - lead capacitor should be connected from v out to fb . setting the switching frequency the lt 8641 uses a constant frequency pwm architecture that can be programmed to switch from 200 khz to 3 mhz by using a resistor tied from the rt pin to ground . a table showing the necessar o y r t value for a desired switching frequency is in table 1 . the r t resistor required for a desired switching frequency can be calculated using : r t = 4 6 . 5 f s w C 5 . 2 ( 3 ) where r t is in k and f sw is the desired switching fre - quency in mhz . table 1. sw frequency vs r t value f sw ( mhz ) r t ( k ) 0.2 232 0.3 150 0.4 110 0.5 88.7 0.6 71.5 0.7 60.4 0.8 52.3 1.0 41.2 1.2 33.2 1.4 28.0 1.6 23.7 1.8 20.5 2.0 18.2 2.2 15.8 3.0 10.7 operating frequency selection and trade - offs selection of the operating frequency is a trade - off between efficiency , component size , and input voltage range . the advantage of high frequency operation is that smaller induc - tor and capacitor values may be used . the disadvantages are lower efficiency and a smaller input voltage range . LT8641 rev a
16 for more information www.analog.com applications information the highest switching frequency ( f sw ( max ) ) for a given application can be calculated as follows : f s w ( m a x ) = v o u t + v s w ( b o t ) t o n ( m i n ) v i n C v s w ( t o p ) + v s w ( b o t ) ( ) ( 4 ) where v in is the typical input voltage , v out is the output voltage , v sw ( top ) and v sw ( bot ) are the internal switch drops (~0.3 v , ~0.15 v , respectively at maximum load ) and t on ( min ) is the minimum top switch on - time ( see the electrical characteristics ). this equation shows that a slower switching frequency is necessary to accommodate a high v in / v out ratio . for transient operation , v in may go as high as the abso - lute maximum rating of 65 v regardless of the r t value , however the lt 8641 will reduce switching frequency as necessary to maintain control of inductor current to as - sure safe operation . the lt 8641 is capable of a maximum duty cycle of ap - proximately 99%, and the v in - to - v out dropout is limited by the r ds ( on ) of the top switch . in this mode the lt 8641 skips switch cycles , resulting in a lower switching frequency than programmed by rt . for applications that cannot allow deviation from the pro - grammed switching frequency at low v in / v out ratios use the following formula to set switching frequency : v i n ( m i n ) = v o u t + v s w ( b o t ) 1 C f s w ? t o f f ( m i n ) C v s w ( b o t ) + v s w ( t o p ) ( 5 ) where v in ( min ) is the minimum input voltage without skipped cycles , v out is the output voltage , v sw ( top ) and v sw ( bot ) are the internal switch drops (~0.3 v , ~0.15 v , respectively at maximum load ), f sw is the switching fre - quency ( set by rt ), and t off ( min ) is the minimum switch off - time . note that higher switching frequency will increase the minimum input voltage below which cycles will be dropped to achieve higher duty cycle . inductor selection and maximum output current the lt 8641 is designed to minimize solution size by allowing the inductor to be chosen based on the output load requirements of the application . during overload or short - circuit conditions the lt 8641 safely tolerates opera - tion with a saturated inductor through the use of a high speed peak - current mode architecture . a good first choice for the inductor value is : l = v o u t + v s w ( b o t ) f s w ( 6 ) where f sw is the switching frequency in mhz , v out is the output voltage , v sw ( bot ) is the bottom switch drop (~0.15 v ) and l is the inductor value in h . to avoid overheating and poor efficiency , an inductor must be chosen with an rms current rating that is greater than the maximum expected output load of the application . in addition , the saturation current ( typically labeled i sat ) rating of the inductor must be higher than the load current plus 1/2 of in inductor ripple current : i l ( p e a k ) = i l o a d ( m a x ) 1 2 i l ( 7 ) where ? i l is the inductor ripple current as calculated in equation 9 and i load ( max ) is the maximum output load for a given application . as a quick example , an application requiring 2 a output should use an inductor with an rms rating of greater than 2 a and an i sat of greater than 3 a . during long duration overload or short - circuit conditions , the inductor rms rating requirement is greater to avoid overheating of the inductor . to keep the efficiency high , the series resistance ( dcr ) should be less than 0.04, and the core material should be intended for high frequency applications . LT8641 rev a
17 for more information www.analog.com applications information the lt 8641 limits the peak switch current in order to protect the switches and the system from overload faults . the top switch current limit ( i lim ) is 8.2 a at low duty cycles and decreases linearly to 6.4 a at dc = 0.8. the inductor value must then be sufficient to supply the desired maximum output current ( i out ( max ) ), which is a function of the switch current limit ( i lim ) and the ripple current . i o u t ( m a x ) = i l i m C i l 2 ( 8 ) the peak - to - peak ripple current in the inductor can be calculated as follows : i l = v o u t l ? f s w ? 1 C v o u t v i n ( m a x ) ? ? ? ? ? ? ? ? 9) where f sw is the switching frequency of the lt 8641 , and l is the value of the inductor . therefore , the maximum output current that the lt 8641 will deliver depends on the switch current limit , the inductor value , and the input and output voltages . the inductor value may have to be increased if the inductor ripple current does not allow sufficient maximum output current ( i out ( max ) ) given the switching frequency , and maximum input voltage used in the desired application . in order to achieve higher light load efficiency , more energy must be delivered to the output during the single small pulses in burst mode operation such that the lt 8641 can stay in sleep mode longer between each pulse . this can be achieved by using a larger value inductor ( i . e ., 4.7 h ), and should be considered independent of switching frequency when choosing an inductor . for example , while a lower inductor value would typically be used for a high switch - ing frequency application , if high light load efficiency is desired , a higher inductor value should be chosen . see curve in typical performance characteristics . the optimum inductor for a given application may differ from the one indicated by this design guide . a larger value inductor provides a higher maximum load current and reduces the output voltage ripple . for applications requir - ing smaller load currents , the value of the inductor may be lower and the lt 8641 may operate with higher ripple current . this allows use of a physically smaller inductor , or one with a lower dcr resulting in higher efficiency . be aware that low inductance may result in discontinuous mode operation , which further reduces maximum load current . for more information about maximum output current and discontinuous operation , see linear technology s application note 44. finally , for duty cycles greater than 50% ( v out / v in > 0.5), a minimum inductance is required to avoid sub - harmonic oscillation . see application note 19. input capacitors the v in of the lt 8641 should be bypassed with at least three ceramic capacitors for best performance . tw o small ceramic capacitors of 1 f should be placed close to the part ; one at the v in 1 / gnd 1 pins and a second at v in 2 / gnd 2 pins . these capacitors should be 0402 or 0603 in size . for automotive applications requiring 2 series input capaci - tors , two small 0402 or 0603 may be placed at each side of the lt 8641 near the v in 1 / gnd 1 and v in 2 / gnd 2 pins . a third , larger ceramic capacitor of 2.2 f or larger should be placed close to v in 1 or v in 2 . see low emi pcb layout section for more detail . x 7 r or x 5 r capacitors are rec - ommended for best performance across temperature and input voltage variations . note that larger input capacitance is required when a lower switching frequency is used . if the input power source has high impedance , or there is significant inductance due to long wires or cables , additional bulk capacitance may be necessary . this can be provided with a low performance electrolytic capacitor . LT8641 rev a
18 for more information www.analog.com applications information a ceramic input capacitor combined with trace or cable inductance forms a high quality ( under damped ) tank cir - cuit . if the lt 8641 circuit is plugged into a live supply , the input voltage can ring to twice its nominal value , possibly exceeding the lt 8641 s voltage rating . this situation is easily avoided ( see linear technology application note 88). output capacitor and output ripple the output capacitor has two essential functions . along with the inductor , it filters the square wave generated by the lt 8641 to produce the dc output . in this role it determines the output ripple , thus low impedance at the switching frequency is important . the second function is to store energy in order to satisfy transient loads and stabilize the lt 8641 s control loop . ceramic capacitors have very low equivalent series resistance ( esr ) and provide the best ripple performance . for good starting values , see the typical applications section . use x 5 r or x 7 r types . this choice will provide low output ripple and good transient response . transient performance can be improved with a higher value output capacitor and the addition of a feedforward capacitor placed between v out and fb . increasing the output capacitance will also decrease the output voltage ripple . a lower value of output capacitor can be used to save space and cost but transient performance will suffer and may cause loop instability . see the typical applications in this data sheet for suggested capacitor values . when choosing a capacitor , special attention should be given to the data sheet to calculate the effective capacitance under the relevant operating conditions of voltage bias and temperature . a physically larger capacitor or one with a higher voltage rating may be required . ceramic capacitors ceramic capacitors are small , robust and have very low esr . however , ceramic capacitors can cause problems when used with the lt 8641 due to their piezoelectric nature . when in burst mode operation , the lt 8641 s switching frequency depends on the load current , and at very light loads the lt 8641 can excite the ceramic capacitor at audio frequencies , generating audible noise . since the lt 8641 operates at a lower current limit during burst mode op - eration , the noise is typically very quiet to a casual ear . if this is unacceptable , use a high performance tantalum or electrolytic capacitor at the output . low noise ceramic capacitors are also available . a final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the lt 8641 . as previously mentioned , a ceramic input capacitor combined with trace or cable inductance forms a high quality ( un - derdamped ) tank circuit . if the lt 8641 circuit is plugged into a live supply , the input voltage can ring to twice its nominal value , possibly exceeding the lt 8641 s rating . this situation is easily avoided ( see linear technology application note 88). enable pin the lt 8641 is in shutdown when the en pin is low and active when the pin is high . the rising threshold of the en comparator is 1.01 v , with 45 mv of hysteresis . the en pin can be tied to v in if the shutdown feature is not used , or tied to a logic level if shutdown control is required . adding a resistor divider from v in to en programs the lt 8641 to regulate the output only when v in is above a desired voltage ( see the block diagram ). typically , this threshold , v in ( en ) , is used in situations where the input supply is current limited , or has a relatively high source resistance . a switching regulator draws constant power from the source , so source current increases as source voltage drops . this looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions . the v in ( en ) threshold prevents the regulator from operating at source voltages where the problems might occur . this threshold LT8641 rev a
19 for more information www.analog.com applications information can be adjusted by setting the values r 3 and r 4 such that they satisfy the following equation : v i n ( e n ) = r 3 r 4 + 1 ? ? ? ? ? ? ? 1 . 0 1 v ( 1 0 ) where the lt 8641 will remain off until v in is above v in ( en ) . due to the comparator s hysteresis , switching will not stop until the input falls slightly below v in ( en ) . when operating in burst mode operation for light load currents , the current through the v in ( en ) resistor network can easily be greater than the supply current consumed by the lt 8641 . therefore , the v in ( en ) resistors should be large to minimize their effect on efficiency at low loads . intv cc regulator an internal low dropout ( ldo ) regulator produces the 3.4 v supply from v in that powers the drivers and the internal bias circuitry . the intv cc can supply enough current for the lt 8641 s circuitry and must be bypassed to ground with a minimum of 1 f ceramic capacitor . good bypassing is necessary to supply the high transient currents required by the power mosfet gate drivers . to improve efficiency the internal ldo can also draw current from the bias pin when the bias pin is at 3.1 v or higher . typically the bias pin can be tied to the output of the lt 8641 , or can be tied to an external supply of 3.3 v or above . if bias is connected to a supply other than v out , be sure to bypass with a local ceramic capacitor . if the bias pin is below 3.0 v , the internal ldo will consume current from v in . applications with high input voltage and high switching frequency where the internal ldo pulls current from v in will increase die temperature because of the higher power dissipation across the ldo . do not connect an external load to the intv cc pin . output voltage tracking and soft - start t he lt 8641 allows the user to program its output voltage ramp rate by means of the tr / ss pin . an internal 1.9 a pulls up the tr / ss pin to intv cc . putting an external capacitor on tr / ss enables soft starting the output to pre - vent current surge on the input supply . during the soft - start ramp the output voltage will proportionally track the tr / ss pin voltage . for output tracking applications , tr / ss can be externally driven by another voltage source . from 0 v to 0.8 v , the tr / ss voltage will override the internal 0.8 v reference input to the error amplifier , thus regulating the fb pin voltage to that of tr / ss pin . when tr / ss is above 0.8 v , tracking is disabled and the feedback voltage will regulate to the internal reference voltage . the tr / ss pin may be left floating if the function is not needed . an active pull - down circuit is connected to the tr / ss pin which will discharge the external soft - start capacitor in the case of fault conditions and restart the ramp when the faults are cleared . fault conditions that clear the soft - start capacitor are the en / uv pin transitioning low , v in voltage falling too low , or thermal shutdown . output power good when the lt 8641 s output voltage is within the 8% window of the regulation point , the output voltage is considered good and the open - drain pg pin goes high impedance and is typically pulled high with an external resistor . otherwise , the internal pull - down device will pull the pg pin low . to prevent glitching both the upper and lower thresholds include 0.4% of hysteresis . the pg pin is also actively pulled low during several fault conditions : en / uv pin is below 1 v , intv cc has fallen too low , v in is too low , or thermal shutdown . synchronization and spread spectrum to select low ripple burst mode operation , tie the sync pin below 0.4 v ( this can be ground or a logic low output ). to synchronize the lt 8641 oscillator to an external frequency connect a square wave ( with 20% to 80% duty cycle ) to the sync pin . the square wave amplitude should have val - leys that are below 0.4 v and peaks above 1.5 v ( up to 6 v ). LT8641 rev a
20 for more information www.analog.com applications information the lt 8641 will not enter burst mode operation at low output loads while synchronized to an external clock , but instead will pulse skip to maintain regulation . the lt 8641 may be synchronized over a 200 khz to 3 mhz range . the r t resistor should be chosen to set the lt 8641 switching frequency equal to or below the lowest synchronization input . for example , if the synchronization signal will be 500 khz and higher , the r t should be selected for 500 khz . the slope compensation is set by the r t value , while the minimum slope compensation required to avoid subhar - monic oscillations is established by the inductor size , input voltage , and output voltage . since the synchroniza - tion frequency will not change the slopes of the inductor current waveform , if the inductor is large enough to avoid subharmonic oscillations at the frequency set by r t , then the slope compensation will be sufficient for all synchro - nization frequencies . for some applications it is desirable for the lt 8641 to operate in pulse - skipping mode , offering two major differ - ences from burst mode operation . first is the clock stays awake at all times and all switching cycles are aligned to the clock . second is that full switching frequency is reached at lower output load than in burst mode operation . these two differences come at the expense of increased quiescent current . to enable pulse - skipping mode , the sync pin is floated . leakage current on this pin should be <1 a . see block diagram for internal pull - up and pull - down resistance . the lt 8641 features spread spectrum operation to further reduce emi emissions . to enable spread spectrum opera - tion , the sync / mode pin should be tied high either to intv cc (~3.4 v ) or an external supply of 3 v to 4 v . in this mode , triangular frequency modulation is used to vary the switching frequency between the value programmed by rt to approximately 20% higher than that value . the modula - tion frequency is approximately 3 khz . for example , when the lt 8641 is programmed to 2 mhz , the frequency will vary from 2 mhz to 2.4 mhz at a 3 khz rate . when spread spectrum operation is selected , burst mode operation is disabled , and the part will run in pulse - skipping mode . the lt 8641 does not operate in forced continuous mode regardless of sync signal . shorted and reversed input protection the lt 8641 will tolerate a shorted output . several features are used for protection during output short - circuit and brownout conditions . the first is the switching frequency will be folded back while the output is lower than the set point to maintain inductor current control . second , the bottom switch current is monitored such that if inductor current is beyond safe levels switching of the top switch will be delayed until such time as the inductor current falls to safe levels . frequency foldback behavior depends on the state of the sync pin : if the sync pin is low the switching frequency will slow while the output voltage is lower than the pro - grammed level . if the sync pin is connected to a clock source , floated , or tied high , the lt 8641 will stay at the programmed frequency without foldback and only slow switching if the inductor current exceeds safe levels . there is another situation to consider in systems where the output will be held high when the input to the lt 8641 is absent . this may occur in battery charging applications or in battery - backup systems where a battery or some other supply is diode ored with the lt 8641 s output . if the v in pin is allowed to float and the en pin is held high ( either by a logic signal or because it is tied to v in ), then the lt 8641 s internal circuitry will pull its quiescent current through its sw pin . this is acceptable if the system can tolerate several a in this state . if the en pin is grounded the sw pin current will drop to near 1 a . however , if the v in pin is grounded while the output is held high , regardless of en , parasitic body diodes inside the lt 8641 can pull current from the output through the sw pin and the v in pin , which may damage the ic . figure 4 shows a connection of the v in and LT8641 rev a
21 for more information www.analog.com applications information en / uv pins that will allow the lt 8641 to run only when the input voltage is present and that protects against a shorted or reversed input . thermal considerations and peak output current for higher ambient temperatures , care should be taken in the layout of the pcb to ensure good heat sinking of the lt 8641 . the ground pins on the bottom of the package should be soldered to a ground plane . this ground should be tied to large copper layers below with thermal vias ; these layers will spread heat dissipated by the lt 8641 . placing additional vias can reduce thermal resistance further . the maximum load current should be derated as the ambient temperature approaches the maximum junction rating . power dissipation within the lt 8641 can be estimated by calculating the total power loss from an efficiency measurement and subtracting the inductor loss . the die temperature is calculated by multiplying the lt 8641 power dissipation by the thermal resistance from junction to ambient . the internal overtemperature protection monitors the junction temperature of the lt 8641 . if the junction tem - perature reaches approximately 160 c , the lt 8641 will stop switching and indicate a fault condition until the temperature drops about 1 c cooler . temperature rise of the lt 8641 is worst when operating at high load , high v in , and high switching frequency . if the case temperature is too high for a given application , then either v in , switching frequency , or load current can be decreased to reduce the temperature to an acceptable level . figure 5 shows examples of how case temperature rise can be managed by reducing v in , switching frequency , or load . the lt 8641 s internal power switches are capable of safely delivering up to 5 a of peak output current . however , due to thermal limits , the package can only handle 5 a loads for short periods of time . this time is determined by how quickly the case temperature approaches the maximum junction rating . figure 6 shows an example of how case temperature rise changes with the duty cycle of a 1 khz pulsed 5 a load . the lt 8641 s top switch current limit decreases with higher duty cycle operation for slope compensation . this also limits the peak output current the lt 8641 can deliver for a given application . see curve in typical performance characteristics . figure 4. reverse v in protection v in v in d1 LT8641 en/uv 8641 f04 gnd figure 5. case temperature rise figure 6. case temperature rise vs 5 a pulsed load LT8641 rev a 1 1.5 2 2.5 3 3.5 0 10 20 30 dc2373a demo board 40 50 60 case temperature rise (c) case temperature rise 8641 f05 dc2373a demo board v in = 12v v out = 5v f sw = 2mhz v in = 12v, f sw = 1mhz standby load = 0.25a 1khz pulsed load = 5a duty cycle of 5a load 0 0.2 0.4 0.6 0.8 0 10 v in = 24v, f sw = 1mhz 20 30 40 50 60 70 80 90 case temperature rise (c) pulsed load v in = 12v, f sw = 2mhz 8641 f06 v in = 24v, f sw = 2mhz load current (a) 0 0.5
22 for more information www.analog.com 5 v 3.5 a step - down converter 3.3 v , 3.5 a step - down converter v in2 v in1 en/uv pg LT8641 8641 ta08 bst sync/mode sw tr/ss bias intv cc fb rt gnd 0.1f 4.7pf 47f 1210 x5r/x7r 1m v out 5v 3.5a 1f 0603 1f 0603 4.7f v in 5.5v to 65v 10nf 41.2k 1f 4.7h 191k gnd2 gnd1 f sw = 1mhz l: vishay ihlp2525ez-01 v in2 v in1 en/uv pg LT8641 8641 ta05 bst sync/mode sw tr/ss bias intv cc fb rt gnd 0.1f 4.7pf 47f 1210 x5r/x7r 1m v out 3.3v 3.5a 1f 0603 1f 0603 4.7f v in 3.8v to 65v 10nf 41.2k 1f 2.2h 324k gnd2 gnd1 f sw = 1mhz l: vishay ihlp2525ez-01 typical applications ultralow emi 5 v , 3.5 a step - down converter v in2 v in1 en/uv pg LT8641 8641 ta02 bst sync/mode sw tr/ss bias intv cc fb rt gnd 0.1f 4.7pf 1m 47f 1210 x5r/x7r v out 5v 3.5a 1f 0603 1f 0603 4.7f 1206 v in 5.5v to 65v 10nf 18.2k 1f f sw = 2mhz fb1 bead: mpz2012s300a l: ihlp2525cz-01 l2: ihlp1212bz-11 l 2.2h l2 0.22h fb1 bead 191k 4.7f 1210 4.7f 1210 gnd2 gnd1 LT8641 rev a
23 for more information www.analog.com 2 mhz 5 v , 3.5 a step - down converter 2 mhz 3.3 v , 3.5 a step - down converter v in2 v in1 en/uv pg LT8641 8641 ta03 bst sync/mode sw tr/ss bias intv cc fb rt gnd 0.1f 4.7pf 47f 1210 x5r/x7r 1m v out 5v 3.5a 1f 0603 1f 0603 4.7f v in 5.5v to 65v 10nf 18.2k 1f 2.2h 191k gnd2 gnd1 f sw = 2mhz l: vishay ihlp2525cz-01 v in2 v in1 en/uv pg LT8641 8641 ta06 bst sync/mode sw tr/ss bias intv cc fb rt gnd 0.1f 4.7pf 47f 1210 x5r/x7r 1m v out 3.3v 3.5a 1f 0603 1f 0603 4.7f v in 3.8v to 65v 10nf 18.2k 1f 1.5h 324k gnd2 gnd1 f sw = 2mhz l: vishay ihlp2525cz-01 typical applications 12 v , 3.5 a step - down converter v in2 v in1 en/uv pg LT8641 8641 ta04 bst sync/mode sw tr/ss bias intv cc fb rt gnd 0.1f 4.7pf 47f 1210 x5r/x7r 1m v out 12v 3.5a 1f 0603 1f 0603 4.7f v in 12.5v to 65v 10nf 41.2k 1f 6.8h 71.5k gnd2 gnd1 f sw = 1mhz l: vishay ihlp2525ez-01 LT8641 rev a
24 for more information www.analog.com package description please refer to http :// www . linear . com / product / lt 8641 # packaging for the most recent package drawings . 3.00 0.10 1.50 ref 4.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 5) 0.40 0.10 pin 1 id 0.12 45 0.356 0.05 0.220 0.05 0.400 0.05 0.770 bsc 0.770 bsc 1 2 bottom view?exposed pad 2.50 ref 2.127 0.10 0.75 0.05 r = 0.110 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (udc20(18)) qfn 1116 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 2.50 ref 3.10 0.05 4.50 0.05 1.50 ref 0.356 0.05 0.055 bsc 0.400 0.05 0.220 0.05 2.10 0.05 3.50 0.05 package outline 0.50 bsc udc package variation: udc20(18) 20(18)-lead plastic qfn (3mm 4mm) (reference ltc dwg # 05-08-1956 rev c) exposed pad variation aa LT8641 rev a
25 for more information www.analog.com information furnished by analog devices is believed to be accurate and reliable . however , no responsibility is assumed by analog devices for its use , nor for any infringements of patents or other rights of third parties that may result from its use . specifications subject to change without notice . no license is granted by implication or otherwise under any patent or patent rights of analog devices . revision history rev date description page number a 05/18 clarified benefits clarified power loss scale added lt 8641 hudc added new note 3, note 3 became note 4 clarified sync / mode ( pin 17) description clarified block diagram clarified applications synchronization and spread spectrum section clarified figure 4 clarified applications section clarified output capacitor in typical applications clarified package page moves to page 24 1 1 2 3 11 11 20 21 21 22, 23 24 LT8641 rev a
26 for more information www.analog.com www.analog.com ? analog devices, inc. 2016-2018 d16866-0-5/18(a) related parts typical applications 2 mhz 1.8 v , 3.5 a step - down converter part description comments lt 8640 / lt 8640 -1 42 v , 5 a , 96% efficiency , 3 mhz synchronous micropower step - down dc / dc converter with i q = 2.5 a v in ( min ) = 3.4 v , v in ( max ) = 42 v , v out ( min ) = 0.97 v , i q = 2.5 a , i sd < 1 a , 3 mm 4 mm qfn -18 lt 8609 / lt 8609 a 42 v , 2 a , 94% efficiency , 2.2 mhz synchronous micropower step - down dc / dc converter with i q = 2.5 a v in ( min ) = 3 v , v in ( max ) = 42 v , v out ( min ) = 0.8 v , i q = 2.5 a , i sd < 1 a , msop -10 e lt 8610 a / lt 8610 ab 42 v , 3.5 a , 96% efficiency , 2.2 mhz synchronous micropower step - down dc / dc converter with i q = 2.5 a v in ( min ) = 3.4 v , v in ( max ) = 42 v , v out ( min ) = 0.97 v , i q = 2.5 a , i sd < 1 a , msop -16 e lt 8610 ac 42 v , 3.5 a , 96% efficiency , 2.2 mhz synchronous micropower step - down dc / dc converter with i q = 2.5 a v in ( min ) = 3 v , v in ( max ) = 42 v , v out ( min ) = 0.8 v , i q = 2.5 a , i sd < 1 a , msop -16 e lt 8610 42 v , 2.5 a , 96% efficiency , 2.2 mhz synchronous micropower step - down dc / dc converter with i q = 2.5 a v in ( min ) = 3.4 v , v in ( max ) = 42 v , v out ( min ) = 0.97 v , i q = 2.5 a , i sd < 1 a , msop -16 e lt 8611 42 v , 2.5 a , 96% efficiency , 2.2 mhz synchronous micropower step - down dc / dc converter with i q = 2.5 a and input / output current limit / monitor v in ( min ) = 3.4 v , v in ( max ) = 42 v , v out ( min ) = 0.97 v , i q = 2.5 a , i sd < 1 a , 3 mm 5 mm qfn -24 lt 8616 42 v , dual 2.5 a + 1.5 a , 95% efficiency , 2.2 mhz synchronous micropower step - down dc / dc converter with i q = 5 a v in ( min ) = 3.4 v , v in ( max ) = 42 v , v out ( min ) = 0.8 v , i q = 5 a , i sd < 1 a , tssop -28 e , 3 mm 6 mm qfn -28 lt 8620 65 v , 2.5 a , 94% efficiency , 2.2 mhz synchronous micropower step - down dc / dc converter with i q = 2.5 a v in ( min ) = 3.4 v , v in ( max ) = 65 v , v out ( min ) = 0.97 v , i q = 2.5 a , i sd < 1 a , msop -16 e , 3 mm 5 mm qfn -24 lt 8614 42 v , 4 a , 96% efficiency , 2.2 mhz synchronous silent switcher step - down dc / dc converter with i q = 2.5 a v in ( min ) = 3.4 v , v in ( max ) = 42 v , v out ( min ) = 0.97 v , i q = 2.5 a , i sd < 1 a , 3 mm 4 mm qfn 18 lt 8612 42 v , 6 a , 96% efficiency , 2.2 mhz synchronous micropower step - down dc / dc converter with i q = 2.5 a v in ( min ) = 3.4 v , v in ( max ) = 42 v , v out ( min ) = 0.97 v , i q = 3.0 a , i sd < 1 a , 3 mm 6 mm qfn -28 lt 8613 42 v , 6 a , 96% efficiency , 2.2 mhz synchronous micropower step - down dc / dc converter with current limiting v in ( min ) = 3.4 v , v in ( max ) = 42 v , v out ( min ) = 0.97 v , i q = 3.0 a , i sd < 1 a , 3 mm 6 mm qfn -28 lt 8602 42 v , quad output (2.5 a + 1.5 a + 1.5 a + 1.5 a ) 95% efficiency , 2.2 mhz synchronous micropower step - down dc / dc converter with i q = 25 a v in ( min ) = 3 v , v in ( max ) = 42 v , v out ( min ) = 0.8 v , i q = 2.5 a , i sd < 1 a , 6 mm 6 mm qfn -40 v in2 v in1 en/uv pg LT8641 8641 ta07 bst sync/mode sw tr/ss bias intv cc fb rt gnd 0.1f 1f external source >3.1v or gnd 100f 1210 x5r/x7r 10pf 1m v out 1.8v 3.5a 1f 0603 1f 0603 4.7f v in 3v to 22v (65v transient) 10nf 18.2k 1f 1h 825k gnd2 gnd1 f sw = 2mhz l: vishay ihlp2525cz-01 LT8641 rev a

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