View 9FGL06_9073848.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

datasheet 9FGL06 revision b 07/17/15 1 ?2015 integrated device technology, inc. 6-output 3.3v pcie gen 1-2-3 clock generator 9FGL06 description the 9FGL0641/51/p1 are members of idt's 3.3v low-power (lp) pcie family. the devices have 6 output enables for clock management and support 2 different spread spectrum levels in addition to spread off. the 9FGL0641/51/p1 supports both common clock (cc) with or without spread spectrum and separate reference no-spread (srns) pcie clocking architectures. the 9FGL06p1 can be programmed with a user-defined power up default smbus configuration. recommended application 3.3v pcie gen1-2-3 clock generator output features ? 6 ? 100 mhz low-power hcsl (lp-hcsl) dif pairs ? 9FGL0641 default z out = 100 ? ? 9FGL0651 default z out = 85 ? ? 9FGL06p1 factory programmable defaults ? 1 - 3.3v lvcmos ref output w/wake-on-lan (wol) support key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1 -2-3 compliant with ssc on or off ? dif 12k-20m phase jitter is <2ps rms when ssc is off ? ref phase jitter is <300fs rms, ssc off, and <1.5ps rms, ssc is on ? 100ppm frequency accuracy on all clocks features/benefits ? direct connection to 100 ? (xx41) or 85 ? (xx51) transmission lines; saves 24 resistors compared to standard pcie devices ? 120mw typical power consumpt ion; eliminates thermal concerns ? smbus-selectable features allows optimization to customer requirements: ? control input polarity ? control input pull up/downs ? slew rate for each output ? differential output amplitude ? 33, 85 or 100 ? output impedance for each output ? spread spectrum amount ? 41 and 51 devices contain default configuration; smbus interface not required for device operation ? p1 device allows factory progr amming of customer-defined smbus power up default; allows exact optimization to customer requirements ? outputs can optionally be supplied from any voltage between 1.05 and 3.3v; maximum power savings ? oe# pins; support dif power management ? 8mhz - 40mhz input frequency (25mhz default); flexibility ? pin/smbus selectable 0%, -0.25% or -0.5% spread on dif outputs %; minimize emi and phase jitter for each application ? dif outputs blocked until pll is locked; clean system start-up ? two selectable smbus address es; multiple devices can easily share an smbus segment ? space saving 40-pin 5x5mm vfqfpn; minimal board space block diagram note: resistors default to internal on 41/51 devices. p1 devices ha ve programmable default impedances on an output-by-output basis. x1_25 x2 control logic vss_en_tri ^ckpwrgd_pd# sdata_3.3 ss capable pll 6 osc ref3.3 voe(5:0)# sclk_3.3 vsadr dif5 dif4 dif3 dif2 dif1 dif0
6-output 3.3v pcie gen 1-2-3 clock generator 2 revision b 07/17/15 9FGL06 datasheet pin configuration smbus address selection table power management table 3 power connections ^ckpwrgd_pd# vddio voe5# dif5# dif5 voe4# dif4# dif4 vddio vdd3.3 40 39 38 37 36 35 34 33 32 31 vss_en_tri 130 voe3# x1_25 229 dif3# x2 328 dif3 vddxtal3.3 427 vddio vddref3.3 526 vdda3.3 vsadr/ref3.3 625 nc nc 724 voe2# gnddig 823 dif2# sclk_3.3 922 dif2 sdata_3.3 10 21 voe1# 11 12 13 14 15 16 17 18 19 20 vdddig3.3 vddio voe0# dif0 dif0# vdd3.3 vddio dif1 dif1# nc v prefix indicates internal 120kohm pull down resistor ^ prefix indicates internal 120kohm pull up resistor 9FGL06xx epad is gnd 40-pin vfqfpn, 5x5 mm, 0.4mm pitch sadr address 0 1101000 1 1101010 state of sadr on first application of ckpwrgd_pd# + read/write bit x x true o/p comp. o/p 0xx low 1 low 1 hi-z 2 1 1 0 running running running 111 disabled 1 disabled 1 running 10x disabled 1 disabled 1 disabled 4 1. the output state is set by b11[1:0] (low/low default) 3. input polarities defined at default values for 9FGL0641/0651. 4. see smbus description for byte 3, bit 4 ref ckpwrgd_pd# smbus oe bit 2. ref is hi-z until the 1st assertion of ckpwrgd_pd# high. after this, when ckpwrg_pd# is low, ref is disabled unless byte3[5]=1, in which case ref is running. difx oex# pin pin number vdd vddio gnd 441 xtal osc 5 41 ref power 11 8 digital (dirty) power 12,17,27,32,39 41 dif outputs 26 41 pll analog description
revision b 07/17/15 3 6-output 3. 3v pcie gen 1-2-3 clock generator 9FGL06 datasheet pin descriptions (9FGL0641/51 configuration) pin # pin name pin type description 1 vss_en_tri latched in latched select input to select spread spectrum amount at initial power up : 1 = -0.5% spread, m = -0.25%, 0 = spread off 2 x1_25 in crystal input, nominally 25.00mhz. 3 x2 out crystal output. 4 vddxtal3.3 pwr power supply for xtal, nominal 3.3v 5 vddref3.3 pwr vdd for ref output. nominal 3.3v. 6 vsadr/ref3.3 latched i/o latch to select smbus address/3.3v lvcmos copy of x1/refin pin 7 nc n/a no connection. 8 gnddig gnd ground pin for digital circuitry 9 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant. 10 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 11 vdddig3.3 pwr 3.3v digital power (dirty power) 12 vddio pwr power supply for differential outputs 13 voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 14 dif0 out differential true clock output 15 dif0# out differential complementary clock output 16 vdd3.3 pwr power supply, nominal 3.3v 17 vddio pwr power supply for differential outputs 18 dif1 out differential true clock output 19 dif1# out differential complementary clock output 20 nc n/a no connection. 21 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 22 dif2 out differential true clock output 23 dif2# out differential complementary clock output 24 voe2# in active low input for enabling dif pair 2. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 25 nc n/a no connection. 26 vdda3.3 pwr 3.3v power for the pll core. 27 vddio pwr power supply for differential outputs 28 dif3 out differential true clock output 29 dif3# out differential complementary clock output 30 voe3# in active low input for enabling dif pair 3. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 31 vdd3.3 pwr power supply, nominal 3.3v 32 vddio pwr power supply for differential outputs 33 dif4 out differential true clock output 34 dif4# out differential complementary clock output 35 voe4# in active low input for enabling dif pair 4. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 36 dif5 out differential true clock output 37 dif5# out differential complementary clock output 38 voe5# in active low input for enabling dif pair 5. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 39 vddio pwr power supply for differential outputs 40 ^ckpwrgd_pd# in input notifies device to sample latched inputs and start up on first high assertion. low enters power down mode, subsequent high assertions exit power down mode. this pin has internal pull-up resistor. 41 epad gnd connect paddle to ground.
6-output 3.3v pcie gen 1-2-3 clock generator 4 revision b 07/17/15 9FGL06 datasheet test loads alternate terminations the 9fgl family can ea sily drive lvpecl, lvds, and cml logic. see ?an-891 driving lvpecl, lvds, and cml logic with idt's "universal" low-power hcsl outputs? for details. ref output 33 ref output test load 5pf zo = 50 ohms rs rs low-power differential output test load 2pf 2pf 5 inches zo=100ohm note: the device can drive transmission line lengths greater than those specified by the pcie sig terminations device zo ( ? )rs ( ? ) 9FGL0641 100 none needed 9FGL0651 100 7.5 9FGL06p1 100 prog. 9FGL0641 85 n/a 9FGL0651 85 none needed 9FGL06p1 85 prog.
revision b 07/17/15 5 6-output 3. 3v pcie gen 1-2-3 clock generator 9FGL06 datasheet absolute maximum ratings stresses above the ratings listed below can cause permanent dama ge to the 9FGL06. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specif ications is not implied. exposur e to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only ov er the recommended operating temperature range. electrical characteris tics?smbus parameters parameter symbol conditions min typ max units notes 3.3v supply voltage vddxx applies to vdd, vdda and vddio, if present. -0.5 3.9 v 1,2 input voltage v in -0.5 v dd + 0.5v v 1, 3 input high voltage, smbus v ihsmb smbus clock and data pins 3.9 v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 4.5v. ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes smbus input low voltage v ilsmb v ddsmb = 3.3v 0.8 v smbus input high voltage v ihsmb v ddsmb = 3.3v 2.1 3.6 v smbus output low voltage v olsmb @ i pullup 0.4 v smbus sink current i pullup @ v ol 4ma nominal bus voltage v ddsmb 2.7 3.6 v sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 400 khz 2 1 guaranteed by design and characterization, not 100% tested in production. 2. the device must be powered up for the smbus to function.
6-output 3.3v pcie gen 1-2-3 clock generator 6 revision b 07/17/15 9FGL06 datasheet electrical characteristics?input/supply /common parameters?normal operating conditions ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes supply voltage vddxxx supply voltage for core, analog and single-ended lvcmos outputs. 3.135 3.3 3.465 v io supply volta g e vddio supply volta g e for differential low power outputs. 0.9975 1.05-3.3 3.465 v ambient operating temperature t amb industrial range -40 25 85 c input high voltage v ih single-ended inputs, except smbus 0.75xv dd v dd +0.3 v input mid voltage v im single-ended tri-level inputs ('_tri' suffix) 0.4xv dd 0.5xv dd 0.6xv dd v input low voltage v il single-ended inputs, except smbus -0.3 0.25xv dd v i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua input frequency f in xtal, or x1 input 8 25 40 mhz 4 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.3 1.8 ms 1,2 ss modulation frequency f mod (triangular modulation) 30 31.6 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 clocks 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of single-ended control inputs 5 ns 1,2 trise t r rise time of single-ended control inputs 5 ns 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 4 the 9fglxxp1 devices can be programmed for various input frequencies from 8 to 40mhz. the 9fglxx41/51 devices use 25mhz. 3 time from deassertion until outputs are >200 mv input current capacitance
revision b 07/17/15 7 6-output 3. 3v pcie gen 1-2-3 clock generator 9FGL06 datasheet electrical characteristics? dif low-power hcsl outputs ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes scope avera g in g on, fast settin g 2.2 3.2 4.5 v/ns 2,3 scope averaging, slow setting 1.4 2.1 3.2 v/ns 2,3 crossing voltage (abs) vcross_abs scope averaging off 250 411 550 mv 1,4,5 crossing voltage (var) -vcross scope averaging off 11 140 mv 1,4,9 avg. clock period accuracy t period_avg -100 0.0 +2600 ppm 2,10,13 absolute period t period_abs includes jitter and spread spectrum modulation 9.94906 10.0 10.1011 ns 2,6 jitter, cycle to cycle t j c y c-c y c 34 50 ps 2 voltage high v hi gh 660 771 850 1 voltage low v low -150 18 150 1 absolute max voltage vmax 821 1150 1,7,15 absolute min volta g e vmin -300 -30 1,8,15 duty cycle t dc 45 49 55 % 2 slew rate matchin g trf 7 20 % 1,14 skew, output to output t sk3 averaging on, v t = 50% 23 50 ps 2 2 measured from differential waveform. 8 defined as the minimum instantaneous voltage including undershoot. 15 at default smbus amplitude settings. measurement on single ended signal using absolute value. (scope avera g in g off) mv slew rate trf mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) 14 matching applies to rising edge rate for refclk+ and falling edge rate for refclk-. it is measured using a 75 mv window cente red on the median cross point where refclk+ rising meets refclk- falling. the median cross point is used to calculate the voltage thre sholds the oscilloscope is to use for the edge rate calculations. the rise edge rate of refclk+ should be compared to the fall edge ra te of refclk-; the maximum allowed difference should not exceed 20% of the slowest edge rate. 1 measured from single-ended waveform. 3 measured from -150 mv to +150 mv on the differential waveform (derived from refclk+ minus refclk-). the signal must be monotoni c through the measurement region for rise and fall time. the 300 mv measurement window is centered on the differential zero cross ing. 4 measured at crossing point where the instantaneous voltage value of the rising edge of refclk+ equals the fa lling edge of refclk-. 5 refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to a ll crossing points for this measurement. 6 defines as the absolute minimum or maximum instantaneous period. this includes cycle to cycle jitter, relative ppm tolerance, and spread spectrum modulation. 7 defined as the maximum instantaneous volta g e includin g overshoot. 9 defined as the total variation of all crossing voltages of rising refclk+ and falling refclk-. this is the maximum allowed var iance in v cross for any particular system. 10 refer to section 4.3.7.1.1 of the pci express base specification, revision 3.0 for information regarding ppm considerations. 11 system board compliance measurements must use the test load. refclk+ and refclk- are to be measured at the load capacitors cl. single ended probes must be used for measurements requiring single ended measurements. either single ended probes with math or differential probe can be used for differential measurements. test load cl = 2 pf. 12 t stable is the time the differential clock must maintain a minimum 150 mv differential voltage after rising/falling edges before it i s allowed to droo p back into the vrb 100 mv differential ran g e. 13 ppm refers to parts per million and is a dc absolute period accuracy specification. 1 ppm is 1/1,000,000th of 100.000000 mhz e xactly or 100 hz. for 300 ppm, then we have an error budget of 100 hz/ppm * 300 ppm = 30 khz. the period is to be measured with a frequen cy counter with measurement window set to 100 ms or greater. the 300 ppm applies to systems that do not employ spread spectrum clocking, or that use common clock source. for systems employing spread spectrum clocking, there is an additional 2,500 ppm nom inal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,800 ppm.
6-output 3.3v pcie gen 1-2-3 clock generator 8 revision b 07/17/15 9FGL06 datasheet electrical characteristics?dif lp-hcs l output phase ji tter parameters electrical characteristi cs?current consumption ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max ind. limit units notes t jphpcieg1 pcie gen 1 19 23 86 ps (p-p) 1,3,4,6 pcie gen 2 lo band 10khz < f < 1.5mhz 0.5 0.7 3 ps (rms) 1,3,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 1.2 1.8 3.1 ps (rms) 1,3,6 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.3 0.5 1 ps (rms) 1,3,6 phase jitter, 12k-20m t jph12k20m 100mhz, ref output enabled 1.5 2 n/a ps (rms) 2,6 1 defined for spread spectrum on or off 6 applies to all differential outputs 2 only defined for spread spectrum off. phase jitter, pci express (common clock architecture) 1 t jphpcieg2 3 see http://www.pcisi g .com for complete specs 4 sample size of at least 100k cycles. this figures extr apolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 5 calculated from intel-supplied clock jitter tool ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes i ddaop vdda, all outputs active @100mhz 13 16 ma i ddop all vdd, except vdda and vddio, all outputs active @100mhz 16 21 ma i ddioop vddio, all outputs active @100mhz 23 29 ma i ddap d vdda, dif outputs off, ref output running 0.8 1 ma 1 i ddpd all vdd, except vdda and vddio, dif outputs off, ref output running 7.59ma1 i ddi op d vddio, dif outputs off, ref output running 0.06 0.1 ma 1 i ddap d vdda, all outputs off 0.8 1.1 ma i ddpd all vdd, except vdda and vddio, all outputs off 2.4 3 ma i ddi opd vddio, all outputs off 0.05 0.1 ma 1 this is the current required to have the ref output running in wake-on-lan mode (byte 3, bit 5 = 1) powerdown current (power down state and byte 3, bit 5 = '0') operating supply current wake-on-lan current (power down state and byte 3, bit 5 = '1')
revision b 07/17/15 9 6-output 3. 3v pcie gen 1-2-3 clock generator 9FGL06 datasheet electrical characteristics? ref ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbo l conditions min typ max units notes long accuracy ppm see tperiod min-max values ppm 1,2 clock period t p eriod ref output ns 2 high output voltage v hi gh ioh = -2ma 0.8xv ddref v low output voltage v low iol = 2ma 0.2xv ddref v rise/fall slew rate t rf1 byte 3 = 1f, v oh = 0.8*vdd, v ol = 0.2*vdd 0.5 0.8 1.2 v/ns 1 rise/fall slew rate t rf1 byte 3 = 5f, voh = 0.8*vdd, vol = 0.2*vdd 1.0 1.4 2.0 v/ns 1,3 rise/fall slew rate t rf1 byte 3 = 9f, voh = 0.8*vdd, vol = 0.2*vdd 1.5 2.0 2.6 v/ns 1 rise/fall slew rate t rf1 byte 3 = df, voh = 0.8*vdd, vol = 0.2*vdd 2.0 2.6 3.2 v/ns 1 duty cycle d t1x v t = vdd/2 v 45 49.8 55 % 1,4 duty cycle distortion d tcd v t = vdd/2 v -1 -0.5 0 % 1,5 jitter, cycle to cycle t j c y c-c y c v t = vdd/2 v 70 150 ps 1,4 noise floor t j dbc1k 1khz offset -145 -135 dbc 1,4 noise floor t j dbc10k 10khz offset to nyquist -150 -140 dbc 1,4 jitter, phase t jp hre f 12khz to 5mhz, dif ssc off 0.13 0.3 ps (rms) 1,4 jitter, phase t jphref 12khz to 5mhz, dif ssc on 1.4 1.5 ps (rms) 1,4 1 guaranteed by design and characterization, not 100% tested in production. 3 default smbus value 4 when driven by a crystal. 5 when driven by an external oscillator via the x1 pin, x2 should be floating. 2 all lon g term accuracy and clock period specifications are g uaranteed assumin g that ref is trimmed to 25.00 mhz 0 40
6-output 3.3v pcie gen 1-2-3 clock generator 10 revision b 07/17/15 9FGL06 datasheet general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit note: smbus address is latched on sadr pin. unless otherwise indicated, default values are for the xx41 and xx51. p1 devices are fully factory programmable. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
revision b 07/17/15 11 6-output 3. 3v pcie gen 1-2-3 clock generator 9FGL06 datasheet smbus table: output enable register 1 byte 0 name control function type 0 1 default bit 7 dif oe5 output enable rw enabled 1 bit 6 dif oe4 output enable rw enabled 1 bit 5 x bit 4 dif oe3 output enable rw enabled 1 bit 3 dif oe2 output enable rw enabled 1 bit 2 dif oe1 output enable rw enabled 1 bit 1 x bit 0 dif oe0 output enable rw see b11[1:0] enabled 1 smbus table: ss readback and control register byte 1 name control function type 0 1 default bit 7 ssenrb1 ss enable re adback bit1 r latch bit 6 ssenrb1 ss enable re adback bit0 r latch bit 5 ssen_swcntrl enable sw control of ss rw ss control locked values in b1[4:3] control ss amount. 0 bit 4 ssensw1 ss enable software ctl bit1 rw 1 0 bit 3 ssensw0 ss enable software ctl bit0 rw 1 0 bit 2 x bit 1 amplitude 1 rw 00 = 0.55v 01= 0.65v 1 bit 0 amplitude 0 rw 10 = 0.7v 11 = 0.8v 0 1. b1[5] must be set to a 1 for these bits to have any effect on the part. smbus table: dif slew rate control register byte 2 name control function type 0 1 default bit 7 dif oe5 output enable rw enabled 1 bit 6 dif oe4 output enable rw enabled 1 bit 5 x bit 4 dif oe3 output enable rw enabled 1 bit 3 dif oe2 output enable rw enabled 1 bit 2 dif oe1 output enable rw enabled 1 bit 1 x bit 0 dif oe0 output enable rw see b11[1:0] enabled 1 note: see "low-power hcsl outputs" table for slew rates. smbus table: nominal vhigh amplitude control/ ref control register byte 3 name control function type 0 1 default bit 7 rw 00 = slowest 01 =slow 0 bit 6 rw 10 = fast 11 = fastest 1 bit 5 ref power down function wake-on-lan enable for ref rw ref disabled in power down ref runs in power down 0 bit 4 ref oe ref output enable rw disabled 1 enabled 1 bit 3 x bit 2 x bit 1 x bit 0 x 1. the disabled state depends on byte11[1:0]. '00' = low, '01'=hiz, '10'=low, '11'=high byte 4 is reserved see b11[1:0] reserved see b11[1:0] reserved see b11[1:0] reserved see b11[1:0] reserved reserved reserved reserved reserved 1. a low on these bits will overide the oe# pin and force the differential output to the state indicated by b11[1:0] (low/low d efault) 00' for ss_en_tri = 0, '01' for ss_en_tri = 'm', '11 for ss_en_tri = '1' 00' = ss off, '01' = -0.25% ss, '10' = reserved, '11'= -0.5% ss reserved controls output amplitude ref slew rate control
6-output 3.3v pcie gen 1-2-3 clock generator 12 revision b 07/17/15 9FGL06 datasheet smbus table: revision and vendor id register byte 5 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 0 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: device type/device id byte 6 name control function type 0 1 default bit 7 device type1 r 0 bit 6 device type0 r 0 bit 5 device id5 r 0 bit 4 device id4 r 0 bit 3 device id3 r 1 bit 2 device id2 r 0 bit 1 device id1 r 0 bit 0 device id0 r 0 smbus table: byte count register byte 7 name control function type 0 1 default bit 7 x bit 6 x bit 5 x bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 bytes 8 and 9 are reserved. smbus table: pll mn enable, pd_restore byte 10 name control function type 0 1 default bit 7 pll m/n en m/n programming enable rw m/n prog. disabled m/n prog. enabled 0 bit 6 power-down (pd) restore restore default config. in pd rw clear config in pd keep config in pd 1 bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 x reserved reserved reserved 00 = fgx, 01 = dbx, 10 = dmx, 11= dbx w/opll device type reserved 0001 = idt vendor id a rev = 0000 revision id writing to this register will configure how many bytes will be read back, default is = 8 bytes. reserved byte count programming reserved reserved reserved 001000 binary or 06 hex device id reserved
revision b 07/17/15 13 6-output 3. 3v pcie gen 1-2-3 clock generator 9FGL06 datasheet smbus table: stop state control byte 11 name control function type 0 1 default bit 7 x bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 stp[1] rw 00 = low/low 10 = high/low 0 bit 0 stp[0] rw 01 = hiz/hiz 11 = low/high 0 smbus table: impedance control byte 12 name control function type 0 1 default bit 7 dif2_imp[1] dif2 zout rw 00=33 ? dif zout 10=100 ? dif zout bit 6 dif2_imp[0] dif2 zout rw 01=85 ? dif zout 11 = reserved bit 5 dif1_imp[1] dif1 zout rw 00=33 ? dif zout 10=100 ? dif zout bit 4 dif1_imp[0] dif1 zout rw 01=85 ? dif zout 11 = reserved bit 3 x bit 2 x bit 1 dif0_imp[1] dif0 zout rw 00=33 ? dif zout 10=100 ? dif zout bit 0 dif0_imp[0] dif0 zout rw 01=85 ? dif zout 11 = reserved smbus table: impedance control byte 13 name control function type 0 1 default bit 7 dif5_imp[1] dif5 zout rw 00=33 ? dif zout 10=100 ? dif zout bit 6 dif5_imp[0] dif5 zout rw 01=85 ? dif zout 11 = reserved bit 5 dif4_imp[1] dif4 zout rw 00=33 ? dif zout 10=100 ? dif zout bit 4 dif4_imp[0] dif6 zout rw 01=85 ? dif zout 11 = reserved bit 3 x bit 2 x bit 1 dif3_imp[1] dif3 zout rw 00=33 ? dif zout 10=100 ? dif zout bit 0 dif3_imp[0] dif3 zout rw 01=85 ? dif zout 11 = reserved smbus table: pull-up pull-down control byte 14 name control function type 0 1 default bit 7 oe2_pu/pd[1] rw 00=none 10=pup 0 bit 6 oe2_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 5 oe1_pu/pd[1] rw 00=none 10=pup 0 bit 4 oe1_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 3 x bit 2 x bit 1 oe0_pu/pd[1] rw 00=none 10=pup 0 bit 0 oe0_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 reserved reserved see note see note see note see note reserved reserved reserved reserved reserved true/complement dif output disable state oe2 pull-up(pup)/ pull-down(pdwn) control oe1 pull-up(pup)/ pull-down(pdwn) control oe0 pull-up(pup)/ pull-down(pdwn) control reserved reserved reserved reserved reserved
6-output 3.3v pcie gen 1-2-3 clock generator 14 revision b 07/17/15 9FGL06 datasheet smbus table: pull-up pull-down control byte 15 name control function type 0 1 default bit 7 oe5_pu/pd[1] rw 00=none 10=pup 0 bit 6 oe5_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 5 oe4_pu/pd[1] rw 00=none 10=pup 0 bit 4 oe4_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 3 x bit 2 x bit 1 oe3_pu/pd[1] rw 00=none 10=pup 0 bit 0 oe3_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 smbus table: pull-up pull-down control byte 16 name control function type 0 1 default bit 7 x bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 ckpwrgd_pd_pu/pd[1] rw 00=none 10=pup 1 bit 0 ckpwrgd_pd_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 0 bytes 17 is reserved smbus table: polarity control byte 18 name control function type 0 1 default bit 7 oe5_polarity sets oe5 polarity rw enabled when low enabled when high 0 bit 6 oe4_polarity sets oe4 polarity rw enabled when low enabled when high 0 bit 5 x bit 4 oe3_polarity sets oe3 polarity rw enabled when low enabled when high 0 bit 3 oe2_polarity sets oe2 polarity rw enabled when low enabled when high 0 bit 2 oe1_polarity sets oe1 polarity rw enabled when low enabled when high 0 bit 1 x bit 0 oe0_polarity sets oe0 polarity rw enabled when low enabled when high 0 smbus table: polarity control byte 19 name control function type 0 1 default bit 7 x bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 ckpwrgd_pd determines ckpwrgd_pd polarity rw power down when low power down when high 0 reserved reserved reserved reserved reserved reserved reserved reserved reserved oe5 pull-up(pup)/ pull-down(pdwn) control oe4 pull-up(pup)/ pull-down(pdwn) control oe3 pull-up(pup)/ pull-down(pdwn) control reserved reserved reserved reserved ckpwrgd_pd pull-up(pup)/ pull-down(pdwn) control reserved reserved reserved reserved
revision b 07/17/15 15 6-output 3. 3v pcie gen 1-2-3 clock generator 9FGL06 datasheet recommended crystal char acteristics ( 3225 package) marking diagrams notes: 1. ?lot? is the lot sequence number. 2. ?coo? denotes country of origin. 3. ?yyww? is the last two digits of the year and week that the part was assembled. 4. line 2: truncated part number 5. ?l? denotes rohs compliant package. 6. ?i? denotes industrial temperature range device. 7. ?p? denotes factory programmable defaults thermal characteristics parameter value units notes frequency 25 mhz 1 resonance mode fundamental - 1 frequency tolerance @ 25c 20 ppm max 1 frequency stability, ref @ 25c over operating temperature range 20 ppm max 1 temperature range (commerical) 0~70 c 1 temperature range (industrial) -40~85 c 1 equivalent series resistance (esr) 50 ? 5 ppm max 1 notes: 1. idt 603-25-150ja4c or 603-25-150ja4i ics gl0641ai yyww coo lot ics gl0651ai yyww coo lot ics 6p1a000i yyww coo lot parameter symbol conditions pkg typ. units notes jc junction to case 42 c/w 1 c/w 1 c/w 1 c/w 1 c/w 1 ja5 junction to air, 5 m/s air flow 27 c/w 1 thermal resistance ndg40 1 epad soldered to board
6-output 3.3v pcie gen 1-2-3 clock generator 16 revision b 07/17/15 9FGL06 datasheet package outline and package dimensions (ndg40) ? use epad option p1
revision b 07/17/15 17 6-output 3. 3v pcie gen 1-2-3 clock generator 9FGL06 datasheet package outline and package dimensions (ndg40) ? use epad 3.65 mm sq
6-output 3.3v pcie gen 1-2-3 clock generator 18 revision b 07/17/15 9FGL06 datasheet ordering information ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. ?a? is the device revision designator (wil l not correlate with the datasheet revision). ?000? is a blank device. ?xxx? is a unique factory assigned number to identify a particular default configuration. revision history part / order number shipping packaging package temperature 9FGL0641akilf trays 40-pin vfqfpn -40 to +85 c 9FGL0641akilft tape and reel 40-pin vfqfpn -40 to +85 c 9FGL0651akilf trays 40-pin vfqfpn -40 to +85 c 9FGL0651akilft tape and reel 40-pin vfqfpn -40 to +85 c 9FGL06p1a000kilf trays 40-pin vfqfpn -40 to +85 c 9FGL06p1a000kilft tape and reel 40-pin vfqfpn -40 to +85 c 9FGL06p1axxxkilf trays 40-pin vfqfpn -40 to +85 c 9FGL06p1axxxkilft tape and reel 40-pin vfqfpn -40 to +85 c rev. issue date intiator description page # a 6/9/2015 rdw 1. updated electrical tables to final 2. updated power management table and smbus to final 3. updated pin description title 4. updated rs values in test loads 5. added note for byte 3, bit 4, changed definition of '0' condition. 6. updated ordering information for '000' part. 7. added voh and vol paramters to ref electrical table, inadvertantly left out. 2-4, 6-9, 11, 18 b 7/17/2015 rdw 1. added voh and ioh to ref table. 2. minor formatting updates for readab ility and consistency. 3. added i-temp crystal part number to crystal characteristics table 4. added reference to an-891 for terminating to other logic families. 5. removed lvds termination drawing (now in an-891) various
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

▲Up To Search▲

Price & Availability of 9FGL06

	To Download 9FGL06 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .