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sp8854e 27ghz parallel load professional synthesiser preliminary information supersedes january 1996 version, ds4238 - 1.2 ds4238 - 2.0 june 1998 the sp8854e is one of a family of parallel load synthesisers containing all the elements apart from the loop amplifier to fabricate a pll synthesis loop. other parts in the series are the sp8852e which is fully programmable, requiring tw0 16- bit words to set the rf and reference counters and the sp8855e which is fully programmable using hard wired links or switches. the sp8854e is programmed using a 16-bit parallel data bus. data is stored in an internal buffer. the 10-bit program- mable reference divider is programmed by connecting the 10 programming pins either to ground or 1 5v. the device can therefore be programmed with a single transfer from the control microprocessor. hard wired inputs can also control the f pd and f ref outputs and the control sense of the loop. features n 27 ghz operating frequency n single 5v supply n low power consumption <13w n high comparison frequency : 20mhz n high gain phase detector : 1ma/rad n zero dead band phase detector n wide range of rf and reference division ratios n programming by single word data transfer absolute maximum ratings supply voltage operating temperature storage temperature prescaler and reference input voltage data inputs junction temperature 2 03v to 1 6v 2 55 c to 1 100 c 2 65 c to 1 150 c 25v p-p v cc 1 03v v ee 2 03v 1 175 c ordering information sp8854e kg hcar non-standard temperature range, 2 55 c to 1 100 c, standard product screening sp8854e ig hcar industrial temperature range, 2 40 c to 1 85 c, standard product screening fig. 1 pin connections - top view *f pd and f ref outputs are reversed using the control direction input, pin 23. the above diagram is correct when pin 23 is high. 144 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 0v (prescaler) rf input rf input v cc (prescaler) v ee lock detect strobe ref div bit 0 ref div bit 1 ref div bit 2 ref div bit 3 ref div bit 4 ref div bit 5 ref div bit 6 ref div bit 7 ref div bit 8 ref div bit 9 c-lock detect r set charge pump output charge pump ref f pd /f ref enable control direction f pd * f ref * v cc ref osc capacitor ref in/crystal data bit 5 data bit 6 data bit 7 data bit 8 data bit 9 data bit 10 data bit 11 data bit 12 data bit 13 data bit 14 data bit 15 sp8854e hc44 thermal data u jc = 5 c/w u ja = 53 c/w esd protection 1000v, human body model
2 sp8854e strobe b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 39 11 10 9 8 7 6 5 4 3 2 1 44 43 42 41 40 input interface 4 8/9 13 14 15 14 v cc prescaler rf input 0v prescaler 3-bit a counter 11-bit m counter b0 b2 b3 b13 b14 b15 load rf buffer phase detector 10-bit reference divider f ref f pd reference crystal reference capacitor 28 27 charge pump output charge pump reference lock detect output r set c-lock detect f pd * f ref * fpd/fref enable control direction v cc v ee modulus control *f ref and f pd outputs are reversed using the control direction input. the pin allocations shown are correct when bit 12 is high. 20 21 17 19 18 24 25 22 23 26 16 rf input bit 0 38 37 36 35 34 33 32 31 30 29 bit 9 reference divider programming fig. 2 block diagram
3 sp8854e pin description these pins are the data inputs to set the rf divider ratio (mn 1 a). high is open circuit on these pins. data is transparent from pins to rf buffer when pin 39 (strobe) is high and frozen in buffers when pin 39 is low. balanced inputs to the rf preamplifier. for single-ended operation the signal is ac-coupled into pin 13 with pin 14 ac-decoupled to ground (or vice-versa). pins 13 and 14 are internally dc biased. a current sink into this pin is enabled when the lock detect circuit indicates lock. used to give an external indication of phase lock. a capacitor connected to this point determines the lock detect integrator time constant and can be used to vary the sensitivity of the phase lock indicator. an external resistor from pin 19 to v cc sets the charge pump output current. the phase detector output is a single ended charge pump sourcing or sinking current to the inverting input of an external loop filter. connected to the non-inverting input of the loop filter to set the optimum dc bias. part of the input bus. when this pin is high, the f ref / f pd outputs are enabled. high is open circuit. this pin controls charge pump output direction. when pin 23 is high, the output sinks current when f pd > f ref or when the rf phase leads the reference phase. when pin 23 is low, the relationship is reversed (see table 3). rf divider output pulses. f pd = rf input frequency/(m.n 1 a). pulse width = 8 rf input cycles (1 cycle of the divide by 8 prescaler output). reference divider output pulses. f ref = reference input frequency/r. pulse width = high period of ref input. leave open circuit if an external reference is used. see fig. 5 for typical connection for use as an onboard crystal oscillator. this pin is the input buffer amplifier for an external reference signal. this amplifier provides the active element if an onboard crystal oscillator is used. these pins set the reference divider ratio r. high is open circuit. when pin 39 is high the a, m, and r counters are held in the reset state and the charge pump output is disabled. when pin 39 is low the data on the rf data and pd gain pins is fixed in the buffers, the buffers are loaded into the rf counters and the pd gain control, all the counters are active, and the charge pump is enabled. high is open circuit. these pins set the charhe pump current multiplication factor (see table 2). the data is transparent into the buffers when pin 39 is high and frozen when pin 39 is low. high is open circuit. 1-11, 42-44 13 (rf input) 14 (rf input) 17 (lock detect input) 18 (c-lock detect) 19 (r set ) 20 (charge pump output) 21 (charge pump ref) 22 (f ref / f pd enable) 23 (control direction) 24 f pd if pin 23 is high f ref if pin 23 is low 25 f pd if pin 23 is low f ref if pin 23 is high 27 (ref. oscillator capacitor) 28 (ref in/xtal) 29-38 39 (strobe) 40, 41 (pd gain) table 1 pin descriptions
4 sp8854e electrical characteristics the electrical characteristics are guaranteed over the following range of operating conditions unless otherwise stated t amb = 2 55 c to 1 100 c (kg parts), 2 40 c to 1 85 c (ig parts); v cc = 475v to 525v characteristic conditions 2 5 56 1 10 0 6 14 6 20 6 34 6 54 35 2 200 v cc 2 16 05 50 100 180 1 6 2 08 2 14 300 6 15 6 23 6 38 6 61 16 1 10 pin 18, 26 13,14 13,14, 24 28, 25 28, 24, 25 28 28 24, 25 24, 25 17 19, 20, 21 1-11, 22, 23, 29, 44 1-11, 22, 23, 29, 44 1-11, 22, 23, 29, 44 1-11, 22, 23, 29, 44 20 21 19 19 18 typ. max. min. ma dbm mhz mhz dbm v v mv ma ma ma ma v v m a m a % v v ma v m a ns ns units value supply current rf input sensitivity rf division ratio reference division ratio comparison frequency reference input frequency reference input voltage f ref /f pd output voltage high f ref /f pd output voltage low lock detect output voltage charge pump current input bus logic level high input bus logic level low input bus current source input bus current sink up/down current matching charge pump reference voltage r set current r set voltage c-lock detect current strobe pulse width data setup time 240 1 7 16383 1023 50 100 1 10 500 6 17 6 25 6 41 6 65 1 10 6 5 v cc 2 05 2 100mhz to 27ghz. see note 3. ref division ratio >2. see note 1 wrt v cc , 22k w to 0v wrt v cc , 22k w to 0v i out = 3ma v pin20 = v pin21 , i pin19 = 16ma, multiplication factor = 1 v pin20 = v pin21 , i pin19 = 16ma, multiplication factor = 15 v pin20 = v pin21 , i pin19 = 16ma, multiplication factor = 25 v pin20 = v pin21 , i pin19 = 16ma, multiplication factor = 40 v in = 0v v in = v cc v pin20 = v pin21 , i pin19 = 16ma i pin19 = 16ma, current multiplication factor = 10 i pin19 = 16ma, current multiplication factor = 40 note 2 i pin19 = 16ma v pin18 = 47v note 3 note 3 notes 1. lower frequencies may be used provided that slew rates are maintained. 2. pin 19 current 3 multiplication factor must be less than 5ma if charge pump accuracy is to be maintained. 3. guranteed but not tested.
5 sp8854e 1 20 1 10 1 7 0 2 5 2 10 2 20 2 30 100mhz frequency rf input to pin 13 (dbm) 1ghz 2ghz 27ghz 10ghz guaranteed operating window typical sensitivity typical overload fig. 3 input sensitivity 11ghz z o = 50 w j 2 j 1 j 0.5 j 0.2 0 2 j 0.2 2 j 0.5 2 j 1 2 j 2 1 0.5 0.2 j 5 2 j 5 2 5 25ghz 50mhz fig. 4 rf input impedance
6 sp8854e fig. 5 typical application diagram 1 5v 1k - + 144 sp8854e 7 8 9 10 11 12 13 14 15 16 17 2 3 4 5 643424140 23 24 22 21 20 19 18 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 f pd 1n ref in f ref 1 5v 1 m 10n 22k 100p 1 5v 1n 1n 1n vco loop filter 1 30v sp8854e 27 28 33p 100p 10mhz application using crystal reference control micro strobe values depend on application op27 etc * * * * 1 5v description prescaler and am counter the programmable divider chain is of a and m counter construction and therefore contains a dual modulus front end prescaler, an a counter which controls the dual modulus ratio and an m counter which performs the bulk multi-modulus division. a programmable divider of this construction has a division ratio of mn 1 a and a minimum integer steppable division ratio of n ( n 2 1), where n is the prescaler value. data entry and storage data is loaded from the 16-bit bus into one of the internal buffers by applying a positive pulse to the strobe input. the input bus can be driven from ttl or cmos logic levels. when strobe is low, the inputs are isolated and the data can be changed without affecting the programmed state. when strobe input is taken high, the a and m counters are reset and the input data is applied to the internal storage register. when the strobe input is again taken low, the data on the input bus is stored in the internal storage register and the a and m counters released. the strobe input is level triggered so that if the data is changed whilst the input is high, the final value before strobe goes low will be stored. in order to prevent disturbances on the vco control voltage when frequency changes are made, the strobe input disables
7 sp8854e the charge pump outputs when high. during this period the vco control voltage will be maintained by the loop filter components around the loop amplifier but due to the com- bined effects of the amplifier input current and charge pump leakage a gradual change will occur. in order to reduce the change, the duration of the strobe pulse should be minimised. selection of a loop amplifier with low input current will reduce the vco voltage droop during the strobe pulse and result in minimum reference sidebands from the synthesiser. reference input the reference source can be either driven from an external sine or square wave source of up to 100mhz or a crystal can be connected as shown in fig. 5. phase comparator and charge pump the sp8854e has a digital phase/frequency comparator driving a charge pump with programmable current output. the charge pump current level at the minimum gain setting is approximately equal to the current fed into the r set input, pin 19, and can be increased by programming the bus according to table 2 by up to 4 times. v cc 2 16v r set pin 19 current = phase detector gain = i pin19 (ma) 3 multiplication factor 2 p ma/rad bit 15 0 0 1 1 bit 14 0 1 0 1 current multiplication factor 10 15 25 40 table 2 to allow for control direction changes introduced by the design of the pll, pin 23 is used to reverse the sense of the phase detector by transposing the f pd and f ref connections. in order that any external phase detector will also be re- versed, programming bit, the f pd and f ref outputs are also interchanged by pin 23 as shown in table 3. the f pd and f ref signals to the phase detector are available on pins 24 and 25 and may be used to monitor the frequency input to the phase detector or used in conjunction with an external phase detector. the outputs are disabled by taking pin 22 low. when the f pd and f ref outputs are to be used at high frequencies, an external pull down resistor of minimum value 330 w may be connected to ground to reduce the fall time of the output pulse. the charge pump connections to the loop amplifier consist of the charge pump output and the charge pump reference. the matching of the charge pump up and down currents will only be maintained if the charge pump output is held at a voltage equal to the charge pump reference using an operational amplifier to produce a virtual earth condition at pin 20. the lock detect circuit can drive an led to give visual indication of phase lock or provide an indication to the control system if a pullup resistor is used in place of the led. a small capacitor connected form the c-lock detector pin to ground may be used to delay lock detect indication and remove glitches produced by momentary phase coincidence during lock up. control direction (pin 23) 1 0 pin 20 current source current sink output for rf phase lag table 3 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 12 2 13 phase detector gain control (see table 2) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? m counter 3-bit a counter 40414243441234567891011 pin fig. 6 programming data format
8 sp8854e fig 7 interface circuit diagrams 500 500 4k 325 325 3ma 13 14 rf input rf input v cc 0v 3k fig. 7a 16-bit input bus, f pd /f ref enable, control direction, reference divider inputs and strobe fig. 7b rf inputs 5k 50 m a input 5k v cc 0v 40k 40k fig. 7c lock detect decouple fig. 7d lock detect output 25k 25k 100 100 3k 3k 1k 1k 400 m a v cc 0v lock detect output (low when locked) 17 c-lock detect (high when locked) v cc 0v 3k 3k v ref 47v 20 m a 100 m a 18 fig. 7e r set pin fig. 7f charge pump circuit v cc 130 charge pump current sources 0v 19 r set v cc f up f dn f up f dn 450 450 83 83 0v v cc output reference 20 21 2ma
9 sp8854e fig. 7 interface circuit diagrams (continued) applications rf layout the sp8854e can operate with input frequencies up to 27ghz but to obtain optimum performance, good rf layout practices should be used. a suitable layout technique is to use double sided printed circuit board with through plated holes. wherever possible the top surface on which the sp8854e is mounted should be left as a continuous sheet of copper to form a low impedance ground plane. the ground pins 12 and 16 should be connected directly to the ground plane. pins such as v cc and the unused rf input should be decoupled with chip capacitors mounted as close to the device pin as possible, with a direct connection to the ground plane; suitable values are 10nf for the power supplies and <1nf for the rf input pin (a lower value should be used sufficient to give good decoupling at the rf frequency of operation). a larger decoupling capacitor mounted as close as possible to pin 26 should be used to prevent modulation of v cc by the charge pump pulses. the r set resistor should also be mounted close to the r set pin to prevent noise pickup. the capacitor connected from the charge pump output should be a chip component with short connections to the sp8852e. all signals such as the programming inputs, rf in, reference in and the connections to the op-amp are best taken through the pc board adjacent to the sp8852d with through plated holes allowing connections to remote points without fragmenting the ground plane. lock detect circuit the lock detect circuit uses the up and down correction pulses from the phase detector to determine whether the loop is in or out of lock. when the loop is locked, both up and down pulses are very narrow compared to the reference frequency, but the pulse width in the out of lock condition continuously varies, depending on the phase difference between the outputs of the reference and rf counters. the logical and of the up and down pulses is used to switch a 20ma current sink to pin 18 and a 50k w resistor provides a load to v cc . the circuit is shown in fig. 7c. when lock is established, the narrow pulses from the phase detector ensure that the current source is off for the majority of the time and so pin 18 will be pulled high by the 50k w resistor. a voltage comparator with a switching threshold at about 47v monitors the voltage at pin 18 and switches pin 17 low when pin 18 is more positive than the 47v threshold. when the loop is unlocked, the frequency difference at the counter outputs will produce a cyclic change in pulse width from the phase detector outputs with a frequency equal to the difference at the reference and rf counter outputs. a small capacitor connected to pin 18 prevents the indication of false phase lock conditions at pin 17 for momentary phase coincidence. because of the variable width pulse nature of the signal at pin 18 the calculation of a suitable capacitor value is complex, but if an indication with a delay amounting to several times the expected lock up time is acceptable, the delay will be approximately equal to the time constant of the capacitor on pin 18 and the internal 50k w resistor. if a faster indication is required, comparable with the loop lock up time, the capacitor will need to be 2 to 3 times smaller than the time constant calculation suggests. the time to respond to an out of lock condition is 2 to 3 times less than that required to indicate lock. charge pump circuit the charge pump circuit converts the variable width up and down pulses from the phase detector into adjustable current pulses which can be directly connected to the loop amplifier. the magnitude of the current and therefore the phase detec- tor gain can be modified when new frequency data is entered to compensate for change in the vco gain characteristic over fig. 7g f pd and f ref outputs fig. 7h reference oscillator v cc 0v f pd, f ref outputs 24, 25 296 296 296 33ma v cc 0v 50 m a50 m a 100 m a 100 m a 100 m a 60k 60k 40k 40k 3k 3k capacitor crystal 28 27 programming bus the input pins are designed to be compatible with ttl or cmos logic with a switching threshold set at about 24v by three forward biased base-emitter diodes. the inputs will be taken high by an internal pull up resistor if left open circuit but for best noise immunity it is better to connect unused inputs directly to v cc or ground. rf inputs the prescaler has a differential input amplifier to improve input sensitivity. generally the input drive will be single ended and the rf signal should be ac coupled to either of the inputs using a chip capacitor.the remaining input should be decoupled to ground, again using a chip capacitor. the inputs can be driven differentially but the input circuit should not provide a dc path between inputs or to ground.
10 sp8854e its frequency band. the charge pump pulse current is determined by the current fed into pin 19 and is approximately equal to pin 19 current when the programmed multiplication ratio is 1. the circuit diagram fig. 7e shows the internal components on pin 19 which mirror the input current into the charge pump. the voltage at pin 19 will be approximately 16v above ground due to two v be drops in the current mirror. this voltage will exhibit a negative temperature coefficient, causing the charge pump current to change with chip temperature by up to 10% over the full military temperature range if the current programming resistor is connected to v cc as shown in the application diagram, fig. 5. in critical applications where this change in charge pump current would be too large the resistor to pin 19 could be increased in value and connected to a higher supply to reduce the effect of v be variation on the current level. a suitable resistor connected to a 30v supply would reduce the variation in pin 19 current due to temperature to less than 15%. alternatively a stable current source could be used to set pin 19 current. the charge pump output on pin 20 will only produce symmetrical up and down currents if the voltage is equal to that on the voltage reference pin 21. in order to ensure that this voltage relationship is maintained, an operational amplifier must be used as shown in the typical application fig. 5. using this configuration pin 20 voltage will be forced to be equal to that on pin 21 since the operational amplifier differential input voltage will be no more than a few millivolts (the input offset voltage of the amplifier). when the synthesiser is first switched on or when a frequency outside the vco range is programmed, the amplifier output will limit, allowing pin 20 voltage to differ from that on pin 21. as soon as an achievable frequency value is programmed and the amplifier output starts to slew the correct voltage relationship between pin 20 and 21 will be restored. because of the importance of voltage equality between the charge pump reference and output pins, a resistor should never be connected in series with the operational amplifier inverting input and pin 20, as is the case with a phase detector giving voltage outputs. any current drawn from the charge pump reference pin should be limited to the few microamps input current of a typical operational amplifier. a resistor between the charge pump reference and the non- inverting input could be added to provide isolation but the value should not be so high that more than a few millivolts drop are produced by the amplifier input current. when selecting a suitable amplifier for the loop filter, a number of parameters are important; input offset voltage in most designs is only a few millivolts and an offset of 5mv will produce a mismatch in the up and down currents of about 4% with the charge pump multiplication factor set at 1. the mismatch in up and down currents caused by input offset voltage will be reduced in proportion to the charge pump multiplication factor in use. if the linearity of the phase detector about the normal phase locked operating point is critical, the input offset voltage of most amplifiers can be adjusted to near zero by means of a potentiometer. the charge pump reference voltage on pin 21 is about 13v below the positive supply and will change with temperature and with the programmed charge pump multiplication factor. in many cases it is convenient to operate the amplifier with the negative power supply pin connected to 0v as this removes the need for an additional power supply. the amplifier selected must have a common mode range to within 34v (minimum charge pump reference voltage) of the negative supply pin to operate correctly without a negative supply. most popular amplifiers can be operated from a 30v positive supply to give a wide vco voltage drive range and have adequate common mode range to operate with inputs at 1 34v with respect to the negative supply. input bias and offset current levels to most operational amplifiers are unlikely to be high enough to significantly affect the accuracy of the charge pump circuit currents but the bias current can be important in reducing reference side bands and local oscillator drift during frequency changes. when the loop is locked, the charge pump produces only very narrow pulses of sufficient width to make up for any charge lost from the loop filter components during the reference cycle. the charge lost will be due to leakage from the charge pump output pin and to the amplifier input bias current, the latter usually being more significant. the result of the lost charge is a sawtooth ripple on the vco control line which frequency modulates the phase locked oscillator at the reference frequency and its harmonics. a similar effect will occur whenever the strobe input is taken high during a programming sequence. in this case the charge pump is disabled when the strobe input is high and any leakage current will cause the oscillator to drift off frequency. to reduce this effect, the duration of the strobe pulse should be minimised. f pd and f ref outputs these outputs provide access to the outputs from the rf and reference dividers and are provided for monitoring purposes during product development or test, and for connection of an external phase detector if required. the output circuit is of ecl type, the circuit diagram being shown in fig. 7g. the outputs can be enabled or disabled under software control by the address 0 control word but are best left in the disabled state when not required as the fast edge speeds on the output can increase the level of reference sidebands on the synthesised oscillator. the emitter follower outputs have no internal pulldown resis- tor to save current and if the outputs are required an external pulldown resistor should be fitted. the value should be kept as high as possible to reduce supply current, about 22k w being suitable for monitoring with a high impedance oscilloscope probe or for driving an ac-coupled 50 w load. a minimum value for the pulldown resistor is 330 w . when the f pd and f ref outputs are disabled the output level will be at the logic low level of about 35v so that the additional supply current due to the load resistors will be present even when the outputs are disabled. reference input the reference input circuit functions as an input amplifier or crystal oscillator. when an external reference signal is used this is simply ac-coupled to pin 28, the base of the input emitter follower. when a low phase noise synthesiser is required the reference signal is critical since any noise present here will be multiplied by the loop. to obtain the lowest possible phase noise from the sp8854e it is best to use the highest possible reference input frequency and to divide this down internally to obtain the required frequency at the phase detector. the amplitude of the reference input is also important, and a level close to the maximum will give the lowest noise. when the use of a low reference input frequency say 4 to 10mhz is essential some advantage may be gained by using a limiting amplifier such as a cmos gate to square up the reference input. in cases where a suitable reference signal is not available, it may be more convenient to use the input buffer as a crystal oscillator in this case the emitter follower input transistor is connected as a colpitts oscillator with the crystal connected from the base to ground and with the feedback necessary for oscillation provided by a capacitor tap at the emitter. the arrangement is shown inset in fig. 5.
11 sp8854e fig. 8 third order loop filter circuit diagram loop filter design generally, the third order filter configuration shown in fig. 8 gives better results than the more commonly used second order because the reference sidebands are reduced. three equations are required to determine values for the three constants, where the equations are: t 1 = c 1 r 1 t 2 = r 2 ( c 1 1 c 2 ) t 3 = c 2 r 2 (2) (3) (1) t 2 = 1 v n 2 t 3 2 2 tan f 0 1 t 3 = v n t 1 = k f k 0 v n 2 n 1 1 v n 2 t 2 2 1 1 v n 2 t 3 2 ? ? 1 2 1 cos f 0 where k f is the phase detector gain factor in ma/radian k 0 is the vco gain factor in radians/seconds/v n is the division ratio from vco to reference frequency v n is the natural loop frequency f 0 is the phase margin, normally set to 45 since the phase detector used is linear over a range of 2 p radians, the phase detector gain is given by: these values can now be substituted in equation (1) to obtain a value for c 1 and in equations (2) and (3) to determine values for c 2 and r 2 . example calculate values for a loop with the following parameters: frequency to be synthesised 1000mhz reference frequency 10mhz division ratio 1000mhz/100mhz = 100 k 0 vco gain factor 2 p3 10mhz/v f 0 phase margin 45 phase comparator current 63ma the phase detector gain factor k f = 63/2 p = 1ma/radian ma/radian phase comparator current setting 2 p k f = from equation (3): 2 tan 45 1 t 3 = 100khz 3 2 p 1 cos 45 \ t 3 = 659 3 10 2 9 = 628319 04142 t 2 = (100khz 3 2 p ) 2 3 659 3 10 2 9 1 \ t 2 = 3844 3 10 2 6 using these values in equation (1): t 1 = 100 3 (100khz 3 2 p ) 2 1 3 10 2 3 3 2 p3 10mhz/v 3 [a] 1 1 v n 2 t 2 2 1 1 v n 2 t 3 2 ? ? where a = = 1 2 1 1 (100khz 3 2 p ) 2 3 (3844 3 10 2 6 ) 2 1 1 (100khz 3 2 p ) 2 3 (659 3 10 2 9 ) 2 t 1 = \ t 1 = 384 3 10 2 9 from equation (2): = 159 3 10 2 9 3 2415 3948 3 10 2 12 62832 ? 6833 11714 ? 1 2 substituting for c2: 3844 3 10 2 6 2 659 3 10 2 9 t 2 = r 2 c 1 1 t 3 r 2 ? ? = 00153 3 10 2 6 \ r 2 = 8294 w = 659 3 10 2 9 8294 t 3 = c 2 r 2 = t 3 r 2 \ c 2 = 0794nf now, t 1 = c 1 \ c 1 = 384nf t 2 = r 2 ( c 1 1 c 2 ) t 2 = c 2 r 2 t 2 2 t 3 c 1 or, r 2 = - + c1 r2 c2 from charge pump to vco from charge pump reference

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