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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-98528 rev. *e revised may 05, 2017 S34ML16G2 16-gbit, 4-bit ecc, 8 i/o, 3 v v cc nand flash for embedded general description cypress S34ML16G2 16-gb nand is offered in 3.3 v cc with 8 i/o interface. this docu ment contains information for the S34ML16G2 device, which is a quad-die stack of four s34ml04g2 die. for detailed specif ications, please refer to the discrete di e data sheet: s34ml01g2_04g2 . distinctive characteristics ? density ? 16-gb (4-gb ? 4) ? architecture (for each 4-gb device) ? input / output bus width: 8-bits ? page size: (2048 + 128) bytes; 128-byte spare area ? block size: 64 pages or (128k + 8k) bytes ? plane size ? 2048 blocks per plane or (256m + 16m) bytes ?device size ? 2 planes per device or 512 mbyte ? nand flash interface ? open nand flash interface (onfi) 1.0 compliant ? address, data and commands multiplexed ? supply voltage ? 3.3 v device: vcc = 2.7 v ~ 3.6 v ? security ? one time programmable (otp) area ? serial number (unique id) ? hardware program/erase disabled during power transition ? additional features ? supports multiplane program and erase commands ? supports copy back program ? supports multiplane copy back program ? supports read cache ? electronic signature ? manufacturer id: 01h ? operating temperature ? industrial: ? 40 c to 85 c performance ? page read / program ? random access: 30 s (max) ? sequential access: 25 ns (min) ? program time / multiplane program time: 300 s (typ) ? block erase / multiplane erase ? block erase time: 3.5 ms (typ) ? reliability ? 100,000 program / erase cycles (typ) (with 4-bit ecc per 528 bytes) ? 10 year data retention (typ) ? blocks zero and one are valid and will be valid for at least 1000 program-erase cycles with ecc ? package options ? lead free and low halogen ? 48-pin tsop 12 ? 20 ? 1.2 mm ? 63-ball bga 9 ? 11 ? 1.2 mm
document number: 001-98528 rev. *e page 2 of 18 S34ML16G2 contents general description ............................................................. 1 distinctive characteristics .................................................. 1 performance .......................................................................... 1 1. connection diagram .................................................... 3 2. pin description ............................................................. 4 3. block diagrams ............................................................ 5 4. addressing ................................................................... 7 5. read status enhanced ................................................ 7 6. read id .......................................................................... 8 6.1 read parameter page ................................................... 9 7. electrical characteristics ........................................... 12 7.1 valid blocks .................................................................. 12 7.2 dc characteristics ........................................................ 12 7.3 pin capacitance............................................................ 12 7.4 power consumptions and pin capacitance for allowed stacking configurations ............................. 13 8. physical interface ....................................................... 14 8.1 physical diagram .......................................................... 14 9. ordering information .................................................. 16 10. document history ....................................................... 17
document number: 001-98528 rev. *e page 3 of 18 S34ML16G2 1. connection diagram figure 1.1 48-pin tsop1 contact x8 device (2 ce#, 16 gb) note: 1. these pins should be c onnected to power supply or ground (as designated) following the onfi specification, however they might not be bonded internally. figure 1.2 63-bga contact, x8 device (balls down, top view) note: 1. these pins should be c onnected to power supply or ground (as designated) following the onfi specification, however they might not be bonded internally. nc nc nc nc nc r/b2# r/b1# re# ce1# ce2# nc vcc vss nc nc cle ale we# wp# nc nc nc nc nc vss nc nc nc i/o7 i/o6 i/o5 i/o4 nc vcc nc vcc vss nc vcc nc i/o3 i/o2 i/o1 i/o0 nc nc nc vss 12 13 37 36 25 48 1 24 nand flash tsop1 (x8) (1) (1) (1) (1) f3 f4 f5 f6 f7 f8 e3 e4 e5 e6 e7 e8 d3 d4 d5 d6 d7 d8 c3 c4 c5 c6 c7 c8 rb# we# ce# vss ale wp# nc nc nc cle re# vcc (1) nc nc nc nc nc nc g3 g4 g5 g6 g7 g8 nc vss (1) nc nc nc nc h3 h4 h5 h6 h7 h8 v cc nc nc nc i/o0 nc b9 a9 nc nc a2 nc nc nc nc nc vcc (1) nc b10 a10 nc nc b1 a1 nc nc j3 j4 j5 j6 j7 j8 i/o7 i/o5 v cc nc i/o1 nc k3 k4 k5 k6 k7 k8 v ss i/o6 i/o4 i/o3 i/o2 v ss l9 nc l2 nc l10 nc l1 nc m9 nc m2 nc m10 nc m1 nc
document number: 001-98528 rev. *e page 4 of 18 S34ML16G2 2. pin description notes: 1. a 0.1 f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current su rges from the power supply. the pcb track widths must be sufficient to carry the curr ents required during program and erase operations. 2. an internal voltage detector disables all functions whenever v cc is below 1.8v to protect the device from any involuntary program/erase during power transitions. pin description pin name description i/o0 - i/o7 inputs/outputs . the i/o pins are used for command input, address input, data input, and data output. the i/o pins float to high-z when the device is deselected or the outputs are disabled. cle command latch enable. this input activates the latching of the i/o inputs inside the command register on the rising edge of write enable (we#). ale address latch enable. this input activates the latching of the i/o inputs inside t he address register on the rising edge of write enable (we#). ce# chip enable. this input controls the selection of the device. when the device is not busy ce# low selects the memory. we# write enable. this input latches command, address and data. the i/o inputs are latched on the rising edge of we#. re# read enable. the re# input is the serial data-out control, and when ac tive drives the data onto the i/o bus. data is valid t rea after the falling edge of re# which also increments the internal column address counter by one. wp# write protect. the wp# pin, when low, provides hardware protection against undesired data modification (program / erase). r/b# ready busy . the ready/busy output is an open drain pin that signals the state of the memory. vcc supply voltage . the v cc supplies the power for all the operations (read, program, er ase). an internal lock circuit prevents the insertion of commands when v cc is less than v lko . vss ground. nc not connected.
document number: 001-98528 rev. *e page 5 of 18 S34ML16G2 3. block diagrams figure 3.1 functional block diagram ? 16 gb figure 3.2 block diagram ? 16 gb (4 gb x 4) 48-pin tsop with 2 ce# (two chip enable signals) address register/ counter controller command interface logic command register data register re# i/o buffer y decoder page buffer x d e c o d e r nand flash memory array wp# ce# we# cle ale i/o0~i/o7 program erase hv generation 16 gb device (4 gb x 4) io0~io7 ce2# ce# we# rb# rb2# re# vss ale vcc cle wp# io0~io7 ce# we# rb# re# vss ale vcc cle wp# io0~io7 ce# we# rb# re# vss ale vcc cle wp# io0~io7 io0~io7 ce1# ce# we# we# rb# rb1# re# re# vss vss ale ale vcc vcc cle cle wp# wp# 4 gb x8 nand flash memory #3 4 gb x8 nand flash memory #4 4 gb x8 nand flash memory #1 4 gb x8 nand flash memory #2
document number: 001-98528 rev. *e page 6 of 18 S34ML16G2 figure 3.3 block diagram ? 16 gb (4 gb x 4) 63-ball bga with 1 ce# (one chip enable signal) io0~io7 ce# we# rb# re# vss ale vcc cle wp# io0~io7 ce# we# rb# re# vss ale vcc cle wp# io0~io7 ce# we# rb# re# vss ale vcc cle wp# io0~io7 io0~io7 ce# ce# we# we# rb# rb# re# re# vss vss ale ale vcc vcc cle cle wp# wp# 4 gb x8 nand flash memory#3 4 gb x8 nand flash memory#4 4 gb x8 nand flash memory#1 4 gb x8 nand flash memory#2
document number: 001-98528 rev. *e page 7 of 18 S34ML16G2 4. addressing notes: 1. cax = column address bit. 2. pax = page address bit. 3. pla0 = plane address bit zero. 4. bax = block address bit. 5. block address concatenated with page address and plane address = actual page address, also known as the row address. 6. a31 for 16 gb (4 gb x 4 - qdp) for the address bits, the following rules apply: ? a0 - a11: column address in the page ? a12 - a17: page address in the block ? a18: plane address (for multiplane operatio ns) / block address (for normal operations) ? a19 - a31: block address 5. read status enhanced read status enhanced is used to retrieve the status value for a previous operation in the following cases: ? in the case of concurrent operations on a multi-die stack. when four dies are stacked to form a quad-die package (qdp), it is possible to run one operati on on the first die, then activat e a different operation on the second die, for exampl e: erase while read, read while program, etc. ? in the case of multiplane operations in the same die. address cycle map bus cycle i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 1st / col. add. 1a0 (ca0)a1 (ca1)a2 (ca2)a3 (ca3)a4 (ca4)a5 (ca5)a6 (ca6)a7 (ca7) 2nd / col. add. 2 a8 (ca8) a9 (ca9) a10 (ca10) a11 (ca11) low low low low 3rd / row add. 1 a12 (pa0) a13 (pa1) a14 (pa2) a15 (pa3) a16 (pa4) a17 (pa5) a18 (pla0) a19 (ba0) 4th / row add. 2 a20 (ba1) a21 (ba2) a22 (ba3) a23 (ba4) a24 (ba5) a25 (ba6) a26 (ba7) a27 (ba8) 5th / row add. 3 (6) a28 (ba9) a29 (ba10) a30 (ba11) a31 (ba12) low low low low
document number: 001-98528 rev. *e page 8 of 18 S34ML16G2 6. read id the device contains a product id entification mode, initiated by wr iting 90h to the command register, followed by an address inp ut of 00h. note : if you want to execute read status command (0x70) after read id sequence, you should input dummy command (0x00) before read status command (0x70). for the S34ML16G2 device, five read cycles sequentially output the manufacturer code (01h), and t he device code and 3rd, 4th, a nd 5th cycle id, respectively. the command register remains in read id mode until further commands are issued to it. figure 6.1 read id operation timing read id for supported configurations density org v cc 1st 2nd 3rd 4th 5th 4 gb x8 3.3v 01h dch 90h 95h 56h 16 gb (4 gb x 4 ? qdp with one ce#) x8 3.3v 01h d5h d2h 95h 5eh 16 gb (4 gb x 4 ? qdp with two ce#) x8 3.3v 01h d3h d1h 95h 5ah ce# we# cle re# ale twhr tar trea read id command address 1 cycle maker code device code 3rd cycle 4th cycle 5th cycle i/ox 01h 90h 00h 95h 5eh d2h d5h
document number: 001-98528 rev. *e page 9 of 18 S34ML16G2 5 th id data 6.1 read parameter page the device supports the onfi read parameter page operation, initiated by writing ech to the command register, followed by an address input of 00h. the command register remains in pa rameter page mode until further commands are issued to it. table explains the parameter fields. note: for 32nm cypress nand, for a particular condition, the read parameter page command does not give the correct values. to overcome this issue, the host must issue a reset command before the read parameter page command. issuance of reset before the read parameter page command will provide th e correct values and will not output 00h values. read id byte 5 description description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 ecc level 1 bit / 512 bytes 2 bit / 512 bytes 4 bit / 512 bytes 8 bit / 512 bytes 0 0 0 1 1 0 1 1 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (without spare area) 64 mb 128 mb 256 mb 512 mb 1 gb 2 gb 4 gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 reserved 0 parameter page description byte o/m description values revision information and features block 0-3 m parameter page signature byte 0: 4fh, ?o? byte 1: 4eh, ?n? byte 2: 46h, ?f? byte 3: 49h, ?i? 4fh, 4eh, 46h, 49h 4-5 m revision number 2-15 reserved (0) 1 1 = supports onfi version 1.0 0 reserved (0) 02h, 00h 6-7 m features supported 5-15 reserved (0) 4 1 = supports odd to even page copyback 3 1 = supports interleaved operations 2 1 = supports non-sequential page programming 1 1 = supports multiple lun operations 0 1 = supports 16-bit data bus width 1eh, 00h 8-9 m optional commands supported 6-15 reserved (0) 5 1 = supports read unique id 4 1 = supports copyback 3 1 = supports read status enhanced 2 1 = supports get features and set features 1 1 = supports read cache commands 0 1 = supports page cache program command 3bh, 00h
document number: 001-98528 rev. *e page 10 of 18 S34ML16G2 10-31 reserved (0) 00h manufacturer information block 32-43 m device manufacturer (12 ascii characters) 53h, 50h, 41h, 4eh, 53h, 49h, 4fh, 4eh, 20h, 20h, 20h, 20h 44-63 m device model (20 ascii characters) 53h, 33h, 34h, 4dh, 4ch, 31h, 36h, 47h, 32h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h 64 m jedec manufacturer id 01h 65-66 o date code 00h 67-79 reserved (0) 00h memory organization block 80-83 m number of data bytes per page 00h, 08h, 00h, 00h 84-85 m number of spare bytes per page 80h, 00h 86-89 m number of data bytes per partial page 00h, 00h, 00h, 00h 90-91 m number of spare bytes per partial page 00h, 00h 92-95 m number of pages per block 40h, 00h, 00h, 00h 96-99 m number of blocks per logical unit (lun) 00h, 40h, 00h, 00h (1 ce#) 00h, 20h, 00h, 00h (2 ce#) 100 m number of logical units (luns) 01h (1 ce#) 02h (2 ce#) 101 m number of address cycles 4-7 column address cycles 0-3 row address cycles 23h 102 m number of bits per cell 01h 103-104 m bad blocks maximum per lun 47h, 01h (1 ce#) a3h, 00h (2 ce#) 105-106 m block endurance 01h, 05h 107 m guaranteed valid blocks at beginning of target 01h 108-109 m block endurance for guaranteed valid blocks 01h, 03h 110 m number of programs per page 04h 111 m partial programming attributes 5-7 reserved 4 1 = partial page layout is partial page data followed by partial page spare 1-3 reserved 0 1 = partial page programming has constraints 00h 112 m number of bits ecc correctability 04h 113 m number of interleaved address bits 4-7 reserved (0) 0-3 number of interleaved address bits 01h 114 o interleaved operation attributes 4-7 reserved (0) 3 address restrictions for program cache 2 1 = program cache supported 1 1 = no block address restrictions 0 overlapped / concurrent interleaving support 04h 115-127 reserved (0) 00h electrical parameters block 128 m i/o pin capacitance 0ah parameter page description (continued) byte o/m description values
document number: 001-98528 rev. *e page 11 of 18 S34ML16G2 note: 1. ?o? stands for optional, ?m? for mandatory. 129-130 m timing mode support 6-15 reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0, shall be 1 1fh, 00h 131-132 o program cache timing mode support 6-15 reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0 1fh, 00h 133-134 m t prog maximum page program time (s) bch, 02h 135-136 m t bers maximum block erase time (s) 10h, 27h 137-138 m t r maximum page read time (s) 1eh, 00h 139-140 m t ccs minimum change column setup time (ns) c8h, 00h 141-163 reserved (0) 00h vendor block 164-165 m vendor specific revision number 00h 166-253 vendor specific 00h 254-255 m integrity crc 6fh, d9h (1ce#) 15h, 32h (2ce#) redundant parameter pages 256-511 m value of bytes 0-255 repeat value of bytes 0-255 512-767 m value of bytes 0-255 repeat value of bytes 0-255 768+ o additional redundant parameter pages ffh parameter page description (continued) byte o/m description values
document number: 001-98528 rev. *e page 12 of 18 S34ML16G2 7. electrical characteristics 7.1 valid blocks 7.2 recommended operating conditions 7.3 dc characteristics notes: 1. all v cc pins, and v ss pins respectively, are shorted together. 2. values listed in this table refer to the complete voltage range for v cc and to a single device in case of device stacking. 3. all current measurements are performed with a 0.1 f capacitor connected between the v cc supply voltage pin and the v ss ground pin. 4. standby current measurement can be performed after the dev ice has completed the initialization process at power up. valid blocks device symbol min typ max unit s34ml04g2 n vb 4016 ? 4096 blocks S34ML16G2 (1 ce) n vb 16057 ? 16384 blocks S34ML16G2 (2 ce) n vb 16058 ? 16384 blocks recommended operating conditions parameter symbol min typ max units vcc supply voltage vcc 2.7 3.3 3.6 v ground supply voltage vss 0 0 0 v dc characteristics and operating conditions (values lis ted are for each 4 gb nand, 16 gb (4 gb x 4) will differ accordingly) parameter symbol test conditions min typ max units power on current i cc0 ffh command input after power on ?? 50 per device ma operating current sequential read i cc1 t rc = t rc (min) ce# = v il , iout = 0 ma ?1530ma program i cc2 normal ? 15 30 ma cache ? 15 30 ma erase i cc3 ??1530ma standby current, (ttl) i cc4 ce# = v ih , wp# = 0v/vcc ?? 1ma standby current, (cmos) i cc5 ce# = v cc -0.2, wp# = 0/v cc ?1050a input leakage current i li v in = 0 to v cc (max) ? ? 10 a output leakage current i lo v out = 0 to v cc (max) ? ? 10 a input high voltage v ih ?v cc x 0.8 ? v cc + 0.3 v input low voltage v il ?-0.3?v cc x 0.2 v output high voltage v oh i oh = -400 a 2.4 ? ? v output low voltage v ol i ol = 2.1 ma ? ? 0.4 v output low current (r/b#) i ol(r/b#) v ol = 0.4v 8 10 ? ma erase and program lockout voltage v lko ??1.8?v
document number: 001-98528 rev. *e page 13 of 18 S34ML16G2 7.4 pin capacitance note: 1. for the stacked devices version the input is 10 pf x [number of stacked chips] and the input/output is 10 pf x [number of sta cked chips]. 7.5 power consumptions and pin ca pacitance for allowed stacking configurations when multiple dies are stacked in the same package, the power co nsumption of the stack will increase according to the number of chips. as an example, the standby current is the sum of the standby currents of a ll the chips, while the active power consumpti on depends on the number of chips concurre ntly executing diff erent operations. when multiple dies are stacked in the same package the pin/ball capacitance for the single input and the single input/output of the combo package must be calculated based on the number of chips sharing that input or that pin/ball. pin capacitance (ta = 25c, f = 1.0 mhz) parameter symbol test condition min max unit input c in v in = 0v ? 10 pf input / output c io v il = 0v ? 10 pf
document number: 001-98528 rev. *e page 14 of 18 S34ML16G2 8. physical interface 8.1 physical diagram 8.1.1 48-pin thin small outline package (tsop1) figure 8.1 ts2 48 ? 48-lead plastic thin small outline, 12 x 20 mm, package outline gs5039 -ts4 048-09.05.14 package ts4 48 jedec mo-142 (d) dd symbol min nom max a --- --- 1.20 a1 0.05 --- 0.15 a2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 --- 0.16 c 0.10 --- 0.21 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 e 11.90 12.00 12.10 e 0.50 basic l 0.50 0.60 0.70 o 0? --- 8 r 0.08 --- 0.20 n48 notes: 1. dimensions are in millimeters (mm). (dimensioning and tolerancing conform to ansi y14.5m-1994). 2. pin 1 identifier for standard pin out (die up). 3. pin 1 identifier for reverse pin out (die down): ink or laser mark. 4. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 5. dimensions d1 and e do not include mold protrusion. allowable mold protrusion on e is 0.15mm per side and on d1 is 0.25mm per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of b dimension at max. material condition. dambar cannot be located on lower radius or the foot. minimum space between protrusion and an adjacent lead to be 0.07mm. 7. these dimensions apply to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. 8. lead coplanarity shall be within 0.10mm as measured from the seating plane. 9. dimension "e" is measured at the centerline of the leads.
document number: 001-98528 rev. *e page 15 of 18 S34ML16G2 8.1.2 63-ball bga package figure 8.2 63-ball bga 9 x 11 x 1.2 mm package jedec d x e symbol a a1 d e d1 e1 md me n o b ee ed min. --- 0.25 0.40 a3-a8,b2-b8,c1,c2,c9,c10,d1, d2,d9,d10,e1,e2,e9,e10,f1,f2, f9,f10,g1,g2,g9,g10,h1,h2,h9, h10,j1,j2,j9,j10,k1,k2,k9,k10, l3-l8,m3-m8 tna 063 mo-207(n) 11.00mm x 9.00mm package nom. --- --- 11.00 bsc 9.00 bsc 8.80 bsc 7.20 bsc 12 10 63 0.45 0.80 bsc 0.80 bsc max. 1.20 --- 0.50 note profile ball height body size body size matrix footprint matrix footprint matrix size d direction matrix size e direction ball count ball diameter ball pitch ball pitch solder ball placement solder ball placement sd 0.40 bsc gs5038-tna063-09.05.14 notes: dimensioning and tolerancing methods per asme y14.5m-1994. all dimensions are in millimeters. ball p osition designation per jep 95, section 3, spp-020. e represents the solder ball grid pitch. symbol md is the ball matrix size in the d direction. symbol me is the ball matrix size in the e direction. n is the number of populated solder ball positions for matrix size md x me. dimension b is measured at the maximum ball diameter in a plane parallel to datum c. sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0. when there is an even number of solder balls in the outer row sd = ed/2 and se = ee/2. a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. + indicates the theoretical center of depopulated balls. 1. 2. 3. 4. 5. 6. 7. 8. 9. se 0.40 bsc depopulated solder balls
document number: 001-98528 rev. *e page 16 of 18 S34ML16G2 9. ordering information the ordering part number is formed by a valid combination of the following: valid combinations valid combinations list configurations planne d to be supported in volume for this device. contact your local sales office to co nfirm availability of specific valid combinations and to check on newly released combinations. s34ml 16g 2 02 t f i 20 0 packing type 0 = tray 3 = 13? tape and reel model number 00 = standard interface / onfi (x8) 20 = two chip enable with standard onfi (x8) temperature range i = industrial (?40 c to + 85 c) materials set f = lead (pb)-free h = lead (pb)-free and low halogen package b = bga t = tsop bus width 00 = x8 nand, single die 04 = x16 nand, single die 01 = x8 nand, dual die 02 = x8 nand, quad die 05 = x16 nand, dual die technology 2 = cypress nand revision 2 (32 nm) density 01g = 1 gb 02g = 2 gb 04g = 4 gb 08g = 8 gb 16g = 16 gb device family s34ml cypress slc nand flash memory for embedded valid combinations device family density technology bus width package type temperature range additional ordering options packing type package description s34ml 16g 2 02 tf/bh i tf ? 20 bh ? 00 0, 3 bga tsop
document number: 001-98528 rev. *e page 17 of 18 S34ML16G2 10. document history document title: S34ML16G2 16-gbi t, 4-bit ecc, 8 i/o, 3 v v cc nand flash for embedded document number: 001-98528 rev. ecn no. orig. of change submission date description of change ** ?? 10/28/2014 initial release (spansion publication number: S34ML16G2) *a ?? 06/10/2015 performance: corrected package options for 63-ball bga to 9 x 11 x 1.2 mm connection diagram: 63-bga contact, x8 devi ce (balls down, top view) figure: added note physical interface: 63-ball bga package: corr ected figure title to ?63-ball bga 9 x 11 x 1.2 mm? 08/19/2015 read id: read id for supported configurations table: added 16 gb (4 gb x 4 ? qdp with two ce#) electrical characterist ics: valid blocks table: added S34ML16G2 (2 ce) *b 4965191 xila 10/15/2015 updated to cypress template. *c 5016364 xila 11/20/2015 updated to new template. *d 5160512 xila 04/25/2016 added recommended operating conditions section. updated dc characteristics section - updated ?vcc supply voltage (erase and program lockout)? to "erase and program lockout voltage?. updated ?read parameter page? section. updated copyright information at the end of the document. *e 5727817 hara 05/05/2017 updated logo and copyright.
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