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ddr4 sdram mt40a2g4 mt40a1g8 mt40a512m16 features ?v dd = v ddq = 1.2v 60mv ?v pp = 2.5v, C125mv, +250mv ? on-die, internal, adjustable v refdq generation ? 1.2v pseudo open-drain i/o ?t c maximum up to 95c C 64ms, 8192-cycle refresh up to 85c C 32ms, 8192-cycle refresh at >85c to 95c ? 16 internal banks (x4, x8): 4 groups of 4 banks each ? 8 internal banks (x16): 2 groups of 4 banks each ?8 n -bit prefetch architecture ? programmable data strobe preambles ? data strobe preamble training ? command/address latency (cal) ? multipurpose register read and write capability ? write and read leveling ? self refresh mode ? low-power auto self refresh (lpasr) ? temperature controlled refresh (tcr) ? fine granularity refresh ? self refresh abort ? maximum power saving ? output driver calibration ? nominal, park, and dynamic on-die termination (odt) ? data bus inversion (dbi) for data bus ? command/address (ca) parity ? databus write cyclic redundancy check (crc) ? per-dram addressability ? connectivity test (x16) ? jedec jesd-79-4 compliant ? sppr and hppr capability options 1 marking ? configuration C 2 gig x 4 2g4 C 1 gig x 8 1g8 C 512 meg x 16 512m16 ? 78-ball fbga package (pb-free) C x4, x8 C 9mm x 13.2mm C rev. a pm C 8mm x 12mm C rev. b, d, g we C 7.5mm x 11mm C rev. e, h sa ? 96-ball fbga package (pb-free) C x16 C 9mm x 14mm C rev. a ha C 8mm x 14mm C rev. b jy C 7.5mm x 13.5mm C rev. d, e, h ly ? timing C cycle time C 0.625ns @ cl = 22 (ddr4-3200) -062e C 0.682ns @ cl = 20 (ddr4-2933) -068e C 0.682ns @ cl = 21 (ddr4-2933) -068 C 0.750ns @ cl = 18 (ddr4-2666) -075e C 0.750ns @ cl = 19 (ddr4-2666) -075 C 0.833ns @ cl = 16 (ddr4-2400) -083e C 0.833ns @ cl = 17 (ddr4-2400) -083 C 0.937ns @ cl = 15 (ddr4-2133) -093e C 0.937ns @ cl = 16 (ddr4-2133) -093 C 1.071ns @ cl = 13 (ddr4-1866) -107e ? operating temperature C commercial (0 t c 95c) none C industrial (C40 t c 95c) it ? revision :a, :b, :d, :g, :e, :h note: 1. not all options listed can be combined to define an offered product. use the part catalog search on http://www.micron.com for available offerings. table 1: key timing parameters speed grade data rate (mt/s) target t rcd- t rp-cl t rcd (ns) t rp (ns) cl (ns) -062e 6 3200 22-22-22 13.75 13.75 13.75 -068e 5 2933 20-20-20 13.64 13.64 13.64 -068 5 2933 21-21-21 14.32 14.32 14.32 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 1: key timing parameters (continued) speed grade data rate (mt/s) target t rcd- t rp-cl t rcd (ns) t rp (ns) cl (ns) -075e 4 2666 18-18-18 13.5 13.5 13.5 -075 4 2666 19-19-19 14.25 14.25 14.25 -083e 3 2400 16-16-16 13.32 13.32 13.32 -083 3 2400 17-17-17 14.16 14.16 14.16 -093e 2 2133 15-15-15 14.06 14.06 14.06 -093 2 2133 16-16-16 15 15 15 -107e 1 1866 13-13-13 13.92 13.92 13.92 notes: 1. backward compatible to 1600, cl = 11. 2. backward compatible to 1600, cl = 11 and 1866, cl = 13. 3. backward compatible to 1600, cl = 11; 1866, cl = 13; and 2133, cl = 15. 4. backward compatible to 1600, cl = 11; 1866, cl = 13; 2133, cl = 15; and 2400, cl = 17. 5. backward compatible to 1600, cl = 11; 1866, cl = 13; 2133, cl = 15; 2400, cl = 17; and 2666, cl = 19. speed offering may have restricted availability. 6. backward compatible to 1600, cl = 11; 1866, cl = 13; 2133, cl = 15; 2400, cl = 17; 2666, cl = 19; and 2933, cl = 20 and cl = 21. speed offering may have restricted availability. table 2: addressing parameter 2048 meg x 4 1024 meg x 8 512 meg x 16 number of bank groups 4 4 2 bank group address bg[1:0] bg[1:0] bg0 bank count per group 4 4 4 bank address in bank group ba[1:0] ba[1:0] ba[1:0] row addressing 128k (a[16:0]) 64k (a[15:0]) 64k (a[15:0]) column addressing 1k (a[9:0]) 1k (a[9:0]) 1k (a[9:0]) page size 1 512b/1kb 2 1kb 2kb notes: 1. page size is per bank, calculated as follows: page size = 2 colbits org/8, where colbit = the number of column address bits and org = the number of dq bits. 2. die rev. dependant. 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 1: order part number example example part number: mt40a1g8-083:b configuration 2 gig x 4 1 gig x 8 512 meg x 16 2g4 1g8 512m16 - configuration mt40a package speed revision :a, :b, :d, :g, :e, :h : commercial industrial temperature { none it package 78-ball 8.0mm x 12.0mm fbga mark we 78-ball 9.0mm x 13.2mm fbga pm speed grade -107e -093 -093e -083 -083e -075 -075e -068 -068e -062e t ck = 1.071ns, cl = 13 t ck = 0.937ns, cl = 16 t ck = 0.937ns, cl = 15 t ck = 0.833ns, cl = 17 t ck = 0.833ns, cl = 16 t ck = 0.750ns, cl = 19 t ck = 0.750ns, cl = 18 t ck = 0.682ns, cl = 21 t ck = 0.682ns, cl = 20 t ck = 0.625ns, cl = 22 case temperature 96-ball 9.0mm x 14.0mm fbga 78-ball 7.5mm x 11.0mm fbga sa ha ly 96-ball 7.5mm x 13.5mm fbga 96-ball 8.0mm x 14.0mm fbga jy revision 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
contents general notes and description ....................................................................................................................... 19 description ............................................................................................................................... ................. 19 industrial temperature ............................................................................................................................... 19 general notes ............................................................................................................................... ............. 19 definitions of the device-pin signal level ................................................................................................... 20 definitions of the bus signal level ............................................................................................................... 20 functional block diagrams ............................................................................................................................. 2 1 ball assignments ............................................................................................................................... ............. 23 ball descriptions ............................................................................................................................... ............. 25 package dimensions ............................................................................................................................... ........ 28 state diagram ............................................................................................................................... ................. 34 functional description ............................................................................................................................... .... 36 reset and initialization procedure ................................................................................................................. 37 power-up and initialization sequence ......................................................................................................... 37 reset initialization with stable power sequence ......................................................................................... 40 uncontrolled power-down sequence .......................................................................................................... 41 programming mode registers ......................................................................................................................... 42 mode register 0 ............................................................................................................................... ............... 45 burst length, type, and order ..................................................................................................................... 47 cas latency ............................................................................................................................... ................ 48 test mode ............................................................................................................................... ................... 48 write recovery(wr)/read-to-precharge ............................................................................................... 48 dll reset ............................................................................................................................... .................. 48 mode register 1 ............................................................................................................................... ............... 49 dll enable/dll disable ............................................................................................................................ 50 output driver impedance control ............................................................................................................... 51 odt r tt(nom) values ............................................................................................................................... ... 51 additive latency ............................................................................................................................... .......... 51 write leveling ............................................................................................................................... ............. 51 output disable ............................................................................................................................... ............ 52 termination data strobe ............................................................................................................................. 5 2 mode register 2 ............................................................................................................................... ............... 53 cas write latency ............................................................................................................................... ..... 55 low-power auto self refresh ....................................................................................................................... 55 dynamic odt ............................................................................................................................... ............. 55 write cyclic redundancy check data bus .................................................................................................... 55 mode register 3 ............................................................................................................................... ............... 56 multipurpose register ............................................................................................................................... . 57 write command latency when crc/dm is enabled ................................................................................. 58 fine granularity refresh mode .................................................................................................................... 58 temperature sensor status ......................................................................................................................... 58 per-dram addressability ........................................................................................................................... 58 gear-down mode ............................................................................................................................... ........ 58 mode register 4 ............................................................................................................................... ............... 59 hard post package repair mode .................................................................................................................. 60 soft post package repair mode .................................................................................................................... 60 write preamble ............................................................................................................................... ......... 61 read preamble ............................................................................................................................... ........... 61 read preamble training ............................................................................................................................ 61 temperature-controlled refresh ................................................................................................................. 61 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
command address latency ........................................................................................................................ 61 internal v ref monitor ............................................................................................................................... .. 61 maximum power savings mode ................................................................................................................... 62 mode register 5 ............................................................................................................................... ............... 63 data bus inversion ............................................................................................................................... ...... 64 data mask ............................................................................................................................... ................... 65 ca parity persistent error mode .................................................................................................................. 65 odt input buffer for power-down .............................................................................................................. 65 ca parity error status ............................................................................................................................... .. 65 crc error status ............................................................................................................................... .......... 65 ca parity latency mode .............................................................................................................................. 65 mode register 6 ............................................................................................................................... ............... 66 t ccd_l programming ............................................................................................................................... .. 67 v refdq calibration enable .......................................................................................................................... 67 v refdq calibration range ........................................................................................................................... 67 v refdq calibration value ............................................................................................................................ 67 truth tables ............................................................................................................................... .................... 68 nop command ............................................................................................................................... ............... 71 deselect command ............................................................................................................................... ..... 71 dll-off mode ............................................................................................................................... ................. 71 dll-on/off switching procedures .................................................................................................................. 73 dll switch sequence from dll-on to dll-off ........................................................................................... 73 dll-off to dll-on procedure .................................................................................................................... 75 input clock frequency change ....................................................................................................................... 76 write leveling ............................................................................................................................... ................. 77 dram setting for write leveling and dram termination function in that mode ..................................... 78 procedure description ............................................................................................................................... . 79 write leveling mode exit ............................................................................................................................ 80 command address latency ............................................................................................................................ 82 low-power auto self refresh mode ................................................................................................................. 87 manual self refresh mode .......................................................................................................................... 87 multipurpose register ............................................................................................................................... ..... 89 mpr reads ............................................................................................................................... .................. 90 mpr readout format ............................................................................................................................... .. 92 mpr readout serial format ........................................................................................................................ 92 mpr readout parallel format ..................................................................................................................... 93 mpr readout staggered format .................................................................................................................. 94 mpr read waveforms ............................................................................................................................... 95 mpr writes ............................................................................................................................... ................. 97 mpr write waveforms .............................................................................................................................. 98 mpr refresh waveforms ......................................................................................................................... 99 gear-down mode ............................................................................................................................... ........... 102 maximum power-saving mode ....................................................................................................................... 105 maximum power-saving mode entry .......................................................................................................... 105 maximum power-saving mode entry in pda .............................................................................................. 106 cke transition during maximum power-saving mode ................................................................................ 106 maximum power-saving mode exit ............................................................................................................ 106 command/address parity .............................................................................................................................. 108 per-dram addressability .............................................................................................................................. 116 v refdq calibration ............................................................................................................................... ......... 119 v refdq range and levels ........................................................................................................................... 120 v refdq step size ............................................................................................................................... ......... 120 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
v refdq increment and decrement timing .................................................................................................. 121 v refdq target settings ............................................................................................................................... 125 connectivity test mode ............................................................................................................................... .. 127 pin mapping ............................................................................................................................... .............. 127 minimum terms definition for logic equations ......................................................................................... 128 logic equations for a x4 device, when supported ....................................................................................... 128 logic equations for a x8 device, when supported ....................................................................................... 129 logic equations for a x16 device ................................................................................................................ 129 ct input timing requirements .................................................................................................................. 129 excessive row activation ............................................................................................................................... 131 post package repair ............................................................................................................................... ........ 132 post package repair ............................................................................................................................... .... 132 hard post package repair .............................................................................................................................. 133 hppr row repair - entry ............................................................................................................................ 13 3 hppr row repair C wra initiated (ref commands allowed) ...................................................................... 133 hppr row repair C wr initiated (ref commands not allowed) ................................................................. 135 sppr row repair ............................................................................................................................... ............ 137 hppr/sppr support identifier ........................................................................................................................ 140 activate command ............................................................................................................................... ..... 140 precharge command ............................................................................................................................... . 141 refresh command ............................................................................................................................... ...... 141 temperature-controlled refresh mode .......................................................................................................... 144 tcr mode C normal temperature range .................................................................................................... 144 tcr mode C extended temperature range ................................................................................................. 144 fine granularity refresh mode ....................................................................................................................... 146 mode register and command truth table .................................................................................................. 146 t refi and t rfc parameters ........................................................................................................................ 146 changing refresh rate ............................................................................................................................... 149 usage with tcr mode ............................................................................................................................... . 149 self refresh entry and exit ......................................................................................................................... 149 self refresh operation .............................................................................................................................. 151 self refresh abort ............................................................................................................................... ....... 153 self refresh exit with nop command ......................................................................................................... 154 power-down mode ............................................................................................................................... ......... 156 power-down clarifications C case 1 ........................................................................................................... 161 power-down entry, exit timing with cal ................................................................................................... 162 odt input buffer disable mode for power-down ............................................................................................ 164 crc write data feature ............................................................................................................................... .. 166 crc write data ............................................................................................................................... .......... 166 write crc data operation ...................................................................................................................... 166 dbi_n and crc both enabled .................................................................................................................... 167 dm_n and crc both enabled .................................................................................................................... 167 dm_n and dbi_n conflict during writes with crc enabled ........................................................................ 167 crc and write preamble restrictions ......................................................................................................... 167 crc simultaneous operation restrictions .................................................................................................. 167 crc polynomial ............................................................................................................................... ......... 167 crc combinatorial logic equations .......................................................................................................... 168 burst ordering for bl8 ............................................................................................................................... 169 crc data bit mapping ............................................................................................................................... 169 crc enabled with bc4 .............................................................................................................................. 170 crc with bc4 data bit mapping ................................................................................................................ 170 crc equations for x8 device in bc4 mode with a2 = 0 and a2 = 1 ................................................................ 173 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
crc error handling ............................................................................................................................... .... 174 crc write data flow diagram ................................................................................................................... 176 data bus inversion ............................................................................................................................... ......... 177 dbi during a write operation .................................................................................................................. 177 dbi during a read operation ................................................................................................................... 178 data mask ............................................................................................................................... ...................... 179 programmable preamble modes and dqs postambles .................................................................................... 181 write preamble mode .............................................................................................................................. 181 read preamble mode ............................................................................................................................... 184 read preamble training ........................................................................................................................... 184 write postamble ............................................................................................................................... ....... 185 read postamble ............................................................................................................................... ........ 185 bank access operation ............................................................................................................................... ... 187 read operation ............................................................................................................................... ............. 191 read timing definitions ............................................................................................................................ 19 1 read timing C clock-to-data strobe relationship ....................................................................................... 192 read timing C data strobe-to-data relationship ........................................................................................ 194 t lz(dqs), t lz(dq), t hz(dqs), and t hz(dq) calculations ............................................................................ 195 t rpre calculation ............................................................................................................................... ...... 196 t rpst calculation ............................................................................................................................... ....... 197 read burst operation ............................................................................................................................... 198 read operation followed by another read operation .............................................................................. 200 read operation followed by write operation .......................................................................................... 205 read operation followed by precharge operation ................................................................................ 211 read operation with read data bus inversion (dbi) .................................................................................. 214 read operation with command/address parity (ca parity) ........................................................................ 215 read followed by write with crc enabled .............................................................................................. 217 read operation with command/address latency (cal) enabled ............................................................... 218 write operation ............................................................................................................................... ........... 220 write timing definitions ........................................................................................................................... 220 write timing C clock-to-data strobe relationship ...................................................................................... 220 t wpre calculation ............................................................................................................................... ..... 222 t wpst calculation ............................................................................................................................... ...... 223 write timing C data strobe-to-data relationship ........................................................................................ 223 write burst operation ............................................................................................................................. 2 27 write operation followed by another write operation ........................................................................... 229 write operation followed by read operation .......................................................................................... 235 write operation followed by precharge operation ............................................................................... 239 write operation with write dbi enabled ................................................................................................ 242 write operation with ca parity enabled ................................................................................................... 244 write operation with write crc enabled ................................................................................................. 245 write timing violations ............................................................................................................................... .. 250 motivation ............................................................................................................................... ................. 250 data setup and hold violations ................................................................................................................. 250 strobe-to-strobe and strobe-to-clock violations ........................................................................................ 250 zq calibration commands ....................................................................................................................... 251 on-die termination ............................................................................................................................... ....... 253 odt mode register and odt state table ........................................................................................................ 253 odt read disable state table .................................................................................................................... 254 synchronous odt mode ............................................................................................................................... . 255 odt latency and posted odt .................................................................................................................... 255 timing parameters ............................................................................................................................... ..... 255 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
odt during reads ............................................................................................................................... ..... 257 dynamic odt ............................................................................................................................... ................ 258 functional description .............................................................................................................................. 258 asynchronous odt mode .............................................................................................................................. 261 electrical specifications ............................................................................................................................... .. 262 absolute ratings ............................................................................................................................... ......... 262 dram component operating temperature range ...................................................................................... 262 electrical characteristics C ac and dc operating conditions .......................................................................... 263 supply operating conditions ..................................................................................................................... 263 leakages ............................................................................................................................... .................... 264 v refca supply ............................................................................................................................... ............. 264 v refdq supply and calibration ranges ....................................................................................................... 265 v refdq ranges ............................................................................................................................... ............ 266 electrical characteristics C ac and dc single-ended input measurement levels .............................................. 267 reset_n input levels ............................................................................................................................... . 267 command/address input levels ................................................................................................................ 267 command, control, and address setup, hold, and derating ........................................................................ 269 data receiver input requirements ............................................................................................................. 271 connectivity test (ct) mode input levels .................................................................................................. 275 electrical characteristics C ac and dc differential input measurement levels ................................................. 279 differential inputs ............................................................................................................................... ...... 279 single-ended requirements for ck differential signals ............................................................................... 280 slew rate definitions for ck differential input signals ................................................................................ 281 ck differential input cross point voltage .................................................................................................... 282 dqs differential input signal definition and swing requirements .............................................................. 283 dqs differential input cross point voltage ................................................................................................. 285 slew rate definitions for dqs differential input signals .............................................................................. 286 electrical characteristics C overshoot and undershoot specifications ............................................................. 288 address, command, and control overshoot and undershoot specifications ................................................ 288 clock overshoot and undershoot specifications ......................................................................................... 289 data, strobe, and mask overshoot and undershoot specifications .............................................................. 290 electrical characteristics C ac and dc output measurement levels ................................................................ 290 single-ended outputs ............................................................................................................................... 290 differential outputs ............................................................................................................................... ... 292 reference load for ac timing and output slew rate ................................................................................... 293 connectivity test mode output levels ........................................................................................................ 294 electrical characteristics C ac and dc output driver characteristics ............................................................... 295 connectivity test mode output driver electrical characteristics ................................................................. 295 output driver electrical characteristics ..................................................................................................... 297 output driver temperature and voltage sensitivity ..................................................................................... 300 alert driver ............................................................................................................................... ................ 300 electrical characteristics C on-die termination characteristics ...................................................................... 301 odt levels and i-v characteristics ............................................................................................................ 301 odt temperature and voltage sensitivity ................................................................................................... 303 odt timing definitions ............................................................................................................................ 30 3 dram package electrical specifications ......................................................................................................... 307 thermal characteristics ............................................................................................................................... .. 311 current specifications C measurement conditions .......................................................................................... 312 i dd , i pp , and i ddq measurement conditions ................................................................................................ 312 i dd definitions ............................................................................................................................... ........... 314 current specifications C patterns and test conditions ..................................................................................... 318 current test definitions and patterns ......................................................................................................... 318 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
i dd specifications ............................................................................................................................... ....... 327 current specifications C limits ....................................................................................................................... 328 speed bin tables ............................................................................................................................... ............ 338 refresh parameters by device density ............................................................................................................ 346 electrical characteristics and ac timing parameters ...................................................................................... 347 electrical characteristics and ac timing parameters: 2666 through 3200 ........................................................ 359 converting time-based specifications to clock-based requirements .............................................................. 371 options tables ............................................................................................................................... ............... 372 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
list of figures figure 1: order part number example .............................................................................................................. 3 figure 2: 2 gig x 4 functional block diagram .................................................................................................. 21 figure 3: 1 gig x 8 functional block diagram .................................................................................................. 21 figure 4: 512 meg x 16 functional block diagram ........................................................................................... 22 figure 5: 78-ball x4, x8 ball assignments ........................................................................................................ 23 figure 6: 96-ball x16 ball assignments ............................................................................................................ 24 figure 7: 78-ball fbga C x4, x8 (pm) ............................................................................................................... 28 figure 8: 78-ball fbga C x4, x8 (we) ............................................................................................................... 29 figure 9: 78-ball fbga C x4, x8 (sa) ................................................................................................................ 30 figure 10: 96-ball fbga C x16 (ha) ................................................................................................................. 31 figure 11: 96-ball fbga C x16 (jy) .................................................................................................................. 32 figure 12: 96-ball fbga C x16 (ly) .................................................................................................................. 33 figure 13: simplified state diagram ............................................................................................................... 34 figure 14: reset and initialization sequence at power-on ramping ............................................................... 40 figure 15: reset procedure at power stable condition ................................................................................... 41 figure 16: t mrd timing ............................................................................................................................... . 43 figure 17: t mod timing ............................................................................................................................... . 43 figure 18: dll-off mode read timing operation ........................................................................................... 72 figure 19: dll switch sequence from dll-on to dll-off .............................................................................. 74 figure 20: dll switch sequence from dll-off to dll-on .............................................................................. 75 figure 21: write leveling concept, example 1 ................................................................................................ 77 figure 22: write leveling concept, example 2 ................................................................................................ 78 figure 23: write leveling sequence (dqs capturing ck low at t1 and ck high at t2) .................................. 80 figure 24: write leveling exit ......................................................................................................................... 81 figure 25: cal timing definition ................................................................................................................... 82 figure 26: cal timing example (consecutive cs_n = low) ............................................................................ 82 figure 27: cal enable timing C t mod_cal ................................................................................................... 83 figure 28: t mod_cal, mrs to valid command timing with cal enabled ....................................................... 83 figure 29: cal enabling mrs to next mrs command, t mrd_cal .................................................................. 84 figure 30: t mrd_cal, mode register cycle time with cal enabled ............................................................... 84 figure 31: consecutive read bl8, cal3, 1 t ck preamble, different bank group ............................................... 85 figure 32: consecutive read bl8, cal4, 1 t ck preamble, different bank group ............................................... 85 figure 33: auto self refresh ranges ................................................................................................................ 88 figure 34: mpr block diagram ....................................................................................................................... 89 figure 35: mpr read timing ........................................................................................................................ 95 figure 36: mpr back-to-back read timing ................................................................................................... 96 figure 37: mpr read-to-write timing ........................................................................................................ 97 figure 38: mpr write and write-to-read timing ...................................................................................... 98 figure 39: mpr back-to-back write timing .................................................................................................. 99 figure 40: refresh timing ........................................................................................................................... 99 figure 41: read-to-refresh timing ........................................................................................................... 100 figure 42: write-to-refresh timing ......................................................................................................... 100 figure 43: clock mode change from 1/2 rate to 1/4 rate (initialization) ......................................................... 103 figure 44: clock mode change after exiting self refresh ................................................................................ 103 figure 45: comparison between gear-down disable and gear-down enable ................................................. 104 figure 46: maximum power-saving mode entry ............................................................................................. 105 figure 47: maximum power-saving mode entry with pda .............................................................................. 106 figure 48: maintaining maximum power-saving mode with cke transition ................................................... 106 figure 49: maximum power-saving mode exit ............................................................................................... 107 figure 50: command/address parity operation ............................................................................................. 108 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 51: command/address parity during normal operation ..................................................................... 110 figure 52: persistent ca parity error checking operation ............................................................................... 111 figure 53: ca parity error checking C sre attempt ........................................................................................ 111 figure 54: ca parity error checking C srx attempt ........................................................................................ 112 figure 55: ca parity error checking C pde/pdx ............................................................................................ 112 figure 56: parity entry timing example C t mrd_par ..................................................................................... 113 figure 57: parity entry timing example C t mod_par ..................................................................................... 113 figure 58: parity exit timing example C t mrd_par ....................................................................................... 113 figure 59: parity exit timing example C t mod_par ....................................................................................... 114 figure 60: ca parity flow diagram ................................................................................................................ 115 figure 61: pda operation enabled, bl8 ........................................................................................................ 117 figure 62: pda operation enabled, bc4 ........................................................................................................ 117 figure 63: mrs pda exit ............................................................................................................................... 118 figure 64: v refdq voltage range ................................................................................................................... 119 figure 65: example of v ref set tolerance and step size .................................................................................. 121 figure 66: v refdq timing diagram for v ref,time parameter .............................................................................. 122 figure 67: v refdq training mode entry and exit timing diagram ................................................................... 123 figure 68: v ref step: single step size increment case .................................................................................... 124 figure 69: v ref step: single step size decrement case ................................................................................... 124 figure 70: v ref full step: from v ref,min to v ref,max case .................................................................................. 125 figure 71: v ref full step: from v ref,max to v ref,min case .................................................................................. 125 figure 72: v refdq equivalent circuit ............................................................................................................. 126 figure 73: connectivity test mode entry ....................................................................................................... 130 figure 74: hppr wra C entry ........................................................................................................................ 135 figure 75: hppr wra C repair and exit ......................................................................................................... 135 figure 76: hppr wr C entry .......................................................................................................................... 136 figure 77: hppr wr C repair and exit ............................................................................................................ 136 figure 78: sppr C entry ............................................................................................................................... .. 139 figure 79: sppr C repair, and exit ................................................................................................................. 139 figure 80: t rrd timing ............................................................................................................................... . 140 figure 81: t faw timing ............................................................................................................................... .. 141 figure 82: refresh command timing ......................................................................................................... 142 figure 83: postponing refresh commands (example) ................................................................................. 143 figure 84: pulling in refresh commands (example) ................................................................................... 143 figure 85: tcr mode example 1 ..................................................................................................................... 145 figure 86: 4gb with fine granularity refresh mode example ......................................................................... 148 figure 87: otf refresh command timing ................................................................................................. 149 figure 88: self refresh entry/exit timing ...................................................................................................... 152 figure 89: self refresh entry/exit timing with cal mode ............................................................................... 153 figure 90: self refresh abort ......................................................................................................................... 154 figure 91: self refresh exit with nop command ............................................................................................ 155 figure 92: active power-down entry and exit ................................................................................................ 157 figure 93: power-down entry after read and read with auto precharge ......................................................... 158 figure 94: power-down entry after write and write with auto precharge ........................................................ 158 figure 95: power-down entry after write ...................................................................................................... 159 figure 96: precharge power-down entry and exit .......................................................................................... 159 figure 97: refresh command to power-down entry ................................................................................... 160 figure 98: active command to power-down entry ......................................................................................... 160 figure 99: precharge/precharge all command to power-down entry .................................................. 161 figure 100: mrs command to power-down entry ......................................................................................... 161 figure 101: power-down entry/exit clarifications C case 1 ............................................................................ 162 figure 102: active power-down entry and exit timing with cal .................................................................... 162 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 103: refresh command to power-down entry with cal ................................................................... 163 figure 104: odt power-down entry with odt buffer disable mode .............................................................. 164 figure 105: odt power-down exit with odt buffer disable mode ................................................................. 165 figure 106: crc write data operation .......................................................................................................... 166 figure 107: crc error reporting ................................................................................................................... 175 figure 108: ca parity flow diagram .............................................................................................................. 176 figure 109: 1 t ck vs. 2 t ck write preamble mode ........................................................................................... 181 figure 110: 1 t ck vs. 2 t ck write preamble mode, t ccd = 4 ............................................................................ 182 figure 111: 1 t ck vs. 2 t ck write preamble mode, t ccd = 5 ............................................................................ 183 figure 112: 1 t ck vs. 2 t ck write preamble mode, t ccd = 6 ........................................................................... 183 figure 113: 1 t ck vs. 2 t ck read preamble mode ............................................................................................ 184 figure 114: read preamble training ............................................................................................................. 185 figure 115: write postamble ....................................................................................................................... 185 figure 116: read postamble ........................................................................................................................ 186 figure 117: bank group x4/x8 block diagram ................................................................................................ 187 figure 118: read burst t ccd_s and t ccd_l examples .................................................................................. 188 figure 119: write burst t ccd_s and t ccd_l examples ................................................................................... 188 figure 120: t rrd timing ............................................................................................................................... 189 figure 121: t wtr_s timing (write-to-read, different bank group, crc and dm disabled) ......................... 189 figure 122: t wtr_l timing (write-to-read, same bank group, crc and dm disabled) .............................. 190 figure 123: read timing definition ............................................................................................................... 192 figure 124: clock-to-data strobe relationship .............................................................................................. 193 figure 125: data strobe-to-data relationship ................................................................................................ 194 figure 126: t lz and t hz method for calculating transitions and endpoints .................................................... 195 figure 127: t rpre method for calculating transitions and endpoints ............................................................. 196 figure 128: t rpst method for calculating transitions and endpoints ............................................................. 197 figure 129: read burst operation, rl = 11 (al = 0, cl = 11, bl8) ................................................................... 198 figure 130: read burst operation, rl = 21 (al = 10, cl = 11, bl8) ................................................................. 199 figure 131: consecutive read (bl8) with 1 t ck preamble in different bank group .......................................... 200 figure 132: consecutive read (bl8) with 2 t ck preamble in different bank group .......................................... 200 figure 133: nonconsecutive read (bl8) with 1 t ck preamble in same or different bank group ....................... 201 figure 134: nonconsecutive read (bl8) with 2 t ck preamble in same or different bank group ....................... 201 figure 135: read (bc4) to read (bc4) with 1 t ck preamble in different bank group ...................................... 202 figure 136: read (bc4) to read (bc4) with 2 t ck preamble in different bank group ...................................... 202 figure 137: read (bl8) to read (bc4) otf with 1 t ck preamble in different bank group ............................... 203 figure 138: read (bl8) to read (bc4) otf with 2 t ck preamble in different bank group ............................... 203 figure 139: read (bc4) to read (bl8) otf with 1 t ck preamble in different bank group ............................... 204 figure 140: read (bc4) to read (bl8) otf with 2 t ck preamble in different bank group ............................... 204 figure 141: read (bl8) to write (bl8) with 1 t ck preamble in same or different bank group ........................ 205 figure 142: read (bl8) to write (bl8) with 2 t ck preamble in same or different bank group ........................ 205 figure 143: read (bc4) otf to write (bc4) otf with 1 t ck preamble in same or different bank group ......... 206 figure 144: read (bc4) otf to write (bc4) otf with 2 t ck preamble in same or different bank group ......... 207 figure 145: read (bc4) fixed to write (bc4) fixed with 1 t ck preamble in same or different bank group ..... 207 figure 146: read (bc4) fixed to write (bc4) fixed with 2 t ck preamble in same or different bank group ..... 208 figure 147: read (bc4) to write (bl8) otf with 1 t ck preamble in same or different bank group ................ 209 figure 148: read (bc4) to write (bl8) otf with 2 t ck preamble in same or different bank group ................ 209 figure 149: read (bl8) to write (bc4) otf with 1 t ck preamble in same or different bank group ................ 210 figure 150: read (bl8) to write (bc4) otf with 2 t ck preamble in same or different bank group ................ 210 figure 151: read to precharge with 1 t ck preamble .................................................................................. 211 figure 152: read to precharge with 2 t ck preamble .................................................................................. 212 figure 153: read to precharge with additive latency and 1 t ck preamble .................................................. 212 figure 154: read with auto precharge and 1 t ck preamble ............................................................................ 213 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 155: read with auto precharge, additive latency, and 1 t ck preamble ................................................. 214 figure 156: consecutive read (bl8) with 1 t ck preamble and dbi in different bank group ............................ 214 figure 157: consecutive read (bl8) with 1 t ck preamble and ca parity in different bank group .................... 215 figure 158: read (bl8) to write (bl8) with 1 t ck preamble and ca parity in same or different bank group ... 216 figure 159: read (bl8) to write (bl8 or bc4: otf) with 1 t ck preamble and write crc in same or different bank group ............................................................................................................................... ................ 217 figure 160: read (bc4: fixed) to write (bc4: fixed) with 1 t ck preamble and write crc in same or different bank group ............................................................................................................................... ................ 218 figure 161: consecutive read (bl8) with cal (3 t ck) and 1 t ck preamble in different bank group .................. 218 figure 162: consecutive read (bl8) with cal (4 t ck) and 1 t ck preamble in different bank group .................. 219 figure 163: write timing definition .............................................................................................................. 221 figure 164: t wpre method for calculating transitions and endpoints ............................................................ 222 figure 165: t wpst method for calculating transitions and endpoints ............................................................ 223 figure 166: rx compliance mask .................................................................................................................. 224 figure 167: v cent_dq v refdq voltage variation .............................................................................................. 224 figure 168: rx mask dq-to-dqs timings ...................................................................................................... 225 figure 169: rx mask dq-to-dqs dram-based timings ................................................................................. 226 figure 170: example of data input requirements without training ................................................................ 227 figure 171: write burst operation, wl = 9 (al = 0, cwl = 9, bl8) ................................................................. 228 figure 172: write burst operation, wl = 19 (al = 10, cwl = 9, bl8) ............................................................. 229 figure 173: consecutive write (bl8) with 1 t ck preamble in different bank group ........................................ 229 figure 174: consecutive write (bl8) with 2 t ck preamble in different bank group ........................................ 230 figure 175: nonconsecutive write (bl8) with 1 t ck preamble in same or different bank group ..................... 231 figure 176: nonconsecutive write (bl8) with 2 t ck preamble in same or different bank group ..................... 231 figure 177: write (bc4) otf to write (bc4) otf with 1 t ck preamble in different bank group .................... 232 figure 178: write (bc4) otf to write (bc4) otf with 2 t ck preamble in different bank group .................... 233 figure 179: write (bc4) fixed to write (bc4) fixed with 1 t ck preamble in different bank group ................. 233 figure 180: write (bl8) to write (bc4) otf with 1 t ck preamble in different bank group ............................ 234 figure 181: write (bc4) otf to write (bl8) with 1 t ck preamble in different bank group ............................ 235 figure 182: write (bl8) to read (bl8) with 1 t ck preamble in different bank group ..................................... 235 figure 183: write (bl8) to read (bl8) with 1 t ck preamble in same bank group .......................................... 236 figure 184: write (bc4) otf to read (bc4) otf with 1 t ck preamble in different bank group ...................... 237 figure 185: write (bc4) otf to read (bc4) otf with 1 t ck preamble in same bank group ........................... 237 figure 186: write (bc4) fixed to read (bc4) fixed with 1 t ck preamble in different bank group ................. 238 figure 187: write (bc4) fixed to read (bc4) fixed with 1 t ck preamble in same bank group ....................... 238 figure 188: write (bl8/bc4-otf) to precharge with 1 t ck preamble ........................................................ 239 figure 189: write (bc4-fixed) to precharge with 1 t ck preamble .............................................................. 240 figure 190: write (bl8/bc4-otf) to auto precharge with 1 t ck preamble ................................................ 240 figure 191: write (bc4-fixed) to auto precharge with 1 t ck preamble ...................................................... 241 figure 192: write (bl8/bc4-otf) with 1 t ck preamble and dbi ................................................................... 242 figure 193: write (bc4-fixed) with 1 t ck preamble and dbi ......................................................................... 243 figure 194: consecutive write (bl8) with 1 t ck preamble and ca parity in different bank group ..................... 244 figure 195: consecutive write (bl8/bc4-otf) with 1 t ck preamble and write crc in same or different bank group ............................................................................................................................... ........................ 245 figure 196: consecutive write (bc4-fixed) with 1 t ck preamble and write crc in same or different bank group ............................................................................................................................... ........................ 246 figure 197: nonconsecutive write (bl8/bc4-otf) with 1 t ck preamble and write crc in same or different bank group ............................................................................................................................... ................ 247 figure 198: nonconsecutive write (bl8/bc4-otf) with 2 t ck preamble and write crc in same or different bank group ............................................................................................................................... ................ 248 figure 199: write (bl8/bc4-otf/fixed) with 1 t ck preamble and write crc in same or different bank group ... 249 figure 200: zq calibration timing ................................................................................................................ 252 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 201: functional representation of odt .............................................................................................. 253 figure 202: synchronous odt timing with bl8 ............................................................................................. 256 figure 203: synchronous odt with bc4 ........................................................................................................ 256 figure 204: odt during reads ...................................................................................................................... 257 figure 205: dynamic odt (1 t ck preamble; cl = 14, cwl = 11, bl = 8, al = 0, crc disabled) .......................... 259 figure 206: dynamic odt overlapped with r tt(nom) (cl = 14, cwl = 11, bl = 8, al = 0, crc disabled) .......... 260 figure 207: asynchronous odt timings with dll off ................................................................................... 261 figure 208: v refdq voltage range .................................................................................................................. 264 figure 209: reset_n input slew rate definition ............................................................................................ 267 figure 210: single-ended input slew rate definition ..................................................................................... 269 figure 211: dq slew rate definitions ............................................................................................................ 272 figure 212: rx mask relative to t ds/ t dh ....................................................................................................... 274 figure 213: rx mask without write training .................................................................................................. 275 figure 214: ten input slew rate definition ................................................................................................... 276 figure 215: ct type-a input slew rate definition .......................................................................................... 276 figure 216: ct type-b input slew rate definition .......................................................................................... 277 figure 217: ct type-c input slew rate definition .......................................................................................... 278 figure 218: ct type-d input slew rate definition ......................................................................................... 278 figure 219: differential ac swing and time exceeding ac-level t dvac ....................................................... 279 figure 220: single-ended requirements for ck .............................................................................................. 281 figure 221: differential input slew rate definition for ck_t, ck_c .................................................................. 282 figure 222: v ix(ck) definition ........................................................................................................................ 282 figure 223: differential input signal definition for dqs_t, dqs_c .................................................................. 283 figure 224: dqs_t, dqs_c input peak voltage calculation and range of exempt non-monotonic signaling ..... 284 figure 225: v ixdqs definition ........................................................................................................................ 285 figure 226: differential input slew rate and input level definition for dqs_t, dqs_c ..................................... 286 figure 227: addr, cmd, cntl overshoot and undershoot definition ........................................................... 288 figure 228: ck overshoot and undershoot definition .................................................................................... 289 figure 229: data, strobe, and mask overshoot and undershoot definition ..................................................... 290 figure 230: single-ended output slew rate definition ................................................................................... 291 figure 231: differential output slew rate definition ...................................................................................... 293 figure 232: reference load for ac timing and output slew rate ................................................................... 294 figure 233: connectivity test mode reference test load ................................................................................ 294 figure 234: connectivity test mode output slew rate definition .................................................................... 295 figure 235: output driver during connectivity test mode ............................................................................. 296 figure 236: output driver: definition of voltages and currents ...................................................................... 297 figure 237: alert driver ............................................................................................................................... . 301 figure 238: odt definition of voltages and currents ..................................................................................... 302 figure 239: odt timing reference load ....................................................................................................... 303 figure 240: t adc definition with direct odt control .................................................................................... 305 figure 241: t adc definition with dynamic odt control ................................................................................ 305 figure 242: t aofas and t aonas definitions .................................................................................................. 306 figure 243: thermal measurement point ....................................................................................................... 312 figure 244: measurement setup and test load for i ddx , i ddpx , and i ddqx ........................................................ 314 figure 245: correlation: simulated channel i/o power to actual channel i/o power ....................................... 314 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
list of tables table 1: key timing parameters ....................................................................................................................... 1 table 2: addressing ............................................................................................................................... .......... 2 table 3: ball descriptions .............................................................................................................................. 25 table 4: state diagram command definitions ................................................................................................ 35 table 5: supply power-up slew rate ............................................................................................................... 37 table 6: address pin mapping ........................................................................................................................ 45 table 7: mr0 register definition .................................................................................................................... 45 table 8: burst type and burst order ............................................................................................................... 47 table 9: address pin mapping ........................................................................................................................ 49 table 10: mr1 register definition .................................................................................................................. 49 table 11: additive latency (al) settings ......................................................................................................... 51 table 12: tdqs function matrix .................................................................................................................... 52 table 13: address pin mapping ...................................................................................................................... 53 table 14: mr2 register definition .................................................................................................................. 53 table 15: address pin mapping ...................................................................................................................... 56 table 16: mr3 register definition .................................................................................................................. 56 table 17: address pin mapping ...................................................................................................................... 59 table 18: mr4 register definition .................................................................................................................. 59 table 19: address pin mapping ...................................................................................................................... 63 table 20: mr5 register definition .................................................................................................................. 63 table 21: address pin mapping ...................................................................................................................... 66 table 22: mr6 register definition .................................................................................................................. 66 table 23: truth table C command .................................................................................................................. 68 table 24: truth table C cke ........................................................................................................................... 70 table 25: mr settings for leveling procedures ................................................................................................ 78 table 26: dram termination function in leveling mode ........................................................................... 78 table 27: auto self refresh mode ................................................................................................................... 87 table 28: mr3 setting for the mpr access mode ............................................................................................. 89 table 29: dram address to mpr ui translation ............................................................................................. 89 table 30: mpr page and mpr x definitions ..................................................................................................... 90 table 31: mpr readout serial format ............................................................................................................. 92 table 32: mpr readout C parallel format ....................................................................................................... 93 table 33: mpr readout staggered format, x4 ................................................................................................. 94 table 34: mpr readout staggered format, x4 C consecutive reads ................................................................ 94 table 35: mpr readout staggered format, x8 and x16 ..................................................................................... 95 table 36: mode register setting for ca parity ................................................................................................. 110 table 37: v refdq range and levels ................................................................................................................ 120 table 38: v refdq settings (v ddq = 1.2v) ......................................................................................................... 126 table 39: connectivity mode pin description and switching levels ................................................................ 128 table 40: mac encoding of mpr page 3 mpr3 ............................................................................................... 131 table 41: ppr mr0 guard key settings .......................................................................................................... 133 table 42: ddr4 hppr timing parameters ddr4-1600 through ddr4-3200 ..................................................... 137 table 43: sppr associated rows .................................................................................................................... 137 table 44: ppr mr0 guard key settings .......................................................................................................... 138 table 45: ddr4 sppr timing parameters ddr4-1600 through ddr4-3200 ..................................................... 139 table 46: ddr4 repair mode support identifier ............................................................................................ 140 table 47: normal t refi refresh (tcr disabled) ............................................................................................. 144 table 48: normal t refi refresh (tcr enabled) .............................................................................................. 145 table 49: mrs definition .............................................................................................................................. 146 table 50: refresh command truth table .................................................................................................... 146 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 51: t refi and t rfc parameters ............................................................................................................. 147 table 52: power-down entry definitions ....................................................................................................... 156 table 53: crc error detection coverage ........................................................................................................ 167 table 54: crc data mapping for x4 devices, bl8 ........................................................................................... 169 table 55: crc data mapping for x8 devices, bl8 ........................................................................................... 169 table 56: crc data mapping for x16 devices, bl8 ......................................................................................... 170 table 57: crc data mapping for x4 devices, bc4 ........................................................................................... 170 table 58: crc data mapping for x8 devices, bc4 ........................................................................................... 171 table 59: crc data mapping for x16 devices, bc4 ......................................................................................... 172 table 60: dbi vs. dm vs. tdqs function matrix ............................................................................................. 177 table 61: dbi write, dq frame format (x8) ................................................................................................... 177 table 62: dbi write, dq frame format (x16) ................................................................................................. 177 table 63: dbi read, dq frame format (x8) .................................................................................................... 178 table 64: dbi read, dq frame format (x16) .................................................................................................. 178 table 65: dm vs. tdqs vs. dbi function matrix ............................................................................................. 179 table 66: data mask, dq frame format (x8) .................................................................................................. 179 table 67: data mask, dq frame format (x16) ................................................................................................ 179 table 68: cwl selection ............................................................................................................................... 182 table 69: ddr4 bank group timing examples .............................................................................................. 187 table 70: read to write and write to read command intervals ....................................................................... 192 table 71: termination state table ................................................................................................................. 254 table 72: read termination disable window ................................................................................................. 254 table 73: odt latency at ddr4-1600/-1866/-2133/-2400/-2666/-3200 .......................................................... 255 table 74: dynamic odt latencies and timing (1 t ck preamble mode and crc disabled) ................................ 258 table 75: dynamic odt latencies and timing with preamble mode and crc mode matrix ............................ 259 table 76: absolute maximum ratings ............................................................................................................ 262 table 77: temperature range ........................................................................................................................ 262 table 78: recommended supply operating conditions .................................................................................. 263 table 79: v dd slew rate ............................................................................................................................... . 263 table 80: leakages ............................................................................................................................... ........ 264 table 81: v refdq specification ...................................................................................................................... 265 table 82: v refdq range and levels ................................................................................................................ 266 table 83: reset_n input levels (cmos) ....................................................................................................... 267 table 84: command and address input levels: ddr4-1600 through ddr4-2400 ........................................... 267 table 85: command and address input levels: ddr4-2666 ............................................................................ 268 table 86: command and address input levels: ddr4-2933 and ddr4-3200 ................................................... 268 table 87: single-ended input slew rates ....................................................................................................... 269 table 88: command and address setup and hold values referenced C ac/dc-based ..................................... 270 table 89: derating values for t is/ t ih C ac100dc75-based .............................................................................. 270 table 90: derating values for t is/ t ih C ac90/dc65-based .............................................................................. 271 table 91: dq input receiver specifications .................................................................................................... 272 table 92: rx mask and t ds/ t dh without write training .................................................................................. 275 table 93: ten input levels (cmos) .............................................................................................................. 275 table 94: ct type-a input levels .................................................................................................................. 276 table 95: ct type-b input levels .................................................................................................................. 277 table 96: ct type-c input levels (cmos) ..................................................................................................... 277 table 97: ct type-d input levels .................................................................................................................. 278 table 98: differential input swing requirements for ck_t, ck_c ..................................................................... 279 table 99: minimum time ac time t dvac for ck ........................................................................................... 280 table 100: single-ended requirements for ck ............................................................................................... 281 table 101: ck differential input slew rate definition ..................................................................................... 281 table 102: cross point voltage for ck differential input signals at ddr4-1600 through ddr4-2400 ................ 283 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 103: cross point voltage for ck differential input signals at ddr4-2666 through ddr4-3200 ................ 283 table 104: ddr4-1600 through ddr4-2400 differential input swing requirements for dqs_t, dqs_c ............. 284 table 105: ddr4-2633 through ddr4-3200 differential input swing requirements for dqs_t, dqs_c ............. 284 table 106: cross point voltage for differential input signals dqs ................................................................... 285 table 107: dqs differential input slew rate definition .................................................................................. 286 table 108: ddr4-1600 through ddr4-2400 differential input slew rate and input levels for dqs_t, dqs_c ... 286 table 109: ddr4-2666 through ddr4-3200 differential input slew rate and input levels for dqs_t, dqs_c ... 287 table 110: addr, cmd, cntl overshoot and undershoot/specifications ...................................................... 288 table 111: ck overshoot and undershoot/ specifications .............................................................................. 289 table 112: data, strobe, and mask overshoot and undershoot/ specifications ................................................ 290 table 113: single-ended output levels ......................................................................................................... 290 table 114: single-ended output slew rate definition .................................................................................... 291 table 115: single-ended output slew rate .................................................................................................... 292 table 116: differential output levels ............................................................................................................. 292 table 117: differential output slew rate definition ....................................................................................... 292 table 118: differential output slew rate ....................................................................................................... 293 table 119: connectivity test mode output levels .......................................................................................... 294 table 120: connectivity test mode output slew rate ..................................................................................... 295 table 121: output driver electrical characteristics during connectivity test mode ......................................... 297 table 122: strong mode (34 ) output driver electrical characteristics ........................................................... 298 table 123: weak mode (48 ) output driver electrical characteristics ............................................................. 299 table 124: output driver sensitivity definitions ............................................................................................ 300 table 125: output driver voltage and temperature sensitivity ....................................................................... 300 table 126: alert driver voltage ...................................................................................................................... 301 table 127: odt dc characteristics ............................................................................................................... 302 table 128: odt sensitivity definitions .......................................................................................................... 303 table 129: odt voltage and temperature sensitivity ..................................................................................... 303 table 130: odt timing definitions ............................................................................................................... 304 table 131: reference settings for odt timing measurements ........................................................................ 304 table 132: dram package electrical specifications for x4 and x8 devices ....................................................... 307 table 133: dram package electrical specifications for x16 devices ................................................................ 308 table 134: pad input/output capacitance ..................................................................................................... 310 table 135: thermal characteristics ............................................................................................................... 311 table 136: basic i dd , i pp , and i ddq measurement conditions .......................................................................... 314 table 137: i dd0 and i pp0 measurement-loop pattern 1 .................................................................................... 318 table 138: i dd1 measurement C loop pattern 1 ............................................................................................... 319 table 139: i dd2n , i dd3n , and i pp3p measurement C loop pattern 1 .................................................................... 320 table 140: i dd2nt and i ddq2nt measurement C loop pattern 1 ......................................................................... 321 table 141: i dd4r measurement C loop pattern 1 .............................................................................................. 322 table 142: i dd4w measurement C loop pattern 1 ............................................................................................. 323 table 143: i dd4wc measurement C loop pattern 1 ............................................................................................ 324 table 144: i dd5r measurement C loop pattern 1 .............................................................................................. 325 table 145: i dd7 measurement C loop pattern 1 ............................................................................................... 326 table 146: timings used for i dd , i pp , and i ddq measurement C loop patterns .................................................. 327 table 147: i dd , i pp , and i ddq current limits; die rev. a .................................................................................. 328 table 148: i dd , i pp , and i ddq current limits; die rev. b .................................................................................. 330 table 149: i dd , i pp , and i ddq current limits; die rev. d .................................................................................. 332 table 150: i dd , i pp , and i ddq current limits; die rev. e, g, h .......................................................................... 334 table 151: ddr4-1600 speed bins and operating conditions ......................................................................... 338 table 152: ddr4-1866 speed bins and operating conditions ......................................................................... 339 table 153: ddr4-2133 speed bins and operating conditions ......................................................................... 340 table 154: ddr4-2400 speed bins and operating conditions ......................................................................... 341 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 155: ddr4-2666 speed bins and operating conditions ......................................................................... 342 table 156: ddr4-2933 speed bins and operating conditions ......................................................................... 343 table 157: ddr4-3200 speed bins and operating conditions ......................................................................... 345 table 158: refresh parameters by device density ........................................................................................... 346 table 159: electrical characteristics and ac timing parameters: ddr4-1600 through ddr4-2400 ................... 347 table 160: electrical characteristics and ac timing parameters ..................................................................... 359 table 161: options - speed based .................................................................................................................. 372 table 162: options - width based .................................................................................................................. 373 8gb: x4, x8, x16 ddr4 sdram features 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
general notes and description description the ddr4 sdram is a high-speed dynamic random-access memory internally config- ured as an eight-bank dram for the x16 configuration and as a 16-bank dram for the x4 and x8 configurations. the ddr4 sdram uses an 8 n -prefetch architecture to ach- ieve high-speed operation. the 8 n -prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write operation for the ddr4 sdram consists of a single 8 n-bit wide, four-clock data transfer at the internal dram core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the i/o pins. industrial temperature an industrial temperature (it) device option requires that the case temperature not ex- ceed below C40c or above 95c. jedec specifications require the refresh rate to double when t c exceeds 85c; this also requires use of the high-temperature self refresh option. additionally, odt resistance and the input/output impedance must be derated when operating outside of the commercial temperature range, when t c is between C40c and 0c. general notes ? the functionality and the timing specifications discussed in this data sheet are for the dll enable mode of operation (normal operation), unless specifically stated other- wise. ? throughout the data sheet, the various figures and text refer to dqs as "dq." the dq term is to be interpreted as any and all dq collectively, unless specifically stated oth- erwise. ? the terms "_t" and "_c" are used to represent the true and complement of a differen- tial signal pair. these terms replace the previously used notation of "#" and/or over- bar characters. for example, differential data strobe pair dqs, dqs# is now referred to as dqs_t, dqs_c. ? the term "_n" is used to represent a signal that is active low and replaces the previ- ously used "#" and/or overbar characters. for example: cs# is now referred to as cs_n. ? the terms "dqs" and "ck" found throughout the data sheet are to be interpreted as dqs_t, dqs_c and ck_t, ck_c respectively, unless specifically stated otherwise. ? complete functionality may be described throughout the entire document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. ? any specific requirement takes precedence over a general statement. ? any functionality not specifically stated here within is considered undefined, illegal, and not supported, and can result in unknown operation. ? addressing is denoted as bg[ n ] for bank group, ba[n ] for bank address, and a[n] for row/col address. ? the nop command is not allowed, except when exiting maximum power savings mode or when entering gear-down mode, and only a des command should be used. 8gb: x4, x8, x16 ddr4 sdram general notes and description 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
? not all features described within this document may be available on the rev. a (first) version. ? not all specifications listed are finalized industry standards; best conservative esti- mates have been provided when an industry standard has not been finalized. ? although it is implied throughout the specification, the dram must be used after v dd has reached the stable power-on level, which is achieved by toggling cke at least once every 8192 t refi. however, in the event cke is fixed high, toggling cs_n at least once every 8192 t refi is an acceptable alternative. placing the dram into self re- fresh mode also alleviates the need to toggle cke. ? not all features designated in the data sheet may be supported by earlier die revisions due to late definition by jedec. definitions of the device-pin signal level ? high: a device pin is driving the logic 1 state. ? low: a device pin is driving the logic 0 state. ? high-z: a device pin is tri-state. ? odt: a device pin terminates with the odt setting, which could be terminating or tri- state depending on the mode register setting. definitions of the bus signal level ? high: one device on the bus is high, and all other devices on the bus are either odt or high-z. the voltage level on the bus is nominally v ddq . ? low: one device on the bus is low, and all other devices on the bus are either odt or high-z. the voltage level on the bus is nominally v ol(dc) if odt was enabled, or v ssq if high-z. ? high-z: all devices on the bus are high-z. the voltage level on the bus is undefined as the bus is floating. ? odt: at least one device on the bus is odt, and all others are high-z. the voltage lev- el on the bus is nominally v ddq . ? the specification requires 8,192 refresh commands within 64ms between 0 o c and 85 o c. this allows for a t refi of 7.8125s (the use of "7.8s" is truncated from 7.8125s). the specification also requires 8,192 refresh commands within 32ms between 85 o c and 95 o c. this allows for a t refi of 3.90625s (the use of "3.9s" is truncated from 3.90625s). 8gb: x4, x8, x16 ddr4 sdram general notes and description 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
functional block diagrams ddr4 sdram is a high-speed, cmos dynamic random access memory. it is internally configured as an 16-bank (4-banks per bank group) dram. figure 2: 2 gig x 4 functional block diagram 6hqvhdpsolilhuv '46bw'46bf &roxpqv dqg 5hdg gulyhuv '4>@ 5($' ),)2 dqg gdwd 08; &roxpqvdqg '%,bq '0bq =4 '46bw '46bf &.bw&.bf '// &.bw&.bf &5& '4>@ %& %& '%, :ulwh gulyhuv dqg lqsxw orjlf 'dwd lqwhuidfh &roxpq %&qleeoh 5rz dgguhvv 08; %* dqg %$ frqwuro orjlf 2'7 frqwuro 9uhi'4 =4 frqwuro &5&dqg sdulw\frqwuro 27) &rqwuro orjlf 0rghuhjlvwhuv $>@ %$>@ %*>@ $$$ $$ 5hiuhvk frxqwhu 7r2'7rxwsxwgulyhuv 7r=4&rqwuro =4&$/ &.( &.bw&.bf 3$5 7(1 &rppdqgghfrgh 5$6bq&$6bq:(bq &6bq $&7bq 5(6(7bq %& 9uhi'4 $gguhvv uhjlvwhu 27) &5& 3dulw\ 9 ''4 5 77z 5 77q 5 77s %dqn %* %dqn %dqn %dqn %dqn %* %dqn %dqn %dqn %dqn %* %dqn %dqn %dqn %dqn %* %dqn %dqn %dqn [ 6hqvhdpsolilhuv huv %dqn %dqn %dqn %dqn %dqn %dqn [ ,2jdwlqj '0pdvnorjlf &roxpq ghfrghu %dqn %dqn*urxs %dqn %dqn*urxs %dqn %dqn*urxs %dqn %dqn %dqn %dqn %dqn %dqn [ *oredo ,2jdwlqj 5rz dgguhvv odwfk dqg ghfrghu &roxpq dgguhvv frxqwhu odwfk 9 ''4 9 ''4 5 77z 5 77q 5 77s 9 ''4 5 77z 5 77q 5 77s $/(57 2'7 6hqvhdpsolilhuv %dqn %dqn*urxs 0hpru\ duud\ [[ 6hqvhdpsolilhuv %dqn %dqn %dqn figure 3: 1 gig x 8 functional block diagram 6hqvhdpsolilhuv '46bw'46bf &roxpqv dqg 5hdg gulyhuv '4>@ 5($' ),)2 dqg gdwd 08; &roxpqvdqg '%,bq '0bq 7'46bw =4 7'46bf '46bw '46bf &.bw&.bf '// &.bw&.bf &5& '4>@ %& %& '%, :ulwh gulyhuv dqg lqsxw orjlf 'dwd lqwhuidfh &roxpq %&qleeoh 5rz dgguhvv 08; %* dqg %$ frqwuro orjlf 2'7 frqwuro 9uhi'4 =4 frqwuro &5&dqg sdulw\frqwuro 27) &rqwuro orjlf 0rghuhjlvwhuv $>@ %$>@ %*>@ $$$ $$ 5hiuhvk frxqwhu 7r2'7rxwsxwgulyhuv 7r=4&rqwuro =4&$/ &.( &.bw&.bf 3$5 7(1 &rppdqgghfrgh 5$6bq&$6bq:(bq &6bq $&7bq 5(6(7bq %& 9uhi'4 $gguhvv uhjlvwhu 27) &5& 3dulw\ 9 ''4 5 77z 5 77q 5 77s %dqn %* %dqn %dqn %dqn %dqn %* %dqn %dqn %dqn %dqn %* %dqn %dqn %dqn %dqn %* %dqn %dqn %dqn [ 6hqvhdpsolilhuv huv %dqn %dqn %dqn %dqn %dqn %dqn [ ,2jdwlqj '0pdvnorjlf &roxpq ghfrghu %dqn %dqn*urxs %dqn %dqn*urxs %dqn %dqn*urxs %dqn %dqn %dqn %dqn %dqn %dqn [ *oredo ,2jdwlqj 5rz dgguhvv odwfk dqg ghfrghu &roxpq dgguhvv frxqwhu odwfk 9 ''4 9 ''4 5 77z 5 77q 5 77s 9 ''4 5 77z 5 77q 5 77s $/(57 2'7 6hqvhdpsolilhuv %dqn %dqn*urxs 0hpru\ duud\ [[ 6hqvhdpsolilhuv %dqn %dqn %dqn 8gb: x4, x8, x16 ddr4 sdram functional block diagrams 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 4: 512 meg x 16 functional block diagram /'46bw/'46bf8'46bw8'46bf &roxpqv dqg 5hdg gulyhuv '4>@ '4>@ 5($' ),)2 dqg gdwd 08; &roxpqvdqg 8'%,bq 8'0bq /'%,bq /'0bq =4 8'46bw 8'46bf /'46bw /'46bf &.bw&.bf '// &.bw&.bf &5& '4>@ %& %& '%, :ulwh gulyhuv dqg lqsxw orjlf 'dwd lqwhuidfh &roxpq %&qleeoh 5rz dgguhvv 08; %* dqg %$ frqwuro orjlf 2'7 frqwuro 9uhi'4 =4 frqwuro &5&dqg sdulw\frqwuro 27) &rqwuro orjlf 0rghuhjlvwhuv $>@ %$>@ %*>@ $$$ $$ 5hiuhvk frxqwhu 7r2'7rxwsxwgulyhuv 7r=4&rqwuro =4&$/ &.( &.bw&.bf 3$5 7(1 &rppdqgghfrgh 5$6bq&$6bq:(bq &6bq $&7bq 5(6(7bq %& 9uhi'4 $gguhvv uhjlvwhu 27) &5& 3dulw\ 9 ''4 5 77z 5 77q 5 77s %dqn %* %dqn %dqn %dqn %dqn %* %dqn %dqn %dqn [ ,2jdwlqj '0pdvnorjlf &roxpq ghfrghu %dqn %dqn*urxs %dqn %dqn %dqn %dqn %dqn %dqn [ *oredo ,2jdwlqj 5rz dgguhvv odwfk dqg ghfrghu &roxpq dgguhvv frxqwhu odwfk 9 ''4 9 ''4 5 77z 5 77q 5 77s 9 ''4 5 77z 5 77q 5 77s $/(57 2'7 6hqvhdpsolilhuv %dqn %dqn*urxs 0hpru\ duud\ [[ 6hqvhdpsolilhuv %dqn %dqn %dqn 8gb: x4, x8, x16 ddr4 sdram functional block diagrams 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
ball assignments figure 5: 78-ball x4, x8 ball assignments 2 v ssq v ddq dq0 dq4/nc v ddq c2/odt1 c0/cke1 we_n/a14 bg0 ba0 a6 a8 a11 3 nf, nf/ tdqs_c dqs_c dqs_t dq2 dq6/nc odt cke act_n a10/ap a4 a0 a2 par 467 nf, nf/dm_n/ dbi_n/tdqs_t dq1 v dd dq3 dq7/nc ck_t cs_n cas_n/ a15 a12/bc_n a3 a1 a9 a17/nf 8 v ssq v ddq v ss dq5/nc v ddq ck_c c1/cs1_n ras_n/a16 bg1 ba1 a5 a7 a13 9 v ss zq v ddq v ssq v ss v dd rfu/ten v ss v dd v ss alert_n v pp v dd 5 a b c d e f g h j k l m n a b c d e f g h j k l m n 1 v dd v pp v ddq v ssq v ss v dd v ss v dd v refca v ss reset_n v dd v ss notes: 1. see ball descriptions. 2. a comma , separates the configuration; a slash / defines a selectable function. for example: ball a7 = nf, nf/dm_n/dbi_n/tdqs_t where nf applies to the x4 configuration only. nf/dm_n/dbi_n/tdqs_t applies to the x8 configuration only and is selectable be- tween nf, dm_n, dbi_n, or tdqs_t via mrs. 3. address bits (including bank groups) are density- and configuration-dependent (see ad- dressing). 8gb: x4, x8, x16 ddr4 sdram ball assignments 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 6: 96-ball x16 ball assignments 123 4 6789 5 v ddq v pp v ddq v dd v ss v ssq v ddq v ssq v dd v ss v dd v refca v ss reset_n v dd v ss v ssq v ss dq12 v ssq v ddq dq0 dq4 v ddq cke we_n/a14 bg0 ba0 a6 a8 a11 dq8 v dd dq10 dq14 v ssq ldqs_c ldqs_t dq2 dq6 odt act_n a10/ap a4 a0 a2 par udqs_c udqs_t dq11 dq15 dq1 v dd dq3 dq7 ck_t cs_n a12/bc_n a3 a1 a9 nc v ssq dq9 dq13 v ssq v ssq v ddq v ss dq5 v ddq ck_c ras_n/a16 cas-n/a15 ba1 a5 a7 a13 v ddq v dd v ssq v ddq v ss zq v ddq v ssq v dd v ss v dd v ss ten v pp v dd a b c d e f g h j k l m n p r t a b c d e f g h j k l m n p r t nf/ldm_n/ ldbi_n alert_n nf/udm_n/ udbi_n notes: 1. see ball descriptions. 2. a slash / defines a selectable function. for example: ball e7 = nf/ldm_n. if data mask is enabled via the mrs, ball e7 = ldm_n. if data mask is disabled in the mrs, e7 = nf (no function). 3. address bits (including bank groups) are density- and configuration-dependent (see ad- dressing). 8gb: x4, x8, x16 ddr4 sdram ball assignments 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
ball descriptions the pin description table below is a comprehensive list of all possible pins for ddr4 de- vices. all pins listed may not be supported on the device defined in this data sheet. see the ball assignments section to review all pins used on this device. table 3: ball descriptions symbol type description a[17:0] input address inputs: provide the row address for activate commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (a10/ap, a12/bc_n, we_n/a14, cas_n/a15, ras_n/a16 have addi- tional functions, see individual entries in this table.) the address inputs also provide the op-code during the mode register set command. a16 is used on some 8gb and 16gb parts, and a17 is only used on some 16gb parts. a10/ap input auto precharge: a10 is sampled during read and write commands to determine whether auto precharge should be performed to the accessed bank after a read or write operation. (high = auto precharge; low = no auto precharge.) a10 is sam- pled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by the bank group and bank addresses. a12/bc_n input burst chop: a12/bc_n is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (high = no burst chop; low = burst chop- ped). see the command truth table. act_n input command input: act_n indicates an activate command. when act_n (along with cs_n) is low, the input pins ras_n/a16, cas_n/a15, and we_n/a14 are treated as row address inputs for the activate command. when act_n is high (along with cs_n low), the input pins ras_n/ a16, cas_n/a15, and we_n/a14 are treated as nor- mal commands that use the ras_n, cas_n, and we_n signals. see the command truth table. ba[1:0] input bank address inputs: define the bank (within a bank group) to which an activate, read, write, or precharge command is being applied. also determines which mode register is to be accessed during a mode register set command. bg[1:0] input bank group address inputs: define the bank group to which a refresh, activate, read, write, or precharge command is being applied. also determines which mode register is to be accessed during a mode register set command. bg[1:0] are used in the x4 and x8 configurations. bg1 is not used in the x16 configuration. c0/cke1, c1/cs1_n, c2/odt1 input stack address inputs: these inputs are used only when devices are stacked; that is, they are used in 2h, 4h, and 8h stacks for x4 and x8 configurations (these pins are not used in the x16 configuration). ddr4 will support a traditional ddp package, which uses these three signals for control of the second die (cs1_n, cke1, odt1). ddr4 is not expected to support a traditional qdp package. for all other stack con- figurations, such as a 4h or 8h, it is assumed to be a single-load (master/slave) type of configuration where c0, c1, and c2 are used as chip id selects in conjunction with a single cs_n, cke, and odt signal. ck_t, ck_c input clock: differential clock inputs. all address, command, and control input signals are sampled on the crossing of the positive edge of ck_t and the negative edge of ck_c. 8gb: x4, x8, x16 ddr4 sdram ball descriptions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 3: ball descriptions (continued) symbol type description cke input clock enable: cke high activates and cke low deactivates the internal clock sig- nals, device input buffers, and output drivers. taking cke low provides precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is asynchronous for self refresh exit. after v refca has become stable during the power-on and initialization sequence, it must be main- tained during all operations (including self refresh). cke must be maintained high throughout read and write accesses. input buffers (excluding ck_t, ck_c, odt, re- set_n, and cke) are disabled during power-down. input buffers (excluding cke and reset_n) are disabled during self refresh. cs_n input chip select: all commands are masked when cs_n is registered high. cs_n provides for external rank selection on systems with multiple ranks. cs_n is considered part of the command code. dm_n, udm_n ldm_n input input data mask: dm_n is an input mask signal for write data. input data is masked when dm is sampled low coincident with that input data during a write access. dm is sampled on both edges of dqs. dm is not supported on x4 configurations. the udm_n and ldm_n pins are used in the x16 configuration: udm_n is associated with dq[15:8]; ldm_n is associated with dq[7:0]. the dm, dbi, and tdqs functions are en- abled by mode register settings. see the data mask section. odt input on-die termination: odt (registered high) enables termination resistance internal to the ddr4 sdram. when enabled, odt (r tt ) is applied only to each dq, dqs_t, dqs_c, dm_n/dbi_n/tdqs_t, and tdqs_c signal for the x4 and x8 configurations (when the tdqs function is enabled via mode register). for the x16 configuration, r tt is applied to each dq, dqsu_t, dqsu_c, dqsl_t, dqsl_c, udm_n, and ldm_n signal. the odt pin will be ignored if the mode registers are programmed to disable r tt . par input parity for command and address: this function can be enabled or disabled via the mode register. when enabled, the parity signal covers all command and address in- puts, including act_n, ras_n/a16, cas_n/a15, we_n/a14, a[17:0], a10/ap, a12/bc_n, ba[1:0], and bg[1:0] with c0, c1, and c2 on 3ds only devices. control pins not cov- ered by the parity signal are cs_n, cke, and odt. unused address pins that are densi- ty- and configuration-specific should be treated internally as 0s by the dram parity logic. command and address inputs will have parity check performed when com- mands are latched via the rising edge of ck_t and when cs_n is low. ras_n/a16, cas_n/a15, we_n/a14 input command inputs: ras_n/a16, cas_n/a15, and we_n/a14 (along with cs_n and act_n) define the command and/or address being entered. see the act_n descrip- tion in this table. reset_n input active low asynchronous reset: reset is active when reset_n is low, and inac- tive when reset_n is high. reset_n must be high during normal operation. reset_n is a cmos rail-to-rail signal with dc high and low at 80% and 20% of v dd (960 mv for dc high and 240 mv for dc low). ten input connectivity test mode: ten is active when high and inactive when low. ten must be low during normal operation. ten is a cmos rail-to-rail signal with dc high and low at 80% and 20% of v dd (960mv for dc high and 240mv for dc low). 8gb: x4, x8, x16 ddr4 sdram ball descriptions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 3: ball descriptions (continued) symbol type description dq i/o data input/output: bidirectional data bus. dq represents dq[3:0], dq[7:0], and dq[15:0] for the x4, x8, and x16 configurations, respectively. if write crc is enabled via mode register, the write crc code is added at the end of data burst. any one or all of dq0, dq1, dq2, and dq3 may be used to monitor the internal v ref level during test via mode register setting mr[4] a[4] = high, training times change when ena- bled. during this mode, the r tt value should be set to high-z. this measurement is for verification purposes and is not an external voltage supply pin. dbi_n, udbi_n, ldbi_n i/o dbi input/output: data bus inversion. dbi_n is an input/output signal used for data bus inversion in the x8 configuration. udbi_n and ldbi_n are used in the x16 configu- ration; udbi_n is associated with dq[15:8], and ldbi_n is associated with dq[7:0]. the dbi feature is not supported on the x4 configuration. dbi can be configured for both read (output) and write (input) operations depending on the mode register set- tings. the dm, dbi, and tdqs functions are enabled by mode register settings. see the data bus inversion section. dqs_t, dqs_c, dqsu_t, dqsu_c, dqsl_t, dqsl_c i/o data strobe: output with read data, input with write data. edge-aligned with read data, centered-aligned with write data. for the x16, dqsl corresponds to the data on dq[7:0]; dqsu corresponds to the data on dq[15:8]. for the x4 and x8 con- figurations, dqs corresponds to the data on dq[3:0] and dq[7:0], respectively. ddr4 sdram supports a differential data strobe only and does not support a single-ended data strobe. alert_n output alert output: this signal allows the dram to indicate to the system's memory con- troller that a specific alert or event has occurred. alerts will include the command/ address parity error and the crc data error when either of these functions is enabled in the mode register. tdqs_t, tdqs_c output termination data strobe: tdqs_t and tdqs_c are used by x8 drams only. when enabled via the mode register, the dram will enable the same r tt termination resist- ance on tdqs_t and tdqs_c that is applied to dqs_t and dqs_c. when the tdqs function is disabled via the mode register, the dm/tdqs_t pin will provide the data mask (dm) function, and the tdqs_c pin is not used. the tdqs function must be dis- abled in the mode register for both the x4 and x16 configurations. the dm function is supported only in x8 and x16 configurations. v dd supply power supply: 1.2v 0.060v. v ddq supply dq power supply: 1.2v 0.060v. v pp supply dram activating power supply: 2.5v C0.125v/+0.250v. v refca supply reference voltage for control, command, and address pins. v ss supply ground. v ssq supply dq ground. zq reference reference ball for zq calibration: this ball is tied to an external 240 resistor (rzq), which is tied to v ssq . rfu C reserved for future use. nc C no connect: no internal electrical connection is present. nf C no function: may have internal connection present but has no function. 8gb: x4, x8, x16 ddr4 sdram ball descriptions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
package dimensions figure 7: 78-ball fbga C x4, x8 (pm) 1.8 ctr nonconductive overmold 0.155 seating plane 0.12 a ball a1 id (covered by sr) ball a1 id a 0.28 min 1.1 0.1 6.4 ctr 9 0.1 0.8 typ 9.6 ctr 13.2 0.1 78x ?0.47 dimensions apply to solder balls post-reflow on ?0.42 smd ball pads. 0.8 typ 123 789 a b c d e f g h j k l m n notes: 1. all dimensions are in millimeters. 2. solder ball material: sac302 (96.8% sn, 3% ag, 0.2% cu). 8gb: x4, x8, x16 ddr4 sdram package dimensions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 8: 78-ball fbga C x4, x8 (we) 1.8 ctr nonconductive overmold 0.155 seating plane 0.12 a ball a1 id (covered by sr) ball a1 id a 0.34 0.05 1.1 0.1 6.4 ctr 8 0.1 0.8 typ 9.6 ctr 12 0.1 78x ?0.47 dimensions apply to solder balls post- reflow on ?0.42 smd ball pads. 0.8 typ 1 23 789 a b c d e f g h j k l m n notes: 1. all dimensions are in millimeters. 2. solder ball material: sac302 (96.8% sn, 3% ag, 0.2% cu). 8gb: x4, x8, x16 ddr4 sdram package dimensions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 9: 78-ball fbga C x4, x8 (sa) 1.8 ctr nonconductive overmold 0.155 seating plane 0.12 a a ball a1 id (covered by sr) ball a1 id 0.34 0.05 1.1 0.1 6.4 ctr 7.5 0.1 0.8 typ 9.6 ctr 11 0.1 78x ?0.47 dimensions apply to solder balls post- reflow on ?0.42 smd ball pads. 0.8 typ 123 789 a b c d e f g h j k l m n notes: 1. all dimensions are in millimeters. 2. solder ball material: sac302 (96.8% sn, 3% ag, 0.2% cu). 8gb: x4, x8, x16 ddr4 sdram package dimensions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 10: 96-ball fbga C x16 (ha) 1.8 ctr nonconductive overmold 0.155 seating plane 0.12 a ball a1 id (covered by sr) ball a1 id a 0.29 min 1.1 0.1 6.4 ctr 9 0.1 0.8 typ 12 ctr 14 0.1 96x ?0.47 dimensions apply to solder balls post- reflow on ?0.42 smd ball pads. 0.8 typ 123 789 a b c d e f g h j k l m n p r t notes: 1. all dimensions are in millimeters. 2. solder ball material: sac302 (96.8% sn, 3% ag, 0.2% cu). 8gb: x4, x8, x16 ddr4 sdram package dimensions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 11: 96-ball fbga C x16 (jy) 1.8 ctr nonconductive overmold 0.155 seating plane 0.12 a ball a1 id (covered by sr) ball a1 id 0.34 0.05 1.1 0.1 6.4 ctr 8 0.1 0.8 typ 12 ctr 14 0.1 96x ?0.47 dimensions apply to solder balls post- reflow on ?0.42 smd ball pads. 0.8 typ 123 789 a b c d e f g h j k l m n p r t a notes: 1. all dimensions are in millimeters. 2. solder ball material: sac302 (96.8% sn, 3% ag, 0.2% cu). 8gb: x4, x8, x16 ddr4 sdram package dimensions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 12: 96-ball fbga C x16 (ly) seating plane 0.12 a ball a1 id (covered by sr) ball a1 id a 0.34 0.05 1.1 0.1 6.4 ctr 7.5 0.1 0.8 typ 12 ctr 13.5 0.1 96x ?0.47 dimensions apply to solder balls post- reflow on ?0.42 smd ball pads. 0.8 typ 1.8 ctr nonconductive overmold 0.155 123 789 a b c d e f g h j k l m n p r t notes: 1. all dimensions are in millimeters. 2. solder ball material: sac302 (96.8% sn, 3% ag, 0.2% cu). 8gb: x4, x8, x16 ddr4 sdram package dimensions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
state diagram this simplified state diagram provides an overview of the possible state transitions and the commands to control them. situations involving more than one bank, the enabling or disabling of on-die termination, and some other events are not captured in full de- tail. figure 13: simplified state diagram bank active reading writing activating refreshing self refresh idle active power- down zq calibration power from any state applied reset procedure power-on initialization mrs, mpr, write leveling, v refdq training precharge power- down writing reading automatic sequence command sequence precharging read read read read a read a read a pre, prea pre, prea pre, prea write write write write a write a write a pde pde pdx pdx srx sre ref act zqcl zqcl,zqcs cke_l cke_l cke_l mpsm pda mode iv refdq , r tt , and so on connectivity test reset reset reset ten = 0 mrs mrs srx* srx* srx* = srx with nop mrs mrs mrs mrs ten = 1 ten = 1 8gb: x4, x8, x16 ddr4 sdram state diagram 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 4: state diagram command definitions command description act active mpr multipurpose register mrs mode register set pde enter power-down pdx exit power-down pre precharge prea precharge all read rd, rds4, rds8 read a rda, rdas4, rdas8 ref refresh, fine granularity refresh reset start reset procedure sre self refresh entry srx self refresh exit ten boundary scan mode enable write wr, wrs4, wrs8 with/without crc write a wra, wras4, wras8 with/without crc zqcl zq calibration long zqcs zq calibration short note: 1. see the command truth table for more details. 8gb: x4, x8, x16 ddr4 sdram state diagram 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
functional description the ddr4 sdram is a high-speed dynamic random-access memory internally config- ured as sixteen banks (4 bank groups with 4 banks for each bank group) for x4/x8 devi- ces, and as eight banks for each bank group (2 bank groups with 4 banks each) for x16 devices. the device uses double data rate (ddr) architecture to achieve high-speed op- eration. ddr4 architecture is essentially an 8 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for a device module effectively consists of a single 8 n -bit-wide, four-clock- cycle-data transfer at the internal dram core and eight corresponding n -bit-wide, one- half-clock-cycle data transfers at the i/o pins. read and write accesses to the device are burst-oriented. accesses start at a selected lo- cation and continue for a burst length of eight or a chopped burst of four in a program- med sequence. operation begins with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (bg[1:0] select the bank group for x4/x8, and bg0 selects the bank group for x16; ba[1:0] select the bank, and a[17:0] select the row. see the addressing section for more details). the address bits registered coincident with the read or write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via a10), and select bc4 or bl8 mode on-the-fly (otf) (via a12) if enabled in the mode register. prior to normal operation, the device must be powered up and initialized in a prede- fined manner. the following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation. note: the use of the nop command is allowed only when exiting maximum power saving mode or when entering gear-down mode. 8gb: x4, x8, x16 ddr4 sdram functional description 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
reset and initialization procedure to ensure proper device function, the power-up and reset initialization default values for the following mode register (mr) settings are defined as: ? gear-down mode (mr3 a[3]): 0 = 1/2 rate ? per-dram addressability (mr3 a[4]): 0 = disable ? maximum power-saving mode (mr4 a[1]): 0 = disable ? cs to command/address latency (mr4 a[8:6]): 000 = disable ? ca parity latency mode (mr5 a[2:0]): 000 = disable ? hard post package repair mode (mr4 a[13]) : 0 = disable ? soft post package repair mode (mr4 a[5]) : 0 = disable power-up and initialization sequence the following sequence is required for power-up and initialization: 1. apply power (reset_n and ten should be maintained below 0.2 v dd while sup- plies ramp up; all other inputs may be undefined). when supplies have ramped to a valid stable level, reset_n must be maintained below 0.2 v dd for a minimum of t pw_reset_l and ten must be maintained below 0.2 v dd for a minimum of 700s. cke is pulled low anytime before reset_n is de-asserted (minimum time of 10ns). the power voltage ramp time between 300mv to v dd,min must be no greater than 200ms, and during the ramp, v dd must be greater than or equal to v ddq and (v dd - v ddq ) < 0.3v. v pp must ramp at the same time or before v dd , and v pp must be equal to or higher than v dd at all times. after v dd has ramped and reached the stable level and after reset_n goes high, the initialization sequence must be started within 3 seconds. for debug purposes, the 3 second delay limit may be extended to 60 minutes provided the dram is operated in this debug mode for no more than 360 cumulative hours. during power-up, the supply slew rate is governed by the limits stated in the table below and either condition a or condition b must be met. table 5: supply power-up slew rate symbol min max unit comment v dd _sl, v ddq _sl, v pp _sl 0.004 600 v/ms measured between 300mv and 80% of supply minimum v dd _ona n/a 200 ms v dd maximum ramp time from 300mv to v dd minimum v ddq _ona n/a 200 ms v ddq maximum ramp time from 300mv to v ddq minimum note: 1. 20 mhz band-limited measurement. ? condition a: C apply v pp without any slope reversal before or at the same time as v dd and v ddq . Cv dd and v ddq are driven from a single-power converter output and apply v dd /v ddq without any slope reversal before or at the same time as v tt and v refca . 8gb: x4, x8, x16 ddr4 sdram reset and initialization procedure 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
C the voltage levels on all balls other than v dd , v ddq , v ss , and v ssq must be less than or equal to v ddq and v dd on one side and must be greater than or equal to v ssq and v ss on the other side. Cv tt is limited to 0.76v max when the power ramp is complete. Cv refca tracks v dd /2. ? condition b: C apply v pp without any slope reversal before or at the same time as v dd . C apply v dd without any slope reversal before or at the same time as v ddq . C apply v ddq without any slope reversal before or at the same time as v tt and v refca . C the voltage levels on all pins other than v pp , v dd , v ddq , v ss , and v ssq must be less than or equal to v ddq and v dd on one side and must be larger than or equal to v ssq and v ss on the other side. 2. after reset_n is de-asserted, wait for another 500s but no longer then 3 seconds until cke becomes active. during this time, the device will start internal state initi- alization; this will be done independently of external clocks. a reasonable attempt was made in the design to power up with the following default mr settings: gear- down mode (mr3 a[3]): 0 = 1/2 rate; per-dram addressability (mr3 a[4]): 0 = dis- able; maximum power-down (mr4 a[1]): 0 = disable; cs to command/address la- tency (mr4 a[8:6]): 000 = disable; ca parity latency mode (mr5 a[2:0]): 000 = disa- ble. however, it should be assumed that at power up the mr settings are unde- fined and should be programmed as shown below. 3. clocks (ck_t, ck_c) need to be started and stabilized for at least 10ns or 5 t ck (whichever is larger) before cke goes active. because cke is a synchronous signal, the corresponding setup time to clock ( t is) must be met. also, a deselect com- mand must be registered (with t is setup time to clock) at clock edge td. after the cke is registered high after reset, cke needs to be continuously registered high until the initialization sequence is finished, including expiration of t dllk and t zq init . 4. the device keeps its odt in high-z state as long as reset_n is asserted. further, the sdram keeps its odt in high-z state after reset_n de-assertion until cke is registered high. the odt input signal may be in an undefined state until t is be- fore cke is registered high. when cke is registered high, the odt input signal may be statically held either low or high. if r tt(nom) is to be enabled in mr1, the odt input signal must be statically held low. in all cases, the odt input sig- nal remains static until the power-up initialization sequence is finished, including the expiration of t dllk and t zq init . 5. after cke is registered high, wait a minimum of reset cke exit time, t xpr, be- fore issuing the first mrs command to load mode register ( t xpr = max ( t xs; 5 t ck). 6. issue mrs command to load mr3 with all application settings, wait t mrd. 7. issue mrs command to load mr6 with all application settings, wait t mrd. 8. issue mrs command to load mr5 with all application settings, wait t mrd. 9. issue mrs command to load mr4 with all application settings, wait t mrd. 10. issue mrs command to load mr2 with all application settings, wait t mrd. 11. issue mrs command to load mr1 with all application settings, wait t mrd. 12. issue mrs command to load mr0 with all application settings, wait t mod. 13. issue a zqcl command to start zq calibration. 14. wait for t dllk and t zq init to complete. 8gb: x4, x8, x16 ddr4 sdram reset and initialization procedure 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
15. the device will be ready for normal operation. once the dram has been initial- ized, if the dram is in an idle state longer than 960ms, then either (a) ref com- mands must be issued within t refi constraints (specification for posting allowed) or (b) cke or cs_n must toggle once within every 960ms interval of idle time. for debug purposes, the 960ms delay limit maybe extended to 60 minutes provided the dram is operated in this debug mode for no more than 360 cumulative hours. a stable valid v dd level is a set dc level (0hz to 250 khz) and must be no less than v dd,min and no greater than v dd,max . if the set dc level is altered anytime after initializa- tion, the dll reset and calibrations must be performed again after the new set dc level is stable. ac noise of 60mv (greater than 250 khz) is allowed on v dd provided the noise doesn't alter v dd to less than v dd,min or greater than v dd,max . a stable valid v ddq level is a set dc level (0hz to 250 khz) and must be no less than v ddq,min and no greater than v ddq,max . if the set dc level is altered anytime after initial- ization, the dll reset and calibrations must be performed again after the new set dc level is stable. ac noise of 60mv (greater than 250 khz) is allowed on v ddq provided the noise doesn't alter v ddq to less than v ddq,min or greater than v ddq,max . a stable valid v pp level is a set dc level (0hz to 250 khz) and must be no less than v pp,min and no greater than v pp,max . if the set dc level is altered anytime after initializa- tion, the dll reset and calibrations must be performed again after the new set dc level is stable. ac noise of 120mv (greater than 250khz) is allowed on v pp provided the noise doesn't alter v pp to less than v pp,min or greater than v pp,max . 8gb: x4, x8, x16 ddr4 sdram reset and initialization procedure 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 14: reset and initialization sequence at power-on ramping cke r tt bg, ba t pw_reset_l ck_t, ck_c command note 1 note 1 td tc dont care time break t is odt th t mrd t mod mrs mrs valid valid t mrd t mrd mrs mrx mrx mrx mrs mrx ti tj tk reset_n t = 500s valid te ta tb tf zqcl t is static low in case r tt(nom) is enabled at time tg, otherwise static high or low t is t is t xpr valid t (min) = 10ns v dd , v ddq v pp t dllk t zqinit t cksrx tg notes: 1. from time point td until tk, a des command must be applied between mrs and zqcl commands. 2. mrs commands must be issued to all mode registers that have defined settings. 3. in general, there is no specific sequence for setting the mrs locations (except for de- pendent or co-related features, such as enable dll in mr1 prior to reset dll in mr0, for example). 4. ten is not shown; however, it is assumed to be held low. reset initialization with stable power sequence the following sequence is required for reset at no power interruption initialization: 1. assert reset_n below 0.2 v dd any time reset is needed (all other inputs may be undefined). reset must be maintained for a minimum of 100ns. cke is pulled low before reset_n is de-asserted (minimum time 10ns). 2. follow steps 2 to 10 in the reset and initialization sequence at power-on ramping procedure. when the reset sequence is complete, all counters except the refresh counters have been reset and the device is ready for normal operation. 8gb: x4, x8, x16 ddr4 sdram reset and initialization procedure 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 15: reset procedure at power stable condition cke r tt bg, ba t pw_reset_s ck_t, ck_c command note 1 note 1 td tc dont care time break t is odt th t mrd t mod mrs mrs valid valid t mrd t mrd mrs mrx mrx mrx mrs mrx ti tj tk reset_n t = 500s valid te ta tb tf zqcl t is static low in case r tt(nom) is enabled at time tg, otherwise static high or low t is t is t xpr valid t (min) = 10ns v dd , v ddq v pp t dllk t zqinit t cksrx tg notes: 1. from time point td until tk, a des command must be applied between mrs and zqcl commands. 2. mrs commands must be issued to all mode registers that have defined settings. 3. in general, there is no specific sequence for setting the mrs locations (except for de- pendent or co-related features, such as enable dll in mr1 prior to reset dll in mr0, for example). 4. ten is not shown; however, it is assumed to be held low. uncontrolled power-down sequence in the event of an uncontrolled ramping down of v pp supply, v pp is allowed to be less than v dd provided the following conditions are met: ? condition a: v pp and v dd /v ddq are ramping down (as part of turning off) from nor- mal operating levels. ? condition b: the amount that v pp may be less than v dd /v ddq is less than or equal to 500mv. ? condition c: the time v pp may be less than v dd is 10ms per occurrence with a total accumulated time in this state 100ms. 8gb: x4, x8, x16 ddr4 sdram reset and initialization procedure 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
? condition d: the time v pp may be less than 2.0v and above v ss while turning off is 15ms per occurrence with a total accumulated time in this state 150ms. programming mode registers for application flexibility, various functions, features, and modes are programmable in seven mode registers (mr n ) provided by the device as user defined variables that must be programmed via a mode register set (mrs) command. because the default val- ues of the mode registers are not defined, contents of mode registers must be fully ini- tialized and/or re-initialized; that is, they must be written after power-up and/or reset for proper operation. the contents of the mode registers can be altered by re-executing the mrs command during normal operation. when programming the mode registers, even if the user chooses to modify only a sub-set of the mrs fields, all address fields within the accessed mode register must be redefined when the mrs command is is- sued. mrs and dll reset commands do not affect array contents, which means these commands can be executed any time after power-up without affecting the array con- tents. the mrs command cycle time, t mrd, is required to complete the write operation to the mode register and is the minimum time required between the two mrs commands shown in the t mrd timing figure. some of the mode register settings affect address/command/control input functionali- ty. in these cases, the next mrs command can be allowed when the function being up- dated by the current mrs command is completed. these mrs commands dont apply t mrd timing to the next mrs command; however, the input cases have unique mr set- ting procedures, so refer to individual function descriptions: ? gear-down mode ? per-dram addressability ? maximum power saving mode ? cs to command/address latency ? ca parity latency mode ?v refdq training value ?v refdq training mode ?v refdq training range some mode register settings may not be supported because they are not required by certain speed bins. 8gb: x4, x8, x16 ddr4 sdram programming mode registers 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 16: t mrd timing t0 t1 t2 ta0 ta1 tb0 tb1 tb2 tc0 tc1 tc2 dont care valid valid valid mrs 2 mrs 2 des des des des des valid ck_t ck_c command settings cke updating settings address valid valid valid valid valid valid valid valid valid valid valid t mrd time break old settings notes: 1. this timing diagram depicts ca parity mode disabled case. 2. t mrd applies to all mrs commands with the following exceptions: gear-down mode ca parity mode cal mode per-dram addressability mode v refdq training value, v refdq training mode, and v refdq training range the mrs command to nonmrs command delay, t mod, is required for the dram to update features, except for those noted in note 2 in figure below where the individual function descriptions may specify a different requirement. t mod is the minimum time required from an mrs command to a nonmrs command, excluding des, as shown in the t mod timing figure. figure 17: t mod timing t0 t1 t2 ta0 ta1 ta2 ta3 ta4 tb0 tb1 tb2 dont care valid valid valid mrs 2 des des des des des valid valid ck_t ck_c command settings cke updating settings new settings address valid valid valid valid valid valid valid valid valid valid valid t mod time break old settings notes: 1. this timing diagram depicts ca parity mode disabled case. 2. t mod applies to all mrs commands with the following exceptions: dll enable, dll reset, gear-down mode v refdq training value, internal v ref training monitor, v refdq training mode, and v refdq training range maximum power savings mode , per-dram addressability mode, and ca parity mode 8gb: x4, x8, x16 ddr4 sdram programming mode registers 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
the mode register contents can be changed using the same command and timing re- quirements during normal operation as long as the device is in idle state; that is, all banks are in the precharged state with t rp satisfied, all data bursts are completed, and cke is high prior to writing into the mode register. if the r tt(nom) feature is enabled in the mode register prior to and/or after an mrs command, the odt signal must contin- uously be registered low, ensuring r tt is in an off state prior to the mrs command. the odt signal may be registered high after t mod has expired. if the r tt(nom) feature is disabled in the mode register prior to and after an mrs command, the odt signal can be registered either low or high before, during, and after the mrs command. the mode registers are divided into various fields depending on functionality and modes. in some mode register setting cases, function updating takes longer than t mod. this type of mrs does not apply t mod timing to the next valid command, excluding des. these mrs command input cases have unique mr setting procedures, so refer to indi- vidual function descriptions. 8gb: x4, x8, x16 ddr4 sdram programming mode registers 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
mode register 0 mode register 0 (mr0) controls various device operating modes as shown in the follow- ing register definition table. not all settings listed may be available on a die; only set- tings required for speed bin support are available. mr0 is written by issuing the mrs command while controlling the states of the bg x, bax, and ax address pins. the map- ping of address pins during the mrs command is shown in the following mr0 register definition table. table 6: address pin mapping address bus bg1 bg0 ba1 ba0 a17 ras _n cas _n we _n a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register 2120191817CCC131211109876543210 note: 1. ras_n, cas_n, and we_n must be low during mode register set command. table 7: mr0 register definition mode register description 21 rfu 0 = must be programmed to 0 1 = reserved 20:18 mr select 000 = mr0 001 = mr1 010 = mr2 011 = mr3 100 = mr4 101 = mr5 110 = mr6 111 = dnu 17 n/a on 4gb and 8gb, rfu 0 = must be programmed to 0 1 = reserved 13,11:9 wr (write recovery)/rtp (read-to-precharge) 0000 = 10 / 5 clocks 1 0001 = 12 / 6 clocks 0010 = 14 / 7 clocks 1 0011 = 16 / 8 / clocks 0100 = 18 / 9 clocks 1 0101 = 20 /10 clocks 0110 = 24 / 12 clocks 0111 = 22 / 11 clocks 1 1000 = 26 / 13 clocks 1 1001 = 28 / 14 clocks 2 1010 through 1111 = reserved 8gb: x4, x8, x16 ddr4 sdram mode register 0 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 7: mr0 register definition (continued) mode register description 8 dll reset 0 = no 1 = yes 7 test mode (tm) C manufacturer use only 0 = normal operating mode, must be programmed to 0 12, 6:4, 2 cas latency (cl) C delay in clock cycles from the internal read command to first data-out 00000 = 9 clocks 1 00001 = 10 clocks 00010 = 11 clocks 1 00011 = 12 clocks 00100 = 13 clocks 1 00101 = 14 clocks 00110 = 15 clocks 1 00111 = 16 clocks 01000 = 18 clocks 01001 = 20 clocks 01010 = 22 clocks 01011 = 24 clocks 01100 = 23 clocks 1 01101 = 17 clocks 1 01110 = 19 clocks 1 01111 = 21 clocks 1 10000 = 25 clocks (3ds use only) 10001 = 26 clocks 10010 = 27 clocks (3ds use only) 10011 = 28 clocks 10100 = 29 clocks 1 10101 = 30 clocks 10110 = 31 clocks 1 10111 = 32 clocks 3 burst type (bt) C data burst ordering within a read or write burst access 0 = nibble sequential 1 = interleave 1:0 burst length (bl) C data burst size associated with each read or write access 00 = bl8 (fixed) 01 = bc4 or bl8 (on-the-fly) 10 = bc4 (fixed) 11 = reserved notes: 1. not allowed when 1/4 rate gear-down mode is enabled. 2. if wr requirement exceeds 28 clocks or rtp exceeds 14 clocks, wr should be set to 28 clocks and rtp should be set to 14 clocks. 8gb: x4, x8, x16 ddr4 sdram mode register 0 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
burst length, type, and order accesses within a given burst may be programmed to sequential or interleaved order. the ordering of accesses within a burst is determined by the burst length, burst type, and the starting column address as shown in the following table. burst length options include fixed bc4, fixed bl8, and on-the-fly (otf), which allows bc4 or bl8 to be selec- ted coincidentally with the registration of a read or write command via a12/bc_n. table 8: burst type and burst order note 1 applies to the entire table burst length read/ write starting column address (a[2, 1, 0]) burst type = sequential (decimal) burst type = interleaved (decimal) notes bc4 read 0 0 0 0, 1, 2, 3, t, t, t, t 0, 1, 2, 3, t, t, t, t 2, 3 0 0 1 1, 2, 3, 0, t, t, t, t 1, 0, 3, 2, t, t, t, t 2, 3 0 1 0 2, 3, 0, 1, t, t, t, t 2, 3, 0, 1, t, t, t, t 2, 3 0 1 1 3, 0, 1, 2, t, t, t, t 3, 2, 1, 0, t, t, t, t 2, 3 1 0 0 4, 5, 6, 7, t, t, t, t 4, 5, 6, 7, t, t, t, t 2, 3 1 0 1 5, 6, 7, 4, t, t, t, t 5, 4, 7, 6, t, t, t, t 2, 3 1 1 0 6, 7, 4, 5, t, t, t, t 6, 7, 4, 5, t, t, t, t 2, 3 1 1 1 7, 4, 5, 6, t, t, t, t 7, 6, 5, 4, t, t, t, t 2, 3 write 0, v, v 0, 1, 2, 3, x, x, x, x 0, 1, 2, 3, x, x, x, x 2, 3 1, v, v 4, 5, 6, 7, x, x, x, x 4, 5, 6, 7, x, x, x, x 2, 3 bl8 read 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 write v, v, v 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 3 notes: 1. 0...7 bit number is the value of ca[2:0] that causes this bit to be the first read during a burst. 2. when setting burst length to bc4 (fixed) in mr0, the internal write operation starts two clock cycles earlier than for the bl8 mode, meaning the starting point for t wr and t wtr will be pulled in by two clocks. when setting burst length to otf in mr0, the in- ternal write operation starts at the same time as a bl8 (even if bc4 was selected during column time using a12/bc4_n) meaning that if the otf mr0 setting is used, the starting point for t wr and t wtr will not be pulled in by two clocks as described in the bc4 (fixed) case. 3. t = output driver for data and strobes are in high-z. v = valid logic level (0 or 1), but respective buffer input ignores level on input pins. x = dont care. 8gb: x4, x8, x16 ddr4 sdram mode register 0 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
cas latency the cas latency (cl) setting is defined in the mr0 register definition table. cas laten- cy is the delay, in clock cycles, between the internal read command and the availability of the first bit of output data. the device does not support half-clock latencies. the overall read latency (rl) is defined as additive latency (al) + cas latency (cl): rl = al + cl. test mode the normal operating mode is selected by mr0[7] and all other bits set to the desired values shown in the mr0 register definition table. programming mr0[7] to a value of 1 places the device into a dram manufacturer-defined test mode to be used only by the manufacturer, not by the end user. no operations or functionality is specified if mr0[7] = 1. write recovery(wr)/read-to-precharge the programmed write recovery (wr) value is used for the auto precharge feature along with t rp to determine t dal. wr for auto precharge (min) in clock cycles is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up to the next integer: wr (min) cycles = roundup ( t wr[ns]/ t ck[ns]). the wr value must be programmed to be equal to or larger than t wr (min). when both dm and write crc are enabled in the mode regis- ter, the device calculates crc before sending the write data into the array; t wr values will change when enabled. if there is a crc error, the device blocks the write opera- tion and discards the data. internal read-to-precharge (rtp) command delay for auto precharge (min) in clock cycles is calculated by dividing t rtp (in ns) by t ck (in ns) and rounding up to the next integer: rtp (min) cycles = roundup ( t rtp[ns]/ t ck[ns]). the rtp value in the mode register must be programmed to be equal to or larger than rtp (min). the pro- grammed rtp value is used with t rp to determine the act timing to the same bank. dll reset the dll reset bit is self-clearing, meaning that it returns to the value of 0 after the dll reset function has been issued. after the dll is enabled, a subsequent dll reset should be applied. any time the dll reset function is used, t dllk must be met before functions requiring the dll can be used, such as read commands or synchronous odt operations, for example,). 8gb: x4, x8, x16 ddr4 sdram mode register 0 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
mode register 1 mode register 1 (mr1) controls various device operating modes as shown in the follow- ing register definition table. not all settings listed may be available on a die; only set- tings required for speed bin support are available. mr1 is written by issuing the mrs command while controlling the states of the bg x, bax, and ax address pins. the map- ping of address pins during the mrs command is shown in the following mr1 register definition table. table 9: address pin mapping address bus bg1 bg0 ba1 ba0 a17 ras _n cas _n we _n a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register 2120191817CCC131211109876543210 note: 1. ras_n, cas_n, and we_n must be low during mode register set command. table 10: mr1 register definition mode register description 21 rfu 0 = must be programmed to 0 1 = reserved 20:18 mr select 000 = mr0 001 = mr1 010 = mr2 011 = mr3 100 = mr4 101 = mr5 110 = mr6 111 = dnu 17 n/a on 4gb and 8gb, rfu 0 = must be programmed to 0 1 = reserved 13 rfu 0 = must be programmed to 0 1 = reserved 12 data output disable (qoff) C output buffer disable 0 = enabled (normal operation) 1 = disabled (both odi and r tt ) 11 termination data strobe (tdqs) C additional termination pins (x8 configuration only) 0 = tdqs disabled 1 = tdqs enabled 8gb: x4, x8, x16 ddr4 sdram mode register 1 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 10: mr1 register definition (continued) mode register description 10, 9, 8 nominal odt (r tt(nom) C data bus termination setting 000 = r tt(nom) disabled 001 = rzq/4 (60 ohm) 010 = rzq/2 (120 ohm) 011 = rzq/6 (40 ohm) 100 = rzq/1 (240 ohm) 101 = rzq/5 (48 ohm) 110 = rzq/3 (80 ohm) 111 = rzq/7 (34 ohm) 7 write leveling (wl) C write leveling mode 0 = disabled (normal operation) 1 = enabled (enter wl mode) 6, 5 rfu 0 = must be programmed to 0 1 = reserved 4, 3 additive latency (al) C command additive latency setting 00 = 0 (al disabled) 01 = cl - 1 1 10 = cl - 2 11 = reserved 2, 1 output driver impedance (odi) C output driver impedance setting 00 = rzq/7 (34 ohm) 01 = rzq/5 (48 ohm) 10 = reserved (although not jedec-defined and not tested, this setting will provide rzq/6 or 40 ohm) 11 = reserved 0 dll enable C dll enable feature 0 = dll disabled 1 = dll enabled (normal operation) note: 1. not allowed when 1/4 rate gear-down mode is enabled. dll enable/dll disable the dll must be enabled for normal operation and is required during power-up initial- ization and upon returning to normal operation after having the dll disabled. during normal operation (dll enabled with mr1[0]) the dll is automatically disabled when entering the self refresh operation and is automatically re-enabled upon exit of the self refresh operation. any time the dll is enabled and subsequently reset, t dllk clock cycles must occur before a read or synchronous odt command can be is- sued to allow time for the internal clock to be synchronized with the external clock. fail- ing to wait for synchronization to occur may result in a violation of the t dqsck, t aon, or t aof parameters. during t dllk, cke must continuously be registered high. the device does not require dll for any write operation, except when r tt(wr) is enabled and the dll is required for proper odt operation. 8gb: x4, x8, x16 ddr4 sdram mode register 1 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
the direct odt feature is not supported during dll off mode. the odt resistors must be disabled by continuously registering the odt pin low and/or by programming the r tt(nom) bits mr1[9,6,2] = 000 via an mrs command during dll off mode. the dynamic odt feature is not supported in dll off mode; to disable dynamic odt externally, use the mrs command to set r tt(wr) , mr2[10:9] = 00. output driver impedance control the output driver impedance of the device is selected by mr1[2,1], as shown in the mr1 register definition table. odt r tt(nom) values the device is capable of providing three different termination values: r tt(park) , r tt(nom) , and r tt(wr) . the nominal termination value, r tt(nom) , is programmed in mr1. a sepa- rate value, r tt(wr) , may be programmed in mr2 to enable a unique r tt value when odt is enabled during write operations. the r tt(wr) value can be applied during write commands even when r tt(nom) is disabled. a third r tt value, r tt(park) , is pro- gramed in mr5. r tt(park) provides a termination value when the odt signal is low. additive latency the additive latency (al) operation is supported to make command and data buses efficient for sustainable bandwidths in the device. in this operation, the device al- lows a read or write command (either with or without auto precharge) to be issued immediately after the activate command. the command is held for the time of al be- fore it is issued inside the device. read latency (rl) is controlled by the sum of the al and cas latency (cl) register settings. write latency (wl) is controlled by the sum of the al and cas write latency (cwl) register settings. table 11: additive latency (al) settings a4 a3 al 0 0 0 (al disabled) 0 1 cl - 1 1 0 cl - 2 1 1 reserved note: 1. al has a value of cl - 1 or cl - 2 based on the cl values programmed in the mr0 regis- ter. write leveling for better signal integrity, the device uses fly-by topology for the commands, addresses, control signals, and clocks. fly-by topology benefits from a reduced number of stubs and their lengths, but it causes flight-time skew between clock and strobe at every dram on the dimm. this makes it difficult for the controller to maintain t dqss, t dss, and t dsh specifications. therefore, the device supports a write leveling feature that al- lows the controller to compensate for skew. 8gb: x4, x8, x16 ddr4 sdram mode register 1 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
output disable the device outputs may be enabled/disabled by mr1[12] as shown in the mr1 register definition table. when mr1[12] is enabled (mr1[12] = 1) all output pins (such as dq and dqs) are disconnected from the device, which removes any loading of the output drivers. for example, this feature may be useful when measuring module power. for normal operation, set mr1[12] to 0. termination data strobe termination data strobe (tdqs) is a feature of the x8 device and provides additional termination resistance outputs that may be useful in some system configurations. be- cause this function is available only in a x8 configuration, it must be disabled for x4 and x16 configurations. while tdqs is not supported in x4 or x16 configurations, the same termination resist- ance function that is applied to the tdqs pins is applied to the dqs pins when enabled via the mode register. the tdqs, dbi, and data mask (dm) functions share the same pin. when the tdqs function is enabled via the mode register, the dm and dbi functions are not supported. when the tdqs function is disabled, the dm and dbi functions can be enabled sepa- rately. table 12: tdqs function matrix tdqs data mask (dm) write dbi read dbi disabled enabled disabled enabled or disabled disabled enabled enabled or disabled disabled disabled enabled or disabled enabled disabled disabled disabled 8gb: x4, x8, x16 ddr4 sdram mode register 1 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
mode register 2 mode register 2 (mr2) controls various device operating modes as shown in the follow- ing register definition table. not all settings listed may be available on a die; only set- tings required for speed bin support are available. mr2 is written by issuing the mrs command while controlling the states of the bg x, bax, and ax address pins. the map- ping of address pins during the mrs command is shown in the following mr2 register definition table. table 13: address pin mapping address bus bg1 bg0 ba1 ba0 a17 ras _n cas _n we _n a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register 2120191817CCC131211109876543210 note: 1. ras_n, cas_n, and we_n must be low during mode register set command. table 14: mr2 register definition mode register description 21 rfu 0 = must be programmed to 0 1 = reserved 20:18 mr select 000 = mr0 001 = mr1 010 = mr2 011 = mr3 100 = mr4 101 = mr5 110 = mr6 111 = dnu 17 n/a on 4gb and 8gb, rfu 0 = must be programmed to 0 1 = reserved 13 rfu 0 = must be programmed to 0 1 = reserved 12 write data bus crc 0 = disabled 1 = enabled 8gb: x4, x8, x16 ddr4 sdram mode register 2 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 14: mr2 register definition (continued) mode register description 11:9 dynamic odt (r tt(wr) ) C data bus termination setting during writes 000 = r tt(wr) disabled (write does not affect r tt value) 001 = rzq/2 (120 ohm) 010 = rzq/1 (240 ohm) 011 = high-z 100 = rzq/3 (80 ohm) 101 = reserved 110 = reserved 111 = reserved 7:6 low-power auto self refresh (lpasr) C mode summary 00 = manual mode - normal operating temperature range (t c : 0cC85c) 01 = manual mode - reduced operating temperature range (t c : 0cC45c) 10 = manual mode - extended operating temperature range (t c : 0cC95c) 11 = asr mode - automatically switching among all modes 5:3 cas write latency (cwl) C delay in clock cycles from the internal write command to first data-in 1 t ck write preamble 000 = 9 (ddr4-1600) 1 001 = 10 (ddr4-1866) 010 = 11 (ddr4-2133/1600) 1 011 = 12 (ddr4-2400/1866) 100 = 14 (ddr4-2666/2133) 101 = 16 (ddr4-2933,3200/2400) 110 = 18 (ddr4-2666) 111 = 20 (ddr4-2933, 3200) cas write latency (cwl) C delay in clock cycles from the internal write command to first data-in 2 t ck write preamble 000 = n/a 001 = n/a 010 = n/a 011 = n/a 100 = 14 (ddr4-2400) 101 = 16 (ddr4-2666/2400) 110 = 18 (ddr4-2933, 3200/2666) 111 = 20 (ddr4-2933, 3200) 8, 2 rfu 0 = must be programmed to 0 1 = reserved 1:0 rfu 0 = must be programmed to 0 1 = reserved note: 1. not allowed when 1/4 rate gear-down mode is enabled. 8gb: x4, x8, x16 ddr4 sdram mode register 2 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
cas write latency cas write latency (cwl) is defined by mr2[5:3] as shown in the mr2 register defini- tion table. cwl is the delay, in clock cycles, between the internal write command and the availability of the first bit of input data. the device does not support any half-clock latencies. the overall write latency (wl) is defined as additive latency (al) + parity la- tency (pl) + cas write latency (cwl): wl = al +pl + cwl. low-power auto self refresh low-power auto self refresh (lpasr) is supported in the device. applications requiring self refresh operation over different temperature ranges can use this feature to opti- mize the i dd6 current for a given temperature range as specified in the mr2 register definition table. dynamic odt in certain applications and to further enhance signal integrity on the data bus, it is de- sirable to change the termination strength of the device without issuing an mrs com- mand. this may be done by configuring the dynamic odt (r tt(wr) ) settings in mr2[11:9]. in write leveling mode, only r tt(nom) is available. write cyclic redundancy check data bus the write cyclic redundancy check (crc) data bus feature during writes has been added to the device. when enabled via the mode register, the data transfer size goes from the normal 8-bit (bl8) frame to a larger 10-bit ui frame, and the extra two uis are used for the crc information. 8gb: x4, x8, x16 ddr4 sdram mode register 2 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
mode register 3 mode register 3 (mr3) controls various device operating modes as shown in the follow- ing register definition table. not all settings listed may be available on a die; only set- tings required for speed bin support are available. mr3 is written by issuing the mrs command while controlling the states of the bg x, bax, and ax address pins. the map- ping of address pins during the mrs command is shown in the following mr3 register definition table. table 15: address pin mapping address bus bg1 bg0 ba1 ba0 a17 ras _n cas _n we _n a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register 2120191817CCC131211109876543210 note: 1. ras_n, cas_n, and we_n must be low during mode register set command. table 16: mr3 register definition mode register description 21 rfu 0 = must be programmed to 0 1 = reserved 20:18 mr select 000 = mr0 001 = mr1 010 = mr2 011 = mr3 100 = mr4 101 = mr5 110 = mr6 111 = dnu 17 n/a on 4gb and 8gb, rfu 0 = must be programmed to 0 1 = reserved 13 rfu 0 = must be programmed to 0 1 = reserved 12:11 multipurpose register (mpr) C read format 00 = serial 01 = parallel 10 = staggered 11 = reserved 10:9 write cmd latency when crc/dm enabled 00 = 4ck (ddr4-1600) 01 = 5ck (ddr4-1866/2133/2400/2666) 10 = 6ck (ddr4-2933/3200) 11 = reserved 8gb: x4, x8, x16 ddr4 sdram mode register 3 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 16: mr3 register definition (continued) mode register description 8:6 fine granularity refresh mode 000 = normal mode (fixed 1x) 001 = fixed 2x 010 = fixed 4x 011 = reserved 100 = reserved 101 = on-the-fly 1x/2x 110 = on-the-fly 1x/4x 111 = reserved 5 temperature sensor status 0 = disabled 1 = enabled 4 per-dram addressability 0 = normal operation (disabled) 1 = enable 3 gear-down mode C ratio of internal clock to external data rate 0 = [1:1]; (1/2 rate data) 1 = [2:1]; (1/4 rate data) 2 multipurpose register (mpr) access 0 = normal operation 1 = data flow from mpr 1:0 mpr page select 00 = page 0 01 = page 1 10 = page 2 11 = page 3 (restricted for dram manufacturer use only) multipurpose register the multipurpose register (mpr) is used for several features: ? readout of the contents of the mr n registers ? write and read system patterns used for data bus calibration ? readout of the error frame when the command address parity feature is enabled to enable mpr, issue an mrs command to mr3[2] = 1. mr3[12:11] define the format of read data from the mpr. prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and t rp met). after mpr is enabled, any subsequent rd or rda commands will be redirected to a specific mode register. the mode register location is specified with the read command using address bits. the mr is split into upper and lower halves to align with a burst length limitation of 8. pow- er-down mode, self refresh, and any other nonrd/rda or nonwr/wra com- mands are not allowed during mpr mode. the reset function is supported during mpr mode, which requires device re-initialization. 8gb: x4, x8, x16 ddr4 sdram mode register 3 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
write command latency when crc/dm is enabled the write command latency (wcl) must be set when both write crc and dm are en- abled for write crc persistent mode. this provides the extra time required when com- pleting a write burst when write crc and dm are enabled. this means at data rates less than or equal to 1600 mt/s then 4nck is used, 5nck or 6nck are not allowed; at data rates greater than 1600 mt/s and less than or equal to 2666 mt/s then 5nck is used, 4nck or 6nck are not allowed; and at data rates greater than 2666 mt/s and less than or equal to 3200 mt/s then 6nck is used; 4nck or 5nck are not allowed. fine granularity refresh mode this mode had been added to ddr4 to help combat the performance penalty due to refresh lockout at high densities. shortening t rfc and increasing cycle time allows more accesses to the chip and can produce higher bandwidth. temperature sensor status this mode directs the dram to update the temperature sensor status at mpr page 2, mpr0 [4,3]. the temperature sensor setting should be updated within 32ms; when an mpr read of the temperature sensor status bits occurs, the temperature sensor status should be no older than 32ms. per-dram addressability this mode allows commands to be masked on a per device basis providing any device in a rank (devices sharing the same command and address signals) to be programmed individually. as an example, this feature can be used to program different odt or v ref values on dram devices within a given rank. gear-down mode the device defaults in 1/2 rate (1n) clock mode and uses a low frequency mrs com- mand followed by a sync pulse to align the proper clock edge for operating the control lines cs_n, cke, and odt when in 1/4 rate (2n) mode. for operation in 1/2 rate mode, no mrs command or sync pulse is required. 8gb: x4, x8, x16 ddr4 sdram mode register 3 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
mode register 4 mode register 4 (mr4) controls various device operating modes as shown in the follow- ing register definition table. not all settings listed may be available on a die; only set- tings required for speed bin support are available. mr4 is written by issuing the mrs command while controlling the states of the bg x, bax, and ax address pins. the map- ping of address pins during the mrs command is shown in the following mr4 register definition table. table 17: address pin mapping address bus bg1 bg0 ba1 ba0 a17 ras _n cas _n we _n a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register 2120191817CCC131211109876543210 note: 1. ras_n, cas_n, and we_n must be low during mode register set (mrs) command. table 18: mr4 register definition mode register description 21 rfu 0 = must be programmed to 0 1 = reserved 20:18 mr select 000 = mr0 001 = mr1 010 = mr2 011 = mr3 100 = mr4 101 = mr5 110 = mr6 111 = dnu 17 n/a on 4gb and 8gb, rfu 0 = must be programmed to 0 1 = reserved 13 hard post package repair (hppr mode) 0 = disabled 1 = enabled 12 write preamble setting 0 = 1 t ck toggle 1 1 = 2 t ck toggle 11 read preamble setting 0 = 1 t ck toggle 1 1 = 2 t ck toggle (when operating in 2 t ck write preamble mode, cwl must be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range.) 10 read preamble training 0 = disabled 1 = enabled 8gb: x4, x8, x16 ddr4 sdram mode register 4 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 18: mr4 register definition (continued) mode register description 9 self refresh abort mode 0 = disabled 1 = enabled 8:6 cmd (cal) address latency 000 = 0 clocks (disabled) 001 =3 clocks 1 010 = 4 clocks 011 = 5 clocks 1 100 = 6 clocks 101 = 8 clocks 110 = reserved 111 = reserved 5 soft post package repair (sppr mode) 0 = disabled 1 = enabled 4 internal v ref monitor 0 = disabled 1 = enabled 3 temperature controlled refresh mode 0 = disabled 1 = enabled 2 temperature controlled refresh range 0 = normal temperature mode 1 = extended temperature mode 1 maximum power savings mode 0 = normal operation 1 = enabled 0 rfu 0 = must be programmed to 0 1 = reserved note: 1. not allowed when 1/4 rate gear-down mode is enabled. hard post package repair mode the hard post package repair (hppr) mode feature is jedec optional for 4gb ddr4 memories. performing an mpr read to page 2 mpr0 [7] indicates whether hppr mode is available (a7 = 1) or not available (a7 = 0). hppr mode provides a simple and easy repair method of the device after placed in the system. one row per bank can be repaired. the repair process is irrevocable so great care should be exercised when using. soft post package repair mode the soft post package repair (sppr) mode feature is jedec optional for 4gb and 8gb ddr4 memories. performing an mpr read to page 2 mpr0 [6] indicates whether sppr mode is available (a6 = 1) or not available (a6 = 0). sppr mode provides a simple and 8gb: x4, x8, x16 ddr4 sdram mode register 4 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
easy repair method of the device after placed in the system. one row per bank can be repaired. the repair process is revocable by either doing a reset or power-down or by rewriting a new address in the same bank. write preamble programmable write preamble, t wpre, can be set to 1 t ck or 2 t ck via the mr4 register. the 1 t ck setting is similar to ddr3. however, when operating in 2 t ck write preamble mode, cwl must be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range. when operating in 2 t ck write preamble mode, cwl must be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range. some even settings will require addition of 2 clocks. if the alternate longer cwl was used, the additional clocks will not be required. read preamble programmable read preamble t rpre can be set to 1 t ck or 2 t ck via the mr4 register. both the 1 t ck and 2 t ck ddr4 preamble settings are different from that defined for the ddr3 sdram. both ddr4 read preamble settings may require the memory controller to train (or read level) its data strobe receivers using the read preamble training. read preamble training programmable read preamble training can be set to 1 t ck or 2 t ck. this mode can be used by the memory controller to train or read level its data strobe receivers. temperature-controlled refresh when temperature-controlled refresh mode is enabled, the device may adjust the inter- nal refresh period to be longer than t refi of the normal temperature range by skipping external refresh commands with the proper gear ratio. for example, the dram tem- perature sensor detected less than 45c. normal temperature mode covers the range of 0c to 85c, while the extended temperature range covers 0c to 95c. command address latency command address latency (cal) is a power savings feature and can be enabled or disabled via the mrs setting. cal is defined as the delay in clock cycles ( t cal) be- tween a cs_n registered low and its corresponding registered command and address. the value of cal (in clocks) must be programmed into the mode register and is based on the roundup (in clocks) of [ t ck(ns)/ t cal(ns)]. internal v ref monitor the device generates its own internal v refdq . this mode may be enabled during v refdq training, and when enabled, v ref,time-short and v ref,time-long need to be increased by 10ns if dq0, dq1, dq2, or dq3 have 0pf loading. an additional 15ns per pf of loading is also needed. 8gb: x4, x8, x16 ddr4 sdram mode register 4 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
maximum power savings mode this mode provides the lowest power mode where data retention is not required. when the device is in the maximum power saving mode, it does not need to guarantee data retention or respond to any external command (except the maximum power saving mode exit command and during the assertion of reset_n signal low). 8gb: x4, x8, x16 ddr4 sdram mode register 4 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
mode register 5 mode register 5 (mr5) controls various device operating modes as shown in the follow- ing register definition table. not all settings listed may be available on a die; only set- tings required for speed bin support are available. mr5 is written by issuing the mrs command while controlling the states of the bg x, bax, and ax address pins. the map- ping of address pins during the mrs command is shown in the following mr5 register definition table. table 19: address pin mapping address bus bg1 bg0 ba1 ba0 a17 ras _n cas _n we _n a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register 2120191817CCC131211109876543210 note: 1. ras_n, cas_n, and we_n must be low during mode register set command. table 20: mr5 register definition mode register description 21 rfu 0 = must be programmed to 0 1 = reserved 20:18 mr select 000 = mr0 001 = mr1 010 = mr2 011 = mr3 100 = mr4 101 = mr5 110 = mr6 111 = dnu 17 n/a on 4gb and 8gb, rfu 0 = must be programmed to 0 1 = reserved 13 rfu 0 = must be programmed to 0 1 = reserved 12 data bus inversion (dbi) C read dbi enable 0 = disabled 1 = enabled 11 data bus inversion (dbi) C write dbi enable 0 = disabled 1 = enabled 10 data mask (dm) 0 = disabled 1 = enabled 8gb: x4, x8, x16 ddr4 sdram mode register 5 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 20: mr5 register definition (continued) mode register description 9 ca parity persistent error mode 0 = disabled 1 = enabled 8:6 parked odt value (r tt(park) ) 000 = r tt(park) disabled 001 = rzq/4 (60 ohm) 010 = rzq/2 (120 ohm) 011 = rzq/6 (40 ohm) 100 = rzq/1 (240 ohm) 101 = rzq/5 (48 ohm) 110 = rzq/3 (80 ohm) 111 = rzq/7 (34 ohm) 5 odt input buffer for power-down 0 = buffer enabled 1 = buffer disabled 4 ca parity error status 0 = clear 1 = error 3 crc error status 0 = clear 1 = error 2:0 ca parity latency mode 000 = disable 001 = 4 clocks (ddr4-1600/1866/2133) 010 = 5 clocks (ddr4-2400/2666) 1 011 = 6 clocks (ddr4-2933/3200) 100 = 8 clocks (ddr4-2933/3200) 101 = reserved 110 = reserved 111 = reserved note: 1. not allowed when 1/4 rate gear-down mode is enabled. data bus inversion the data bus inversion (dbi) function has been added to the device and is suppor- ted only for x8 and x16 configurations (x4 is not supported). the dbi function shares a common pin with the dm and tdqs functions. the dbi function applies to both read and write operations; write dbi cannot be enabled at the same time the dm function is enabled. refer to the tdqs function matrix table for valid configurations for all three functions (tdqs/dm/dbi). dbi is not allowed during mpr read operation; during an mpr read, the dram ignores the read dbi enable setting in mr5 bit a12. dbi is not al- lowed during mpr read operations. 8gb: x4, x8, x16 ddr4 sdram mode register 5 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
data mask the data mask (dm) function, also described as a partial write, has been added to the device and is supported only for x8 and x16 configurations (x4 is not supported). the dm function shares a common pin with the dbi and tdqs functions. the dm function applies only to write operations and cannot be enabled at the same time the write dbi function is enabled. refer to the tdqs function matrix table for valid configurations for all three functions (tdqs/dm/dbi). ca parity persistent error mode normal ca parity mode (ca parity persistent mode disabled) no longer performs ca parity checking while the parity error status bit remains set at 1. however, with ca pari- ty persistent mode enabled, ca parity checking continues to be performed when the parity error status bit is set to a 1. odt input buffer for power-down this feature determines whether the odt input buffer is on or off during power-down. if the input buffer is configured to be on (enabled during power-down), the odt input signal must be at a valid logic level. if the input buffer is configured to be off (disabled during power-down), the odt input signal may be floating and the device does not pro- vide r tt(nom) termination. however, the device may provide r tt(park) termination de- pending on the mr settings. this is primarily for additional power savings. ca parity error status the device will set the error status bit to 1 upon detecting a parity error. the parity error status bit remains set at 1 until the device controller clears it explicitly using an mrs command. crc error status the device will set the error status bit to 1 upon detecting a crc error. the crc error status bit remains set at 1 until the device controller clears it explicitly using an mrs command. ca parity latency mode ca parity is enabled when a latency value, dependent on t ck, is programmed; this ac- counts for parity calculation delay internal to the device. the normal state of ca parity is to be disabled. if ca parity is enabled, the device must ensure there are no parity er- rors before executing the command. ca parity signal (par) covers act_n, ras_n/a16 , cas_n/a15, we_n/a14, and the address bus including bank address and bank group bits. the control signals cke, odt, and cs_n are not included in the parity calculation. 8gb: x4, x8, x16 ddr4 sdram mode register 5 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
mode register 6 mode register 6 (mr6) controls various device operating modes as shown in the follow- ing register definition table. not all settings listed may be available on a die; only set- tings required for speed bin support are available. mr6 is written by issuing the mrs command while controlling the states of the bg x, bax, and ax address pins. the map- ping of address pins during the mrs command is shown in the following mr6 register definition table. table 21: address pin mapping address bus bg1 bg0 ba1 ba0 a17 ras _n cas _n we _n a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register 2120191817CCC131211109876543210 note: 1. ras_n, cas_n, and we_n must be low during mode register set command. table 22: mr6 register definition mode register description 21 rfu 0 = must be programmed to 0 1 = reserved 20:18 mr select 000 = mr0 001 = mr1 010 = mr2 011 = mr3 100 = mr4 101 = mr5 110 = mr6 111 = dnu 17 na on 4gb and 8gb, rfu 0 = must be programmed to 0 1 = reserved 13 rfu 0 = must be programmed to 0 1 = reserved 12:10 t ccd_l 000 = 4 clocks (1333 mb/s) 001 = 5 clocks (>1333 mb/s and 1866 mb/s) 010 = 6 clocks (>1866 mb/s and 2400 mb/s) 011 = 7 clocks (>2400 mb/s and 2666 mb/s) 100 = 8 clocks (>2666 mb/s and 3200 mb/s) 101 = reserved 110 = reserved 111 = reserved 8gb: x4, x8, x16 ddr4 sdram mode register 6 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 22: mr6 register definition (continued) mode register description 9, 8 rfu 0 = must be programmed to 0 1 = reserved 7 v ref calibration enable 0 = disable 1 = enable 6 v ref calibration range 0 = range 1 1 = range 2 5:0 v ref calibration value see the v refdq range and levels table in the v refdq calibration section t ccd_l programming the device controller must program the correct t ccd_l value. t ccd_l will be program- med according to the value defined per operating frequency in the ac parameter table. although jedec specifies the larger of 5 n ck or xns, micron's dram supports the larger of 4n ck or xns. v refdq calibration enable v refdq calibration is where the device internally generates its own v refdq to be used by the dq input receivers. the v refdq value will be output on any dq of dq[3:0] for evalu- ation only. the device controller is responsible for setting and calibrating the internal v refdq level using an mrs protocol (adjust up, adjust down, and so on). it is assumed that the controller will use a series of writes and reads in conduction with v refdq ad- justments to optimize and verify the data eye. enabling v refdq calibration must be used whenever values are being written to the mr6[6:0] register. v refdq calibration range the device defines two v refdq calibration ranges: range 1 and range 2. range 1 sup- ports v refdq between 60% and 92% of v ddq while range 2 supports v refdq between 45% and 77% of v ddq , as seen in v refdq specification table. although not a restriction, range 1 was targeted for module-based designs and range 2 was added to target point- to-point designs. v refdq calibration value fifty settings provide approximately 0.65% of granularity steps sizes for both range 1 and range 2 of v refdq , as seen in v refdq range and levels table in the v refdq calibra- tion section. 8gb: x4, x8, x16 ddr4 sdram mode register 6 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
truth tables table 23: truth table C command notes 1C5 apply to the entire table; note 6 applies to all read/write commands function symbol prev. cke pres. cke cs_n act_n ras_n/a16 cas_n/a15 we_n/a14 bg[1:0] ba [1:0] c[2:0] a12/bc_n a[13,11] a10/ap a[9:0] notes mode register set mrs h h l h l l l bg ba v op code 7 refresh ref h h l h l l h v v vvvvv self refresh entry sre h l l h l l h v v v v v v v 8, 9, 10 self refresh exit srx l h h x x x x x x x x x x x 8, 9, 10, 11 lhhhhvvvvvvv single-bank precharge pre h h l h l h l bg ba v v v l v precharge all banks prea h h l h l h l v v v v v h v reserved for future use rfu h h lhlhh rfu bank activate act h h l l row address (ra) bg ba v row address (ra) write bl8 fixed, bc4 fixed wr h h l h h l l bg ba v v v l ca bc4otf wrs4 h h l h h l l bg ba v l v l ca bl8otf wrs8 h h l h h l l bg ba v h v l ca write with auto precharge bl8 fixed, bc4 fixed wra h h l h h l l bg ba v v v h ca bc4otf wras4 h h l h h l l bg ba v l v h ca bl8otf wras8 h h l h h l l bg ba v h v h ca read bl8 fixed, bc4 fixed rd h h l h h l h bg ba v v v l ca bc4otf rds4 h h l h h l h bg ba v l v l ca bl8otf rds8 h h l h h l h bg ba v h v l ca read with auto precharge bl8 fixed, bc4 fixed rda h h l h h l h bg ba v v v h ca bc4otf rdas4 h h l h h l h bg ba v l v h ca bl8otf rdas8 h h l h h l h bg ba v h v h ca no operation nop h h l h h h h v v v v v v v 12 device deselected des h h h x x x x xxxxxxx 13 power-down entry pde h l h x x x x x x x x x x x 10, 14 power-down exit pdx l h h x x x x x xxxxxx 10, 14 zq calibration long zqcl h h l h h h l x x x x x h x zq calibration short zqcs h h l h h h l x x x x x l x 8gb: x4, x8, x16 ddr4 sdram truth tables 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
notes: 1. ? bg = bank group address ? ba = bank address ? ra = row address ? ca = column address ? bc_n = burst chop ? x = dont care ? v = valid 2. all ddr4 sdram commands are defined by states of cs_n, act_n, ras_n/a16, cas_n/ a15, we_n/a14, and cke at the rising edge of the clock. the msb of bg, ba, ra, and ca are device density- and configuration-dependent. when act_n = h, pins ras_n/a16, cas_n/a15, and we_n/a14 are used as command pins ras_n, cas_n, and we_n, respec- tively. when act_n = l, pins ras_n/a16, cas_n/a15, and we_n/a14 are used as address pins a16, a15, and a14, respectively. 3. reset_n is enabled low and is used only for asynchronous reset and must be main- tained high during any function. 4. bank group addresses (bg) and bank addresses (ba) determine which bank within a bank group is being operated upon. for mrs commands, the bg and ba selects the spe- cific mode register location. 5. v means high or low (but a defined logic level), and x means either defined or unde- fined (such as floating) logic level. 6. read or write bursts cannot be terminated or interrupted, and fixed/on-the-fly (otf) bl will be defined by mrs. 7. during an mrs command, a17 is rfu and is device density- and configuration-depend- ent. 8. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 9. v pp and v ref (v refca ) must be maintained during self refresh operation. 10. refer to the truth table C cke table for more details about cke transition. 11. controller guarantees self refresh exit to be synchronous. dram implementation has the choice of either synchronous or asynchronous. 12. the no operation (nop) command may be used only when exiting maximum power saving mode or when entering gear-down mode. 13. the nop command may not be used in place of the deselect command. 14. the power-down mode does not perform any refresh operation. 8gb: x4, x8, x16 ddr4 sdram truth tables 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 24: truth table C cke notes 1C7, 9, and 20 apply to the entire table current state cke command (n) action (n) notes previous cycle (n - 1) present cycle (n) power-down l l x maintain power-down 8, 10, 11 l h des power-down exit 8, 10, 12 self refresh l l x maintain self refresh 11, 13 l h des self refresh exit 8, 13, 14, 15 bank(s) active h l des active power-down entry 8, 10, 12, 16 reading h l des power-down entry 8, 10, 12, 16, 17 writing h l des power-down entry 8, 10, 12, 16, 17 precharging h l des power-down entry 8, 10, 12, 16, 17 refreshing h l des precharge power-down entry 8, 12 all banks idle h l des precharge power-down entry 8, 10, 12, 16, 18 h l refresh self refresh 16, 18, 19 notes: 1. current state is defined as the state of the ddr4 sdram immediately prior to clock edge n. 2. cke (n) is the logic state of cke at clock edge n; cke (n-1) was the state of cke at the previous clock edge. 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n); odt is not included here. 4. all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 6. during any cke transition (registration of cke h->l or cke h->l), the cke level must be maintained until 1 nck prior to t cke (min) being satisfied (at which time cke may tran- sition again). 7. deselect and nop are defined in the truth table C command table. 8. for power-down entry and exit parameters, see the power-down modes section. 9. cke low is allowed only if t mrd and t mod are satisfied. 10. the power-down mode does not perform any refresh operations. 11. x = "dont care" (including floating around v ref ) in self refresh and power-down. x al- so applies to address pins. 12. the deselect command is the only valid command for power-down entry and exit. 13. v pp and v refca must be maintained during self refresh operation. 14. on self refresh exit, the deselect command must be issued on every clock edge occur- ring during the t xs period. read or odt commands may be issued only after t xsdll is satisfied. 15. the deselect command is the only valid command for self refresh exit. 16. self refresh cannot be entered during read or write operations. for a detailed list of restrictions see the self refresh operation and power-down modes sections. 17. if all banks are closed at the conclusion of the read, write, or precharge command, then precharge power-down is entered; otherwise, active power-down is entered. 8gb: x4, x8, x16 ddr4 sdram truth tables 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
18. idle state is defined as all banks are closed ( t rp, t dal, and so on, satisfied), no data bursts are in progress, cke is high, and all timings from previous operations are satis- fied ( t mrd, t mod, t rfc, t zqinit, t zqoper, t zqcs, and so on), as well as all self refresh ex- it and power-down exit parameters are satisfied ( t xs, t xp, t xsdll, and so on). 19. self refresh mode can be entered only from the all banks idle state. 20. for more details about all signals, see the truth table C command table; must be a legal command as defined in the table. nop command the no operation (nop) command was originally used to instruct the selected ddr4 sdram to perform a nop (cs_n = low and act_n, ras_n/a16, cas_n/a15, and we_n/a14 = high). this prevented unwanted commands from being registered during idle or wait states. nop command general support has been removed and the com- mand should not be used unless specifically allowed, which is when exiting maximum power-saving mode or when entering gear-down mode. deselect command the deselect function (cs_n high) prevents new commands from being executed; therefore, with this command, the device is effectively deselected. operations already in progress are not affected. dll-off mode dll-off mode is entered by setting mr1 bit a0 to 0, which will disable the dll for sub- sequent operations until the a0 bit is set back to 1. the mr1 a0 bit for dll control can be switched either during initialization or during self refresh mode. refer to the input clock frequency change section for more details. the maximum clock frequency for dll-off mode is specified by the parameter t ckdll_off. there is no minimum frequency limit besides the need to satisfy the re- fresh interval, t refi. due to latency counter and timing restrictions, only one cl value and cwl value (in mr0 and mr2 respectively) are supported. the dll-off mode is only required to sup- port setting both cl = 10 and cwl = 9. dll-off mode will affect the read data clock-to-data strobe relationship ( t dqsck), but not the data strobe-to-data relationship ( t dqsq, t qh). special attention is needed to line up read data to the controller time domain. compared with dll-on mode, where t dqsck starts from the rising clock edge (al + cl) cycles after the read command, the dll-off mode t dqsck starts (al + cl - 1) cy- cles after the read command. another difference is that t dqsck may not be small compared to t ck (it might even be larger than t ck), and the difference between t dqsck (min) and t dqsck (max) is significantly larger than in dll-on mode. the t dqsck (dll-off ) values are vendor-specific. the timing relations on dll-off mode read operation are shown in the following dia- gram, where cl = 10, al = 0, and bl = 8. 8gb: x4, x8, x16 ddr4 sdram nop command 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 18: dll-off mode read timing operation ck_c ck_t command t0 t1 t6 t7 t8 t9 t10 t11 t12 t13 t14 address dqs_t, dqs_c (dll-on) dqs_c (dll-on) cl = 10, al = 0 cl = 10, al = 0 rl (dll-on) = al + cl = 10 rl (dll-off) = al + (cl - 1) = 9 t dqsck (dll-off) max t dqsck (dll-off) min t dqsck (max) dqs_t, dqs_c (dll-off) dqs_c (dll-off) dqs_c (dll-off) dqs_t, dqs_c (dll-off) rd des des des des des des des des des des dont care transitioning data d in b ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) d in b+1 d in b+2 d in b+3 d in b+4 d in b+5 d in b+6 d in b+7 d in b d in b+1 d in b+2 d in b+3 d in b+4 d in b+5 d in b+6 d in b+7 d in b d in b+1 d in b+2 d in b+3 d in b+4 d in b+5 d in b+6 d in b+7 ( ) ( ) t dqsck (min) a rd 8gb: x4, x8, x16 ddr4 sdram dll-off mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
dll-on/off switching procedures the dll-off mode is entered by setting mr1 bit a0 to 0; this will disable the dll for subsequent operations until the a0 bit is set back to 1. dll switch sequence from dll-on to dll-off to switch from dll-on to dll-off requires the frequency to be changed during self re- fresh, as outlined in the following procedure: 1. starting from the idle state (all banks pre-charged, all timings fulfilled, and, to dis- able the dll, the dram on-die termination resistors, r tt(nom) , must be in high-z before mrs to mr1.) 2. set mr1 bit a0 to 1 to disable the dll. 3. wait t mod. 4. enter self refresh mode; wait until t cksre/ t cksre_par is satisfied. 5. change frequency, following the guidelines in the input clock frequency change section. 6. wait until a stable clock is available for at least t cksrx at device inputs. 7. starting with the self refresh exit command, cke must continuously be regis- tered high until all t mod timings from any mrs command are satisfied. in addi- tion, if any odt features were enabled in the mode registers when self refresh mode was entered, the odt signal must continuously be registered low until all t mod timings from any mrs command are satisfied. if r tt(nom) was disabled in the mode registers when self refresh mode was entered, the odt signal is "don't care." 8. wait t xs_fast, t xs_abort, or t xs, and then set mode registers with appropriate values (an update of cl, cwl, and wr may be necessary; a zqcl command can also be issued after t xs_fast). ? t xs_fast: zqcl, zqcs, and mrs commands. for mrs commands, only cl and wr/rtp registers in mr0, the cwl register in mr2, and gear-down mode in mr3 may be accessed provided the device is not in per-dram addressability mode. access to other device mode registers must satisfy t xs timing. ? t xs_abort: if mr4 [9] is enabled, then the device aborts any ongoing refresh and does not increment the refresh counter. the controller can issue a valid command after a delay of t xs_abort. upon exiting from self refresh, the device requires a minimum of one extra refresh command before it is put back into self refresh mode. this requirement remains the same regardless of the mrs bit setting for self refresh abort. ? t xs: act, pre, prea, ref, sre, pde, wr, wrs4, wrs8, wra, wras4, wras8, rd, rds4, rds8, rda, rdas4, and rdas8. 9. wait t mod to complete. the device is ready for the next command. 8gb: x4, x8, x16 ddr4 sdram dll-on/off switching procedures 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 19: dll switch sequence from dll-on to dll-off ck_c ck_t ta tb0 tb1 tc td te0 te1 tf tg th dont care time break cke command enter self refresh exit self refresh odt valid sre 3 des srx 6 valid valid valid valid mrs 2 t xs_fast t xs_abort t rp t xs note 4 t cpded t is t cksre/ t cksre_par t cksrx 5 valid address valid valid 7 valid 8 valid 9 t is t ckesr/ t ckesr_par notes: 1. starting in the idle state. r tt in stable state. 2. disable dll by setting mr1 bit a0 to 0. 3. enter sr. 4. change frequency. 5. clock must be stable t cksrx. 6. exit sr. 7. update mode registers allowed with dll-off settings met. 8gb: x4, x8, x16 ddr4 sdram dll-on/off switching procedures 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
dll-off to dll-on procedure to switch from dll-off to dll-on (with required frequency change) during self refresh: 1. starting from the idle state (all banks pre-charged, all timings fulfilled, and dram odt resistors (r tt(nom) ) must be in high-z before self refresh mode is entered.) 2. enter self refresh mode; wait until t cksre/ t cksre_par are satisfied. 3. change frequency (following the guidelines in the input clock frequency change section). 4. wait until a stable clock is available for at least t cksrx at device inputs. 5. starting with the self refresh exit command, cke must continuously be regis- tered high until t dllk timing from the subsequent dll reset command is sat- isfied. in addition, if any odt features were enabled in the mode registers when self refresh mode was entered, the odt signal must continuously be registered low or high until t dllk timing from the subsequent dll reset command is satisfied. if r tt(nom) disabled in the mode registers when self refresh mode was entered, the odt signal is "don't care." 6. wait t xs or t xs_abort, depending on bit 9 in mr4, then set mr1 bit a0 to 0 to en- able the dll. 7. wait t mrd, then set mr0 bit a8 to 1 to start dll reset. 8. wait t mrd, then set mode registers with appropriate values; an update of cl, cwl, and wr may be necessary. after t mod is satisfied from any proceeding mrs command, a zqcl command can also be issued during or after t dllk. 9. wait for t mod to complete. remember to wait t dllk after dll reset before ap- plying any command requiring a locked dll. in addition, wait for t zqoper in case a zqcl command was issued. the device is ready for the next command. figure 20: dll switch sequence from dll-off to dll-on ck_c ck_t ta tb0 tb1 tc td te0 te1 tf tg th dont care time break cke command enter self refresh exit self refresh odt valid sre 3 des srx 6 valid valid valid valid mrs 2 t xs_abort t rp t xs t mrd note 4 note 1 t cpded t is t cksre/ t cksre_par t cksrx 5 valid address valid valid 7 t is valid 7 valid 7 t ckesr/ t ckesr_par notes: 1. starting in the idle state. 8gb: x4, x8, x16 ddr4 sdram dll-on/off switching procedures 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
2. enter sr. 3. change frequency. 4. clock must be stable t cksrx. 5. exit sr. 6. set dll to on by setting mr1 to a0 = 0. 7. update mode registers. 8. issue any valid command. input clock frequency change after the device is initialized, it requires the clock to be stable during almost all states of normal operation. this means that after the clock frequency has been set and is in the stable state, the clock period is not allowed to deviate except for what is allowed by the clock jitter and spread spectrum clocking (ssc) specifications. the input clock frequen- cy can be changed from one stable clock rate to another stable clock rate only when in self refresh mode. outside of self refresh mode, it is illegal to change the clock frequen- cy. after the device has been successfully placed in self refresh mode and t cksre/ t cksre_par have been satisfied, the state of the clock becomes a "dont care." follow- ing a "dont care," changing the clock frequency is permissible, provided the new clock frequency is stable prior to t cksrx. when entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the self refresh entry and exit specifica- tions must still be met as outlined in self refresh operation. for the new clock frequency, additional mrs commands to mr0, mr2, mr3, mr4, mr5, and mr6 may need to be issued to program appropriate cl, cwl, gear-down mode, read and write preamble, command address latency, and t ccd_l/ t dllk values. when the clock rate is being increased (faster), the mr settings that require additional clocks should be updated prior to the clock rate being increased. in particular, the pl latency must be disabled when the clock rate changes, ie. while in self refresh mode. for example, if changing the clock rate from ddr4-2133 to ddr4-2933 with ca parity mode enabled, mr5[2:0] must first change from pl = 4 to pl = disable prior to pl = 6. the correct procedure would be to (1) change pl = 4 to disable via mr5 [2:0], (2) enter self refresh mode, (3) change clock rate from ddr4-2133 to ddr4-2933, (4) exit self re- fresh mode, (5) enable ca parity mode setting pl = 6 vis mr5 [2:0]. if the mr settings that require additional clocks are updated after the clock rate has been increased, for example. after exiting self refresh mode, the required mr settings must be updated prior to removing the dram from the idle state, unless the dram is reset. if the dram leaves the idle state to enter self refresh mode or zq calibration, the updating of the required mr settings may be deferred to the next time the dram enters the idle state. if mr6 is issued prior to self refresh entry for new the t dllk value, dll will relock auto- matically at self refresh exit. however, if mr6 is issued after self refresh entry, mr0 must be issued to reset the dll. the device input clock frequency can change only within the minimum and maximum operating frequency specified for the particular speed grade. any frequency change be- low the minimum operating frequency would require the use of dll-on mode to dll- off mode transition sequence (see dll-on/off switching procedures). 8gb: x4, x8, x16 ddr4 sdram input clock frequency change 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
write leveling for better signal integrity, ddr4 memory modules use fly-by topology for the com- mands, addresses, control signals, and clocks. fly-by topology has benefits from the re- duced number of stubs and their length, but it also causes flight-time skew between clock and strobe at every dram on the dimm. this makes it difficult for the controller to maintain t dqss, t dss, and t dsh specifications. therefore, the device supports a write leveling feature to allow the controller to compensate for skew. this feature may not be required under some system conditions, provided the host can maintain the t dqss, t dss, and t dsh specifications. the memory controller can use the write leveling feature and feedback from the device to adjust the dqs (dqs_t, dqs_c) to ck (ck_t, ck_c) relationship. the memory con- troller involved in the leveling must have an adjustable delay setting on dqs to align the rising edge of dqs with that of the clock at the dram pin. the dram asynchronously feeds back ck, sampled with the rising edge of dqs, through the dq bus. the controller repeatedly delays dqs until a transition from 0 to 1 is detected. the dqs delay estab- lished though this exercise would ensure the t dqss specification. besides t dqss, t dss and t dsh specifications also need to be fulfilled. one way to achieve this is to combine the actual t dqss in the application with an appropriate duty cycle and jitter on the dqs signals. depending on the actual t dqss in the application, the actual values for t dqsl and t dqsh may have to be better than the absolute limits provided in the ac timing parameters section in order to satisfy t dss and t dsh specifications. a conceptual tim- ing of this scheme is shown below. figure 21: write leveling concept, example 1 diff_dqs diff_dqs dq diff_dqs dq t0 t1 t2 t3 t4 t5 ck_c ck_t t6 t7 tn t0 t1 t2 t3 t4 ck_c ck_t t5 t6 0 or 1 00 0 0 or 1 push dqs to capture the 0-1 transition 111 source destination dqs driven by the controller during leveling mode must be terminated by the dram based on the ranks populated. similarly, the dq bus driven by the dram must also be terminated at the controller. all data bits carry the leveling feedback to the controller across the dram configura- tions: x4, x8, and x16. on a x16 device, both byte lanes should be leveled independently. therefore, a separate feedback mechanism should be available for each byte lane. the upper data bits should provide the feedback of the upper diff_dqs(diff_udqs)-to- clock relationship; the lower data bits would indicate the lower diff_dqs(diff_ldqs)- to-clock relationship. 8gb: x4, x8, x16 ddr4 sdram write leveling 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 77 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
the figure below is another representative way to view the write leveling procedure. al- though it shows the clock varying to a static strobe, this is for illustrative purpose only; the clock does not actually change phase, the strobe is what actually varies. by issuing multiple wl bursts, the dqs strobe can be varied to capture with fair accuracy the time at which the clock edge arrives at the dram clock input buffer. figure 22: write leveling concept, example 2 x xx ck_t ck_c ck_t ck_c ck_t ck_c dqs_t/ dqs_c dq (ck 0 to 1) t wlh t wlh t wlo t wls t wls 000 000 000 0 000 000 0 000 x xx 1111 11 111 11 11 11 111 1 11 11 11 111 dq (ck 1 to 0) dram setting for write leveling and dram termination function in that mode the dram enters into write leveling mode if a7 in mr1 is high. when leveling is fin- ished, the dram exits write leveling mode if a7 in mr1 is low (see the mr leveling procedures table). note that in write leveling mode, only dqs terminations are activa- ted and deactivated via the odt pin, unlike normal operation (see dram dram ter- mination function in leveling mode table). table 25: mr settings for leveling procedures function mr1 enable disable write leveling enable a7 1 0 output buffer mode (q off) a12 0 1 table 26: dram termination function in leveling mode odt pin at dram dqs_t/dqs_c termination dq termination r tt(nom) with odt high on off 8gb: x4, x8, x16 ddr4 sdram write leveling 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 78 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 26: dram termination function in leveling mode (continued) odt pin at dram dqs_t/dqs_c termination dq termination r tt(park) with odt low on off notes: 1. in write leveling mode, with the mode's output buffer either disabled (mr1[bit7] = 1 and mr1[bit12] = 1) or with its output buffer enabled (mr1[bit7] = 1 and mr1[bit12] = 0), all r tt(nom) and r tt(park) settings are supported. 2. r tt(wr) is not allowed in write leveling mode and must be set to disable prior to enter- ing write leveling mode. procedure description the memory controller initiates the leveling mode of all dram by setting bit 7 of mr1 to 1. when entering write leveling mode, the dq pins are in undefined driving mode. during write leveling mode, only the deselect command is supported, other than mrs commands to change the qoff bit (mr1[a12]) and to exit write leveling (mr1[a7]). upon exiting write leveling mode, the mrs command performing the exit (mr1[a7] = 0) may also change the other mr1 bits. because the controller levels one rank at a time, the output of other ranks must be disabled by setting mr1 bit a12 to 1. the controller may assert odt after t mod, at which time the dram is ready to accept the odt signal, unless dodtlon or dodtloff have been altered (the odt internal pipe delay is in- creased when increasing write latency [wl] or read latency [rl] by the previous mr command), then odt assertion should be delayed by dodtlon after t mod is satisfied, which means the delay is now t mod + dodtlon. the controller may drive dqs_t low and dqs_c high after a delay of t wldqsen, at which time the dram has applied odt to these signals. after t dqsl and t wlmrd, the controller provides a single dqs_t, dqs_c edge, which is used by the dram to sample ck driven from the controller. t wlmrd (max) timing is controller dependent. the dram samples ck status with the rising edge of dqs and provides feedback on all the dq bits asynchronously after t wlo timing. there is a dq output uncertainty of t wloe defined to allow mismatch on dq bits. the t wloe period is defined from the transition of the earliest dq bit to the corresponding transition of the latest dq bit. there are no read strobes (dqs_t, dqs_c) needed for these dqs. the controller sam- ples incoming dq and either increments or decrements dqs delay setting and launch- es the next dqs pulse after some time, which is controller dependent. after a 0-to-1 transition is detected, the controller locks the dqs delay setting, and write leveling is achieved for the device. the following figure shows the timing diagram and parameters for the overall write leveling procedure. 8gb: x4, x8, x16 ddr4 sdram write leveling 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 79 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 23: write leveling sequence (dqs capturing ck low at t1 and ck high at t2) t mod t wldqsen t wlmrd t wlh t dqsh 6 t dqsl 6 t dqsh 6 t dqsl 6 t wls t wlh t wls nop ck_t ck_c 5 command t1 t2 early prime dq 1 odt late prime dq 1 diff_dqs 4 des mrs 2 des des des des des des des des des dont care undefined driving mode time break t wlo t wlo t wlo t wlo t wloe t wloe des 3 notes: 1. the device drives leveling feedback on all dqs. 2. mrs: load mr1 to enter write leveling mode. 3. diff_dqs is the differential data strobe. timing reference points are the zero crossings. dqs_t is shown with a solid line; dqs_c is shown with a dotted line. 4. ck_t is shown with a solid dark line; ck_c is shown with a dotted line. 5. dqs needs to fulfill minimum pulse width requirements, t dqsh (min) and t dqsl (min), as defined for regular writes; the maximum pulse width is system dependent. 6. t wldqsen must be satisfied following equation when using odt: ? dll = enable, then t wldqsen > t mod (min) + dodtlon + t adc ? dll = disable, then t wldqsen > t mod (min) + t aonas write leveling mode exit write leveling mode should be exited as follows: 1. after the last rising strobe edge (see ~t0), stop driving the strobe signals (see ~tc0). note that from this point on, dq pins are in undefined driving mode and will remain undefined, until t mod after the respective mr command (te1). 2. drive odt pin low ( t is must be satisfied) and continue registering low (see tb0). 3. after r tt is switched off, disable write leveling mode via the mrs command (see tc2). 4. after t mod is satisfied (te1), any valid command can be registered. (mr com- mands can be issued after t mrd [td1]). 8gb: x4, x8, x16 ddr4 sdram write leveling 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 80 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 24: write leveling exit t mod t wlo odtl (off) t is t mrd ck_t t0 t1 t2 ta0 tb0 tc0 tc1 tc2 td0 td1 te0 te1 ck_c command odt r tt(dqs_t) r tt(dqs_c) r tt(dq) dq 1 dqs_t, dqs_c des des des des des des des des des address mr1 valid valid valid valid dont care transitioning time break r tt(non) undefined driving mode t adc (max) t adc (min) des r tt(park) result = 1 notes: 1. the dq result = 1 between ta0 and tc0 is a result of the dqs signals capturing ck_t high just after the t0 state. 2. see previous figure for specific t wlo timing. 8gb: x4, x8, x16 ddr4 sdram write leveling 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 81 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
command address latency ddr4 supports the command address latency (cal) function as a power savings fea- ture. this feature can be enabled or disabled via the mrs setting. cal timing is defined as the delay in clock cycles ( t cal) between a cs_n registered low and its correspond- ing registered command and address. the value of cal in clocks must be programmed into the mode register (see mr1 register definition table) and is based on the equation t ck(ns)/ t cal(ns), rounded up in clocks. figure 25: cal timing definition clk cmd/addr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cs_n t cal cal gives the dram time to enable the command and address receivers before a com- mand is issued. after the command and the address are latched, the receivers can be disabled if cs_n returns to high. for consecutive commands, the dram will keep the command and address input receivers enabled for the duration of the command se- quence. figure 26: cal timing example (consecutive cs_n = low) clk cmd/addr 123456789101112 cs_n 8gb: x4, x8, x16 ddr4 sdram command address latency 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 82 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
when the cal mode is enabled, additional time is required for the mrs command to complete. the earliest the next valid command can be issued is t mod_cal, which should be equal to t mod + t cal. the two following figures are examples. figure 27: cal enable timing C t mod_cal t0 t1 ta0 ta1 ta2 ck_c ck_t address cs_n settings command ta3 ta4 old settings mrs valid des des des des valid valid valid valid valid valid valid valid dont care time break tb0 tb1 tb2 tb3 new settings valid valid valid valid valid t mod_cal t cal updating settings des des des note: 1. cal mode is enabled at t1. figure 28: t mod_cal, mrs to valid command timing with cal enabled t0 t1 ta0 ta1 ta2 ck_c ck_t address cs_n settings command tb0 tb1 old settings valid des des des des valid valid valid valid valid valid valid valid dont care time break tb2 tc0 tc1 tc2 new settings valid valid valid t mod_cal t cal t cal updating settings des des des mrs valid valid note: 1. mrs at ta1 may or may not modify cal, t mod_cal is computed based on new t cal set- ting if modified. 8gb: x4, x8, x16 ddr4 sdram command address latency 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 83 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
when the cal mode is enabled or being enabled, the earliest the next mrs command can be issued is t mrd_cal is equal to t mod + t cal. the two following figures are ex- amples. figure 29: cal enabling mrs to next mrs command, t mrd_cal t0 t1 ta0 ta1 ta2 ck_c ck_t address cs_n settings command ta3 ta4 old settings mrs mrs valid des des des des des valid valid valid valid valid valid valid valid dont care time break tb0 tb1 tb2 tb3 valid valid valid t mrd_cal t cal updating settings updating settings des des des note: 1. command address latency mode is enabled at t1. figure 30: t mrd_cal, mode register cycle time with cal enabled 7 7 7d 7d 7d ck_c ck_t address cs_n settings command 7e 7e 2ogvhwwlqjv 9dolg '(6 '(6 '(6 '(6 9dolg 9dolg 9dolg 9dolg 9dolg 9dolg 9dolg 9dolg 'rq?w&duh 7lph%uhdn 7e 7f 7f 7f 1hzvhwwlqjv 9dolg 9dolg 9dolg w 05'b&$/ w &$/ w &$/ 8sgdwlqjvhwwlqjv '(6 '(6 '(6 056 '(6 056 note: 1. mrs at ta1 may or may not modify cal, t mrd_cal is computed based on new t cal set- ting if modified. cal examples: consecutive read bl8 with two different cals and 1 t ck preamble in different bank group shown in the following figures. 8gb: x4, x8, x16 ddr4 sdram command address latency 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 84 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 31: consecutive read bl8, cal3, 1 t ck preamble, different bank group d out n d out n + 1 d out n + 2 d out n + 3 rl = 11 rl = 11 t0 t1 t2 t3 t4 t5 t6 t7 t14 t13 t cal = 3 t15 t16 dont care transitioning data t17 t18 t19 t20 t21 t22 bank, col n t rpst des des des des des des des des des des des des des des read read ck_t ck_c command cs_n dq dqs_t, dqs_c address bank group address t cal = 3 t ccd_s = 4 bg a bank, col b bg b t rpre (1nck) d out n + 4 d out n + 5 d out n + 6 d out n + 7 d out b d out b + 7 d out b + 2 d out b + 3 d out b + 4 d out b + 5 d out b + 6 d out b + 7 notes: 1. bl = 8, al = 0, cl = 11, cal = 3, preamble = 1 t ck. 2. d out n = data-out from column n; d out b = data-out from column b. 3. des commands are shown for ease of illustration, other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during read command at t3 and t7. 5. ca parity = disable, cs to ca latency = enable, read dbi = disable. 6. enabling cal mode does not impact odt control timings. odt control timings should be maintained with the same timing relationship relative to the command/address bus as when cal is disabled. figure 32: consecutive read bl8, cal4, 1 t ck preamble, different bank group ' 287 q ' 287 q ' 287 q ' 287 q 5/ 5/ 7 7 7 7 7 7 7 7 7 7 w &$/ 7 7 'rq?w&duh 7udqvlwlrqlqj'dwd 7 7 7 7 7 7 7 %dqn &roq w 5367 '(6 '(6 '(6 '(6 '(6 '(6 '(6 '(6 '(6 '(6 '(6 '(6 '(6 '(6 '(6 '(6 5($' 5($' &.bw &.bf &rppdqg &6bq '4 '46bw'46bf $gguhvv %dqn*urxs $gguhvv w &$/ w &&'b6 %*d %dqn &roe %*e w 535(q&. ' 287 q ' 287 q ' 287 q ' 287 q ' 287 e ' 287 e ' 287 e ' 287 e ' 287 e ' 287 e ' 287 e ' 287 e notes: 1. bl = 8, al = 0, cl = 11, cal = 4, preamble = 1 t ck. 2. d out n = data-out from column n; d out b = data-out from column b. 3. des commands are shown for ease of illustration, other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during read command at t4 and t8. 8gb: x4, x8, x16 ddr4 sdram command address latency 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 85 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
5. ca parity = disable, cs to ca latency = enable, read dbi = disable. 6. enabling cal mode does not impact odt control timings. odt control timings should be maintained with the same timing relationship relative to the command/address bus as when cal is disabled. 8gb: x4, x8, x16 ddr4 sdram command address latency 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 86 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
low-power auto self refresh mode an auto self refresh mode is provided for application ease. auto self refresh mode is en- abled by setting mr2[6] = 1 and mr2[7] = 1. the device will manage self refresh entry over the supported temperature range of the dram. in this mode, the device will change its self refresh rate as the dram operating temperature changes, going lower at low temperatures and higher at high temperatures. manual self refresh mode if auto self refresh mode is not enabled, the low-power auto self refresh mode register must be manually programmed to one of the three self refresh operating modes. this mode provides the flexibility to select a fixed self refresh operating mode at the entry of the self refresh, according to the system memory temperature conditions. the user is responsible for maintaining the required memory temperature condition for the mode selected during the self refresh operation. the user may change the selected mode after exiting self refresh and before entering the next self refresh. if the temperature condition is exceeded for the mode selected, there is a risk to data retention resulting in loss of data. table 27: auto self refresh mode mr2[7] mr2[6] low-power auto self refresh mode self refresh operation operating temperature range for self refresh mode (dram t case ) 0 0 normal fixed normal self refresh rate maintains data retention at the normal operating tempera- ture. user is required to ensure that 85c dram t case (max) is not exceeded to avoid any risk of data loss. 0c to 85c 1 0 extended temperature fixed high self refresh rate optimizes data re- tention to support the extended tempera- ture range. 0c to 95c 0 1 reduced temperature variable or fixed self refresh rate or any oth- er dram power consumption reduction con- trol for the reduced temperature range. user is required to ensure 45c dram t case (max) is not exceeded to avoid any risk of data loss. 0c to 45c 1 1 auto self refresh auto self refresh mode enabled. self refresh power consumption and data retention are optimized for any given operating tempera- ture condition. all of the above 8gb: x4, x8, x16 ddr4 sdram low-power auto self refresh mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 87 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 33: auto self refresh ranges 45c 25c i dd6 tc 85c 95c reduced temperature range normal temperature range 2x refresh rate 1x refresh rate 1/2x refresh rate extended temperature range 8gb: x4, x8, x16 ddr4 sdram low-power auto self refresh mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 88 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
multipurpose register the multipurpose register (mpr) function, mpr access mode, is used to write/ read specialized data to/from the dram. the mpr consists of four logical pages, mpr page 0 through mpr page 3, with each page having four 8-bit registers, mpr0 through mpr3. page 0 can be read by any of three readout modes (serial, parallel, or staggered) while pages 1, 2, and 3 can be read by only the serial readout mode. page 3 is for dram vendor use only. mpr mode enable and page selection is done with mrs commands. data bus inversion (dbi) is not allowed during mpr read operation. once the mpr access mode is enabled (mr3[2] = 1), only the following commands are allowed: mrs, rd, rda wr, wra, des, ref, and reset; rda/wra have the same func- tionality as rd/wr which means the auto precharge part of rda/wra is ignored. pow- er-down mode and self refresh command are not allowed during mpr enable mode. no other command can be issued within t rfc after a ref command has been issued; 1x refresh (only) is to be used during mpr access mode. while in mpr access mode, mpr read or write sequences must be completed prior to a refresh command. figure 34: mpr block diagram memory core (all banks precharged) mr3 [2] = 1 dq,s dm_n/dbi_n, dqs_t, dqs_c four multipurpose registers (pages), each with four 8-bit registers: data patterns (rd/wr) error log (rd) mode registers (rd) dram manufacture only (rd) m p r d a t a f l o w table 28: mr3 setting for the mpr access mode address operation mode description a[12:11] mpr data read format 00 = serial ........... 01 = parallel 10 = staggered .... 11 = reserved a2 mpr access 0 = standard operation (mpr not enabled) 1 = mpr data flow enabled a[1:0] mpr page selection 00 = page 0 .... 01 = page 1 10 = page 2 .... 11 = page 3 table 29: dram address to mpr ui translation mpr location [7] [6] [5] [4] [3] [2] [1] [0] dram address C ax a7 a6 a5 a4 a3 a2 a1 a0 mpr ui C uix ui0 ui1 ui2 ui3 ui4 ui5 ui6 ui7 8gb: x4, x8, x16 ddr4 sdram multipurpose register 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 89 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 30: mpr page and mpr x definitions address mpr location [7] [6] [5] [4] [3] [2] [1] [0] note mpr page 0 C read or write (data patterns) ba[1:0] 00 = mpr0 01010 1 01 read/ write (default value lis- ted) 01 = mpr1 00110 0 11 10 = mpr2 00001 1 11 11 = mpr3 00000 0 00 mpr page 1 C read-only (error log) ba[1:0] 00 = mpr0 a7 a6 a5 a4 a3 a2 a1 a0 read-on- ly 01 = mpr1 cas_n/a 15 we_n/a1 4 a13 a12 a11 a10 a9 a8 10 = mpr2 par act_n bg1 bg0 ba1 ba0 a17 ras_n/a 16 11 = mpr3 crc er- ror sta- tus ca pari- ty error status ca parity latency: [5] = mr5[2], [4] = mr5[1], [3] = mr5[0] c2 c1 c0 mpr page 2 C read-only (mrs readout) ba[1:0] 00 = mpr0 hppr support sppr support r tt(wr) mr2[11] temperature sen- sor status 2 crc write enable mr2[12] r tt(wr) mr2[10:9] read-on- ly 01 = mpr1 v refdq traing- ing range mr6[6] v refdq training value: [6:1] = mr6[5:0] gear- down enable mr3[3] 10 = mpr2 cas latency: [7:3] = mr0[6:4,2,12] cas write latency [2:0] = mr2[5:3] 11 = mpr3 r tt(nom) : [7:5] = mr1[10:8] r tt(park) : [4:2] = mr5[8:6] r on : [1:0] = mr2[2:1] mpr page 3 C read-only (restricted, except for mpr3 [3:0]) ba[1:0] 00 = mpr0 dc dc dc dc dc dc dc dc read-on- ly 01 = mpr1 dc dc dc dc dc dc dc dc 10 = mpr2 dc dc dc dc dc dc dc dc 11 = mpr3 dc dc dc dc mac mac mac mac notes: 1. dc = "don't care" 2. mpr[4:3] 00 = sub 1x refresh; mpr[4:3] 01 = 1x refresh; mpr[4:3] 10 = 2x refresh; mpr[4:3] 11 = reserved mpr reads mpr reads are supported using bl8 and bc4 modes. burst length on-the-fly is not sup- ported for mpr reads. data bus inversion (dbi) is not allowed during mpr read opera- tion; the device will ignore the read dbi enable setting in mr5 [12] when in mpr mode. read commands for bc4 are supported with a starting column address of a[2:0] = 000 8gb: x4, x8, x16 ddr4 sdram multipurpose register 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 90 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
or 100. after power-up, the content of mpr page 0 has the default values, which are de- fined in table 30. mpr page 0 can be rewritten via an mpr write command. the de- vice maintains the default values unless it is rewritten by the dram controller. if the dram controller does overwrite the default values (page 0 only), the device will main- tain the new values unless re-initialized or there is power loss. timing in mpr mode: ? reads (back-to-back) from page 0 may use t ccd_s or t ccd_l timing between read commands ? reads (back-to-back) from pages 1, 2, or 3 may not use t ccd_s timing between read commands; t ccd_l must be used for timing between read commands the following steps are required to use the mpr to read out the contents of a mode reg- ister (mpr page x, mpry). 1. the dll must be locked if enabled. 2. precharge all; wait until t rp is satisfied. 3. mrs command to mr3[2] = 1 (enable mpr data flow), mr3[12:11] = mpr read for- mat, and mr3[1:0] mpr page. a. mr3[12:11] mpr read format: 1. 00 = serial read format 2. 01 = parallel read format 3. 10 = staggered read format 4. 11 = rfu b. mr3[1:0] mpr page: 1. 00 = mpr page 0 2. 01 = mpr page 1 3. 10 = mpr page 2 4. 11 = mpr page 3 4. t mrd and t mod must be satisfied. 5. redirect all subsequent read commands to specific mpr x location. 6. issue rd or rda command. a. ba1 and ba0 indicate mpr x location: 1. 00 = mpr0 2. 01 = mpr1 3. 10 = mpr2 4. 11 = mpr3 b. a12/bc = 0 or 1; bl8 or bc4 fixed-only, bc4 otf not supported. 1. if bl = 8 and mr0 a[1:0] = 01, a12/bc must be set to 1 during mpr read commands. c. a2 = burst-type dependant: 1. bl8: a2 = 0 with burst order fixed at 0, 1, 2, 3, 4, 5, 6, 7 2. bl8: a2 = 1 not allowed 3. bc4: a2 = 0 with burst order fixed at 0, 1, 2, 3, t, t, t, t 4. bc4: a2 = 1 with burst order fixed at 4, 5, 6, 7, t, t, t, t d. a[1:0] = 00, data burst is fixed nibble start at 00. e. remaining address inputs, including a10, and bg1 and bg0 are "dont care." 7. after rl = al + cl, dram bursts data from mpr x location; mpr readout format determined by mr3[a12,11,1,0]. 8. steps 5 through 7 may be repeated to read additional mpr x locations. 9. after the last mpr x read burst, t mprr must be satisfied prior to exiting. 10. issue mrs command to exit mpr mode; mr3[2] = 0. 8gb: x4, x8, x16 ddr4 sdram multipurpose register 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 91 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
11. after the t mod sequence is completed, the dram is ready for normal operation from the core (such as act). mpr readout format the mpr read data format can be set to three different settings: serial, parallel, and staggered. mpr readout serial format the serial format is required when enabling the mpr function to read out the contents of an mrx , temperature sensor status, and the command address parity error frame. however, data bus calibration locations (four 8-bit registers) can be programmed to read out any of the three formats. the dram is required to drive associated strobes with the read data similar to normal operation (such as using mrs preamble settings). serial format implies that the same pattern is returned on all dq lanes, as shown the table below, which uses values programmed into the mpr via [7:0] as 0111 1111. table 31: mpr readout serial format serial ui0 ui1 ui2 ui3 ui4 ui5 ui6 ui7 x4 device dq0 01111111 dq1 01111111 dq2 01111111 dq3 01111111 x8 device dq0 01111111 dq1 01111111 dq2 01111111 dq3 01111111 dq4 01111111 dq5 01111111 dq6 01111111 dq7 01111111 x16 device dq0 01111111 dq1 01111111 dq2 01111111 dq3 01111111 dq4 01111111 dq5 01111111 dq6 01111111 dq7 01111111 dq8 01111111 8gb: x4, x8, x16 ddr4 sdram multipurpose register 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 92 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 31: mpr readout serial format (continued) serial ui0 ui1 ui2 ui3 ui4 ui5 ui6 ui7 dq9 01111111 dq10 0 1 1 1 1 1 1 1 dq11 0 1 1 1 1 1 1 1 dq12 0 1 1 1 1 1 1 1 dq13 0 1 1 1 1 1 1 1 dq14 0 1 1 1 1 1 1 1 dq15 0 1 1 1 1 1 1 1 mpr readout parallel format parallel format implies that the mpr data is returned in the first data ui and then repea- ted in the remaining uis of the burst, as shown in the table below. data pattern location 0 is the only location used for the parallel format. rd/rda from data pattern locations 1, 2, and 3 are not allowed with parallel data return mode. in this example, the pattern programmed in the data pattern location 0 is 0111 1111. the x4 configuration only out- puts the first four bits (0111 in this example). for the x16 configuration, the same pat- tern is repeated on both the upper and lower bytes. table 32: mpr readout C parallel format parallel ui0 ui1 ui2 ui3 ui4 ui5 ui6 ui7 x4 device dq0 00000000 dq1 11111111 dq2 11111111 dq3 11111111 x8 device dq0 00000000 dq1 11111111 dq2 11111111 dq3 11111111 dq4 11111111 dq5 11111111 dq6 11111111 dq7 11111111 x16 device dq0 00000000 dq1 11111111 dq2 11111111 dq3 11111111 dq4 11111111 8gb: x4, x8, x16 ddr4 sdram multipurpose register 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 93 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 32: mpr readout C parallel format (continued) parallel ui0 ui1 ui2 ui3 ui4 ui5 ui6 ui7 dq5 11111111 dq6 11111111 dq7 11111111 dq8 00000000 dq9 11111111 dq10 1 1 1 1 1 1 1 1 dq11 1 1 1 1 1 1 1 1 dq12 1 1 1 1 1 1 1 1 dq13 1 1 1 1 1 1 1 1 dq14 1 1 1 1 1 1 1 1 dq15 1 1 1 1 1 1 1 1 mpr readout staggered format staggered format of data return is defined as the staggering of the mpr data across the lanes. in this mode, an rd/rda command is issued to a specific data pattern location and then the data is returned on the dq from each of the different data pattern loca- tions. for the x4 configuration, an rd/rda to data pattern location 0 will result in data from location 0 being driven on dq0, data from location 1 being driven on dq1, data from location 2 being driven on dq2, and so on, as shown below. similarly, an rd/rda command to data pattern location 1 will result in data from location 1 being driven on dq0, data from location 2 being driven on dq1, data from location 3 being driven on dq2, and so on. examples of different starting locations are also shown. table 33: mpr readout staggered format, x4 x4 read mpr0 command x4 read mpr1 command x4 read mpr2 command x4 read mpr3 command stagger ui[7:0] stagger ui[7:0] stagger ui[7:0] stagger ui[7:0] dq0 mpr0 dq0 mpr1 dq0 mpr2 dq0 mpr3 dq1 mpr1 dq1 mpr2 dq1 mpr3 dq1 mpr0 dq2 mpr2 dq2 mpr3 dq2 mpr0 dq2 mpr1 dq3 mpr3 dq3 mpr0 dq3 mpr1 dq3 mpr2 it is expected that the dram can respond to back-to-back rd/rda commands to the mpr for all ddr4 frequencies so that a sequence (such as the one that follows) can be created on the data bus with no bubbles or clocks between read data. in this case, the system memory controller issues a sequence of rd(mpr0), rd(mpr1), rd(mpr2), rd(mpr3), rd(mpr0), rd(mpr1), rd(mpr2), and rd(mpr3). table 34: mpr readout staggered format, x4 C consecutive reads stagger ui[7:0] ui[15:8] ui[23:16] ui[31:24] ui[39:32] ui[47:40] ui[55:48] ui[63:56] dq0 mpr0 mpr1 mpr2 mpr3 mpr0 mpr1 mpr2 mpr3 dq1 mpr1 mpr2 mpr3 mpr0 mpr1 mpr2 mpr3 mpr0 8gb: x4, x8, x16 ddr4 sdram multipurpose register 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 94 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 34: mpr readout staggered format, x4 C consecutive reads (continued) stagger ui[7:0] ui[15:8] ui[23:16] ui[31:24] ui[39:32] ui[47:40] ui[55:48] ui[63:56] dq2 mpr2 mpr3 mpr0 mpr1 mpr2 mpr3 mpr0 mpr1 dq3 mpr3 mpr0 mpr1 mpr2 mpr3 mpr0 mpr1 mpr2 for the x8 configuration, the same pattern is repeated on the lower nibble as on the up- per nibble. reads to other mpr data pattern locations follow the same format as the x4 case. a read example to mpr0 for x8 and x16 configurations is shown below. table 35: mpr readout staggered format, x8 and x16 x8 read mpr0 command x16 read mpr0 command x16 read mpr0 command stagger ui[7:0] stagger ui[7:0] stagger ui[7:0] dq0 mpr0 dq0 mpr0 dq8 mpr0 dq1 mpr1 dq1 mpr1 dq9 mpr1 dq2 mpr2 dq2 mpr2 dq10 mpr2 dq3 mpr3 dq3 mpr3 dq11 mpr3 dq4 mpr0 dq4 mpr0 dq12 mpr0 dq5 mpr1 dq5 mpr1 dq13 mpr1 dq6 mpr2 dq6 mpr2 dq14 mpr2 dq7 mpr3 dq7 mpr3 dq15 mpr3 mpr read waveforms the following waveforms show mpr read accesses. figure 35: mpr read timing t0 ta0 ta1 ck_t ck_c dq dqs_t, dqs_c t mod t mprr tb0 tc0 tc1 tc2 tc3 td0 td1 te0 tf0 tf1 des des des des mrs 3 valid 4 des command mrs 1 prea des read des des valid valid valid valid valid valid valid valid valid valid add 2 valid valid address cke pl 5 + al + cl t rp t mod ui0 ui1 ui2 ui5 ui6 ui7 mpe enable mpe disable dont care time break notes: 1. t ccd_s = 4 t ck, read preamble = 1 t ck. 2. address setting: a[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) 8gb: x4, x8, x16 ddr4 sdram multipurpose register 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 95 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
a2 = 0b (for bl = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7) ba1 and ba0 indicate the mpr location a10 and other address pins are "dont care," including bg1 and bg0. a12 is "dont care" when mr0 a[1:0] = 00 or 10 and must be 1b when mr0 a[1:0] = 01 3. multipurpose registers read/write disable (mr3 a2 = 0). 4. continue with regular dram command. 5. parity latency (pl) is added to data output delay when ca parity latency mode is ena- bled. figure 36: mpr back-to-back read timing t0 t1 t2 dq dqs_t, dqs_c t3 t4 t5 t6 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 ta8 ta9 ta10 des des des des des des des des des des des des command read des des des des read valid valid valid valid valid valid valid valid valid valid valid valid add 2 valid valid add 2 valid valid address cke pl 3 + al + cl t ccd_s 1 dq dqs_t, dqs_c ui0 ui1 ui2 ui3 ui0 ui1 ui2 ui3 ui0 ui1 ui2 ui3 ui4 ui5 ui6 ui7 ui0 ui1 ui2 ui3 ui4 ui5 ui6 ui7 ck_t ck_c dont care time break notes: 1. t ccd_s = 4 t ck, read preamble = 1 t ck. 2. address setting: a[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) a2 = 0b (for bl = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7; for bc = 4, burst order is fixed at 0, 1, 2, 3, t, t, t, t) ba1 and ba0 indicate the mpr location a10 and other address pins are "dont care," including bg1 and bg0. a12 is "dont care" when mr0 a[1:0] = 00 or 10 and must be 1b when mr0 a[1:0] = 01 3. parity latency (pl) is added to data output delay when ca parity latency mode is ena- bled. 8gb: x4, x8, x16 ddr4 sdram multipurpose register 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 96 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 37: mpr read-to-write timing t0 t1 t2 dq dqs_t, dqs_c t mprr ta0 ta1 ta2 ta3 ta4 ta5 ta6 tb0 tb1 tb2 des des des des write des des command des read des des des des valid valid valid valid add 2 valid valid valid add 1 valid valid valid valid address cke pl 3 + al + cl ui2 ui3 ui0 ui1 ui4 ui5 ui6 ui7 ck_t ck_c dont care time break notes: 1. address setting: a[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) a2 = 0b (for bl = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7) ba1 and ba0 indicate the mpr location a10 and other address pins are "dont care," including bg1 and bg0. a12 is "dont care" when mr0 a[1:0] = 00 and must be 1b when mr0 a[1:0] = 01 2. address setting: ba1 and ba0 indicate the mpr location a[7:0] = data for mpr ba1 and ba0 indicate the mpr location a10 and other address pins are "dont care" 3. parity latency (pl) is added to data output delay when ca parity latency mode is ena- bled. mpr writes mpr access mode allows 8-bit writes to the mpr page 0 using the address bus a[7:0]. data bus inversion (dbi) is not allowed during mpr write operation. the dram will maintain the new written values unless re-initialized or there is power loss. the following steps are required to use the mpr to write to mode register mpr page 0. 1. the dll must be locked if enabled. 2. precharge all; wait until t rp is satisfied. 3. mrs command to mr3[2] = 1 (enable mpr data flow) and mr3[1:0] = 00 (mpr page 0); writes to 01, 10, and 11 are not allowed. 4. t mrd and t mod must be satisfied. 5. redirect all subsequent write commands to specific mpr x location. 6. issue wr or wra command: a. ba1 and ba0 indicate mpr x location 1. 00 = mpr0 2. 01 = mpr1 3. 10 = mpr2 4. 11 = mpr3 b. a[7:0] = data for mpr page 0, mapped a[7:0] to ui[7:0]. 8gb: x4, x8, x16 ddr4 sdram multipurpose register 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 97 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
c. remaining address inputs, including a10, and bg1 and bg0 are "dont care." 7. t wr_mpr must be satisfied to complete mpr write. 8. steps 5 through 7 may be repeated to write additional mpr x locations. 9. after the last mpr x write, t mprr must be satisfied prior to exiting. 10. issue mrs command to exit mpr mode; mr3[2] = 0. 11. when the t mod sequence is completed, the dram is ready for normal operation from the core (such as act). mpr write waveforms the following waveforms show mpr write accesses. figure 38: mpr write and write-to-read timing t0 ta0 ta1 dq dqs_t, dqs_c t rp t mod t wr_mpr tb0 tc0 tc1 tc2 td0 td1 td2 td3 td4 td5 read des des des des des des command mrs 1 prea des write des des add valid valid valid add 2 valid valid valid valid valid add 2 valid valid address cke pl 3 + al + cl ui2 ui3 ui0 ui1 ui4 ui5 ui6 ui7 ck_t ck_c mpr enable dont care time break notes: 1. multipurpose registers read/write enable (mr3 a2 = 1). 2. address setting: ba1 and ba0 indicate the mpr location a10 and other address pins are "dont care" 3. parity latency (pl) is added to data output delay when ca parity latency mode is ena- bled. 8gb: x4, x8, x16 ddr4 sdram multipurpose register 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 98 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 39: mpr back-to-back write timing t0 t1 ta0 dq dqs_t, dqs_c t wr_mpr ta1 ta2 ta3 ta4 ta5 ta6 ta7 ta8 ta9 ta10 des des des des des des des command des write des write des des add valid valid valid valid valid valid valid add 1 valid add 1 valid valid address cke ck_t ck_c dont care time break note: 1. address setting: ba1 and ba0 indicate the mpr location a[7:0] = data for mpr a10 and other address pins are "dont care" mpr refresh waveforms the following waveforms show mpr accesses interaction with refreshes. figure 40: refresh timing t0 t mod t rp tc4 ta0 ta1 tb0 tb1 tb2 tb3 tb4 tc0 tc1 tc2 tc3 des des des des valid valid valid command mrs 1 prea des ref 2 des des valid valid valid valid valid valid valid valid valid valid valid valid valid address ck_t ck_c t rfc mpr enable dont care time break notes: 1. multipurpose registers read/write enable (mr3 a2 = 1). redirect all subsequent read and writes to mpr locations. 2. 1x refresh is only allowed when mpr mode is enabled. 8gb: x4, x8, x16 ddr4 sdram multipurpose register 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 99 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 41: read-to-refresh timing t0 t1 t2 dq bl = 8 dqs_t, dqs_c ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 ta8 ta9 des des des des ref 2 des des command des read des des des des valid valid valid valid valid valid valid valid add 1 valid valid valid valid address cke t rfc ui2 ui3 ui0 ui1 ui4 ui5 ui6 ui7 dq bc = 4 dqs_t, dqs_c ui2 ui3 ui0 ui1 (4 + 1) + clocks pl + al + cl ck_t ck_c dont care time break notes: 1. address setting: a[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) a2 = 0b (for bl = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7) ba1 and ba0 indicate the mpr location a10 and other address pins are "dont care," including bg1 and bg0. a12 is "dont care" when mr0 a[1:0] = 00 or 10, and must be 1b when mr0 a[1:0] = 01 2. 1x refresh is only allowed when mpr mode is enabled. figure 42: write-to-refresh timing t0 t1 ta0 dq dqs_t, dqs_c t rfc dont care ta1 ta2 ta3 ta4 ta5 ta6 ta7 ta8 ta9 ta10 des des des des des des des command des write des des ref 2 des valid valid valid valid valid valid valid valid add 1 valid valid valid valid time break address cke ck_t ck_c t wr_mpr notes: 1. address setting: ba1 and ba0 indicate the mpr location 8gb: x4, x8, x16 ddr4 sdram multipurpose register 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 100 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
a[7:0] = data for mpr a10 and other address pins are "dont care" 2. 1x refresh is only allowed when mpr mode is enabled. 8gb: x4, x8, x16 ddr4 sdram multipurpose register 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 101 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
gear-down mode the ddr4 sdram defaults in 1/2 rate (1n) clock mode and uses a low-frequency mrs command (the mrs command has relaxed setup and hold) followed by a sync pulse (first cs pulse after mrs setting) to align the proper clock edge for operating the control lines cs_n, cke, and odt when in 1/4 rate (2n) mode. gear-down mode is only sup- ported at ddr4-2666 and faster. for operation in 1/2 rate mode, neither an mrs com- mand or a sync pulse is required. gear-down mode may only be entered during initiali- zation or self refresh exit and may only be exited during self refresh exit. cal mode and ca parity mode must be disabled prior to gear-down mode entry. the two modes may be enabled after tsync_gear and tcmd_gear periods have been satisfied. the gener- al sequence for operation in 1/4 rate during initialization is as follows: 1. the device defaults to a 1n mode internal clock at power-up/reset. 2. assertion of reset. 3. assertion of cke enables the dram. 4. mrs is accessed with a low-frequency n t ck gear-down mrs command. (n t ck static mrs command is qualified by 1n cs_n. ) 5. the memory controller will send a 1n sync pulse with a low-frequency n t ck nop command. t sync_gear is an even number of clocks. the sync pulse is on an even edge clock boundary from the mrs command. 6. initialization sequence, including the expiration of t dllk and t zqinit, starts in 2n mode after t cmd_gear from 1n sync pulse. the device resets to 1n gear-down mode after entering self refresh. the general se- quence for operation in gear-down after self refresh exit is as follows: 1. mrs is set to 1, via mr3[3], with a low-frequency n t ck gear-down mrs com- mand. a. the n t ck static mrs command is qualified by 1n cs_n, which meets t xs or t xs_abort. b. only a refresh command may be issued to the dram before the n t ck stat- ic mrs command. 2. the dram controller sends a 1n sync pulse with a low-frequency n t ck nop command. a. t sync_gear is an even number of clocks. b. the sync pulse is on even edge clock boundary from the mrs command. 3. a valid command not requiring locked dll is available in 2n mode after t cmd_gear from the 1n sync pulse. a. a valid command requiring locked dll is available in 2n mode after t xsdll or t dllk from the 1n sync pulse. 4. if operation is in 1n mode after self refresh exit, n t ck mrs command or sync pulse is not required during self refresh exit. the minimum exit delay to the first valid command is t xs, or t xs_abort. the dram may be changed from 2n to 1n by entering self refresh mode, which will re- set to 1n mode. changing from 2n to by any other means can result in loss of data and make operation of the dram uncertain. when operating in 2n gear-down mode, the following mr settings apply: ? cas latency (mr0[6:4,2]): even number of clocks ? write recovery and read to precharge (mr0[11:9]): even number of clocks ? additive latency (mr1[4:3]): cl - 2 ? cas write latency (mr2 a[5:3]): even number of clocks 8gb: x4, x8, x16 ddr4 sdram gear-down mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 102 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
? cs to command/address latency mode (mr4[8:6]): even number of clocks ? ca parity latency mode (mr5[2:0]): even number of clocks figure 43: clock mode change from 1/2 rate to 1/4 rate (initialization) t xpr_gear t cmd_gear t sync_gear tdkn ck_c ck_t dont care time break tdkn + n even configure dram to 1/4 rate t dsrx n t ck setup n t ck hold n t ck setup n t ck hold 1n sync pulse 2n mode dram internal clk reset_n cke cs_n command mrs nop valid figure 44: clock mode change after exiting self refresh tdkn ck_c ck_t dont care time break tdkn + n even configure dram to 1/4 rate n t ck setup n t ck hold n t ck setup n t ck hold 1n sync pulse 2n mode dram internal clk cke cs_n command mrs nop valid t xpr_gear t cmd_gear t sync_gear 8gb: x4, x8, x16 ddr4 sdram gear-down mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 103 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 45: comparison between gear-down disable and gear-down enable t0 t rcd = 16 t33 t1 t2 t3 t15 t16 t17 t18 t19 t30 t31 t32 des des des des des des des command des act des des des read dq ck_t ck_c rl =cl= 16 (al = 0) t38 t34 t35 t36 t37 al = 0 (geardown = disable) dont care transitioning data time break do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do n + 2 do n + 1 do n des des des des des des des des des des des des command read act des des des des read dq rl = al + cl = 31 (al = cl - 1 = 15) al = cl - 1 (geardown = disable) do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do n + 2 do n + 1 do n des des des des des des des des command act read des read dq al + cl = rl = 30 (al = cl - 2 = 14) do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do n + 2 do n + 1 do n des des des 8gb: x4, x8, x16 ddr4 sdram gear-down mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 104 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
maximum power-saving mode maximum power-saving mode provides the lowest power mode where data retention is not required. when the device is in the maximum power-saving mode, it does not maintain data retention or respond to any external command, except the maximum power saving mode exit command and during the assertion of reset_n signal low. this mode is more like a hibernate mode than a typical power-saving mode. the intent is to be able to park the dram at a very low-power state; the device can be switched to an active state via the per-dram addressability (pda) mode. maximum power-saving mode entry maximum power-saving mode is entered through an mrs command. for devices with shared control/address signals, a single dram device can be entered into the maxi- mum power-saving mode using the per-dram addressability mrs command. large cs_n hold time to cke upon the mode exit could cause dram malfunction; as a result, ca parity, cal, and gear-down modes must be disabled prior to the maximum power- saving mode entry mrs command. the mrs command may use both address and dq information, as defined in the per- dram addressability section. as illustrated in the figure below, after t mped from the mode entry mrs command, the dram is not responsive to any input signals except cke, cs_n, and reset_n. all other inputs are disabled (external input signals may be- come high-z). the system will provide a valid clock until t ckmpe expires, at which time clock inputs (ck) should be disabled (external clock signals may become high-z). figure 46: maximum power-saving mode entry ta0 ta1 ta2 tb0 tb1 command mrs des des des des ck_t ck_c reset_n tc11 tb3 tc0 tc1 tc2 tc3 tc4 tc7 tc5 tc6 tc8 tc9 tc10 dont care time break cs_n cke t mped cke low makes cs_n a care; cke low followed by cs_n low followed by cke high exits mode mr4[a1=1] mpsm enable) address valid t ckmpe 8gb: x4, x8, x16 ddr4 sdram maximum power-saving mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 105 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
maximum power-saving mode entry in pda the sequence and timing required for the maximum power-saving mode with the per- dram addressability enabled is illustrated in the figure below. figure 47: maximum power-saving mode entry with pda ta0 ta1 ta2 tb0 tb1 command mrs des des des des des des des des des des des des des ck_t ck_c dqs_t dqs_c dq tb3 tb4 tb5 tb6 tb7 tb8 tc1 tb9 tc0 tc2 td0 td1 td2 dont care time break cs_n cke reset_n mr4[a1 = 1] mpsm enable) al + cwl t mped t pda_h t pda_s t ckmpe cke transition during maximum power-saving mode the following figure shows how to maintain maximum power-saving mode even though the cke input may toggle. to prevent the device from exiting the mode, cs_n should be high at the cke low-to-high edge, with appropriate setup ( t mpx_s) and hold ( t mpx_h) timings. figure 48: maintaining maximum power-saving mode with cke transition cmd cs_n cke reset_n dont care clk t mpx_hh t mpx_s maximum power-saving mode exit to exit the maximum power-saving mode, cs_n should be low at the cke low-to- high transition, with appropriate setup ( t mpx_s) and hold ( t mpx_lh) timings, as 8gb: x4, x8, x16 ddr4 sdram maximum power-saving mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 106 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
shown in the figure below. because the clock receivers (ck_t, ck_c) are disabled during this mode, cs_n = low is captured by the rising edge of the cke signal. if the cs_n sig- nal level is detected low, the dram clears the maximum power-saving mode mrs bit and begins the exit procedure from this mode. the external clock must be restarted and be stable by t ckmpx before the device can exit the maximum power-saving mode. dur- ing the exit time ( t xmp), only nop and des commands are allowed: nop during t mpx_lh and des the remainder of t xmp. after t xmp expires, valid commands not re- quiring a locked dll are allowed; after t xmp_dll expires, valid commands requiring a locked dll are allowed. figure 49: maximum power-saving mode exit ta0 t ckmpx t mpx_s t xmp t xmp_dll ta1 ta2 ta3 tb0 nop nop nop nop nop des des command ck_t ck_c reset_n te1 tb1 tb2 tb3 tc0 tc1 tc2 td1 tc4 td0 td2 td3 te0 dont care time break des des valid des des cs_n cke t mpx_lh 8gb: x4, x8, x16 ddr4 sdram maximum power-saving mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 107 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
command/address parity command/address (ca) parity takes the ca parity signal (par) input carrying the parity bit for the generated address and commands signals and matches it to the internally generated parity from the captured address and commands signals. ca parity is suppor- ted in the dll enabled state only; if the dll is disabled, ca parity is not supported. figure 50: command/address parity operation cmd/addr dram controller dram cmd/addr even parity bit even parity bit even parity gen even parity gen cmd/addr compare parity bit ca parity is disabled or enabled via an mrs command. if ca parity is enabled by pro- gramming a non-zero value to ca parity latency in the mr, the dram will ensure that there is no parity error before executing commands. there is an additional delay re- quired for executing the commands versus when parity is disabled. the delay is pro- grammed in the mr when ca parity is enabled (parity latency) and applied to all com- mands which are registered by cs_n (rising edge of ck_t and falling cs_n). the com- mand is held for the time of the parity latency (pl) before it is executed inside the de- vice. the command captured by the input clock has an internal delay before executing and is determined with pl. when ca parity is enabled, only des are allowed between valid commands. par will go active when the dram detects a ca parity error. ca parity covers act_n, ras_n/a16, cas_n/a15, we_n/a14, the address bus including bank address and bank group bits, and c[2:0] on 3ds devices; the control signals cke, odt, and cs_n are not covered. for example, for a 4gb x4 monolithic device, parity is computed across bg[1:0], ba[1:0], a16/ras_n, a15/cas_n, a14/ we_n, a[13:0], and act_n. the dram treats any unused address pins internally as zeros; for example, if a common die has stacked pins but the device is used in a monolithic application, then the address pins used for stacking and not connected are treated internally as zeros. the convention for parity is even parity; for example, valid parity is defined as an even number of ones across the inputs used for parity computation combined with the pari- ty signal. in other words, the parity bit is chosen so that the total number of ones in the transmitted signal, including the parity bit, is even. if a dram device detects a ca parity error in any command qualified by cs_n, it will perform the following steps: 1. ignore the erroneous command. commands in the max n n ck window ( t par_unknown) prior to the erroneous command are not guaranteed to be exe- cuted. when a read command in this n n ck window is not executed, the device 8gb: x4, x8, x16 ddr4 sdram command/address parity 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 108 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
does not activate dqs outputs. if write crc is enabled and a write crc occurs during the t par_unknown window, the write crc error status bit located at mr5[3] may or may not get set. when ca parity and write crc are both enabled and a ca parity occurs, the write crc error status bit should be reset. 2. log the error by storing the erroneous command and address bits in the mpr er- ror log. 3. set the parity error status bit in the mode register to 1. the parity error status bit must be set before the alert_n signal is released by the dram (that is, t par_alert_on + t par_alert_pw (min)). 4. assert the alert_n signal to the host (alert_n is active low) within t par_alert_on time. 5. wait for all in-progress commands to complete. these commands were received t par_unkown before the erroneous command. 6. wait for t ras (min) before closing all the open pages. the dram is not executing any commands during the window defined by ( t par_alert_on + t par_alert_pw). 7. after t par_alert_pw (min) has been satisfied, the device may de-assert alert_n. a. when the device is returned to a known precharged state, alert_n is al- lowed to be de-asserted. 8. after ( t par_alert_pw (max)) the dram is ready to accept commands for nor- mal operation. parity latency will be in effect; however, parity checking will not re- sume until the memory controller has cleared the parity error status bit by writing a zero. the dram will execute any erroneous commands until the bit is cleared; unless persistent mode is enabled. ? the dram should have only des commands issued around alert_n going high such that at least 3 clocks prior and 1 clock plus 3ns after the release of alert_n. ? it is possible that the device might have ignored a refresh command during t par_alert_pw or the refresh command is the first erroneous frame, so it is rec- ommended that extra refresh cycles be issued, as needed. ? the parity error status bit may be read anytime after t par_alert_on + t par_alert_pw to determine which dram had the error. the device maintains the error log for the first erroneous command until the parity error status bit is reset to a zero or a second ca parity occurs prior to resetting. the mode register for the ca parity error is defined as follows: ca parity latency bits are write only, the parity error status bit is read/write, and error logs are read-only bits. the dram controller can only program the parity error status bit to zero. if the dram con- troller illegally attempts to write a 1 to the parity error status bit, the dram can not be certain that parity will be checked; the dram may opt to block the dram controller from writing a 1 to the parity error status bit. the device supports persistent parity error mode. this mode is enabled by setting mr5[9] = 1; when enabled, ca parity resumes checking after the alert_n is de-asser- ted, even if the parity error status bit remains a 1. if multiple errors occur before the er- ror status bit is cleared the error log in mpr page 1 should be treated as "dont care." in persistent parity error mode the alert_n pulse will be asserted and de-asserted by the dram as defined with the min and max value t par_alert_pw. the dram controller must issue deselect commands once it detects the alert_n signal, this response time is defined as t par_alert_rsp. the following figures capture the flow of events on the ca bus and the alert_n signal. 8gb: x4, x8, x16 ddr4 sdram command/address parity 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 109 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 36: mode register setting for ca parity ca parity latency mr5[2:0] 1 applicable speed bin parity error status parity persistent mode erroneous ca frame 000 = disabled n/a mr5 [4] 0 = clear mr5 [4] 1 = error mr5 [9] 0 = disabledmr5 [9] 1 = enabled c[2:0], act_n, bg1, bg0, ba[1:0], par, a17, a16/ras_n, a15/ cas_n, a14/we_n, a[13:0] 001 = 4 clocks 1600, 1866, 2133 010 = 5 clocks 2400, 2666 011 = 6 clocks 2933, 3200 100 = 8 clocks rfu 101 = reserved rfu 110 = reserved rfu 111 = reserved rfu notes: 1. parity latency is applied to all commands. 2. parity latency can be changed only from a ca parity disabled state; for example, a direct change from pl = 3 to pl = 4 is not allowed. the correct sequence is pl = 3 to disabled to pl = 4. 3. parity latency is applied to write and read latency. write latency = al + cwl + pl. read latency = al + cl + pl. figure 51: command/address parity during normal operation dont care time break command execution unknown command not executed command executed des 2 valid 3 valid error ck_t ck_c command/ address valid 2 valid 2 valid 2 valid 3 valid 3 t0 t1 ta0 ta1 tb0 tc0 alert_n tc1 t par_alert_on td0 valid valid valid error t par_unknown 2 ta2 te1 t par_alert_pw 1 te0 des 2 des 2 valid 2 t > 1nck + 3ns t > 2nck notes: 1. dram is emptying queues. precharge all and parity checking are off until parity error status bit is cleared. 2. command execution is unknown; the corresponding dram internal state change may or may not occur. the dram controller should consider both cases and make sure that the command sequence meets the specifications. if write crc is enabled and a write crc occurs during the t par_unknown window, the write crc error status bit located at mr5[3] may or may not get set. 3. normal operation with parity latency (ca parity persistent error mode disabled). parity checking is off until parity error status bit is cleared. 8gb: x4, x8, x16 ddr4 sdram command/address parity 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 110 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 52: persistent ca parity error checking operation dont care time break command execution unknown command not executed command executed des valid 3 valid error ck_t ck_c command/ address valid 2 valid 2 valid 2 valid 3 t0 t1 ta0 ta1 tb0 tc0 alert_n tc1 t par_alert_on td0 valid valid valid error t par_unknown 2 ta2 te1 t par_alert_pw 1 t par_alert_rsp te0 des des des valid 2 t > 1nck + 3ns t > 2nck notes: 1. dram is emptying queues. precharge all and parity check re-enable finished by t par_alert_pw. 2. command execution is unknown; the corresponding dram internal state change may or may not occur. the dram controller should consider both cases and make sure that the command sequence meets the specifications. if write crc is enabled and a write crc occurs during the t par_unknown window, the write crc error status bit located at mr5[3] may or may not get set 3. normal operation with parity latency and parity checking (ca parity persistent error mode enabled). figure 53: ca parity error checking C sre attempt dont care time break command not executed command executed des 6 command execution unknown des 5 valid 3 des 1 error 2 ck_t ck_c command/ address des 1, 5 valid 3 t0 t1 ta0 ta1 tb1 tc0 alert_n tc1 t par_alert_on td0 des 1 note 4 error 2 tb0 td2 t par_alert_pw 1 td1 des 6 des 6 des 5 des 1, 5 t > 1nck + 3ns t > 2nck t ih t is t xp + pl t cpded + pl td3 te0 te1 cke t is notes: 1. only deselect command is allowed. 2. self refresh command error. the dram masks the intended sre command and enters precharge power-down. 3. normal operation with parity latency (ca parity persistent error mode disabled). parity checking is off until the parity error status bit cleared. 4. the controller cannot disable the clock until it has been capable of detecting a possible ca parity error. 5. command execution is unknown; the corresponding dram internal state change may or may not occur. the dram controller should consider both cases and make sure that the command sequence meets the specifications. 6. only a deselect command is allowed; cke may go high prior to tc2 as long as des commands are issued. 8gb: x4, x8, x16 ddr4 sdram command/address parity 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 111 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 54: ca parity error checking C srx attempt dont care time break command execution unknown command not executed command executed des valid 3, 5 valid 4,5,6,7 valid error ck_t ck_c command/ address srx 1 des des valid 2, 4, 5 valid 2, 4, 7 valid 2, 4, 6 t0 ta0 tb0 ta1 tc0 tc1 alert_n tc2 t par_alert_on td0 valid 2 valid 2 valid 2 error 2 t par_unknown t xs_fast 8 t xs t xsdll tb1 te0 t par_alert_pw td1 des 2, 3 des 2, 3 srx 1 t > 1nck + 3ns t > 2nck tf0 cke t is notes: 1. self refresh abort = disable: mr4 [9] = 0. 2. input commands are bounded by t xsdll, t xs, t xs_abort, and t xs_fast timing. 3. command execution is unknown; the corresponding dram internal state change may or may not occur. the dram controller should consider both cases and make sure that the command sequence meets the specifications. 4. normal operation with parity latency (ca parity persistent error mode disabled). parity checking off until parity error status bit cleared. 5. only an mrs (limited to those described in the self refresh operation section), zqcs, or zqcl command is allowed. 6. valid commands not requiring a locked dll. 7. valid commands requiring a locked dll. 8. this figure shows the case from which the error occurred after t xs_fast. an error may also occur after t xs_abort and t xs. figure 55: ca parity error checking C pde/pdx dont care time break command not executed command executed des 5 command execution unknown valid 3 des 1 error 2 ck_t ck_c command/ address valid 3 t0 t1 ta0 ta1 tb1 tc0 alert_n tc1 t par_alert_on td0 des 1 des 1 error 2 tb0 td2 t par_alert_pw 1 td1 des 5 des 5 des 4 des 4 t > 1nck + 3ns t > 2nck t ih t is t xp + pl t cpded + pl td3 te0 te1 cke t is notes: 1. only deselect command is allowed. 2. error could be precharge or activate. 3. normal operation with parity latency (ca parity persistent error mode disabled). parity checking is off until parity error status bit cleared. 8gb: x4, x8, x16 ddr4 sdram command/address parity 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 112 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
4. command execution is unknown; the corresponding dram internal state change may or may not occur. the dram controller should consider both cases and make sure that the command sequence meets the specifications. 5. only a deselect command is allowed; cke may go high prior to td2 as long as des commands are issued. figure 56: parity entry timing example C t mrd_par ta0 t mrd_par ta1 ta2 tb0 tb1 tb2 command mrs des des des mrs des pl = 0 updating setting pl = n parity latency ck_t ck_c enable parity dont care time break note: 1. t mrd_par = t mod + n; where n is the programmed parity latency. figure 57: parity entry timing example C t mod_par ta0 t mod_par ta1 ta2 tb0 tb1 tb2 command mrs des des des valid des parity latency ck_t ck_c enable parity dont care time break pl = 0 updating setting pl = n note: 1. t mod_par = t mod + n; where n is the programmed parity latency. figure 58: parity exit timing example C t mrd_par ta0 t mrd_par ta1 ta2 tb0 tb1 tb2 command mrs des des des mrs des parity latency ck_t ck_c disable parity dont care time break pl = n updating setting note: 1. t mrd_par = t mod + n; where n is the programmed parity latency. 8gb: x4, x8, x16 ddr4 sdram command/address parity 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 113 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 59: parity exit timing example C t mod_par ta0 t mod_par ta1 ta2 tb0 tb1 tb2 command mrs des des des valid des parity latency ck_t ck_c disable parity dont care time break pl = n updating setting note: 1. t mod_par = t mod + n; where n is the programmed parity latency. 8gb: x4, x8, x16 ddr4 sdram command/address parity 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 114 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 60: ca parity flow diagram ca latched in yes ca process start mr5[2:0] set parity latency (pl) mr5[4] set parity error status to 0 mr5[9] enable/disable persistent mode no yes no yes no yes no yes no ca parity enabled ca error persistent mode enabled good ca processed good ca processed good ca processed ignore bad cmd ignore bad cmd log error/ set parity status internal precharge all alert_n high command execution unknown command execution unknown normal operation ready mr5[4] reset to 0 if desired normal operation ready mr5[4] reset to 0 if desired yes no ca parity error alert_n low 44 to 144 cks alert_n low 44 to 144 cks internal precharge all alert_n high command execution unknown command execution unknown no yes log error/ set parity status mr5[4] = 0 @ addr/cmd latched mr5[4] = 0 @ addr/cmd latched ca parity error normal operation ready bad ca processed operation ready? 8gb: x4, x8, x16 ddr4 sdram command/address parity 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 115 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
per-dram addressability ddr4 allows programmability of a single, specific dram on a rank. as an example, this feature can be used to program different odt or v ref values on each dram on a given rank. because per-dram addressability (pda) mode may be used to program optimal v ref for the dram, the data set up for first dq0 transfer or the hold time for the last dq0 transfer cannot be guaranteed. the dram may sample dq0 on either the first fall- ing or second rising dqs transfer edge. this supports a common implementation be- tween bc4 and bl8 modes on the dram. the dram controller is required to drive dq0 to a stable low or high state during the length of the data transfer for bc4 and bl8 cases. 1. before entering pda mode, write leveling is required. ? bl8 or bc4 may be used. 2. before entering pda mode, the following mr settings are possible: ?r tt(park) mr5 a[8:6] = enable ?r tt(nom) mr1 a[10:8] = enable 3. enable pda mode using mr3 [4] = 1. (the default programed value of mr3[4] = 0.) 4. in pda mode, all mrs commands are qualified with dq0. the device captures dq0 by using dqs signals. if the value on dq0 is low, the dram executes the mrs command. if the value on dq0 is high, the dram ignores the mrs com- mand. the controller can choose to drive all the dq bits. 5. program the desired dram and mode registers using the mrs command and dq0. 6. in pda mode, only mrs commands are allowed. 7. the mode register set command cycle time in pda mode, al + cwl + bl/2 - 0.5 t ck + t mrd_pda + pl, is required to complete the write operation to the mode register and is the minimum time required between two mrs commands. 8. remove the device from pda mode by setting mr3[4] = 0. (this command re- quires dq0 = 0.) note: removing the device from pda mode will require programming the entire mr3 when the mrs command is issued. this may impact some pda values programmed within a rank as the exit command is sent to the rank. to avoid such a case, the pda enable/disable control bit is located in a mode register that does not have any pda mode controls. in pda mode, the device captures dq0 using dqs signals the same as in a normal write operation; however, dynamic odt is not supported. extra care is required for the odt setting. if r tt(nom) mr1 [10:8] = enable, device data termination needs to be controlled by the odt pin, and applies the same timing parameters (defined below). symbol parameter dodtlon direct odt turnon latency dodtloff direct odt turn off latency t adc r tt change timing skew t aonas asynchronous r tt(nom) turn-on delay t aofas asynchronous r tt(nom) turn-off delay 8gb: x4, x8, x16 ddr4 sdram per-dram addressability 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 116 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 61: pda operation enabled, bl8 &.bw &.bf '4 2'7 w 3'$b6 w 02' &:/$/3/ w 05'b3'$ '46bw '46bf 05$ 3'$hqdeoh 056 056 056 '2'7/rii :/ '2'7/rq :/ w 3'$b+ 5 773dun 5 773dun 5 77 5 77120 note: 1. r tt(park) = enable; r tt(nom) = enable; write preamble set = 2 t ck; and dll = on. figure 62: pda operation enabled, bc4 ck_t ck_c dq0 odt t pda_s t mod cwl+al+pl t mrd_pda dqs_t dqs_c mr3 a4 = 1 (pda enable) mrs mrs mrs dodtloff = wl-3 dodtlon = wl-3 t pda_h r tt(park) r tt(park) r tt r tt(nom) note: 1. r tt(park) = enable; r tt(nom) = enable; write preamble set = 2 t ck; and dll = on. 8gb: x4, x8, x16 ddr4 sdram per-dram addressability 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 117 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 63: mrs pda exit &.bw &.bf '4 2'7 5 77 w 3'$b6 &:/$/3/ w 02'b3'$ '46bw '46bf 05$ 3'$glvdeoh 056 9dolg '2'7/rii :/ '2'7/rq :/ w 3'$b+ 5 773dun 5 77120 5 773dun note: 1. r tt(park) = enable; r tt(nom) = enable; write preamble set = 2 t ck; and dll = on. 8gb: x4, x8, x16 ddr4 sdram per-dram addressability 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 118 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
v refdq calibration the v refdq level, which is used by the dram dq input receivers, is internally gener- ated. the dram v refdq does not have a default value upon power-up and must be set to the desired value, usually via v refdq calibration mode. if pda or ppr modes (hppr or sppr) are used prior to v refdq calibration, v refdq should initially be set at the midpoint between the v dd,max , and the low as determined by the driver and odt termination selected with wide voltage swing on the input levels and setup and hold times of ap- proximately 0.75ui. the memory controller is responsible for v refdq calibration to de- termine the best internal v refdq level. the v refdq calibration is enabled/disabled via mr6[7], mr6[6] selects range 1 (60% to 92.5% of v ddq ) or range 2 (45% to 77.5% of v ddq ), and an mrs protocol using mr6[5:0] to adjust the v refdq level up and down. mr6[6:0] bits can be altered using the mrs command if mr6[7] is disabled. the dram controller will likely use a series of writes and reads in conjunction with v refdq adjust- ments to obtain the best v refdq , which in turn optimizes the data eye. the internal v refdq specification parameters are voltage range, step size, v ref step time, v ref full step time, and v ref valid level. the voltage operating range specifies the minimum required v ref setting range for ddr4 sdram devices. the minimum range is defined by v refdq,min and v refdq,max . as noted, a calibration sequence, determined by the dram controller, should be performed to adjust v refdq and optimize the timing and voltage margin of the dram data input receivers. the internal v refdq voltage value may not be exactly within the voltage range setting coupled with the v ref set tolerance; the device must be calibrated to the correct internal v refdq voltage. figure 64: v refdq voltage range v ddq v ref range v swing small v swing large system variance total range v ref,max v ref,min 8gb: x4, x8, x16 ddr4 sdram v refdq calibration 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 119 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
v refdq range and levels table 37: v refdq range and levels mr6[5:0] range 1 mr6[6] 0 range 2 mr6[6] 1 mr6[5:0] range 1 mr6[6] 0 range 2 mr6[6] 1 00 0000 60.00% 45.00% 01 1010 76.90% 61.90% 00 0001 60.65% 45.65% 01 1011 77.55% 62.55% 00 0010 61.30% 46.30% 01 1100 78.20% 63.20% 00 0011 61.95% 46.95% 01 1101 78.85% 63.85% 00 0100 62.60% 47.60% 01 1110 79.50% 64.50% 00 0101 63.25% 48.25% 01 1111 80.15% 65.15% 00 0110 63.90% 48.90% 10 0000 80.80% 65.80% 00 0111 64.55% 49.55% 10 0001 81.45% 66.45% 00 1000 65.20% 50.20% 10 0010 82.10% 67.10% 00 1001 65.85% 50.85% 10 0011 82.75% 67.75% 00 1010 66.50% 51.50% 10 0100 83.40% 68.40% 00 1011 67.15% 52.15% 10 0101 84.05% 69.05% 00 1100 67.80% 52.80% 10 0110 84.70% 69.70% 00 1101 68.45% 53.45% 10 0111 85.35% 70.35% 00 1110 69.10% 54.10% 10 1000 86.00% 71.00% 00 1111 69.75% 54.75% 10 1001 86.65% 71.65% 01 0000 70.40% 55.40% 10 1010 87.30% 72.30% 01 0001 71.05% 56.05% 10 1011 87.95% 72.95% 01 0010 71.70% 56.70% 10 1100 88.60% 73.60% 01 0011 72.35% 57.35% 10 1101 89.25% 74.25% 01 0100 73.00% 58.00% 10 1110 89.90% 74.90% 01 0101 73.65% 58.65% 10 1111 90.55% 75.55% 01 0110 74.30% 59.30% 11 0000 91.20% 76.20% 01 0111 74.95% 59.95% 11 0001 91.85% 76.85% 01 1000 75.60% 60.60% 11 0010 92.50% 77.50% 01 1001 76.25% 61.25% 11 0011 to 11 1111 = reserved v refdq step size the v ref step size is defined as the step size between adjacent steps. v ref step size rang- es from 0.5% v ddq to 0.8% v ddq . however, for a given design, the device has one value for v ref step size that falls within the range. the v ref set tolerance is the variation in the v ref voltage from the ideal setting. this ac- counts for accumulated error over multiple steps. there are two ranges for v ref set tol- erance uncertainty. the range of v ref set tolerance uncertainty is a function of number of steps n. the v ref set tolerance is measured with respect to the ideal line, which is based on the min and max v ref value endpoints for a specified range. the internal v refdq voltage 8gb: x4, x8, x16 ddr4 sdram v refdq calibration 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 120 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
value may not be exactly within the voltage range setting coupled with the v ref set tol- erance; the device must be calibrated to the correct internal v refdq voltage. figure 65: example of v ref set tolerance and step size v ref v ref step size v ref set tolerance v ref set tolerance straight line (endpoint fit) actual v ref output digital code note: 1. maximum case shown. v refdq increment and decrement timing the v ref increment/decrement step times are defined by v ref,time . v ref,time is defined from t0 to t1, where t1 is referenced to the v ref voltage at the final dc level within the v ref valid tolerance (v ref,val_tol ). the v ref valid level is defined by v ref,val tolerance to qualify the step time t1. this parameter is used to insure an adequate rc time constant behavior of the voltage level change after any v ref increment/decrement adjustment. note: t0 is referenced to the mrs command clock t1 is referenced to v ref,tol 8gb: x4, x8, x16 ddr4 sdram v refdq calibration 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 121 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 66: v refdq timing diagram for v ref,time parameter mrs v ref setting adjustment command dq v ref v ref_time t0 t1 old v ref setting new v ref setting updating v ref setting dont care ck_t ck_c v refdq calibration mode is entered via an mrs command, setting mr6[7] to 1 (0 disa- bles v refdq calibration mode) and setting mr6[6] to either 0 or 1 to select the desired range (mr6[5:0] are "don't care"). after v refdq calibration mode has been entered, v refdq calibration mode legal commands may be issued once t vrefdqe has been sat- isfied. legal commands for v refdq calibration mode are act, wr, wra, rd, rda, pre, des, and mrs to set v refdq values, and mrs to exit v refdq calibration mode. also, after v refdq calibration mode has been entered, dummy write commands are allowed prior to adjusting the v refdq value the first time v refdq calibration is performed after initialization. setting v refdq values requires mr6[7] be set to 1 and mr6[6] be unchanged from the initial range selection; mr6[5:0] may be set to the desired v refdq values. if mr6[7] is set to 0, mr6[6:0] are not written. v ref,time-short or v ref,time-long must be satisfied after each mr6 command to set v refdq value before the internal v refdq value is valid. if pda mode is used in conjunction with v refdq calibration, the pda mode require- ment that only mrs commands are allowed while pda mode is enabled is not waived. that is, the only v refdq calibration mode legal commands noted above that may be used are the mrs commands: mrs to set v refdq values and mrs to exit v refdq calibra- tion mode. the last mr6[6:0] setting written to mr6 prior to exiting v refdq calibration mode is the range and value used for the internal v refdq setting. v refdq calibration mode may be exited when the dram is in idle state. after the mrs command to exit v refdq calibra- tion mode has been issued, des must be issued until t vrefdqx has been satisfied where any legal command may then be issued. v refdq setting should be updated if the die temperature changes too much from the calibration temperature. the following are typical script when applying the above rules for v refdq calibration routine when performing v refdq calibration in range 1: ? mr6[7:6]10 [5:0]xxxxxxx. C subsequent legal commands while in v refdq calibration mode: act, wr, wra, rd, rda, pre, des, and mrs (to set v refdq values and exit v refdq calibration mode). 8gb: x4, x8, x16 ddr4 sdram v refdq calibration 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 122 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
? all subsequent v refdq calibration mr setting commands are mr6[7:6]10 [5:0]vvvvvv. C "vvvvvv" are desired settings for v refdq . ? issue act/wr/rd looking for pass/fail to determine v cent (midpoint) as needed. ? to exit v refdq calibration, the last two v refdq calibration mr commands are: C mr6[7:6]10 [5:0]vvvvvv* where vvvvvv* = desired value for v refdq . C mr6[7]0 [6:0]xxxxxxx to exit v refdq calibration mode. the following are typical script when applying the above rules for v refdq calibration routine when performing v refdq calibration in range 2: ? mr6[7:6]11 [5:0]xxxxxxx. C subsequent legal commands while in v refdq calibration mode: act, wr, wra, rd, rda, pre, des, and mrs (to set v refdq values and exit v refdq calibration mode). ? all subsequent v refdq calibration mr setting commands are mr6[7:6]11 [5:0]vvvvvv. C "vvvvvv" are desired settings for v refdq . ? issue act/wr/rd looking for pass/fail to determine v cent (midpoint) as needed. ? to exit v refdq calibration, the last two v refdq calibration mr commands are: C mr6[7:6]11 [5:0]vvvvvv* where vvvvvv* = desired value for v refdq . C mr6[7]0 [6:0]xxxxxxx to exit v refdq calibration mode. note: range may only be set or changed when entering v refdq calibration mode; changing range while in or exiting v refdq calibration mode is illegal. figure 67: v refdq training mode entry and exit timing diagram t0 t1 ta0 ta1 tb0 ck_c ck_t command tb1 tc0 mrs wr des cmd des des cmd des tc1 td0 td1 td2 t vrefdqe v refdq training on t vrefdqx des mrs 1,2 des new v refdq value or write new v refdq value or write v refdq training off dont care notes: 1. new v refdq values are not allowed with an mrs command during calibration mode en- try. 2. depending on the step size of the latest programmed v ref value, v ref must be satisfied before disabling v refdq training mode. 8gb: x4, x8, x16 ddr4 sdram v refdq calibration 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 123 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 68: v ref step: single step size increment case v ref voltage time v ref,val_tol t1 v ref (v ddq(dc) ) step size figure 69: v ref step: single step size decrement case v ref voltage time v ref,val_tol t1 v ref (v ddq(dc) ) step size 8gb: x4, x8, x16 ddr4 sdram v refdq calibration 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 124 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 70: v ref full step: from v ref,min to v ref,max case v ref voltage time v ref,val_tol v ref,max v ref,min t1 v ref (v ddq(dc) ) full range step figure 71: v ref full step: from v ref,max to v ref,min case v ref voltage time v ref,val_tol v ref,max v ref,min t1 v ref (v ddq(dc) ) full range step v refdq target settings the v refdq initial settings are largely dependant on the odt termination settings. the table below shows all of the possible initial settings available for v refdq training; it is unlikely the lower odt settings would be used in most cases. 8gb: x4, x8, x16 ddr4 sdram v refdq calibration 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 125 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 38: v refdq settings (v ddq = 1.2v) r on odt vx C v in low (mv) v refdq (mv) v refdq (%v ddq ) 34 ohm 34 ohm 600 900 75% 40 ohm 550 875 73% 48 ohm 500 850 71% 60 ohm 435 815 68% 80 ohm 360 780 65% 120 ohm 265 732 61% 240 ohm 150 675 56% 48 ohm 34 ohm 700 950 79% 40 ohm 655 925 77% 48 ohm 600 900 75% 60 ohm 535 865 72% 80 ohm 450 825 69% 120 ohm 345 770 64% 240 ohm 200 700 58% figure 72: v refdq equivalent circuit rxer v refdq (internal) r on odt vx v ddq v ddq 8gb: x4, x8, x16 ddr4 sdram v refdq calibration 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 126 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
connectivity test mode connectivity test (ct) mode is similar to boundary scan testing but is designed to sig- nificantly speed up the testing of electrical continuity of pin interconnections between the device and the memory controller on the pc boards. designed to work seamlessly with any boundary scan device, ct mode is supported in all x4,x8, and x16 devices (je- dec states ct mode for x4 and x8 is not required on 4gb and is an optional feature on 8gb and above). contrary to other conventional shift-register-based test modes, where test patterns are shifted in and out of the memory devices serially during each clock, the ct mode allows test patterns to be entered on the test input pins in parallel and the test results to be extracted from the test output pins of the device in parallel. these two functions are al- so performed at the same time, significantly increasing the speed of the connectivity check. when placed in ct mode, the device appears as an asynchronous device to the external controlling agent. after the input test pattern is applied, the connectivity test results are available for extraction in parallel at the test output pins after a fixed propa- gation delay time. note: a reset of the device is required after exiting ct mode (see reset and initializa- tion procedure). pin mapping only digital pins can be tested using the ct mode. for the purposes of a connectivity check, all the pins used for digital logic in the device are classified as one of the follow- ing types: ? test enable (ten): when asserted high, this pin causes the device to enter ct mode. in ct mode, the normal memory function inside the device is bypassed and the i/o pins appear as a set of test input and output pins to the external controlling agent. additionally, the device will set the internal v refdq to v ddq 0.5 during ct mode (this is the only time the dram takes direct control over setting the internal v refdq ). the ten pin is dedicated to the connectivity check function and will not be used dur- ing normal device operation. ? chip select (cs_n): when asserted low, this pin enables the test output pins in the device. when de-asserted, these output pins will be high-z. the cs_n pin in the de- vice serves as the cs_n pin in ct mode. ? test input: a group of pins used during normal device operation designated as test input pins. these pins are used to enter the test pattern in ct mode. ? test output: a group of pins used during normal device operation designated as test output pins. these pins are used for extraction of the connectivity test results in ct mode. ? reset_n: this pin must be fixed high level during ct mode, as in normal function. 8gb: x4, x8, x16 ddr4 sdram connectivity test mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 127 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 39: connectivity mode pin description and switching levels ct mode pins pin name during normal memory operation switching level notes test enable ten cmos (20%/80% v dd ) 1, 2 chip select cs_n v refca 200mv 3 test input a ba[1:0], bg[1:0], a[9:0], a10/ap, a11, a12/bc_n, a13, we_n/a14, cas_n/a15, ras_n/a16, cke, act_n, odt, clk_t, clk_c, par v refca 200mv 3 b ldm_n/ldbi_n, udm_n/udbi_n; dm_n/dbi_n v refdq 200mv 4 c alert_n cmos (20%/80% v dd ) 2, 5 d reset_n cmos (20%/80% v dd )2 test output dq[15:0], udqs_t, udqs_c, ldqs_t, ldqs_c; dqs_t, dqs_c v tt 100mv 6 notes: 1. ten: connectivity test mode is active when ten is high and inactive when ten is low. ten must be low during normal operation. 2. cmos is a rail-to-rail signal with dc high at 80% and dc low at 20% of v dd (960mv for dc high and 240mv for dc low.) 3. v refca should be v dd /2. 4. v refdq should be v ddq /2. 5. alert_n switching level is not a final setting. 6. v tt should be set to v dd /2. minimum terms definition for logic equations the test input and output pins are related by the following equations, where inv de- notes a logical inversion operation and xor a logical exclusive or operation: mt0 = xor (a1, a6, par) mt1 = xor (a8, alert_n, a9) mt2 = xor (a2, a5, a13) mt3 = xor (a0, a7, a11) mt4 = xor (ck_c, odt, cas_n/a15) mt5 = xor (cke, ras_n/a16, a10/ap) mt6 = xor (act_n, a4, ba1) mt7 = x16: xor (dmu_n/dbiu_n , dml_n/dbil_n, ck_t) = x8: xor (bg1, dml_n/dbil_n, ck_t) = x4: xor (bg1, ck_t) mt8 = xor (we_n/a14, a12 / bc, ba0) mt9 = xor (bg0, a3, reset_n and ten) logic equations for a x4 device, when supported dq0 = xor (mt0, mt1) dq1 = xor (mt2, mt3) dq2 = xor (mt4, mt5) dq3 = xor (mt6, mt7) dqs_t = mt8 dqs_c = mt9 8gb: x4, x8, x16 ddr4 sdram connectivity test mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 128 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
logic equations for a x8 device, when supported dq0 = mt0 dq5 = mt5 dq1 = mt1 dq6 = mt6 dq2 = mt2 dq7 = mt7 dq3 = mt3 dqs_t = mt8 dq4 = mt4 dqs_c = mt9 logic equations for a x16 device dq0 = mt0 dq10 = inv dq2 dq1 = mt1 dq11 = inv dq3 dq2 = mt2 dq12 = inv dq4 dq3 = mt3 dq13 = inv dq5 dq4 = mt4 dq14 = inv dq6 dq5 = mt5 dq15 = inv dq7 dq6 = mt6 ldqs_t = mt8 dq7 = mt7 ldqs_c = mt9 dq8 = inv dq0 udqs_t = inv ldqs_t dq9 = inv dq1 udqs_c = inv ldqs_c ct input timing requirements prior to the assertion of the ten pin, all voltage supplies, including vrefca, must be val- id and stable and reset_n registered high prior to entering ct mode. upon the asser- tion of the ten pin high with reset_n, cke and cs_n held high; clk_t, clk_c, and cke signals become test inputs within t ctect_valid. the remaining ct inputs become valid t ct_enable after ten goes high when cs_n allows input to begin sampling, pro- vided inputs were valid for at least t ct_valid. while in ct mode, refresh activities in the memory arrays are not allowed; they are initiated either externally (auto refresh) or in- ternally (self refresh). the ten pin may be asserted after the dram has completed power-on. after the dram is initialized and v refdq is calibrated, ct mode may no longer be used. the ten pin may be de-asserted at any time in ct mode. upon exiting ct mode, the states and the integrity of the original content of the memory array are unknown. a full reset of the memory device is required. after ct mode has been entered, the output signals will be stable within t ct_valid after the test inputs have been applied as long as ten is maintained high and cs_n is main- tained low. 8gb: x4, x8, x16 ddr4 sdram connectivity test mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 129 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 73: connectivity test mode entry t ctcke_valid t = 10ns cs_n ct inputs ct outputs t ct_enable t cksrx t ctcke_valid >10ns t ct_is >0ns t = 500s t = 200s t is t ct_valid t ct_valid t ct_valid ten valid input valid input valid input valid input valid input valid input valid valid reset_n cke ck_c ck_t ta tb tc td t ct_is t ct_is t ct_is t ct_is dont care 8gb: x4, x8, x16 ddr4 sdram connectivity test mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 130 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
excessive row activation rows can be accessed a limited number of times within a certain time period before ad- jacent rows require refresh. the maximum activate count (mac) is the maximum num- ber of activates that a single row can sustain within a time interval of equal to or less than the maximum activate window ( t maw) before the adjacent rows need to be re- freshed, regardless of how the activates are distributed over t maw. micron's ddr4 devices automatically perform a type of trr mode in the background and provide an mpr page 3 mpr3[3:0] of 1000, indicating there is no restriction to the number of activate commands to a given row in a refresh period provided dram tim- ing specifications are not violated. table 40: mac encoding of mpr page 3 mpr3 [7] [6] [5] [4] [3] [2] [1] [0] mac comments xxxx0000 untested the device has not been tested for mac. xxxx0001 t mac = 700k xxxx0010 t mac = 600k xxxx 0011 t mac = 500k xxxx0100 t mac = 400k xxxx0101 t mac = 300k xxxx0110 reserved xxxx0111 t mac = 200k x x x x 1 0 0 0 unlimited there is no restriction to the number of ac- tivate commands to a given row in a re- fresh period provided dram timing specifi- cations are not violated. x x x x 1 0 0 1 reserved x x x x : : : : reserved x x x x 1 1 1 1 reserved note: 1. mac encoding in mpr page 3 mpr3. 8gb: x4, x8, x16 ddr4 sdram excessive row activation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 131 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
post package repair post package repair jedec defines two modes of post package repair (ppr): soft post package repair (sppr) and hard post package repair (hppr). sppr is non-persistent so the repair row maybe altered; that is, sppr is not a permanent repair and even though it will repair a row, the repair can be reversed, reassigned via another sppr, or made permanent via hppr. hard post package repair is persistent so once the repair row is assigned for a hppr ad- dress, further ppr commands to a previous hppr section should not be performed, that is, hppr is a permanent repair; once repaired, it cannot be reversed. the controller pro- vides the failing row address in the hppr/sppr sequence to the device to perform the row repair. hppr mode and sppr mode may not be enabled at the same time. jedec states hppr is optional for 4gb and sppr is optional for 4gb and 8gb parts how- ever micron 4gb and 8gb ddr4 drams should have both sppr and hppr support. the hppr support is identified via an mpr read from mpr page 2, mpr0[7] and sppr sup- port is identified via an mpr read from mpr page 2, mpr0[6]. the jedec minimum support requirement for ddr4 ppr (hppr or sppr) is to provide one row of repair per bank group (bg), x4/x8 have 4 bg and x16 has 2 bg; this is a total of 4 repair rows available on x4/x8 and 2 repair rows available on x16. micron ppr sup- port exceeds the jedec minimum requirements; micron ddr4 drams have at least one row of repair for each bank which is essentially 4 row repairs per bg for a total of 16 repair rows for x4 and x8 and 8 repair rows for x16; a 4x increase in repair rows. jedec requires the user to have all sppr row repair addresses reset and cleared prior to enabling hppr mode. micron ddr4 ppr does not have this restriction, the existing sppr row repair addresses are not required to be cleared prior to entering hppr mode. each bank in a bg is ppr independent: sppr or hppr issued to a bank will not alter a sppr row repair existing in a different bank. sppr followed by sppr to same bank when ppr is issued to a bank for the first time and is a sppr command, the repair row will be a sppr. when a subsequent sppr is issued to the same bank, the previous sppr repair row will be cleared and used for the subsequent sppr address as the sppr opera- tion is non-persistent. sppr followed by hppr to same bank when a ppr is issued to a bank for the first time and is a sppr command, the repair row will be a sppr. when a subsequent hppr is issued to the same bank, the initial sppr repair row will be cleared and used for the hppr address. if a further subsequent ppr (hppr or sppr) is issued to the same bank, the further subsequent ppr ( hppr or sppr) repair row will not clear or overwrite the previous hppr address as the hppr operation is persistent. hppr followed by hppr or sppr to same bank when a ppr is issued to a bank for the first time and is a hppr command, the repair row will be a hppr. when a subsequent ppr (hppr or sppr) is issued to the same bank, the subsequent ppr ( hppr or sppr) repair row will not clear or overwrite the initial hppr address as the initial hppr is persistent. 8gb: x4, x8, x16 ddr4 sdram post package repair 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 132 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
hard post package repair all banks must be precharged and idle. dbi and crc modes must be disabled. both sppr and hppr must be disabled. sppr is disabled with mr4[5] = 0. hppr is disabled with mr4[13] = 0, which is the normal state, and hppr is enabled with mr4 [13]= 1, which is the hppr enabled state. there are two forms of hppr mode. both forms of hppr have the same entry requirement as defined in the sections below. the first com- mand sequence uses a wra command and supports data retention with a refresh operation except for the bank containing the row that is being repaired; jedec has re- laxed this requirement and allows ba[0] to be a don't care regarding the banks which are not required to maintain data a refresh operation during hppr. the second com- mand sequence uses a wr command (a refresh operation can't be performed in this command sequence). the second command sequence doesn't support data retention for the target dram. hppr row repair - entry as stated above, all banks must be precharged and idle. dbi and crc modes must be disabled, and all timings must be followed as shown in the timing diagram that follows. all other commands except those listed in the following sequences are illegal. 1. issue mr4[13] 1 to enter hppr mode enable. a. all dq are driven high. 2. issue four consecutive guard key commands (shown in the table below) to mr0 with each command separated by t mod. the ppr guard key settings are the same whether performing sppr or hppr mode. a. any interruption of the key sequence by other commands, such as act, wr, rd, pre, ref, zq, and nop, are not allowed. b. if the guard key bits are not entered in the required order or interrupted with other mr commands, hppr will not be enabled, and the programming cycle will result in a nop. c. when the hppr entry sequence is interrupted and followed by act and wr commands, these commands will be conducted as normal dram com- mands. d. jedec allows a6:0 to be "don't care" on 4gb and 8gb devices from a suppli- er perspective and the user should rely on vendor datasheet. table 41: ppr mr0 guard key settings mr0 bg1:0 ba1:0 a17:12 a11 a10 a9 a8 a7 a6:0 first guard key 0 0 xxxxxx 1 1 0 0 1 1111111 second guard key 0 0 xxxxxx 0 1 1 1 1 1111111 third guard key 0 0 xxxxxx 1 0 1 1 1 1111111 fourth guard key 0 0 xxxxxx 0 0 1 1 1 1111111 hppr row repair C wra initiated (ref commands allowed) 1. issue an act command with failing bg and ba with the row address to be re- paired. 2. issue a wra command with bg and ba of failing row address. a. the address must be at valid levels, but the address is "don't care." 8gb: x4, x8, x16 ddr4 sdram hard post package repair 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 133 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
3. all dq of the target dram should be driven low for 4 n ck (bit 0 through bit 7) after wl (wl = cwl + al + pl) in order for hppr to initiate repair. a. repair will be initiated to the target dram only if all dq during bit 0 through bit 7 are low. the bank under repair does not get the refresh command ap- plied to it. b. repair will not be initiated to the target dram if any dq during bit 0 through bit 7 is high. 1. jedec states: all dqs of target dram should be low for 4 t ck. if high is driven to all dqs of a dram consecutively for equal to or longer than 2 t ck, then dram does not conduct hppr and retains data if ref com- mand is properly issued; if all dqs are neither low for 4 t ck nor high for equal to or longer than 2 t ck, then hppr mode execution is un- known. c. dqs should function normally. 4. ref command may be issued anytime after the wra command followed by wl + 4nck + t wr + t rp. a. multiple ref commands are issued at a rate of t refi or t refi/2, however back-to-back ref commands must be separated by at least t refi/4 when the dram is in hppr mode. b. all banks except the bank under repair will perform refresh. 5. issue pre after t pgm time so that the device can repair the target row during t pgm time. a. wait t pgm_exit after pre to allow the device to recognize the repaired target row address. 6. issue mr4[13] 0 command to hppr mode disable. a. wait t pgmpst for hppr mode exit to complete. b. after t pgmpst has expired, any valid command may be issued. the entire sequence from hppr mode enable through hppr mode disable may be re- peated if more than one repair is to be done. after completing hppr mode, mr0 must be re-programmed to a prehppr mode state if the device is to be accessed. after hppr mode has been exited, the dram controller can confirm if the target row was repaired correctly by writing data into the target row and reading it back. 8gb: x4, x8, x16 ddr4 sdram hard post package repair 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 134 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 74: hppr wra C entry $''5 &0' 056 &.( '46bw '46bf '4v 9dolg %$ 9dolg %$i %* 9dolg 9dolg %*i w 02' w 5&' &.bw &.bf 1$ 1$ 1$ '(6 1$ 1$ 1$ 056 '(6 1$ 1$ 1$ 056 '(6 1$ 1$ 1$ 056 '(6 1$ 1$ 1$ 056 '(6 1$ 1$ 1$ 1rupdo 0rgh $oo%dqnv 3uhfkdujhg dqglgohvwdwh k3355hsdlu $&7 :5$ k335(qwu\ vw *xdug.h\9dolgdwh qg *xdug.h\9dolgdwh ug *xdug.h\9dolgdwh wk *xdug.h\9dolgdwh w 02' w 02' w 02' w 02' '(6 %$i %*i 7 7 7d 7d 7e 7e 7f 7f 7g 7g 7h 7i 7j vw .h\ qg .h\ ug .h\ wk .h\ 9dolg $ 'rq?w&duh figure 75: hppr wra ? repair and exit addr cmd cke dqs_t dqs_c dqs 1 valid ba baf bg valid bgf t rcd wl = cwl+al+pl t wr + t rp + 1nck ck_t ck_c n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a all banks precharged and idle state normal mode hppr recognition hppr exit hppr repair hppr repair hppr repair mrsx t pgm act wra valid (a13 = 0) valid valid valid valid valid valid valid valid n/a n/a n/a t pgm_exit t pgmpst ref/des ref/des ref/des des des des des des n/a n/a n/a des pre valid baf bgf te0 tf0 tg0 tg1 th0 th1 tj0 tj1 tj2 tk0 tk1 tm0 tm1 tn0 4nck bit 0 bit 7 bit 6 bit 1 dont care hppr row repair C wr initiated (ref commands not allowed) 1. issue an act command with failing bg and ba with the row address to be re- paired. 2. issue a wr command with bg and ba of failing row address. a. the address must be at valid levels, but the address is "don't care." 3. all dq of the target dram should be driven low for 4 n ck (bit 0 through bit 7) after wl (wl = cwl + al + pl) in order for hppr to initiate repair. a. repair will be initiated to the target dram only if all dq during bit 0 through bit 7 are low. b. repair will not be initiated to the target dram if any dq during bit 0 through bit 7 is high. 1. jedec states: all dqs of target dram should be low for 4 t ck. if high is driven to all dqs of a dram consecutively for equal to or longer than 2 t ck, then dram does not conduct hppr and retains data if ref com- mand is properly issued; if all dqs are neither low for 4 t ck nor high for equal to or longer than 2 t ck, then hppr mode execution is un- known. 8gb: x4, x8, x16 ddr4 sdram hard post package repair 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 135 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
c. dqs should function normally. 4. ref commands may not be issued at anytime while in ppt mode. 5. issue pre after t pgm time so that the device can repair the target row during t pgm time. a. wait t pgm_exit after pre to allow the device to recognize the repaired target row address. 6. issue mr4[13] 0 command to hppr mode disable. a. wait t pgmpst for hppr mode exit to complete. b. after t pgmpst has expired, any valid command may be issued. the entire sequence from hppr mode enable through hppr mode disable may be re- peated if more than one repair is to be done. after completing hppr mode, mr0 must be re-programmed to a prehppr mode state if the device is to be accessed. after hppr mode has been exited, the dram controller can confirm if the target row was repaired correctly by writing data into the target row and reading it back. figure 76: hppr wr C entry $''5 &0' 056 &.( '46bw '46bf '4v 9dolg %$ 9dolg %$i %* 9dolg 9dolg %*i w 02' w 5&' :/ &:/ &.bw &.bf 1$ 1$ 1$ '(6 1$ 1$ 1$ 056 '(6 1$ 1$ 1$ 056 '(6 1$ 1$ 1$ 056 '(6 1$ 1$ 1$ 056 '(6 1$ 1$ 1$ 1rupdo 0rgh $oo%dqnv 3uhfkdujhg dqglgohvwdwh k3355hsdlu $&7 :5 k335(qwu\ vw *xdug.h\9dolgdwh qg *xdug.h\9dolgdwh ug *xdug.h\9dolgdwh wk *xdug.h\9dolgdwh w 02' w 02' w 02' w 02' '(6 %$i %*i 7 7 7d 7d 7e 7e 7f 7f 7g 7g 7h 7i 7j vw .h\ qg .h\ ug .h\ wk .h\ 9dolg $ 'rq?w&duh figure 77: hppr wr ? repair and exit addr cmd cke dqs_t dqs_c dqs 1 valid ba baf bg valid bgf t rcd wl = cwl + al + pl ck_t ck_c n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a all banks precharged and idle state normal mode hppr recognition hppr exit hppr repair hppr repair hppr repair mrsx t pgm act wr valid (a13 = 0) valid valid valid valid valid valid valid valid n/a n/a n/a t pgm_exit t pgmpst des des des des des des des des n/a n/a n/a des pre valid baf bgf te0 tf0 tg0 tg1 th0 th1 tj0 tj1 tj2 tk0 tk1 tm0 tm1 tn0 4nck bit 0 bit 7 bit 6 bit 1 dont care 8gb: x4, x8, x16 ddr4 sdram hard post package repair 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 136 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 42: ddr4 hppr timing parameters ddr4-1600 through ddr4-3200 parameter symbol min max unit hppr programming time t pgm x4, x8 1000 C ms x16 2000 C ms hppr precharge exit time t pgm_exit 15 C ns hppr exit time t pgmpst 50 C s sppr row repair soft post package repair (sppr) is a way to quickly, but temporarily, repair a row ele- ment in a bank on a dram device, where hppr takes longer but permanently repairs a row element. sppr mode is entered in a similar fashion as hppr, sppr uses mr4[5] while hppr uses mr4[13]. sppr is disabled with mr4[5] = 0, which is the normal state, and sppr is enabled with mr4[5] = 1, which is the sppr enabled state. sppr requires the same guard key sequence as hppr to qualify the mr4 ppr entry. after sppr entry, an act command will capture the target bank and target row, herein seed row, where the row repair will be made. after t rcd time, a wr command is used to se- lect the individual dram, through the dq bits, to transfer the repair address into an in- ternal register in the dram. after a write recovery time and pre command, the sppr mode can be exited and normal operation can resume. the dram will retain the soft repair information as long as v dd remains within the op- erating region unless rewritten by a subsequent sppr entry to the same bank. if dram power is removed or the dram is reset, the soft repair will revert to the unrepaired state. hppr and sppr should not be enabled at the same time; micron sppr does not have to be disabled and cleared prior to entering hppr mode. with sppr, micron ddr4 can repair one row per bank. when a subsequent sppr re- quest is made to the same bank, the subsequently issued sppr address will replace the previous sppr address. when the hppr resource for a bank is used up, the bank should be assumed to not have available resources for sppr. if a repair sequence is issued to a bank with no repair resource available, the dram will ignore the programming se- quence. the bank receiving sppr change is expected to retain memory array data in all rows ex- cept for the seed row and its associated row addresses. if the data in the memory array in the bank under sppr repair is not required to be retained, then the handling of the seed rows associated row addresses is not of interest and can be ignored. if the data in the memory array is required to be retained in the bank under sppr mode, then prior to executing the sppr mode, the seed row and its associated row addresses should be backed up and subsequently restored after sppr has been completed. sppr associated seed row addresses are specified in the table below; ba0 is not required by micron drams however it is jedec reserved. table 43: sppr associated rows sppr associated row address ba0* a17 a16 a15 a14 a13 a1 a0 8gb: x4, x8, x16 ddr4 sdram sppr row repair 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 137 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
all banks must be precharged and idle. dbi and crc modes must be disabled, and all sppr timings must be followed as shown in the timing diagram that follows. all other commands except those listed in the following sequences are illegal. 1. issue mr4[5] 1 to enter sppr mode enable. a. all dq are driven high. 2. issue four consecutive guard key commands (shown in the table below) to mr0 with each command separated by t mod. please note that jedec recently added the four guard key entry used for hppr to sppr entry; early drams may not re- quire four guard key entry code. a prudent controller design should accommodate either option in case an earlier dram is used. a. any interruption of the key sequence by other commands, such as act, wr, rd, pre, ref, zq, and nop, are not allowed. b. if the guard key bits are not entered in the required order or interrupted with other mr commands, sppr will not be enabled, and the programming cycle will result in a nop. c. when the sppr entry sequence is interrupted and followed by act and wr commands, these commands will be conducted as normal dram com- mands. d. jedec allows a6:0 to be "don't care" on 4gb and 8gb devices from a suppli- er perspective and the user should rely on vendor datasheet. table 44: ppr mr0 guard key settings mr0 bg1:0 ba1:0 a17:12 a11 a10 a9 a8 a7 a6:0 first guard key 0 0 xxxxxx 1 1 0 0 1 1111111 second guard key 0 0 xxxxxx 0 1 1 1 1 1111111 third guard key 0 0 xxxxxx 1 0 1 1 1 1111111 fourth guard key 0 0 xxxxxx 0 0 1 1 1 1111111 3. after t mod, issue an act command with failing bg and ba with the row address to be repaired. 4. after t rcd, issue a wr command with bg and ba of failing row address. a. the address must be at valid levels, but the address is a "don't care." 5. all dq of the target dram should be driven low for 4 n ck (bit 0 through bit 7) after wl (wl = cwl + al + pl) in order for sppr to initiate repair. a. repair will be initiated to the target dram only if all dq during bit 0 through bit 7 are low. b. repair will not be initiated to the target dram if any dq during bit 0 through bit 7 is high. 1. jedec states: all dqs of target dram should be low for 4 t ck. if high is driven to all dqs of a dram consecutively for equal to or longer than the first 2 t ck, then dram does not conduct hppr and retains data if ref command is properly issued; if all dqs are neither low for 4 t ck nor high for equal to or longer than the first 2 t ck, then hppr mode ex- ecution is unknown. c. dqs should function normally. 6. ref command may not be issued at anytime while in sppr mode. 7. issue pre after t wr time so that the device can repair the target row during t wr time. a. wait t pgm_exit_s after pre to allow the device to recognize the repaired tar- get row address. 8gb: x4, x8, x16 ddr4 sdram sppr row repair 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 138 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
8. issue mr4[5] 0 command to sppr mode disable. a. wait t pgmpst_s for sppr mode exit to complete. b. after t pgmpst_s has expired, any valid command may be issued. the entire sequence from sppr mode enable through sppr mode disable may be repea- ted if more than one repair is to be done. after sppr mode has been exited, the dram controller can confirm if the target row was repaired correctly by writing data into the target row and reading it back. figure 78: sppr C entry $''5 &0' 056 &.( '46bw '46bf '4v 9dolg %$ 9dolg %$i %* 9dolg 9dolg %*i w 02' w 5&' &.bw &.bf 1$ 1$ 1$ '(6 1$ 1$ 1$ 056 '(6 1$ 1$ 1$ 056 '(6 1$ 1$ 1$ 056 '(6 1$ 1$ 1$ 056 '(6 1$ 1$ 1$ 1rupdo 0rgh $oo%dqnv 3uhfkdujhg dqglgohvwdwh v3355hsdlu $&7 :5 v335(qwu\ vw *xdug.h\9dolgdwh qg *xdug.h\9dolgdwh ug *xdug.h\9dolgdwh wk *xdug.h\9dolgdwh w 02' w 02' w 02' w 02' '(6 %$i %*i 7 7 7d 7d 7e 7e 7f 7f 7g 7g 7h 7i 7j vw .h\ qg .h\ ug .h\ wk .h\ 9dolg $ 'rq?w&duh figure 79: sppr ? repair, and exit bit 1 addr cmd cke dqs_t dqs_c dqs 1 valid ba baf bg valid bgf t rcd wl = cwl + al + pl ck_t ck_c n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a all banks precharged and idle state normal mode sppr recognition sppr exit sppr repair sppr repair sppr repair sppr repair mrs4 t pgm_s act wr valid (a5=0) valid valid valid valid valid valid valid valid n/a n/a n/a des des des des des des des des n/a n/a n/a des pre valid baf bgf te0 tf0 tg0 tg1 th0 th1 tj0 tj1 tj2 tk0 tk1 tm0 tm1 tn0 4nck bit 0 bit 7 bit 6 t wr t pgm_exit_s t pgmpst_s dont care table 45: ddr4 sppr timing parameters ddr4-1600 through ddr4-3200 parameter symbol min max unit sppr programming time t pgm_s t rcd (min)+ wl + 4nck + t wr (min) Cns sppr precharge exit time t pgm_exit_s 20 C ns sppr exit time t pgmpst_s t mod C ns 8gb: x4, x8, x16 ddr4 sdram sppr row repair 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 139 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
hppr/sppr support identifier table 46: ddr4 repair mode support identifier mpr page 2 a7 a6 a5 a4 a3 a2 a1 a0 ui0 ui1 ui2 ui3 ui4 ui5 ui6 ui7 mpr0 hppr 1 sppr 2 r tt_wr temp sensor crc r tt_wr notes: 1. 0 = hppr mode is not available, 1 = hppr mode is available. 2. 0 = sppr mode is not available, 1 = sppr mode is available. 3. gray shaded areas are for reference only. activate command the activate command is used to open (activate) a row in a particular bank for subse- quent access. the values on the bg[1:0] inputs select the bank group, the ba[1:0] inputs select the bank within the bank group, and the address provided on inputs a[17:0] se- lects the row within the bank. this row remains active (open) for accesses until a pre- charge command is issued to that bank. a precharge command must be issued be- fore opening a different row in the same bank. bank-to-bank command timing for ac- tivate commands uses two different timing parameters, depending on whether the banks are in the same or different bank group. t rrd_s (short) is used for timing be- tween banks located in different bank groups. t rrd_l (long) is used for timing between banks located in the same bank group. another timing restriction for consecutive acti- vate commands [issued at t rrd (min)] is t faw (fifth activate window). because there is a maximum of four banks in a bank group, the t faw parameter applies across differ- ent bank groups (five activate commands issued at t rrd_l (min) to the same bank group would be limited by t rc). figure 80: t rrd timing t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t rrd_s t10 t11 dont care bg a des act act des des des des des des des des ck_t ck_c command bank group (bg) bank c bank row n bg b bank c row n bg b bank d row n address t rrd_l act notes: 1. t rrd_s; activate-to-activate command period (short); applies to consecutive acti- vate commands to different bank groups (that is, t0 and t4). 2. t rrd_l; activate-to-activate command period (long); applies to consecutive acti- vate commands to the different banks in the same bank group (that is, t4 and t10). 8gb: x4, x8, x16 ddr4 sdram hppr/sppr support identifier 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 140 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 81: t faw timing t0 ta0 tb0 tc0 tc1 tc2 t rrd t rrd td0 td1 dont care time break valid valid act act valid valid valid valid valid nop ck_t ck_c command bank group (bg) valid bank valid act act address t faw act valid valid valid valid valid valid valid valid valid valid valid valid t rrd note: 1. t faw; four activate windows. precharge command the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row activation for a specified time ( t rp) after the precharge command is issued. an exception to this is the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. after a bank is precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. however, the precharge period will be determined by the last precharge command issued to the bank. the auto precharge feature is engaged when a read or write command is issued with a10 high. the auto precharge feature uses the ras lockout circuit to internally delay the precharge operation until the array restore operation has completed. the ras lockout circuit feature allows the precharge operation to be partially or com- pletely hidden during burst read cycles when the auto precharge feature is engaged. the precharge operation will not begin until after the last data of the burst write se- quence is properly stored in the memory array. refresh command the refresh command (ref) is used during normal operation of the device. this command is nonpersistent, so it must be issued each time a refresh is required. the de- vice requires refresh cycles at an average periodic interval of t refi. when cs_n, ras_n/a16, and cas_n/a15 are held low and we_n/a14 high at the rising edge of the clock, the device enters a refresh cycle. all banks of the sdram must be pre- charged and idle for a minimum of the precharge time, t rp (min), before the refresh command can be applied. the refresh addressing is generated by the internal dram re- fresh controller. this makes the address bits dont care during a refresh command. an internal address counter supplies the addresses during the refresh cycle. no con- trol of the external address bus is required once this cycle has started. when the re- fresh cycle has completed, all banks of the sdram will be in the precharged (idle) 8gb: x4, x8, x16 ddr4 sdram precharge command 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 141 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
state. a delay between the refresh command and the next valid command, except des, must be greater than or equal to the minimum refresh cycle time t rfc (min), as shown in figure 82 (page 142). note: the t rfc timing parameter depends on memory density. in general, a refresh command needs to be issued to the device regularly every t refi interval. to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided for postponing and pulling- in the refresh command. a limited number refresh commands can be postponed depending on refresh mode: a maximum of 8 refresh commands can be postponed when the device is in 1x refresh mode; a maximum of 16 refresh commands can be postponed when the device is in 2x refresh mode; and a maximum of 32 refresh commands can be postponed when the device is in 4x refresh mode. when 8 consecutive refresh commands are postponed, the resulting maximum inter- val between the surrounding refresh commands is limited to 9 t refi (see figure 83 (page 143)). for both the 2x and 4x refresh modes, the maximum consecutive re- fresh commands allowed is limited to 17 t refi2 and 36 t refi4, respectively. a limited number refresh commands can be pulled-in as well. a maximum of 8 addi- tional refresh commands can be issued in advance or pulled-in in 1x refresh mode, a maximum of 16 additional refresh commands can be issued when in advance in 2x refresh mode, and a maximum of 32 additional refresh commands can be issued in advance when in 4x refresh mode. each of these refresh commands reduces the number of regular refresh commands required later by one. note that pulling in more than the maximum allowed refresh commands in advance does not further re- duce the number of regular refresh commands required later, so that the resulting maximum interval between two surrounding refresh commands is limited to 9 t re- fi (figure 84 (page 143)), 18 t rfei2, or 36 t refi4. at any given time, a maximum of 16 ref commands can be issued within 2 t refi, 32 ref2 commands can be issued within 4 t refi2, and 64 ref4 commands can be issued within 8 t refi4. figure 82: refresh command timing des ref des ref valid valid valid valid ref valid valid valid ck_t ck_c command t rfc t rfc (min) t refi (max 9 t refi) dont care time break t0 t1 ta0 ta1 tb0 tb1 tb2 tb3 tc0 tc1 tc2 tc3 valid des des dram must be idle dram must be idle notes: 1. only des commands are allowed after a refresh command is registered until t rfc (min) expires. 2. time interval between two refresh commands may be extended to a maximum of 9 t refi. 8gb: x4, x8, x16 ddr4 sdram refresh command 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 142 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 83: postponing refresh commands (example) w 8 ref-commands postponed t rfc t refi 9 t refi figure 84: pulling in refresh commands (example) w 8 ref-commands pulled-in t rfc t refi 9 t refi 8gb: x4, x8, x16 ddr4 sdram refresh command 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 143 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
temperature-controlled refresh mode during normal operation, temperature-controlled refresh (tcr) mode disabled, the de- vice must have a refresh command issued once every t refi, except for what is al- lowed by posting (see refresh command section). this means a refresh command must be issued once every 3.9s if t c is greater than or equal to 85c, and once every 7.8s if t c is less than 85c. this mode is disabled setting mr4[3] = 0 while mode is ena- bled setting mr4[3] = 1. when enabled (mr4[3] = 1), the temperature range must be se- lected where mr4[2] = 0 enables the normal temperature range while mr4[2] = 1 ena- bles the extended temperature range table 47: normal t refi refresh (tcr disabled) temperature normal temperature extended temperature external refresh period internal refresh period external refresh period internal refresh period t c < 45c 7.8s 7.8s 3.9s 1 3.9s 1 45c t c < 85c 85c t c < 95c n/a note: 1. if t c is less than 85c, the external refresh period can be 7.8s instead of 3.9s. when tcr mode is enabled, the device will register the externally supplied refresh command and adjust the internal refresh period to be longer than t refi of the normal temperature range, when allowed, by skipping refresh commands with the proper gear ratio. tcr mode has two ranges to select between the normal temperature range and the extended temperature range; the correct range must be selected so the internal control operates correctly. the dram must have the correct refresh rate applied exter- nally; the internal refresh rate is determined by the dram based upon the temperature. tcr mode C normal temperature range refresh commands should be issued to the device with the refresh period equal to or shorter than t refi of normal temperature range (0c to 85c). in this mode, the system must guarantee that the t c does not exceed 85c. the device may adjust the internal refresh period to be longer than t refi of the normal temperature range by skipping ex- ternal refresh commands with the proper gear ratio when t c is below 45c. the in- ternal refresh period is automatically adjusted inside the dram, and the dram con- troller does not need to provide any additional control. tcr mode C extended temperature range refresh commands should be issued to the device with the refresh period equal to or shorter than t refi of extended temperature range (85c to 95c). in this mode, the sys- tem must guarantee that the t c does not exceed 95c. even though the external refresh supports the extended temperature range, the device will adjust its internal refresh peri- od to t refi of the normal temperature range by skipping external refresh commands with proper gear ratio when operating in the normal temperature range (0c to 85c). the device may adjust the internal refresh period to be longer than t refi of the normal temperature range by skipping external refresh commands with the proper gear ratio when t c is below 45c. the internal refresh period is automatically adjusted inside the dram, and the dram controller does not need to provide any additional control. 8gb: x4, x8, x16 ddr4 sdram temperature-controlled refresh mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 144 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 48: normal t refi refresh (tcr enabled) normal temperature range extended temperature range temperature external refresh period internal refresh period external refresh period internal refresh period t c < 45c 7.8s > 7.8s 3.9s 1 >>3.9s 45c t c < 85c 7.8s 7.8s >3.9s 85c t c < 95c n/a 3.9s note: 1. if the external refresh period is slower than 3.9s, the device will refresh internally at too slow of a refresh rate and will violate refresh specifications. figure 85: tcr mode example 1 external refresh commands are not ignored every other external refresh ignored at low temperature, more refresh commands can be ignored controller 95c to 85c 85c to 45c below 45c controller issues refresh commands at extended temperature rate refresh external t refi <3.9s internal t refi 3.9s internal t refi >3.9s internal t refi >>3.9s refresh refresh refresh refresh refresh refresh refresh refresh refresh refresh refresh refresh refresh refresh refresh refresh refresh refresh refresh refresh note: 1. tcr enabled with extended temperature range selected. 8gb: x4, x8, x16 ddr4 sdram temperature-controlled refresh mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 145 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
fine granularity refresh mode mode register and command truth table the refresh cycle time ( t rfc) and the average refresh interval ( t refi) can be pro- grammed by the mrs command. the appropriate setting in the mode register will set a single set of refresh cycle times and average refresh interval for the device (fixed mode), or allow the dynamic selection of one of two sets of refresh cycle times and average refresh interval for the device (on-the-fly mode [otf]). otf mode must be ena- bled by mrs before any otf refresh command can be issued. table 49: mrs definition mr3[8] mr3[7] mr3[6] refresh rate mode 0 0 0 normal mode (fixed 1x) 0 0 1 fixed 2x 0 1 0 fixed 4x 0 1 1 reserved 1 0 0 reserved 1 0 1 on-the-fly 1x/2x 1 1 0 on-the-fly 1x/4x 1 1 1 reserved there are two types of otf modes (1x/2x and 1x/4x modes) that are selectable by pro- gramming the appropriate values into the mode register mr3 [8:6]. when either of the two otf modes is selected, the device evaluates the bg0 bit when a refresh com- mand is issued, and depending on the status of bg0, it dynamically switches its internal refresh configuration between 1x and 2x (or 1x and 4x) modes, and then executes the corresponding refresh operation. table 50: refresh command truth table refresh cs_n act_n ras_n/a 15 cas_n/a 14 we_n/ a13 bg1 bg0 a10/ ap a[9:0], a[12:11], a[20:16] mr3[8:6 ] fixed rate l h l l h v v v v 0vv otf: 1x l h l l h v l v v 1vv otf: 2x l h l l h v h v v 101 otf: 4x l h l l h v h v v 110 t refi and t rfc parameters the default refresh rate mode is fixed 1x mode where refresh commands should be issued with the normal rate; that is, t refi1 = t refi(base) (for t c 85c), and the dura- tion of each refresh command is the normal refresh cycle time ( t rfc1). in 2x mode (either fixed 2x or otf 2x mode), refresh commands should be issued to the device at the double frequency ( t refi2 = t refi(base)/2) of the normal refresh rate. in 4x mode, the refresh command rate should be quadrupled ( t refi4 = t refi(base)/4). per 8gb: x4, x8, x16 ddr4 sdram fine granularity refresh mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 146 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
each mode and command type, the t rfc parameter has different values as defined in the following table. for discussion purposes, the refresh command that should be issued at the normal refresh rate and has the normal refresh cycle duration may be referred to as an ref1x command. the refresh command that should be issued at the double frequency ( t refi2 = t refi(base)/2) may be referred to as a ref2x command. finally, the refresh command that should be issued at the quadruple rate ( t refi4 = t refi(base)/4) may be referred to as a ref4x command. in the fixed 1x refresh rate mode, only ref1x commands are permitted. in the fixed 2x refresh rate mode, only ref2x commands are permitted. in the fixed 4x refresh rate mode, only ref4x commands are permitted. when the on-the-fly 1x/2x refresh rate mode is enabled, both ref1x and ref2x commands are permitted. when the otf 1x/4x refresh rate mode is enabled, both ref1x and ref4x commands are permitted. table 51: t refi and t rfc parameters refresh mode parameter 2gb 4gb 8gb 16gb units t refi (base) 7.8 7.8 7.8 7.8 s 1x mode t refi1 0c t c 85c t refi(base) t refi(base) t refi(base) t refi(base) s 85c t c 95c t refi(base)/2 t refi(base)/2 t refi(base)/2 t refi(base)/2 s t rfc1 160 260 350 550 ns 2x mode t refi2 0c t c 85c t refi(base)/2 t refi(base)/2 t refi(base)/2 t refi(base)/2 s 85c t c 95c t refi(base)/4 t refi(base)/4 t refi(base)/4 t refi(base)/4 s t rfc2 110 160 260 350 ns 4x mode t refi4 0c t c 85c t refi(base)/4 t refi(base)/4 t refi(base)/4 t refi(base)/4 s 85c t c 95c t refi(base)/8 t refi(base)/8 t refi(base)/8 t refi(base)/8 s t rfc4 90 110 160 260 ns 8gb: x4, x8, x16 ddr4 sdram fine granularity refresh mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 147 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 86: 4gb with fine granularity refresh mode example t refi = 0.975s t refi = 0.975s t refi = 0.975s t refi = 0.975s t refi = 0.975s t refi = 0.975s t refi = 0.975s t refi = 0.975s t refi = 0.975s t refi = 0.975s t refi = 0.975s t refi = 0.975s t refi = 0.975s t refi = 0.975s t refi = 0.975s t refi = 0.975s 1x mode (0c to 85c) 2x mode (0c to 85c) 4x mode (0c to 85c) normal temperature operation C 0c to 85c ref@260ns ref@160ns ref@110ns ref@110ns ref@160ns ref@110ns ref@110ns ref@260ns ref@160ns ref@110ns ref@110ns ref@160ns ref@110ns ref@110ns ref@260ns ref@160ns ref@110ns t refi = 7.8s t refi = 7.8s t refi = 3.9s t refi = 3.9s t refi = 3.9s t refi = 3.9s t refi = 1.95s t refi = 1.95s t refi = 1.95s t refi = 1.95s t refi = 1.95s t refi = 1.95s t refi = 1.95s t refi = 1.95s 1x mode (0c to 95c) 2x mode (0c to 95c) 4x mode (0c to 95c) ref@260ns ref@160ns ref@110ns ref@110ns ref@160ns ref@110ns ref@110ns ref@260ns ref@160ns ref@110ns ref@110ns ref@160ns ref@110ns ref@110ns ref@260ns ref@260ns ref@260ns ref@160ns ref@160ns ref@160ns ref@160ns ref@160ns ref@110ns ref@110ns ref@110ns ref@110ns ref@110ns ref@110ns ref@110ns ref@110ns ref@110ns t refi = 3.9s t refi = 3.9s t refi = 3.9s t refi = 3.9s t refi = 1.95s t refi = 1.95s t refi = 1.95s t refi = 1.95s t refi = 1.95s t refi = 1.95s t refi = 1.95s t refi = 1.95s extended temperature operation C 0c to 95c 8gb: x4, x8, x16 ddr4 sdram fine granularity refresh mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 148 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
changing refresh rate if the refresh rate is changed by either mrs or otf. new t refi and t rfc parameters will be applied from the moment of the rate change. when the ref1x command is issued to the dram, t ref1 and t rfc1 are applied from the time that the command was issued; when the ref2x command is issued, t ref2 and t rfc2 should be satisfied. figure 87: otf refresh command timing ref1 des des des valid des ref2 des valid valid des des des ref2 t rfc1 (min) t rfc2 (min) t refi1 t refi2 dont care command ck_t ck_c the following conditions must be satisfied before the refresh rate can be changed. oth- erwise, data retention cannot be guaranteed. ? in the fixed 2x refresh rate mode or the otf 1x/2x refresh mode, an even number of ref2x commands must be issued because the last change of the refresh rate mode with an mrs command before the refresh rate can be changed by another mrs com- mand. ? in the otf1x/2x refresh rate mode, an even number of ref2x commands must be is- sued between any two ref1x commands. ? in the fixed 4x refresh rate mode or the otf 1x/4x refresh mode, a multiple-of-four number of ref4x commands must be issued because the last change of the refresh rate with an mrs command before the refresh rate can be changed by another mrs command. ? in the otf1x/4x refresh rate mode, a multiple-of-four number of ref4x commands must be issued between any two ref1x commands. there are no special restrictions for the fixed 1x refresh rate mode. switching between fixed and otf modes keeping the same rate is not regarded as a refresh rate change. usage with tcr mode if the temperature controlled refresh mode is enabled, only the normal mode (fixed 1x mode, mr3[8:6] = 000) is allowed. if any other refresh mode than the normal mode is selected, the temperature controlled refresh mode must be disabled. self refresh entry and exit the device can enter self refresh mode anytime in 1x, 2x, and 4x mode without any re- striction on the number of refresh commands that have been issued during the mode before the self refresh entry. however, upon self refresh exit, extra refresh com- mand(s) may be required, depending on the condition of the self refresh entry. the conditions and requirements for the extra refresh command(s) are defined as follows: ? in the fixed 2x refresh rate mode or the enable-otf 1x/2x refresh rate mode, it is rec- ommended there be an even number of ref2x commands before entry into self re- fresh after the last self refresh exit, ref1x command, or mrs command that set the 8gb: x4, x8, x16 ddr4 sdram fine granularity refresh mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 149 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
refresh mode. if this condition is met, no additional refresh commands are re- quired upon self refresh exit. in the case that this condition is not met, either one ex- tra ref1x command or two extra ref2x commands must be issued upon self refresh exit. these extra refresh commands are not counted toward the computation of the average refresh interval ( t refi). ? in the fixed 4x refresh rate mode or the enable-otf 1x/4x refresh rate mode, it is rec- ommended there be a multiple-of-four number of ref4x commands before entry in- to self refresh after the last self refresh exit, ref1x command, or mrs command that set the refresh mode. if this condition is met, no additional refresh commands are re- quired upon self refresh exit. when this condition is not met, either one extra ref1x command or four extra ref4x commands must be issued upon self refresh exit. these extra refresh commands are not counted toward the computation of the average refresh interval ( t refi). there are no special restrictions on the fixed 1x refresh rate mode. this section does not change the requirement regarding postponed refresh com- mands. the requirement for the additional refresh command(s) described above is independent of the requirement for the postponed refresh commands. 8gb: x4, x8, x16 ddr4 sdram fine granularity refresh mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 150 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
self refresh operation the self refresh command can be used to retain data in the device, even if the rest of the system is powered down. when in self refresh mode, the device retains data with- out external clocking. the device has a built-in timer to accommodate self refresh operation. the self refresh command is defined by having cs_n, ras_n, cas_n, and cke held low with we_n and act_n high at the rising edge of the clock. before issuing the self refresh entry command, the device must be idle with all banks in the precharge state and t rp satisfied. idle state is defined as: all banks are closed ( t rp, t dal, and so on, satisfied), no data bursts are in progress, cke is high, and all timings from previous operations are satisfied ( t mrd, t mod, t rfc, t zqinit, t zqoper, t zqcs, and so on). after the self refresh entry command is registered, cke must be held low to keep the device in self refresh mode. the dram automatically disables odt termination, regardless of the odt pin, when it enters self refresh mode and auto- matically enables odt upon exiting self refresh. during normal operation (dll_on), the dll is automatically disabled upon entering self refresh and is automatically ena- bled (including a dll reset) upon exiting self refresh. when the device has entered self refresh mode, all of the external control signals, except cke and reset_n, are dont care. for proper self refresh operation, all power supply and reference pins (v dd , v ddq , v ss , v ssq , v pp , and v refca ) must be at valid levels. the dram internal v refdq generator circuitry may remain on or be turned off depend- ing on the mrx bit y setting. if the internal v refdq circuit is on in self refresh, the first write operation or first write-leveling activity may occur after t xs time after self re- fresh exit. if the dram internal v refdq circuitry is turned off in self refresh, it ensures that the v refdq generator circuitry is powered up and stable within the t xsdll period when the dram exits the self refresh state. the first write operation or first write-lev- eling activity may not occur earlier than t xsdll after exiting self refresh. the device ini- tiates a minimum of one refresh command internally within the t cke period once it enters self refresh mode. the clock is internally disabled during a self refresh operation to save power. the minimum time that the device must remain in self refresh mode is t ckesr/ t ckesr_par. the user may change the external clock frequency or halt the external clock t cksre/ t cksre_par after self refresh entry is registered; however, the clock must be restarted and t cksrx must be stable before the device can exit self refresh oper- ation. the procedure for exiting self refresh requires a sequence of events. first, the clock must be stable prior to cke going back high. once a self refresh exit command (srx, combination of cke going high and deselect on the command bus) is registered, the following timing delay must be satisfied: commands that do not require locked dll: ? t xs = act, pre, prea, ref, sre, and pde. ? t xs_fast = zqcl, zqcs, and mrs commands. for an mrs command, only dram cl, wr/rtp register, and dll reset in mr0; r tt(nom) register in mr1; the cwl and r tt(wr) registers in mr2; and gear-down mode register in mr3; write and read pre- amble registers in mr4; r tt(park) register in mr5; t ccd_l/ t dllk and v refdq calibra- tion value registers in mr6 may be accessed provided the dram is not in per-dram mode. access to other dram mode registers must satisfy t xs timing. write com- mands (wr, wrs4, wrs8, wra, wras4, and wras8) that require synchronous odt and dynamic odt controlled by the write command require a locked dll. 8gb: x4, x8, x16 ddr4 sdram self refresh operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 151 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
commands that require locked dll in the normal operating range: ? t xsdll C rd, rds4, rds8, rda, rdas4, and rdas8 (unlike ddr3, wr, wrs4, wrs8, wra, wras4, and wras8 because synchronous odt is required). depending on the system environment and the amount of time spent in self refresh, zq calibration commands may be required to compensate for the voltage and tempera- ture drift described in the zq calibration commands section. to issue zq calibra- tion commands, applicable timing requirements must be satisfied (see the zq calibra- tion timing figure). cke must remain high for the entire self refresh exit period t xsdll for proper opera- tion except for self refresh re-entry. upon exit from self refresh, the device can be put back into self refresh mode or power-down mode after waiting at least t xs period and issuing one refresh command (refresh period of t rfc). the deselect command must be registered on each positive clock edge during the self refresh exit interval t xs. odt must be turned off during t xsdll. the use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh, the device requires a minimum of one extra refresh command before it is put back into self refresh mode. figure 88: self refresh entry/exit timing ck_t ck_c command des des sre addr cke odt srx valid 1 valid 2 valid valid t rp t xs t xsdll t ckesr/ t ckesr_par t cpded t is t cksre/ t cksre_par t cksrx enter self refresh exit self refresh t0 t1 ta0 td0 td1 te0 tc0 dont care tf0 time break tb0 tg0 t xs_fast valid 3 valid valid valid valid valid notes: 1. only mrs (limited to those described in the self refresh operation section), zqcs, or zqcl commands are allowed. 2. valid commands not requiring a locked dll. 3. valid commands requiring a locked dll. 8gb: x4, x8, x16 ddr4 sdram self refresh operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 152 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 89: self refresh entry/exit timing with cal mode 7 &.bw &.bf 7 7 7 &rppdqg $''5 zr&6bq &6bq &.( 'rq?w&duh 7d 7 7 7d 7d 7 7e 7e 7d 7d 7 e '(6 '(6 '(6 65; '(6 '(6 '(6 '(6 9dolg 9dolg '(6 65( 9dolg w &.65( w ;6b)$67 w &.65; w &$/ w &3'(' w &$/ 1rwh 1rwh notes: 1. t cal = 3nck, t cpded = 4nck, t cksre/ t cksre_par = 8 nck, t cksrx = 8nck, t xs_fast = t refc4 (min) + 10ns. 2. cs_n = high, act_n = "don't care," ras_n/a16 = "don't care," cas_n/a15 = "don't care," we_n/a14 = "don't care." 3. only mrs (limited to those described in the self refresh operations section), zqcs, or zqcl commands are allowed. self refresh abort the exit timing from self refresh exit to the first valid command not requiring a locked dll is t xs. the value of t xs is ( t rfc + 10ns). this delay allows any refreshes started by the device time to complete. t rfc continues to grow with higher density devices, so t xs will grow as well. an mrs bit enables the self refresh abort mode. if the bit is disabled, the controller uses t xs timings (location mr4, bit 9). if the bit is enabled, the device aborts any ongoing refresh and does not increment the refresh counter. the controller can issue a valid command not requiring a locked dll after a delay of t xs_abort. upon exit from self refresh, the device requires a minimum of one extra refresh com- mand before it is put back into self refresh mode. this requirement remains the same irrespective of the setting of the mrs bit for self refresh abort. 8gb: x4, x8, x16 ddr4 sdram self refresh operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 153 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 90: self refresh abort ck_t ck_c command des des sre addr cke odt srx valid 1 valid 2 valid valid t rp t xs_abort t xsdll t ckesr/ t ckesr_par t cpded t is t cksre/ t cksre_par t cksrx enter self refresh exit self refresh t0 t1 ta0 td0 td1 te0 tc0 dont care tf0 time break tb0 tg0 t xs_fast valid 3 valid valid valid valid valid notes: 1. only mrs (limited to those described in the self refresh operation section), zqcs, or zqcl commands are allowed. 2. valid commands not requiring a locked dll with self refresh abort mode enabled in the mode register. 3. valid commands requiring a locked dll. self refresh exit with nop command exiting self refresh mode using the no operation command (nop) is allowed under a specific system application. this special use of nop allows for a common command/ address bus between active dram devices and dram(s) in maximum power saving mode. self refresh mode may exit with nop commands provided: ? the device entered self refresh mode with ca parity and cal disabled. ? t mpx_s and t mpx_lh are satisfied. ? nop commands are only issued during t mpx_lh window. no other command is allowed during the t mpx_lh window after an self refresh ex- it (srx) command is issued. 8gb: x4, x8, x16 ddr4 sdram self refresh operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 154 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 91: self refresh exit with nop command 7d &.bw &.bf 7d 7d 7d 7g 7e 7e 7e 7g 7f 7e 7f 7f 7f 7h 7h 7f 7 g 7 g &.( 2'7 w &.65; w 03;b/+ w 03;b6 &rppdqg $''5 &6bq 'rq?w&duh '(6 '(6 '(6 9dolg '(6 '(6 9dolg 9dolg 9dolg 9dolg 65; 123 123 123 123 w ;6 w ;6'// w ;6 9dolg 1rwh 1rwh '(6 9dolg 9dolg 9dolg 9dolg 8gb: x4, x8, x16 ddr4 sdram self refresh operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 155 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
power-down mode power-down is synchronously entered when cke is registered low (along with a dese- lect command). cke is not allowed to go low when the following operations are in progress: mrs command, mpr operations, zqcal operations, dll locking, or read/ write operations. cke is allowed to go low while any other operations, such as row activation, precharge or auto precharge, or refresh, are in progress, but the power-down i dd specification will not be applied until those operations are complete. the timing diagrams that follow illustrate power-down entry and exit. for the fastest power-down exit timing, the dll should be in a locked state when pow- er-down is entered. if the dll is not locked during power-down entry, the dll must be reset after exiting power-down mode for proper read operation and synchronous odt operation. dram design provides all ac and dc timing and voltage specification as well as proper dll operation with any cke intensive operations as long as the control- ler complies with dram specifications. during power-down, if all banks are closed after any in-progress commands are com- pleted, the device will be in precharge power-down mode; if any bank is open after in- progress commands are completed, the device will be in active power-down mode. entering power-down deactivates the input and output buffers, excluding ck, cke, and reset_n. in power-down mode, dram odt input buffer deactivation is based on mrx bit y. if it is configured to 0b, the odt input buffer remains on and the odt input signal must be at valid logic level. if it is configured to 1b, the odt input buffer is deactivated and the dram odt input signal may be floating and the device does not provide r tt(nom) termination. note that the device continues to provide r tt(park) termination if it is enabled in the mode register mra bit b. to protect internal delay on the cke line to block the input signals, multiple des commands are needed during the cke switch off and on cycle(s); this timing period is defined as t cpded. cke low will result in deacti- vation of command and address receivers after t cpded has expired. table 52: power-down entry definitions dram status dll power- down exit relevant parameters active (a bank or more open) on fast t xp to any valid command. precharged (all banks precharged) on fast t xp to any valid command. the dll is kept enabled during precharge power-down or active power-down. in pow- er-down mode, cke is low, reset_n is high, and a stable clock signal must be main- tained at the inputs of the device. odt should be in a valid state, but all other input sig- nals are "don't care." (if reset_n goes low during power-down, the device will be out of power-down mode and in the reset state.) cke low must be maintained until t cke has been satisfied. power-down duration is limited by 9 t refi. the power-down state is synchronously exited when cke is registered high (along with des command). cke high must be maintained until t cke has been satisfied. the odt input signal must be at a valid level when the device exits from power-down mode, independent of mrx bit y if r tt(nom) is enabled in the mode register. if r tt(nom) is disa- bled, the odt input signal may remain floating. a valid, executable command can be 8gb: x4, x8, x16 ddr4 sdram power-down mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 156 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
applied with power-down exit latency, t xp, after cke goes high. power-down exit laten- cy is defined in the ac specifications table. figure 92: active power-down entry and exit ck_t ck_c command des des des des des address cke enter power-down mode exit power-down mode t pd valid valid valid valid t cpded valid valid odt (odt buffer enabled - mr5 [5] = 0) 2 odt (odt buffer disbled - mr5 [5] = 1) 3 t ih t ih t is t is t is t0 t1 t2 ta0 ta1 tb0 tb1 tc0 des t xp t cke dont care time break notes: 1. valid commands at t0 are act, des, or pre with one bank remaining open after comple- tion of the precharge command. 2. odt pin driven to a valid state; mr5[5] = 0 (normal setting). 3. odt pin driven to a valid state; mr5[5] = 1. 8gb: x4, x8, x16 ddr4 sdram power-down mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 157 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 93: power-down entry after read and read with auto precharge t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 rl = al + cl ta8 tb0 tb1 des valid valid rd or rda des des des des des des des des des des valid valid ck_t ck_c command dq bl8 dq bc4 dqs_t, dqs_c address cke t cpded t is t pd t rdpden power-down entry transitioning data dont care time break di b+3 di b+2 di b+1 di b di n+3 di n+2 di n+1 di n di b+7 di b+6 di b+5 di b+4 note: 1. di n (or b) = data-in from column n (or b). figure 94: power-down entry after write and write with auto precharge t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 wl = al + cwl tb0 tb1 tb2 tc0 tc1 bank, col n di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 des write des des des des des des des des des des des des ck_t ck_c command dq bl8 dq bc4 dqs_t, dqs_c address a10 cke wr t cpded t is t pd t wrapden power-down entry start internal precharge di n + 3 di n + 2 di n + 1 di n transitioning data 'rq?w&duh 7lph%uhdn valid valid valid notes: 1. di n (or b) = data-in from column n (or b). 2. valid commands at t0 are act, des, or pre with one bank remaining open after comple- tion of the precharge command. 8gb: x4, x8, x16 ddr4 sdram power-down mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 158 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 95: power-down entry after write t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 wl = al + cwl tb0 tb1 tb2 tc0 tc1 bank, col n des write des des des des des des des des des des des des ck_t ck_c command dq bl8 dq bc4 dqs_t, dqs_c address a10 cke t wr t cpded t is t pd t wrpden power-down entry valid valid valid transitioning data dont care time break di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 di n + 3 di n + 2 di n + 1 di n note: 1. di n (or b) = data-in from column n (or b). figure 96: precharge power-down entry and exit ck_t ck_c command des des des des des des cke enter power-down mode exit power-down mode t pd t xp t cpded t is t ih t is t0 t1 t2 ta0 ta1 tb0 tb1 tc0 t cke dont care time break valid valid valid 8gb: x4, x8, x16 ddr4 sdram power-down mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 159 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 97: refresh command to power-down entry ck_t ck_c command ref des des des address valid cke t refpden t cpded t cke t0 t1 t2 ta0 tb0 tb1 t pd dont care time break valid t is des figure 98: active command to power-down entry ck_t ck_c command act des des des address valid cke t actpden t cpded t cke t is t0 t1 t2 ta0 tb0 tb1 t pd dont care time break valid des 8gb: x4, x8, x16 ddr4 sdram power-down mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 160 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 99: precharge/precharge all command to power-down entry ck_t ck_c command pre or prea des des des valid address valid cke t prepden t cpded t0 t1 t2 ta0 tb0 tb1 t pd t cke dont care time break t is figure 100: mrs command to power-down entry ck_t ck_c command mrs des des des address valid cke t mrspden t cpded t0 t1 tb0 tb1 ta0 ta1 t pd t cke dont care time break valid t is des power-down clarifications C case 1 when cke is registered low for power-down entry, t pd (min) must be satisfied before cke can be registered high for power-down exit. the minimum value of parameter t pd (min) is equal to the minimum value of parameter t cke (min) as shown in the timing parameters by speed bin table. a detailed example of case 1 follows. 8gb: x4, x8, x16 ddr4 sdram power-down mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 161 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 101: power-down entry/exit clarifications C case 1 ck_t ck_c command valid des des des des address valid cke t cpded enter power-down mode exit power-down mode enter power-down mode t cpded t0 t1 t2 ta0 ta1 t pd t pd dont care time break tb0 tb1 tb2 t is t is t ih t is t cke t ih des des power-down entry, exit timing with cal command/address latency is used and additional timing restrictions are required when entering power-down, as noted in the following figures. figure 102: active power-down entry and exit timing with cal &.bw &.bf &rppdqg '(6 9dolg '(6 '(6 '(6 $gguhvv &.( w 3' '(6 9dolg w &3'(' w &$/ w ;3 w &$/ 9dolg w ,+ w ,+ w ,6 w ,6 7 7 7d 7d 7d 7e 7e 7f 7f 7g 7g 7h 'rq?w&duh 7lph%uhdn &6bq '(6 '(6 9dolg '(6 '(6 8gb: x4, x8, x16 ddr4 sdram power-down mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 162 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 103: refresh command to power-down entry with cal &.bw &.bf &rppdqg '(6 5() '(6 '(6 '(6 $gguhvv &.( w 3' '(6 9dolg w &3'(' w &$/ w 5()3'(1 w ;3 w &$/ 9dolg w ,+ w ,+ w ,6 w ,6 7 7 7d 7 e 7 e 7f 7f 7g 7g 7h 7h 7i 'rq?w&duh 7lph%uhdn &6bq '(6 '(6 9dolg '(6 '(6 8gb: x4, x8, x16 ddr4 sdram power-down mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 163 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
odt input buffer disable mode for power-down odt input buffer disable mode, when enabled via mr5[5], will prevent the device from providing r tt(nom) termination during power-down for additional power savings. the internal delay on the cke path to disable the odt buffer and block the sampled output must be accounted for; therefore, odt must be continuously driven to a valid level, either low or high, when entering power-down. however, after t cpded (min) has been satisfied, the odt signal may float. when odt input buffer disable mode is enabled, r tt(nom) termination corresponding to sampled odt after cke is first registered low (and t anpd before that) may not be provided. t anpd is equal to (wl - 1) and is counted backward from pde, with cke reg- istered low. figure 104: odt power-down entry with odt buffer disable mode diff_ck t dodtloff +1 t cpded (min) cke odt floating dram_r tt_sync (dll enabled) ca parity disabled dram_r tt_async (dll disabled) r tt(park) r tt(nom) t cpded (min) + t adc (max) t adc (min) dodtloff r tt(park) r tt(nom) t aonas (min) t cpded (min) + t aofas (max) dram_r tt_sync (dll enabled) ca parity enabled r tt(park) r tt(nom) t cpded (min) + t adc (max) + pl t adc (min) dodtloff 8gb: x4, x8, x16 ddr4 sdram odt input buffer disable mode for power-down 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 164 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 105: odt power-down exit with odt buffer disable mode diff_ck cke odt_a (dll enabled) t adc (max) t xp t xp floating dram_r tt _a r tt(park) r tt(nom) t adc (min) dodtlon odt_b (dll disabled) floating dram_r tt _b r tt(park) t aonas (min) t aofas (max) r tt(nom) 8gb: x4, x8, x16 ddr4 sdram odt input buffer disable mode for power-down 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 165 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
crc write data feature crc write data the crc write data feature takes the crc generated data from the dram controller and compares it to the internally crc generated data and determines whether the two match (no crc error) or do not match (crc error). figure 106: crc write data operation data dram controller dram data crc code crc code crc engine data crc code crc engine compare crc write crc data operation a dram controller generates a crc checksum using a 72-bit crc tree and forms the write data frames, as shown in the following crc data mapping tables for the x4, x8, and x16 configurations. a x4 device has a crc tree with 32 input data bits used, and the re- maining upper 40 bits d[71:32] being 1s. a x8 device has a crc tree with 64 input data bits used, and the remaining upper 8 bits dependant upon whether dm_n/dbi_n is used (1s are sent when not used). a x16 device has two identical crc trees each, one for the lower byte and one for the upper byte, with 64 input data bits used by each, and the remaining upper 8 bits on each byte dependant upon whether dm_n/dbi_n is used (1s are sent when not used). for a x8 and x16 drams, the dram memory controller must send 1s in transfer 9 location whether or not dm_n/dbi_n is used. the dram checks for an error in a received code word d[71:0] by comparing the re- ceived checksum against the computed checksum and reports errors using the alert_n signal if there is a mismatch. the dram can write data to the dram core without waiting for the crc check for full writes when dm is disabled. if bad data is written to the dram core, the dram memory controller will try to overwrite the bad data with good data; this means the dram controller is responsible for data coherency when dm is disabled. however, in the case where both crc and dm are enabled via 8gb: x4, x8, x16 ddr4 sdram crc write data feature 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 166 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
mrs (that is, persistent mode), the dram will not write bad data to the core when a crc error is detected. dbi_n and crc both enabled the dram computes the crc for received written data d[71:0]. data is not inverted back based on dbi before it is used for computing crc. the data is inverted back based on dbi before it is written to the dram core. dm_n and crc both enabled when both dm and write crc are enabled in the dram mode register, the dram cal- culates crc before sending the write data into the array. if there is a crc error, the dram blocks the write operation and discards the data. the nonconsecutive write (bl8/bc4-otf) with 2 t ck preamble and write crc in same or different bank group and the write (bl8/bc4-otf/fixed) with 1 t ck preamble and write crc in same or different bankgroup figures in the write operation section show timing differences when dm is enabled. dm_n and dbi_n conflict during writes with crc enabled both write dbi_n and dm_n can not be enabled at the same time; read dbi_n and dm_n can be enabled at the same time. crc and write preamble restrictions when write crc is enabled: ? and 1 t ck write preamble mode is enabled, a t ccd_s or t ccd_l of 4 clocks is not allowed. ? and 2 t ck write preamble mode is enabled, a t ccd_s or t ccd_l of 6 clocks is not allowed. crc simultaneous operation restrictions when write crc is enabled, neither mpr writes nor per-dram mode is allowed. crc polynomial the crc polynomial used by ddr4 is the atm-8 hec, x 8 + x 2 + x 1 + 1. a combinatorial logic block implementation of this 8-bit crc for 72 bits of data in- cludes 272 two-input xor gates contained in eight 6-xor-gate-deep trees. the crc polynomial and combinatorial logic used by ddr4 is the same as used on gddr5. the error coverage from the ddr4 polynomial used is shown in the following table. table 53: crc error detection coverage error type detection capability random single-bit errors 100% random double-bit errors 100% 8gb: x4, x8, x16 ddr4 sdram crc write data feature 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 167 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 53: crc error detection coverage (continued) error type detection capability random odd count errors 100% random multibit ui vertical column error detection excluding dbi bits 100% crc combinatorial logic equations module crc8_d72; // polynomial: (0 1 2 8) // data width: 72 // convention: the first serial data bit is d[71] //initial condition all 0 implied // "^" = xor function [7:0] nextcrc8_d72; input [71:0] data; input [71:0] d; reg [7:0] crc; begin d = data; crc[0] = d[69]^d[68]^d[67]^d[66]^d[64]^d[63]^d[60]^d[56]^d[54]^d[53]^d[52]^d[50]^d[49 ]^d[48]^d[45]^d[43]^d[40]^d[39]^d[35]^d[34]^d[31]^d[30]^d[28]^d[23]^d[21]^d[1 9]^d[18]^d[16]^d[14]^d[12]^d[8]^d[7]^d[6]^d[0] ; crc[1] = d[70]^d[66]^d[65]^d[63]^d[61]^d[60]^d[57]^d[56]^d[55]^d[52]^d[51]^d[48]^d[46 ]^d[45]^d[44]^d[43]^d[41]^d[39]^d[36]^d[34]^d[32]^d[30]^d[29]^d[28]^d[24]^d[2 3]^d[22]^d[21]^d[20]^d[18]^d[17]^d[16]^d[15]^d[14]^d[13]^d[12]^d[9]^d[6]^d[1 ]^d[0]; crc[2] = d[71]^d[69]^d[68]^d[63]^d[62]^d[61]^d[60]^d[58]^d[57]^d[54]^d[50]^d[48]^d[47 ]^d[46]^d[44]^d[43]^d[42]^d[39]^d[37]^d[34]^d[33]^d[29]^d[28]^d[25]^d[24]^d[2 2]^d[17]^d[15]^d[13]^d[12]^d[10]^d[8]^d[6]^d[2]^d[1]^d[0]; crc[3] = d[70]^d[69]^d[64]^d[63]^d[62]^d[61]^d[59]^d[58]^d[55]^d[51]^d[49]^d[48]^d[47 ]^d[45]^d[44]^d[43]^d[40]^d[38]^d[35]^d[34]^d[30]^d[29]^d[26]^d[25]^d[23]^d[1 8]^d[16]^d[14]^d[13]^d[11]^d[9]^d[7]^d[3]^d[2]^d[1]; crc[4] = d[71]^d[70]^d[65]^d[64]^d[63]^d[62]^d[60]^d[59]^d[56]^d[52]^d[50]^d[49]^d[48 ]^d[46]^d[45]^d[44]^d[41]^d[39]^d[36]^d[35]^d[31]^d[30]^d[27]^d[26]^d[24]^d[1 9]^d[17]^d[15]^d[14]^d[12]^d[10]^d[8]^d[4]^d[3]^d[2]; crc[5] = d[71]^d[66]^d[65]^d[64]^d[63]^d[61]^d[60]^d[57]^d[53]^d[51]^d[50]^d[49]^d[47 ]^d[46]^d[45]^d[42]^d[40]^d[37]^d[36]^d[32]^d[31]^d[28]^d[27]^d[25]^d[20]^d[1 8]^d[16]^d[15]^d[13]^d[11]^d[9]^d[5]^d[4]^d[3]; 8gb: x4, x8, x16 ddr4 sdram crc write data feature 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 168 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
crc[6] = d[67]^d[66]^d[65]^d[64]^d[62]^d[61]^d[58]^d[54]^d[52]^d[51]^d[50]^d[48]^d[47 ]^d[46]^d[43]^d[41]^d[38]^d[37]^d[33]^d[32]^d[29]^d[28]^d[26]^d[21]^d[19]^d[1 7]^d[16]^d[14]^d[12]^d[10]^d[6]^d[5]^d[4]; crc[7] = d[68]^d[67]^d[66]^d[65]^d[63]^d[62]^d[59]^d[55]^d[53]^d[52]^d[51]^d[49]^d[48 ]^d[47]^d[44]^d[42]^d[39]^d[38]^d[34]^d[33]^d[30]^d[29]^d[27]^d[22]^d[20]^d[1 8]^d[17]^d[15]^d[13]^d[11]^d[7]^d[6]^d[5]; nextcrc8_d72 = crc; burst ordering for bl8 ddr4 supports fixed write burst ordering [a2:a1:a0 = 0:0:0] when write crc is ena- bled in bl8 (fixed). crc data bit mapping table 54: crc data mapping for x4 devices, bl8 func- tion transfer 0 1 2 3 4 5 6 7 8 9 dq0 d0 d1 d2 d3 d4 d5 d6 d7 crc0 crc4 dq1 d8 d9 d10 d11 d12 d13 d14 d15 crc1 crc5 dq2 d16 d17 d18 d19 d20 d21 d22 d23 crc2 crc6 dq3 d24 d25 d26 d27 d28 d29 d30 d31 crc3 crc7 table 55: crc data mapping for x8 devices, bl8 func- tion transfer 0 1 2 3 4 5 6 7 8 9 dq0 d0 d1 d2 d3 d4 d5 d6 d7 crc0 1 dq1 d8 d9 d10 d11 d12 d13 d14 d15 crc1 1 dq2 d16 d17 d18 d19 d20 d21 d22 d23 crc2 1 dq3 d24 d25 d26 d27 d28 d29 d30 d31 crc3 1 dq4 d32 d33 d34 d35 d36 d37 d38 d39 crc4 1 dq5 d40 d41 d42 d43 d44 d45 d46 d47 crc5 1 dq6 d48 d49 d50 d51 d52 d53 d54 d55 crc6 1 dq7 d56 d57 d58 d59 d60 d61 d62 d63 crc7 1 dm_n/ dbi_n d64 d65 d66 d67 d68 d69 d70 d71 1 1 a x16 device is treated as two x8 devices; a x16 device will have two identical crc trees implemented. crc[7:0] covers data bits d[71:0], and crc[15:8] covers data bits d[143:72]. 8gb: x4, x8, x16 ddr4 sdram crc write data feature 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 169 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 56: crc data mapping for x16 devices, bl8 func- tion transfer 0 1 2 3 4 5 6 7 8 9 dq0 d0 d1 d2 d3 d4 d5 d6 d7 crc0 1 dq1 d8 d9 d10 d11 d12 d13 d14 d15 crc1 1 dq2 d16 d17 d18 d19 d20 d21 d22 d23 crc2 1 dq3 d24 d25 d26 d27 d28 d29 d30 d31 crc3 1 dq4 d32 d33 d34 d35 d36 d37 d38 d39 crc4 1 dq5 d40 d41 d42 d43 d44 d45 d46 d47 crc5 1 dq6 d48 d49 d50 d51 d52 d53 d54 d55 crc6 1 dq7 d56 d57 d58 d59 d60 d61 d62 d63 crc7 1 ldm_n/ ldbi_n d64 d65 d66 d67 d68 d69 d70 d71 1 1 dq8 d72 d73 d74 d75 d76 d77 d78 d79 crc8 1 dq9 d80 d81 d82 d83 d84 d85 d86 d87 crc9 1 dq10 d88 d89 d90 d91 d92 d93 d94 d95 crc10 1 dq11 d96 d97 d98 d99 d100 d101 d102 d103 crc11 1 dq12 d104 d105 d106 d107 d108 d109 d110 d111 crc12 1 dq13 d112 d113 d114 d115 d116 d117 d118 d119 crc13 1 dq14 d120 d121 d122 d123 d124 d125 d126 d127 crc14 1 dq15 d128 d129 d130 d131 d132 d133 d134 d135 crc15 1 udm_n/ udbi_n d136 d137 d138 d139 d140 d141 d142 d143 1 1 crc enabled with bc4 if crc and bc4 are both enabled, then address bit a2 is used to transfer critical data first for bc4 writes. crc with bc4 data bit mapping for a x4 device, the crc tree inputs are 16 data bits, and the inputs for the remaining bits are 1. when a2 = 1, data bits d[7:4] are used as inputs for d[3:0], d[15:12] are used as inputs to d[11:8], and so forth, for the crc tree. table 57: crc data mapping for x4 devices, bc4 function transfer 0 1 2 3 4 5 6 7 8 9 a2 = 0 dq0 d0d1d2d31111 crc0 crc4 dq1 d8d9d10d111111 crc1 crc5 dq2 d16d17d18d191111 crc2 crc6 8gb: x4, x8, x16 ddr4 sdram crc write data feature 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 170 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 57: crc data mapping for x4 devices, bc4 (continued) function transfer 0 1 2 3 4 5 6 7 8 9 dq3 d24 d25 d26 d27 1 1 1 1 crc3 crc7 a2 = 1 dq0 d4 d5 d6 d7 1 1 1 1 crc0 crc4 dq1 d12 d13 d14 d15 1 1 1 1 crc1 crc5 dq2 d20 d21 d22 d23 1 1 1 1 crc2 crc6 dq3 d28 d29 d30 d31 1 1 1 1 crc3 crc7 for a x8 device, the crc tree inputs are 36 data bits. when a2 = 0, the input bits d[67:64]) are used if dbi_n or dm_n functions are enabled; if dbi_n and dm_n are disabled, then d[67:64]) are 1. when a2 = 1, data bits d[7:4] are used as inputs for d[3:0], d[15:12] are used as inputs to d[11:8], and so forth, for the crc tree. the input bits d[71:68]) are used if dbi_n or dm_n functions are enabled; if dbi_n and dm_n are disabled, then d[71:68]) are 1. table 58: crc data mapping for x8 devices, bc4 function transfer 0 1 2 3 4 5 6 7 8 9 a2 = 0 dq0 d0 d1 d2 d3 1 1 1 1 crc0 1 dq1 d8 d9 d10 d11 1 1 1 1 crc1 1 dq2 d16 d17 d18 d19 1 1 1 1 crc2 1 dq3 d24 d25 d26 d27 1 1 1 1 crc3 1 dq4 d32 d33 d34 d35 1 1 1 1 crc4 1 dq5 d40 d41 d42 d43 1 1 1 1 crc5 1 dq6 d48 d49 d50 d51 1 1 1 1 crc6 1 dq7 d56 d57 d58 d59 1 1 1 1 crc7 1 dm_n/dbi_n d64 d65 d66 d67 1 1 1111 a2 = 1 dq0 d4 d5 d6 d7 1 1 1 1 crc0 1 dq1 d12 d13 d14 d15 1 1 1 1 crc1 1 dq2 d20 d21 d22 d23 1 1 1 1 crc2 1 dq3 d28 d29 d30 d31 1 1 1 1 crc3 1 dq4 d36 d37 d38 d39 1 1 1 1 crc4 1 dq5 d44 d45 d46 d47 1 1 1 1 crc5 1 dq6 d52 d53 d54 d55 1 1 1 1 crc6 1 dq7 d60 d61 d62 d63 1 1 1 1 crc7 1 dm_n/dbi_n d68 d69 d70 d71 1 1 1111 there are two identical crc trees for x16 devices, each have crc tree inputs of 36 bits. 8gb: x4, x8, x16 ddr4 sdram crc write data feature 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 171 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
when a2 = 0, input bits d[67:64] are used if dbi_n or dm_n functions are enabled; if dbi_n and dm_n are disabled, then d[67:64] are 1s. the input bits d[139:136] are used if dbi_n or dm_n functions are enabled; if dbi_n and dm_n are disabled, then d[139:136] are 1s. when a2 = 1, data bits d[7:4] are used as inputs for d[3:0], d[15:12] are used as inputs for d[11:8], and so forth, for the crc tree. input bits d[71:68] are used if dbi_n or dm_n functions are enabled; if dbi_n and dm_n are disabled, then d[71:68] are 1s. the input bits d[143:140] are used if dbi_n or dm_n functions are enabled; if dbi_n and dm_n are disabled, then d[143:140] are 1s. table 59: crc data mapping for x16 devices, bc4 function transfer 0 1 2 3 4 5 6 7 8 9 a2 = 0 dq0 d0 d1 d2 d3 1 1 1 1 crc0 1 dq1 d8 d9 d10 d11 1 1 1 1 crc1 1 dq2 d16 d17 d18 d19 1 1 1 1 crc2 1 dq3 d24 d25 d26 d27 1 1 1 1 crc3 1 dq4 d32 d33 d34 d35 1 1 1 1 crc4 1 dq5 d40 d41 d42 d43 1 1 1 1 crc5 1 dq6 d48 d49 d50 d51 1 1 1 1 crc6 1 dq7 d56 d57 d58 d59 1 1 1 1 crc7 1 ldm_n/ldbi_n d64 d65 d66 d67 1 1 1111 dq8 d72 d73 d74 d75 1 1 1 1 crc8 1 dq9 d80 d81 d82 d83 1 1 1 1 crc9 1 dq10 d88 d89 d90 d91 1 1 1 1 crc10 1 dq11 d96 d97 d98 d99 1 1 1 1 crc11 1 dq12 d104 d105 d106 d107 1 1 1 1 crc12 1 dq13 d112 d113 d114 d115 1 1 1 1 crc13 1 dq14 d120 d121 d122 d123 1 1 1 1 crc14 1 dq15 d128 d129 d130 d131 1 1 1 1 crc15 1 udm_n/udbi_n d136 d137 d138 d139 1 1 1111 a2 = 1 dq0 d4 d5 d6 d7 1 1 1 1 crc0 1 dq1 d12 d13 d14 d15 1 1 1 1 crc1 1 dq2 d20 d21 d22 d23 1 1 1 1 crc2 1 dq3 d28 d29 d30 d31 1 1 1 1 crc3 1 dq4 d36 d37 d38 d39 1 1 1 1 crc4 1 dq5 d44 d45 d46 d47 1 1 1 1 crc5 1 dq6 d52 d53 d54 d55 1 1 1 1 crc6 1 dq7 d60 d61 d62 d63 1 1 1 1 crc7 1 ldm_n/ldbi_n d68 d69 d70 d71 1 1 1111 8gb: x4, x8, x16 ddr4 sdram crc write data feature 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 172 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 59: crc data mapping for x16 devices, bc4 (continued) function transfer 0 1 2 3 4 5 6 7 8 9 dq8 d76 d77 d78 d79 1 1 1 1 crc8 1 dq9 d84 d85 d86 d87 1 1 1 1 crc9 1 dq10 d92 d93 d94 d95 1 1 1 1 crc10 1 dq11 d100 d101 d102 d103 1 1 1 1 crc11 1 dq12 d108 d109 d110 d111 1 1 1 1 crc12 1 dq13 d116 d117 d118 d119 1 1 1 1 crc13 1 dq14 d124 d125 d126 d127 1 1 1 1 crc14 1 dq15 d132 d133 d134 d135 1 1 1 1 crc15 1 udm_n/udbi_n d140 d141 d142 d143 1 1 1111 crc equations for x8 device in bc4 mode with a2 = 0 and a2 = 1 the following example is of a crc tree when x8 is used in bc4 mode (x4 and x16 crc trees have similar differences). crc[0], a2=0 = 1^1^d[67]^d[66]^d[64]^1^1^d[56]^1^1^1^d[50]^d[49]^d[48]^1^d[43]^d[40]^1^d[3 5]^d[34]^1^1^1^1^1^d[19]^d[18]^d[16]^1^1^d[8] ^1^1^ d[0] ; crc[0], a2=1 = 1^1^d[71]^d[70]^d[68]^1^1^d[60]^1^1^1^d[54]^d[53]^d[52]^1^d[47]^d[44]^1^d[3 9]^d[38]^1^1^1^1^1^d[23]^d[22]^d[20]^1^1^d[12]^1^1^d[4] ; crc[1], a2=0 = 1^d[66]^d[65]^1^1^1^d[57]^d[56]^1^1^d[51]^d[48]^1^1^1^d[43]^d[41]^1^1^d[34 ]^d[32]^1^1^1^d[24]^1^1^1^1^d[18]^d[17]^d[16]^1^1^1^1^d[9] ^1^ d[1]^d[0]; crc[1], a2=1 = 1^d[70]^d[69]^1^1^1^d[61]^d[60]^1^1^d[55]^d[52]^1^1^1^d[47]^d[45]^1^1^d[38 ]^d[36]^1^1^1^d[28]^1^1^1^1^d[22]^d[21]^d[20]^1^1^1^1^d[13]^1^d[5]^d[4]; crc[2], a2=0 = 1^1^1^1^1^1^1^d[58]^d[57]^1^d[50]^d[48]^1^1^1^d[43]^d[42]^1^1^d[34]^d[33]^1 ^1^d[25]^d[24]^1^d[17]^1^1^1^d[10]^d[8] ^1^d[2]^d[1]^d[0]; crc[2], a2=1 = 1^1^1^1^1^1^1^d[62]^d[61]^1^d[54]^d[52]^1^1^1^d[47]^d[46]^1^1^d[38]^d[37]^1 ^1^d[29]^d[28]^1^d[21]^1^1^1^d[14]^d12]^1^d[6]^d[5]^d[4]; crc[3], a2=0 = 1^1^d[64]^1^1^1^d[59]^d[58]^1^d[51]^d[49]^d[48]^1^1^1^d[43]^d[40]^1^d[35]^ d[34]^1^1^d[26]^d[25]^1^d[18]^d[16]^1^1^d[11]^d[9] ^1^d[3]^d[2]^d[1]; crc[3], a2=1 = 1^1^d[68]^1^1^1^d[63]^d[62]^1^d[55]^d[53]^d[52]^1^1^1^d[47]^d[44]^1^d[39]^ d[38]^1^1^d[30]^d[29]^1^d[22]^d[20]^1^1^d[15]^d[13]^1^d[7]^d[6]^d[5]; 8gb: x4, x8, x16 ddr4 sdram crc write data feature 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 173 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
crc[4], a2=0 = 1^1^d[65]^d[64]^1^1^1^d[59]^d[56]^1^d[50]^d[49]^d[48]^1^1^1^d[41]^1^1^d[35 ]^1^1^d[27]^d[26]^d[24]^d[19]^d[17]^1^1^1^d[10]^d[8] ^1^d[3]^d[2]; crc[4], a2=1 = 1^1^d[69]^d[68]^1^1^1^d[63]^d[60]^1^d[54]^d[53]^d[52]^1^1^1^d[45]^1^1^d[39 ]^1^1^d[31]^d[30]^d[28]^d[23]^d[21]^1^1^1^d[14]^d[12]^1^d[7]^d[6]; crc[5], a2=0 = 1^d[66]^d[65]^d[64]^1^1^1^d[57]^1^d[51]^d[50]^d[49]^1^1^1^d[42]^d[40]^1^1^ d[32]^1^1^d[27]^d[25]^1^d[18]^d[16]^1^1^d[11]^d[9] ^1^1^d[3]; crc[5], a2=1 = 1^d[70]^d[69]^d[68]^1^1^1^d[61]^1^d[55]^d[54]^d[53]^1^1^1^d[46]^d[44]^1^1^ d[36]^1^1^d[31]^d[29]^1^d[22]^d[20]^1^1^d[15]^d[13]^1^1^d[7]; crc[6], a2=0 = d[67]^d[66]^d[65]^d[64]^1^1^d[58]^1^1^d[51]^d[50]^d[48]^1^1^d[43]^d[41]^1^1 ^d[33]^d[32]^1^1^d[26]^1^d[19]^d[17]^d[16]^1^1^d[10]^1^1^1; crc[6], a2=1 = d[71]^d[70]^d[69]^d[68]^1^1^d[62]^1^1^d[55]^d[54]^d[52]^1^1^d[47]^d[45]^1^1 ^d[37]^d[36]^1^1^d[30]^1^d[23]^d[21]^d[20]^1^1^d[14]^1^1^1; crc[7], a2=0 = 1^d[67]^d[66]^d[65]^1^1^d[59]^1^1^1^d[51]^d[49]^d[48]^1^1^d[42]^1^1^d[34]^ d[33]^1^1^d[27]^1^1^d[18]^d[17]^1^1^d[11]^1^1^1; crc[7], a2=1 = 1^d[71]^d[70]^d[69]^1^1^d[63]^1^1^1^d[55]^d[53]^d[52]^1^1^d[46]^1^1^d[38]^ d[37]^1^1^d[31]^1^1^d[22]^d[21]^1^1^d[15]^1^1^1; crc error handling the crc error mechanism shares the same alert_n signal as ca parity for reporting write errors to the dram. the controller has two ways to distinguish between crc er- rors and ca parity errors: 1) read dram mode/mpr registers, and 2) measure time alert_n is low. to speed up recovery for crc errors, crc errors are only sent back as a "short" pulse; the maximum pulse width is roughly ten clocks (unlike ca parity where alert_n is low longer than 45 clocks). the alert_n low could be longer than the maximum limit at the controller if there are multiple crc errors as the alert_n signals are connected by a daisy chain bus. the latency to alert_n signal is defined as t crc_alert in the following figure. the dram will set the error status bit located at mr5[3] to a 1 upon detecting a crc error, which will subsequently set the crc error status flag in the mpr error log high (mpr page1, mpr3[7]). the crc error status bit (and crc error status flag) remains set at 1 until the dram controller clears the crc error status bit using an mrs command to set mr5[3] to a 0. the dram controller, upon seeing an error as a pulse width, will retry the write transactions. the controller should consider the worst-case delay for alert_n (during initialization) and backup the transactions accordingly. the dram controller may also be made more intelligent and correlate the write crc error to a spe- cific rank or a transaction. 8gb: x4, x8, x16 ddr4 sdram crc write data feature 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 174 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 107: crc error reporting dx t0 t1 t2 t3 t4 t5 t6 ta0 ta1 ta2 ta3 tb0 ck_t ck_c dq in dx+1 dx+2 dx+3 dx+4 dx+5 dx+6 dx+7 crcy 1 alert_n crc alert_pw (min) tb1 t crc_alert crc alert_pw (max) dont care transition data notes: 1. d[71:1] crc computed by dram did not match crc[7:0] at t5 and started error generat- ing process at t6. 2. crc alert_pw is specified from the point where the dram starts to drive the signal low to the point where the dram driver releases and the controller starts to pull the signal up. 3. timing diagram applies to x4, x8, and x16 devices. 8gb: x4, x8, x16 ddr4 sdram crc write data feature 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 175 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
crc write data flow diagram figure 108: ca parity flow diagram capture data transfer data internally transfer data internally yes dram write process start mr2 12 enable crc mr5 3 set crc error clear to 0 mr5 10 enable/disable dm mr3[10:9] wcl if dm enabled no no yes yes no alert_n low 6 to 10 cks alert_n high set error status page1 mpr3[7] 1 set error flag mr5[a3] 1 transfer data internally yes no yes no crc enabled ca error persistent mode enabled mr5[a3] and page1 mpr3[7] remain set to 1 no yes dram crc same as controller crc dram crc same as controller crc mr5[3] = 0 at write write burst completed write burst completed write burst completed write burst completed write burst completed bad data written mr5 3 reset to 0 if desired alert_n low 6 to 10 cks alert_n high set error status page1 mpr3[7] 1 set error flag mr5[a3] 1 yes no mr5[a3] and page1 mpr3[7] remain set to 1 mr5[3] = 0 at write write burst rejected bad data not written mr5 3 reset to 0 if desired 8gb: x4, x8, x16 ddr4 sdram crc write data feature 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 176 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
data bus inversion the data bus inversion (dbi) function is supported only for x8 and x16 configura- tions (it is not supported on x4 devices). dbi opportunistically inverts data bits, and in conjunction with the dbi_n i/o, less than half of the dqs will switch low for a given dqs strobe edge. the dbi function shares a common pin with the data mask (dm) and tdqs functions. the dbi function applies to either or both read and write oper- ations: write dbi cannot be enabled at the same time the dm function is enabled, and dbi is not allowed during mpr read operation. valid configurations for tdqs, dm, and dbi functions are shown below. table 60: dbi vs. dm vs. tdqs function matrix read dbi write dbi data mask (dm) tdqs (x8 only) enabled (or disabled) mr5[12]=1 (or mr5[12] = 0) disabled mr5[11] = 0 disabled mr5[10] = 0 disabled mr1[11] = 0 enabled mr5[11] = 1 disabled mr5[10] = 0 disabled mr1[11] = 0 disabled mr5[11] = 0 enabled mr5[10] = 1 disabled mr1[11] = 0 disabled mr5[12] = 0 disabled mr5[11] = 0 disabled mr5[10] = 0 enabled mr1[11] = 1 dbi during a write operation if dbi_n is sampled low on a given byte lane during a write operation, the dram in- verts write data received on the dq inputs prior to writing the internal memory array. if dbi_n is sampled high on a given byte lane, the dram leaves the data received on the dq inputs noninverted. the write dq frame format is shown below for x8 and x16 con- figurations (the x4 configuration does not support the dbi function). table 61: dbi write, dq frame format (x8) function transfer 0 1 2 3 4 5 6 7 dq[7:0] byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 dm_n or dbi_n dm0 or dbi0 dm1 or dbi1 dm2 or dbi2 dm3 or dbi3 dm4 or dbi4 dm5 or dbi5 dm6 or dbi6 dm7 or dbi7 table 62: dbi write, dq frame format (x16) function transfer, lower (l) and upper(u) 0 1 2 3 4 5 6 7 dq[7:0] lbyte 0 lbyte 1 lbyte 2 lbyte 3 lbyte 4 lbyte 5 lbyte 6 lbyte 7 ldm_n or ldbi_n ldm0 or ldbi0 ldm1 or ldbi1 ldm2 or ldbi2 ldm3 or ldbi3 ldm4 or ldbi4 ldm5 or ldbi5 ldm6 or ldbi6 ldm7 or ldbi7 dq[15:8] ubyte 0 ubyte 1 ubyte 2 ubyte 3 ubyte 4 ubyte 5 ubyte 6 ubyte 7 8gb: x4, x8, x16 ddr4 sdram data bus inversion 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 177 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 62: dbi write, dq frame format (x16) (continued) function transfer, lower (l) and upper(u) 0 1 2 3 4 5 6 7 udm_n or udbi_n udm0 or udbi0 udm1 or udbi1 udm2 or udbi2 udm3 or udbi3 udm4 or udbi4 udm5 or udbi5 udm6 or udbi6 udm7 or udbi7 dbi during a read operation if the number of 0 data bits within a given byte lane is greater than four during a read operation, the dram inverts read data on its dq outputs and drives the dbi_n pin low; otherwise, the dram does not invert the read data and drives the dbi_n pin high. the read dq frame format is shown below for x8 and x16 configurations (the x4 configuration does not support the dbi function). table 63: dbi read, dq frame format (x8) function transfer byte 0 1 2 3 4 5 6 7 dq[7:0] byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 dbi_n dbi0 dbi1 dbi2 dbi3 dbi4 dbi5 dbi6 dbi7 table 64: dbi read, dq frame format (x16) function transfer byte, lower (l) and upper(u) 0 1 2 3 4 5 6 7 dq[7:0] lbyte 0 lbyte 1 lbyte 2 lbyte 3 lbyte 4 lbyte 5 lbyte 6 lbyte 7 ldbi_n ldbi0 ldbi1 ldbi2 ldbi3 ldbi4 ldbi5 ldbi6 ldbi7 dq[15:8] ubyte 0 ubyte 1 ubyte 2 ubyte 3 ubyte 4 ubyte 5 ubyte 6 ubyte 7 udbi_n udbi0 udbi1 udbi2 udbi3 udbi4 udbi5 udbi6 udbi7 8gb: x4, x8, x16 ddr4 sdram data bus inversion 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 178 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
data mask the data mask (dm) function, also described as partial write, is supported only for x8 and x16 configurations (it is not supported on x4 devices). the dm function shares a common pin with the dbi_n and tdqs functions. the dm function applies only to write operations and cannot be enabled at the same time the write dbi function is enabled. the valid configurations for the tdqs, dm, and dbi functions are shown here. table 65: dm vs. tdqs vs. dbi function matrix data mask (dm) tdqs (x8 only) write dbi read dbi enabled mr5[10] = 1 disabled mr1[11] = 0 disabled mr5[11] = 0 enabled or disabled mr5[12] = 1 or mr5[12] = 0 disabled mr5[10] = 0 enabled mr1[11] = 1 disabled mr5[11] = 0 disabled mr5[12] = 0 disabled mr1[11] = 0 enabled mr5[11] = 1 enabled or disabled mr5[12] = 1 or mr5[12] = 0 disabled mr1[11] = 0 disabled mr5[11] = 0 enabled (or disabled) mr5[12] = 1 (or mr5[12] = 0) when enabled, the dm function applies during a write operation. if dm_n is sampled low on a given byte lane, the dram masks the write data received on the dq inputs. if dm_n is sampled high on a given byte lane, the dram does not mask the data and writes this data into the dram core. the dq frame format for x8 and x16 configurations is shown below. if both crc write and dm are enabled (via mrs), the crc will be checked and valid prior to the dram writing data into the dram core. if a crc error occurs while the dm feature is enabled, crc write persistent mode will be enabled and data will not be written into the dram core. in the case of crc write enabled and dm disabled (via mrs), that is, crc write nonpersistent mode, data is written to the dram core even if a crc error occurs. table 66: data mask, dq frame format (x8) function transfer 0 1 2 3 4 5 6 7 dq[7:0] byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 dm_n or dbi_n dm0 or dbi0 dm1 or dbi1 dm2 or dbi2 dm3 or dbi3 dm4 or dbi4 dm5 or dbi5 dm6 or dbi6 dm7 or dbi7 table 67: data mask, dq frame format (x16) function transfer, lower (l) and upper (u) 0 1 2 3 4 5 6 7 dq[7:0] lbyte 0 lbyte 1 lbyte 2 lbyte 3 lbyte 4 lbyte 5 lbyte 6 lbyte 7 8gb: x4, x8, x16 ddr4 sdram data mask 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 179 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 67: data mask, dq frame format (x16) (continued) function transfer, lower (l) and upper (u) 0 1 2 3 4 5 6 7 ldm_n or ldbi_n ldm0 or ldbi0 ldm1 or ldbi1 ldm2 or ldbi2 ldm3 or ldbi3 ldm4 or ldbi4 ldm5 or ldbi5 ldm6 or ldbi6 ldm7 or ldbi7 dq[15:8] ubyte 0 ubyte 1 ubyte 2 ubyte 3 ubyte 4 ubyte 5 ubyte 6 ubyte 7 udm_n or udbi_n udm0 or udbi0 udm1 or udbi1 udm2 or udbi2 udm3 or udbi3 udm4 or udbi4 udm5 or udbi5 udm6 or udbi6 udm7 or udbi7 8gb: x4, x8, x16 ddr4 sdram data mask 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 180 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
programmable preamble modes and dqs postambles the device supports programmable write and read preamble modes, either the nor- mal 1 t ck preamble mode or special 2 t ck preamble mode. the 2 t ck preamble mode places special timing constraints on many operational features as well as being suppor- ted for data rates of ddr4-2400 and faster. the write preamble 1 t ck or 2 t ck mode can be selected independently from read preamble 1 t ck or 2 t ck mode. read preamble training is also supported; this mode can be used by the dram con- troller to train or "read level" the dqs receivers. there are t ccd restrictions under some circumstances: ? when 2 t ck read preamble mode is enabled, a t ccd_s or t ccd_l of 5 clocks is not allowed. ? when 2 t ck write preamble mode is enabled and write crc is not enabled, a t ccd_s or t ccd_l of 5 clocks is not allowed. ? when 2 t ck write preamble mode is enabled and write crc is enabled, a t ccd_s or t ccd_l of 6 clocks is not allowed. write preamble mode mr4[12] = 0 selects 1 t ck write preamble mode while mr4[12] = 1 selects 2 t ck write preamble mode. examples are shown in the figures below. figure 109: 1 t ck vs. 2 t ck write preamble mode dq ck_c ck_t preamble 2 t ck mode d0 d1 d2 d3 d4 d5 d6 d7 wl wr dq dqs_t, dqs_c dqs_t, dqs_c ck_c ck_t preamble 1 t ck mode d0 d1 d2 d3 d4 d5 d6 d7 wr wl 8gb: x4, x8, x16 ddr4 sdram programmable preamble modes and dqs postambles 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 181 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
cwl has special considerations when in the 2 t ck write preamble mode. the cwl val- ue selected in mr2[5:3], as seen in table below, requires at least one additional clock when the primary cwl value and 2 t ck write preamble mode are used; no additional clocks are required when the alternate cwl value and 2 t ck write preamble mode are used. table 68: cwl selection cwl - primary choice cwl - alternate choice speed bin 1 t ck preamble 2 t ck preamble 1 t ck preamble 2 t ck preamble ddr4-1600 9 n/a 11 n/a ddr4-1866 10 n/a 12 n/a ddr4-2133 11 n/a 14 n/a ddr4-2400 12 14 16 16 ddr4-2666 14 16 18 18 ddr4-2933 16 18 20 20 ddr4-3200 16 18 20 20 note: 1. cwl programmable requirement for mr2[5:3]. when operating in 2 t ck write preamble mode, t wtr (command based) and t wr (mr0[11:9]) must be programmed to a value 1 clock greater than the t wtr and t wr set- ting normally required for the applicable speed bin to be jedec compliant; however, micron's ddr4 drams do not require these additional t wtr and t wr clocks. the cas_n-to-cas_n command delay to either a different bank group ( t ccd_s) or the same bank group ( t ccd_l) have minimum timing requirements that must be satisfied be- tween write commands and are stated in the timing parameters by speed bin tables. figure 110: 1 t ck vs. 2 t ck write preamble mode, t ccd = 4 dq dqs_t, dqs_c t ccd = 4 wl preamble 1 t ck mode d0 d1 write write d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 ck_t ck_c cmd dq dqs_t, dqs_c t ccd = 4 wl preamble 2 t ck mode d0 d1 write write d2 d3 d4 d5 d6 d7 d0 d1 ck_t ck_c cmd 8gb: x4, x8, x16 ddr4 sdram programmable preamble modes and dqs postambles 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 182 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 111: 1 t ck vs. 2 t ck write preamble mode, t ccd = 5 dq dqs_t, dqs_c t ccd = 5 wl preamble preamble 1 t ck mode d0 d1 write write d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 ck_t ck_c cmd 2 t ck mode: t ccd = 5 is not allowed in 2 t ck mode. note: 1. t ccd_s and t ccd_l = 5 t cks is not allowed when in 2 t ck write preamble mode. figure 112: 1 t ck vs. 2 t ck write preamble mode, t ccd = 6 dq t ccd = 6 dqs_t, dqs_c wl preamble preamble 1 t ck mode d0 d1 write write d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 ck_t ck_c cmd 2 t ck mode dq t ccd = 6 dqs_t, dqs_c wl preamble preamble d0 d1 write write d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 ck_t ck_c cmd 8gb: x4, x8, x16 ddr4 sdram programmable preamble modes and dqs postambles 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 183 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
read preamble mode mr4[11] = 0 selects 1 t ck read preamble mode and mr4[11] = 1 selects 2 t ck read pre- amble mode. examples are shown in the following figure. figure 113: 1 t ck vs. 2 t ck read preamble mode dq dqs_t, dqs_c dqs_t, dqs_c ck_c ck_t preamble 2 t ck mode d0 d1 d2 d3 d4 d5 d6 d7 cl rd dq ck_c ck_t preamble 1 t ck mode d0 d1 d2 d3 d4 d5 d6 d7 rd cl read preamble training ddr4 supports read preamble training via mpr reads; that is, read preamble train- ing is allowed only when the dram is in the mpr access mode. the read preamble training mode can be used by the dram controller to train or "read level" its dqs re- ceivers. read preamble training is entered via an mrs command (mr4[10] = 1 is ena- bled and mr4[10] = 0 is disabled). after the mrs command is issued to enable read preamble training, the dram dqs signals are driven to a valid level by the time t sdo is satisfied. during this time, the data bus dq signals are held quiet, that is, driven high. the dqs_t signal remains driven low and the dqs_c signal remains driven high until an mpr page0 read command is issued (mpr0 through mpr3 determine which pat- tern is used), and when cas latency (cl) has expired, the dqs signals will toggle nor- mally depending on the burst length setting. to exit read preamble training mode, an mrs command must be issued, mr4[10] = 0. 8gb: x4, x8, x16 ddr4 sdram programmable preamble modes and dqs postambles 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 184 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 114: read preamble training cmd dqs cl dqs_c dqs_t, t sdo mpr rd (quiet/driven high) mrs d0 d1 d2 d3 d4 d5 d6 d7 write postamble whether the 1 t ck or 2 t ck write preamble mode is selected, the write postamble re- mains the same at ? t ck. figure 115: write postamble dq dqs_t, dqs_c dqs_t, dqs_c ck_c ck_t 2 t ck mode d0 d1 d2 d3 d4 d5 d6 d7 wl wr dq ck_c ck_t postamble 1 t ck mode d0 d1 d2 d3 d4 d5 d6 d7 wr wl postamble read postamble whether the 1 t ck or 2 t ck read preamble mode is selected, the read postamble re- mains the same at ? t ck. 8gb: x4, x8, x16 ddr4 sdram programmable preamble modes and dqs postambles 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 185 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 116: read postamble dq ck_c ck_t 2 t ck mode d0 d1 d2 d3 d4 d5 d6 d7 cl rd dq dqs_t, dqs_c dqs_t, dqs_c ck_c ck_t 1 t ck mode d0 d1 d2 d3 d4 d5 d6 d7 rd cl postamble postamble 8gb: x4, x8, x16 ddr4 sdram programmable preamble modes and dqs postambles 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 186 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
bank access operation ddr4 supports bank grouping: x4/x8 drams have four bank groups (bg[1:0]), and each bank group is comprised of four subbanks (ba[1:0]); x16 drams have two bank groups (bg[0]), and each bank group is comprised of four subbanks. bank accesses to different banks' groups require less time delay between accesses than bank accesses to within the same bank's group. bank accesses to different bank groups require t ccd_s (or short) delay between commands while bank accesses within the same bank group require t ccd_l (or long) delay between commands. figure 117: bank group x4/x8 block diagram local i/o gating global i/o gating bank 0 memory array sense amplifiers bank 1 bank 2 bank 3 local i/o gating bank 0 memory array sense amplifiers bank 1 bank 2 bank 3 local i/o gating bank 0 memory array sense amplifiers bank 1 bank 2 bank 3 local i/o gating bank 0 memory array sense amplifiers bank 1 bank 2 bank 3 cmd/addr register cmd/addr data i/o bank group 0 bank group 1 bank group 2 bank group 3 notes: 1. bank accesses to different bank groups require t ccd_s. 2. bank accesses within the same bank group require t ccd_l. table 69: ddr4 bank group timing examples parameter ddr4-1600 ddr4-2133 ddr4-2400 t ccd_s 4nck 4nck 4nck t ccd_l 4n ck or 6.25ns 4n ck or 5.355ns 4nck or 5ns t rrd_s (?k) 4nck or 5ns 4n ck or 3.7ns 4nck or 3.3ns t rrd_l (?k) 4nck or 6ns 4n ck or 5.3ns 4nck or 4.9ns t rrd_s (1k) 4nck or 5ns 4n ck or 3.7ns 4nck or 3.3ns t rrd_l (1k) 4nck or 6ns 4n ck or 5.3ns 4nck or 4.9ns t rrd_s (2k) 4nck or 6ns 4n ck or 5.3ns 4nck or 5.3ns t rrd_l (2k) 4n ck or 7.5ns 4n ck or 6.4ns 4nck or 6.4ns 8gb: x4, x8, x16 ddr4 sdram bank access operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 187 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 69: ddr4 bank group timing examples (continued) parameter ddr4-1600 ddr4-2133 ddr4-2400 t wtr_s 2n ck or 2.5ns 2n ck or 2.5ns 2nck or 2.5ns t wtr_l 4n ck or 7.5ns 4n ck or 7.5ns 4nck or 7.5ns notes: 1. refer to timing tables for actual specification values, these values are shown for refer- ence only and are not verified for accuracy. 2. timings with both nck and ns require both to be satisfied; that is, the larger time of the two cases must be satisfied. figure 118: read burst t ccd_s and t ccd_l examples t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t ccd_s t10 t11 dont care bg a des read read des des des des des des des des ck_t ck_c command bank group (bg) bank c bank col n bg b bank c col n bg b bank c col n address t ccd_l read notes: 1. t ccd_s; cas_n-to-cas_n delay (short). applies to consecutive cas_n to different bank groups (t0 to t4). 2. t ccd_l; cas_n-to-cas_n delay (long). applies to consecutive cas_n to the same bank group (t4 to t10). figure 119: write burst t ccd_s and t ccd_l examples t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t ccd_s t10 t11 dont care bg a des write write des des des des des des des des ck_t ck_c command bank group (bg) bank c bank col n bg b bank c col n bg b bank c col n address t ccd_l write notes: 1. t ccd_s; cas_n-to-cas_n delay (short). applies to consecutive cas_n to different bank groups (t0 to t4). 2. t ccd_l; cas_n-to-cas_n delay (long). applies to consecutive cas_n to the same bank group (t4 to t10). 8gb: x4, x8, x16 ddr4 sdram bank access operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 188 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 120: t rrd timing t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t rrd_s t10 t11 dont care bg a des act act des des des des des des des des ck_t ck_c command bank group (bg) bank c bank row n bg b bank c row n bg b bank d row n address t rrd_l act notes: 1. t rrd_s; activate-to-activate command period (short); applies to consecutive acti- vate commands to different bank groups (t0 and t4). 2. t rrd_l; activate-to-activate command period (long); applies to consecutive acti- vate commands to the different banks in the same bank group (t4 and t10). figure 121: t wtr_s timing (write-to-read, different bank group, crc and dm disabled) t0 tb0 t1 t2 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 valid valid valid valid valid read valid command valid write valid valid valid valid bgb bank group bga bank c bank col n bank c col n address ck_t ck_c tb1 dont care transitioning data time break dq wl t wpre t wpst rl t wtr_s di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di n + 2 di n + 1 di n dqs, dqs_c note: 1. t wtr_s: delay from start of internal write transaction to internal read command to a different bank group. 8gb: x4, x8, x16 ddr4 sdram bank access operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 189 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 122: t wtr_l timing (write-to-read, same bank group, crc and dm disabled) t0 tb0 t1 t2 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 valid valid valid valid valid read valid command valid write valid valid valid valid bga bank group bga bank c bank col n bank c col n address ck_t ck_c tb1 dont care transitioning data time break dq wl t wpre t wpst rl t wtr_l di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di n + 2 di n + 1 di n dqs, dqs_c note: 1. t wtr_l: delay from start of internal write transaction to internal read command to the same bank group. 8gb: x4, x8, x16 ddr4 sdram bank access operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 190 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
read operation read timing definitions the read timings shown below are applicable in normal operation mode, that is, when the dll is enabled and locked. note: t dqsq = both rising/falling edges of dqs; no t ac defined. rising data strobe edge parameters: ? t dqsck (min)/(max) describes the allowed range for a rising data strobe edge rela- tive to ck. ? t dqsck is the actual position of a rising strobe edge relative to ck. ? t qsh describes the dqs differential output high time. ? t dqsq describes the latest valid transition of the associated dq pins. ? t qh describes the earliest invalid transition of the associated dq pins. falling data strobe edge parameters: ? t qsl describes the dqs differential output low time. ? t dqsq describes the latest valid transition of the associated dq pins. ? t qh describes the earliest invalid transition of the associated dq pins. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 191 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 123: read timing definition ck_t ck_c dqs_c dqs_t t dqsck t dqsck t dqsq t dqsq rising strobe region window rising strobe region window t qsh/dqs_c t qsh/dqs_t t qh t qh t dqsck (max) t dqsck (min) t dqsck (max) t dqsck (min) associated dq pins t dqscki t dqsck min t dqscki rising strobe region window rising strobe region window t dqscki t dqsck center t dqscki rising strobe region window rising strobe region window t dqscki t dqsck max t dqscki table 70: read to write and write to read command intervals access type bank group timing parameters note read to write, mini- mum same cl - cwl + rbl/2 + 1 t ck + t wpre 1,2 different cl - cwl + rbl/2 + 1 t ck + t wpre 1,2 write to read, mini- mum same cwl + wbl/2 + t wtr_l 1,3 different cwl + wbl/2 + t wtr_s 1,3 notes: 1. these timings require extended calibrations times t zqinit and t zqcs. 2. rbl : read burst length associated with read command, rbl = 8 for fixed 8 and on-the- fly mode 8 and rbl = 4 for fixed bc4 and on-the-fly mode bc4. 3. wbl : write burst length associated with write command, wbl = 8 for fixed 8 and on- the-fly mode 8 or bc4 and wbl = 4 for fixed bc4 only. read timing C clock-to-data strobe relationship the clock-to-data strobe relationship shown below is applicable in normal operation mode, that is, when the dll is enabled and locked. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 192 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
rising data strobe edge parameters: ? t dqsck (min)/(max) describes the allowed range for a rising data strobe edge rela- tive to ck. ? t dqsck is the actual position of a rising strobe edge relative to ck. ? t qsh describes the data strobe high pulse width. ? t hz(dqs) dqs strobe going to high, nondrive level (shown in the postamble section of the figure below). falling data strobe edge parameters: ? t qsl describes the data strobe low pulse width. ? t lz(dqs) dqs strobe going to low, initial drive level (shown in the preamble section of the figure below). figure 124: clock-to-data strobe relationship rl measured to this point dqs_t, dqs_c early strobe ck_t ck_c t lz(dqs) min t lz(dqs) max dqs_t, dqs_c late strobe t dqsck (min) t dqsck (max) t dqsck (max) t dqsck (max) t dqsck (max) t dqsck (min) t dqsck (min) t dqsck (min) t hz(dqs) min t hz(dqs) max t rpre t rpre t qsh t qsl t qsh t qsl t qsh t qsl t qsh t qsl t qsh t qsl bit 0 bit 1 bit 2 bit 7 bit 6 bit 4 bit 3 bit 5 bit 0 bit 1 bit 2 bit 7 bit 6 bit 4 bit 3 bit 5 t rpst t rpst notes: 1. within a burst, the rising strobe edge will vary within t dqsckj while at the same volt- age and temperature. however, when the device, voltage, and temperature variations are incorporated, the rising strobe edge variance window can shift between t dqsck (min) and t dqsck (max). a timing of this window's right edge (latest) from rising ck_t, ck_c is limited by a devi- ce's actual t dqsck (max). a timing of this window's left inside edge (earliest) from ris- ing ck_t, ck_c is limited by t dqsck (min). 2. notwithstanding note 1, a rising strobe edge with t dqsck (max) at t(n) can not be im- mediately followed by a rising strobe edge with t dqsck (min) at t(n + 1) because other timing relationships ( t qsh, t qsl) exist: if t dqsck(n + 1) < 0: t dqsck(n) < 1.0 t ck - ( t qsh (min) + t qsl (min)) - | t dqsck(n + 1) |. 3. the dqs_t, dqs_c differential output high time is defined by t qsh, and the dqs_t, dqs_c differential output low time is defined by t qsl. 4. t lz(dqs) min and t hz(dqs) min are not tied to t dqsck (min) (early strobe case), and t lz(dqs) max and t hz(dqs) max are not tied to t dqsck (max) (late strobe case). 5. the minimum pulse width of read preamble is defined by t rpre (min). 6. the maximum read postamble is bound by t dqsck (min) plus t qsh (min) on the left side and t hzdsq (max) on the right side. 7. the minimum pulse width of read postamble is defined by t rpst (min). 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 193 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
8. the maximum read preamble is bound by t lzdqs (min) on the left side and t dqsck (max) on the right side. read timing C data strobe-to-data relationship the data strobe-to-data relationship is shown below and is applied when the dll is en- abled and locked. note: t dqsq: both rising/falling edges of dqs; no t ac defined. rising data strobe edge parameters: ? t dqsq describes the latest valid transition of the associated dq pins. ? t qh describes the earliest invalid transition of the associated dq pins. falling data strobe edge parameters: ? t dqsq describes the latest valid transition of the associated dq pins. ? t qh describes the earliest invalid transition of the associated dq pins. data valid window parameters: ? t dvwd is the data valid window per device per ui and is derived from [ t qh - t dqsq] of each ui on a given dram ? t dvwp is the data valid window per pin per ui and is derived [ t qh - t dqsq] of each ui on a pin of a given dram figure 125: data strobe-to-data relationship ck_t ck_c command 3 read bank, col n des des des des des des des des des des address 4 dqs_t, dqs_c dq 2 (last data ) dq 2 (first data no longer) all dq collectively rl = al + cl t dqsq (max) t rpre (1nck) t rpst t qh t qh t dvwp t dvwp t dvwd t dvwd t0 t1 t2 t9 t10 t11 t12 t13 dont care t14 t15 t16 d out n + 2 d out n + 1 d out n + 4 d out n + 5 d out n + 6 d out n + 7 d out n + 2 d out n + 1 d out n + 3 d out n + 4 d out n + 5 d out n + 6 d out n + 7 t dqsq (max) d out n d out n + 2 d out n + 1 d out n + 3 d out n + 4 d out n + 5 d out n + 6 d out n + 7 d out n d out n + 3 d out n notes: 1. bl = 8, rl = 11 (al = 0, cl = 1) , premable = 1 t ck. 2. d out n = data-out from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during read commands at t0. 5. output timings are referenced to v ddq , and dll on for locking. 6. t dqsq defines the skew between dqs to data and does not define dqs to clock. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 194 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
7. early data transitions may not always happen at the same dq. data transitions of a dq can vary (either early or late) within a burst. t lz(dqs), t lz(dq), t hz(dqs), and t hz(dq) calculations t hz and t lz transitions occur in the same time window as valid data transitions. these parameters are referenced to a specific voltage level that specifies when the device out- put is no longer driving t hz(dqs) and t hz(dq), or begins driving t lz(dqs) and t lz(dq). the figure below shows a method to calculate the point when the device is no longer driving t hz(dqs) and t hz(dq), or begins driving t lz(dqs) and t lz(dq), by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. t lz(dqs), t lz(dq), t hz(dqs), and t hz(dq) are defined as singled-ended parameters. figure 126: t lz and t hz method for calculating transitions and endpoints ck_t ck_c t lz t hz dq 0.7 v ddq 0.4 v ddq dq begin point: extrapolated point at v ddq v ddq v sw2 begin point: extrapolated point (low level) v ddq t lz(dq): ck_t, ck_c rising crossing at rl t hz(dq) with bl8: ck_t, ck_c rising crossing at rl + 4ck t hz(dq) with bc4: ck_t, ck_c rising crossing at rl + 2ck v sw1 v sw2 v sw1 0.7 v ddq 0.4 v ddq notes: 1. v sw1 = (0.70 - 0.04) v ddq for both t lz and t hz. 2. v sw2 = (0.70 + 0.04) v ddq for both t lz and t hz. 3. extrapolated point (low level) = v ddq /(50 + 34) 34 = 0.4 v ddq driver impedance = rzq/7 = 34 v tt test load = 50 to v ddq . 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 195 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
t rpre calculation figure 127: t rpre method for calculating transitions and endpoints dqs_t t rpre ends ( t 2) ck_t ck_c resulting differential signal relevant for t rpre specification single-ended signal provided as background information 0v dqs_c dqs_t, dqs_c dqs_t dqs_c dqs_t dqs_c t rpre begins ( t 1) v sw1 v sw2 0.7 v ddq 0.7 v ddq 0.4 v ddq 0.4 v ddq v ddq v ddq v ddq 0.7 v ddq 0.3 v ddq 0.6 v ddq 0.4 v ddq v dd /2 notes: 1. v sw1 = (0.3 - 0.04) v ddq . 2. v sw2 = (0.30 + 0.04) v ddq . 3. dqs_t and dqs_c low level = v ddq /(50 + 34) 34 = 0.4 v ddq driver impedance = rzq/7 = 34 v tt test load = 50 to v ddq . 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 196 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
t rpst calculation figure 128: t rpst method for calculating transitions and endpoints dqs_t, dqs_c v sw1 v sw2 dqs_t t rpst ends ( t 2) ck_t ck_c resulting differential signal relevant for t rpst specification single-ended signal provided as background information 0v dqs_c dqs_t dqs_c t rpst begins ( t 1) 0.7 v ddq 0.7 v ddq 0.4 v ddq 0.4 v ddq v ddq v ddq v ddq 0.7 v ddq C0.3 v ddq C0.6 v ddq v dd /2 notes: 1. v sw1 = (C0.3 - 0.04) v ddq . 2. v sw2 = (C0.30 + 0.04) v ddq . 3. dqs_t and dqs_c low level = v ddq /(50 + 34) 34 = 0.4 v ddq driver impedance = rzq/7 = 34 v tt test load = 50 to v ddq . 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 197 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
read burst operation ddr4 read commands support bursts of bl8 (fixed), bc4 (fixed), and bl8/bc4 on- the-fly (otf); otf uses address a12 to control otf when otf is enabled: ? a12 = 0, bc4 (bc4 = burst chop) ? a12 = 1, bl8 read commands can issue precharge automatically with a read with auto precharge command (rda), and is enabled by a10 high: ? read command with a10 = 0 (rd) performs standard read, bank remains active after read burst. ? read command with a10 = 1 (rda) performs read with auto precharge, bank goes in to precharge after read burst. figure 129: read burst operation, rl = 11 (al = 0, cl = 11, bl8) t0 cl = 11 rl = al + cl t rpre t1 t2 ta1 ta0 ta2 ta3 ta4 ta5 ta6 ta7 ta8 ta9 des des des des des des command des read des des des des des dq ck_t ck_c dont care transitioning data time break do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do n + 2 do n + 1 do n bank group address dqs_t dqs_c bga address bank col n t rpst notes: 1. bl8, rl = 0, al = 0, cl = 11, preamble = 1 t ck. 2. do n = data-out from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read command at t0. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 198 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 130: read burst operation, rl = 21 (al = 10, cl = 11, bl8) t0 cl = 11 al = 10 rl = al + cl t rpre t1 ta0 ta1 ta2 ta3 tb0 tb1 tb2 tb3 tb4 tb5 tb6 des des des des des command des read des des des des dq ck_t ck_c dont care transitioning data time break do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do n + 2 do n + 1 do n bank group address dqs_t dqs_c bga address bank col n t rpst des des notes: 1. bl8, rl = 21, al = (cl - 1), cl = 11, preamble = 1 t ck. 2. do n = data-out from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read command at t0. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 199 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
read operation followed by another read operation figure 131: consecutive read (bl8) with 1 t ck preamble in different bank group t0 t ccd_s = 4 t rpre rl = 11 t rpst t16 t1 t2 t3 t4 t9 t10 t11 t12 t13 t14 t15 des des des des des des des command des read des des read des dq ck_t ck_c dqs_t, dqs_c rl = 11 t21 t17 t18 t19 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do b do b + 1 do b + 2 do b + 3 do b + 4 do b + 5 do b + 6 do b + 7 do n des des des des des bank group address bga bgb address bank col n bank col b notes: 1. bl8, al = 0, cl = 11, preamble = 1 t ck. 2. do n (or b) = data-out from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read commands at t0 and t4. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. figure 132: consecutive read (bl8) with 2 t ck preamble in different bank group t0 t ccd_s = 4 t rpre rl = 11 t rpst t16 t1 t2 t3 t4 t9 t10 t11 t12 t13 t14 t15 des des des des des des des command des read des des read des dq ck_t ck_c dqs_t, dqs_c rl = 11 t21 t17 t18 t19 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do b do b + 1 do b + 2 do b + 3 do b + 4 do b + 5 do b + 6 do b + 7 do n des des des des des bank group address bga bgb address bank col n bank col b notes: 1. bl8, al = 0, cl = 11, preamble = 2 t ck. 2. do n (or b) = data-out from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read commands at t0 and t4. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 200 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 133: nonconsecutive read (bl8) with 1 t ck preamble in same or different bank group t0 t ccd_s/l = 5 t rpre rl = 11 t rpst t16 t1 t2 t3 t4 t5 t10 t11 t12 t13 t14 t15 des des des des des des des command des read des des des read dq ck_t ck_c dqs_t, dqs_c rl = 11 t21 t17 t18 t19 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do b do b + 1 do b + 2 do b + 3 do b + 4 do b + 5 do b + 6 do b + 7 do n des des des des des bank group address bga bgb address bank col n bank col b notes: 1. bl8, al = 0, cl = 11, preamble = 1 t ck, t ccd_s/l = 5. 2. do n (or b ) = data-out from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read commands at t0 and t5. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. figure 134: nonconsecutive read (bl8) with 2 t ck preamble in same or different bank group t0 t ccd_s/l = 6 t rpre rl = 11 t rpst t16 t1 t2 t5 t6 t9 t10 t11 t12 t13 t14 t15 des des des des des des des command des read des des read des dq ck_t ck_c dqs_t, dqs_c rl = 11 t21 t17 t18 t19 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do b do b + 1 do b + 2 do b + 3 do b + 4 do b + 5 do b + 6 do b + 7 do n des des des des des bank group address bga bga or bgb address bank col n bank col b t rpre notes: 1. bl8, al = 0, cl = 11, preamble = 2 t ck, t ccd_s/l = 6. 2. do n (or b ) = data-out from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0 = 00] or mr0[a1:0 = 01] and a12 = 1 during read commands at t0 and t6. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. 6. 6 t ccd_s/l = 5 isnt allowed in 2 t ck preamble mode. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 201 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 135: read (bc4) to read (bc4) with 1 t ck preamble in different bank group t0 t ccd_s = 4 t rpre rl = 11 t rpst t16 t1 t2 t3 t4 t9 t10 t11 t12 t13 t14 t15 des des des des des des des command des read des des read des dq ck_t ck_c dqs_t, dqs_c rl = 11 t21 t17 t18 t19 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do b do b + 1 do b + 2 do b + 3 do n des des des des des bank group address bga bgb address bank col n bank col b t rpre t rpst notes: 1. bl8, al = 0, cl = 11, preamble = 1 t ck. 2. do n (or b) = data-out from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by either mr0[1:0] = 10 or mr0[1:0] = 01 and a12 = 0 during read commands at t0 and t4. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. figure 136: read (bc4) to read (bc4) with 2 t ck preamble in different bank group t0 t ccd_s = 4 t rpre rl = 11 t rpst t16 t1 t2 t3 t4 t9 t10 t11 t12 t13 t14 t15 des des des des des des des command des read des des read des dq ck_t ck_c dqs_t, dqs_c rl = 11 t21 t17 t18 t19 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do b do b + 1 do b + 2 do b + 3 do n des des des des des bank group address bga bgb address bank col n bank col b t rpre notes: 1. bl8, al = 0, cl = 11, preamble = 2 t ck. 2. do n (or b) = data-out from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by either mr0[1:0] = 10 or mr0[1:0] = 01 and a12 = 0 during read commands at t0 and t4. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 202 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 137: read (bl8) to read (bc4) otf with 1 t ck preamble in different bank group t0 t ccd_s = 4 t rpre rl = 11 t rpst t16 t1 t2 t3 t4 t9 t10 t11 t12 t13 t14 t15 des des des des des des des command des read des des read des dq ck_t ck_c dqs_t, dqs_c rl = 11 t21 t17 t18 t19 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do b do b + 1 do b + 2 do b + 3 do n des des des des des bank group address bga bgb address bank col n bank col b notes: 1. bl = 8, al =0, cl = 11, preamble = 1 t ck. 2. do n (or b) = data-out from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0[1:0] = 01 and a12 = 1 during read commands at t0. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during read commands at t4. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. figure 138: read (bl8) to read (bc4) otf with 2 t ck preamble in different bank group t0 t ccd_s = 4 t rpre rl = 11 t rpst t16 t1 t2 t3 t4 t9 t10 t11 t12 t13 t14 t15 des des des des des des des command des read des des read des dq ck_t ck_c dqs_t, dqs_c rl = 11 t21 t17 t18 t19 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do b do b + 1 do b + 2 do b + 3 do n des des des des des bank group address bga bgb address bank col n bank col b notes: 1. bl = 8, al =0, cl = 11, preamble = 2 t ck. 2. do n (or b) = data-out from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0[1:0] = 01 and a12 = 1 during read commands at t0. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during read commands at t4. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 203 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 139: read (bc4) to read (bl8) otf with 1 t ck preamble in different bank group t0 t ccd_s = 4 t rpre rl = 11 t1 t2 t3 t4 des des des des des des des command des read des des read des dq ck_t ck_c dqs_t, dqs_c rl = 11 t20 t21 t14 t9 t10 t11 t12 t13 t19 t15 t16 t17 t18 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do b do b + 1 do b + 2 do b + 3 do b + 4 do b + 5 do b + 6 do b + 7 do n des des des des des bank group address address bank col n bank col b bgb t rpre t rpst t rpst bga notes: 1. bl = 8, al =0, cl = 11, preamble = 1 t ck. 2. do n (or b) = data-out from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during read commands at t0. bl8 setting activated by mr0[1:0] = 01 and a12 = 1 during read commands at t4. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. figure 140: read (bc4) to read (bl8) otf with 2 t ck preamble in different bank group t0 t ccd_s = 4 t rpre rl = 11 t1 t2 t3 t4 des des des des des des des command des read des des read des dq ck_t ck_c dqs_t, dqs_c rl = 11 t20 t21 t14 t9 t10 t11 t12 t13 t19 t15 t16 t17 t18 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do b do b + 1 do b + 2 do b + 3 do b + 4 do b + 5 do b + 6 do b + 7 do n des des des des des bank group address address bank col n bank col b bgb t rpst bga notes: 1. bl = 8, al = 0, cl = 11, preamble = 2 t ck. 2. do n (or b) = data-out from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during read commands at t0. bl8 setting activated by mr0[1:0] = 01 and a12 = 1 during read commands at t4. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 204 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
read operation followed by write operation figure 141: read (bl8) to write (bl8) with 1 t ck preamble in same or different bank group t0 read to write command delay = rl +bl/2 - wl + 2 t ck 4 clocks t rpre rl = 11 t rpst t1 t7 t8 t9 des des des des des des des command des read des write des des dq ck_t ck_c dqs_t, dqs_c wl = 9 t22 t16 t10 t11 t12 t13 t14 t15 t21 t17 t18 t19 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 do n des des des des des bank group address address bank col n bank col b bga bga or bgb t wpre t wpst t wtr t wr notes: 1. bl = 8, rl = 11 (cl = 11, al = 0), read preamble = 1 t ck, wl = 9 (cwl = 9, al = 0), write preamble = 1 t ck. 2. do n = data-out from column n; di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read commands at t0 and write commands at t8. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. figure 142: read (bl8) to write (bl8) with 2 t ck preamble in same or different bank group t0 read to write command delay = rl +bl/2 - wl + 3 t ck 4 clocks t rpre rl = 11 t rpst t1 t7 t8 t9 des des des des des des des command des read des write des des dq ck_t ck_c dqs_t, dqs_c wl = 10 t22 t16 t10 t11 t12 t13 t14 t15 t21 t17 t18 t19 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 do n des des des des des bank group address address bank col n bank col b bga bga or bgb t wpre t wpst t wtr t wr notes: 1. bl = 8, rl = 11 (cl = 11, al = 0), read preamble = 2 t ck, wl = 10 (cwl = 9+1 [see note 5], al = 0), write preamble = 2 t ck. 2. do n = data-out from column n; di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 205 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read commands at t0 and write commands at t8. 5. when operating in 2 t ck write preamble mode, cwl may need to be programmed to a value at least 1 clock greater than the lowest cwl setting. 6. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. figure 143: read (bc4) otf to write (bc4) otf with 1 t ck preamble in same or different bank group t0 read to write command delay = rl +bl/2 - wl + 2 t ck 4 clocks t rpre rl = 11 t rpst t1 t5 t6 t7 des des des des des des des command des read des write des des dq ck_t ck_c dqs_t, dqs_c wl = 9 t20 t14 t8 t9 t10 t11 t12 t13 t19 t15 t16 t17 t18 dont care transitioning data time break do n + 1 do n + 2 do n + 3 di b di b + 1 di b + 2 di b + 3 do n des des des des des bank group address address bank col n bank col b bga bga or bgb t wpre t wpst t wtr t wr notes: 1. bc = 4, rl = 11 (cl = 11, al = 0), read preamble = 1 t ck, wl = 9 (cwl = 9, al = 0), write preamble = 1 t ck. 2. do n = data-out from column n; di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 (otf) setting activated by mr0[1:0] = 01 and a12 = 0 during read commands at t0 and write commands at t6. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 206 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 144: read (bc4) otf to write (bc4) otf with 2 t ck preamble in same or different bank group t0 read to write command delay = rl +bl/2 - wl + 3 t ck 4 clocks t rpre rl = 11 t rpst t1 t5 t6 t7 des des des des des des des command des read des write des des dq ck_t ck_c dqs_t, dqs_c wl = 10 t20 t14 t8 t9 t10 t11 t12 t13 t19 t15 t16 t17 t18 dont care transitioning data time break do n + 1 do n + 2 do n + 3 di b di b + 1 di b + 2 di b + 3 do n des des des des des bank group address address bank col n bank col b bga bga or bgb t wpre t wpst t wtr t wr notes: 1. bc = 4, rl = 11 (cl = 11, al = 0), read preamble = 2 t ck, wl = 10 (cwl = 9 + 1 [see note 5], al = 0), write preamble = 2 t ck. 2. do n = data-out from column n; di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 (otf) setting activated by mr0[1:0] = 01 and a12 = 0 during read commands at t0 and write commands at t6. 5. when operating in 2 t ck write preamble mode, cwl may need to be programmed to a value at least 1 clock greater than the lowest cwl setting. 6. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. figure 145: read (bc4) fixed to write (bc4) fixed with 1 t ck preamble in same or different bank group t0 read to write command delay = rl +bl/2 - wl + 2 t ck t rpre rl = 11 t rpst t1 t5 t6 t7 des des des des des des des command des read des write des des dq ck_t ck_c dqs_t, dqs_c wl = 9 t20 t14 t8 t9 t10 t11 t12 t13 t19 t15 t16 t17 t18 dont care transitioning data time break do n + 1 do n + 2 do n + 3 di b di b + 1 di b + 2 di b + 3 do n des des des des des bank group address address bank col n bank col b bga or bgb t wpre t wpst t wtr t wr bga 2 clocks notes: 1. bc = 4, rl = 11 (cl = 11, al = 0), read preamble = 1 t ck, wl = 9 (cwl = 9, al = 0), write preamble = 1 t ck. 2. do n = data-out from column n; di b = data-in from column b. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 207 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 (fixed) setting activated by mr0[1:0] = 01. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. figure 146: read (bc4) fixed to write (bc4) fixed with 2 t ck preamble in same or different bank group t0 read to write command delay = rl +bl/2 - wl + 3 t ck 2 clocks t rpre rl = 11 t rpst t1 t5 t6 t7 des des des des des des des command des read des write des des dq ck_t ck_c dqs_t, dqs_c wl = 10 t20 t14 t8 t9 t10 t11 t12 t13 t19 t15 t16 t17 t18 dont care transitioning data time break do n + 1 do n + 2 do n + 3 di b di b + 1 di b + 2 di b + 3 do n des des des des des bank group address address bank col n bank col b bga bga or bgb t wpre t wpst t wtr t wr notes: 1. bc = 4, rl = 11 (cl = 11, al = 0), read preamble = 2 t ck, wl = 9 (cwl = 9 + 1 [see note 5], al = 0), write preamble = 2 t ck. 2. do n = data-out from column n; di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 (fixed) setting activated by mr0[1:0] = 10. 5. when operating in 2 t ck write preamble mode, cwl may need to be programmed to a value at least 1 clock greater than the lowest cwl setting. 6. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 208 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 147: read (bc4) to write (bl8) otf with 1 t ck preamble in same or different bank group t0 read to write command delay = rl +bl/2 - wl + 2 t ck t wpre rl = 11 t wpst t1 des des des des des des des command des read des write des des dq ck_t ck_c dqs_t, dqs_c wl = 9 t5 t6 t7 t20 t14 t8 t9 t10 t11 t12 t13 t19 t15 t16 t17 t18 dont care transitioning data time break do n + 1 do n + 2 do n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di b di b + 1 di b + 2 di b + 3 do n des des des des des bank group address address bank col n bank col b bga bga or bgb t rpre t rpst t wtr t wr 4 clocks notes: 1. bl = 8, rl = 11 (cl = 11, al = 0), read preamble = 1 t ck, wl = 9 (cwl = 9, al = 0), write preamble = 1 t ck. 2. do n = data-out from column n; di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write commands at t0. bl8 setting activated by mr0[1:0] = 01 and a12 = 1 during read commands at t6. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. figure 148: read (bc4) to write (bl8) otf with 2 t ck preamble in same or different bank group t0 read to write command delay = rl +bl/2 - wl + 3 t ck t wpre rl = 11 t wpst t1 des des des des des des des command des read des write des des dq ck_t ck_c dqs_t, dqs_c wl = 10 t5 t6 t7 t20 t14 t8 t9 t10 t11 t12 t13 t19 t15 t16 t17 t18 dont care transitioning data time break do n + 1 do n + 2 do n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di b di b + 1 di b + 2 di b + 3 do n des des des des des bank group address address bank col n bank col b bga bga or bgb t rpre t rpst t wtr t wr 4 clocks notes: 1. bl = 8, rl = 11 (cl = 11, al = 0), read preamble = 2 t ck, wl = 10 (cwl = 9 + 1 [see note 5], al = 0), write preamble = 2 t ck. 2. do n = data-out from column n; di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write commands at t0. bl8 setting activated by mr0[1:0] = 01 and a12 = 1 during read commands at t6. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 209 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. figure 149: read (bl8) to write (bc4) otf with 1 t ck preamble in same or different bank group t0 read to write command delay = rl +bl/2 - wl + 2 t ck 4 clocks t rpre rl = 11 t rpst t1 des des des des des des des command des read des write des des dq ck_t ck_c dqs_t, dqs_c wl = 9 t22 t21 t7 t20 t14 t8 t9 t10 t11 t12 t13 t19 t15 t16 t17 t18 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di b di b + 1 di b + 2 di b + 3 do n des des des des des bank group address address bank col n bank col b bga bga or bgb t wpre t wpst t wtr t wr notes: 1. bl = 8, rl = 11 (cl = 11, al = 0), read preamble = 1 t ck, wl = 9 (cwl = 9, al = 0), write preamble = 1 t ck. 2. do n = data-out from column n; di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0[1:0] = 01 and a12 = 1 during read commands at t0. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write commands at t8. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. figure 150: read (bl8) to write (bc4) otf with 2 t ck preamble in same or different bank group t0 read to write command delay = rl +bl/2 - wl + 3 t ck 4 clocks t rpre rl = 11 t rpst t1 des des des des des des des command des read des write des des dq ck_t ck_c dqs_t, dqs_c wl = 10 t22 t21 t7 t20 t14 t8 t9 t10 t11 t12 t13 t19 t15 t16 t17 t18 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di b di b + 1 di b + 2 di b + 3 do n des des des des des bank group address address bank col n bank col b bga bga or bgb t wpre t wpst t wtr t wr notes: 1. bl = 8, rl = 11 (cl = 11, al = 0), read preamble = 2 t ck, wl = 10 (cwl = 9 + 1 [see note 5], al = 0), write preamble = 2 t ck. 2. do n = data-out from column n; di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 210 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
4. bl8 setting activated by mr0[1:0] = 01 and a12 = 1 during read commands at t0. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write commands at t8. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. read operation followed by precharge operation the minimum external read command to precharge command spacing to the same bank is equal to al + t rtp with t rtp being the internal read command to precharge command delay. note that the minimum act to pre timing, t ras, must be satisfied as well. the minimum value for the internal read command to precharge command delay is given by t rtp (min) = max (4 n ck, 7.5ns). a new bank activate command may be issued to the same bank if the following two conditions are satisfied simultane- ously: ? the minimum ras precharge time ( t rp [min]) has been satisfied from the clock at which the precharge begins. ? the minimum ras cycle time ( t rc [min]) from the previous bank activation has been satisfied. figure 151: read to precharge with 1 t ck preamble t0 rl = al + cl t rtp t rp t1 t2 t3 t6 des des des des des des des command read des des des des pre dq bc4 opertaion ck_t ck_c dqs_t, dqs_c t20 t21 t14 t7 t10 t11 t12 t13 t19 t15 t16 t17 t18 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n des act des des des bank group address bga bga or bgb bga address bank a col n bank a (or all) bank a row b dq bl8 opertaion dqs_t, dqs_c do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do n notes: 1. rl = 11 (cl = 11, al = 0 ), preamble = 1 t ck, t rtp = 6, t rp = 11. 2. do n = data-out from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. the example assumes that t ras (min) is satisfied at the precharge command time (t7) and that t rc (min) is satisfied at the next activate command time (t18). 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 211 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 152: read to precharge with 2 t ck preamble rl = al + cl t rtp t rp dq bc4 opertaion dqs_t, dqs_c dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n dq bl8 opertaion dqs_t, dqs_c do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do n t0 t1 t2 t3 t6 des des des des des des des command read des des des des pre ck_t ck_c t20 t21 t14 t7 t10 t11 t12 t13 t19 t15 t16 t17 t18 des act des des des bank group address bga bga bga or bgb address bank a col n bank a (or all) bank a row b notes: 1. rl = 11 (cl = 11, al = 0 ), preamble = 2 t ck, t rtp = 6, t rp = 11. 2. do n = data-out from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. the example assumes that t ras (min) is satisfied at the precharge command time (t7) and that t rc (min) is satisfied at the next activate command time (t18). 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. figure 153: read to precharge with additive latency and 1 t ck preamble t0 cl = 11 al = cl - 2 = 9 t rtp t1 t2 t3 des des pre des des des des command read des des des des des dq bc4 opertaion ck_t ck_c dqs_t, dqs_c t26 t27 t10 t11 t12 t13 t24 t25 t22 t23 t21 t20 t19 t16 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n des des des des act bank group address bga bga or bgb t rp dq bl8 opertaion dqs_t, dqs_c do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do n address bank a col n bank a (or all) bank a row b bga notes: 1. rl =20 (cl = 11, al = cl - 2), preamble = 1 t ck, t rtp = 6, t rp = 11. 2. do n = data-out from column n. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 212 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. the example assumes that t ras (min) is satisfied at the precharge command time (t16) and that t rc (min) is satisfied at the next activate command time (t27). 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. figure 154: read with auto precharge and 1 t ck preamble t0 rl = al + cl t rtp t rp t1 t2 t3 t6 des des des des des des des command rda des des des des pre dq bc4 opertaion ck_t ck_c dqs_t, dqs_c t20 t21 t14 t7 t10 t11 t12 t13 t19 t15 t16 t17 t18 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n des act des des des bank group address bga bga address bank a col n bank a col n bga or bgb bank a row b dq bl8 opertaion dqs_t, dqs_c do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do n notes: 1. rl = 11 (cl = 11, al = 0 ), preamble = 1 t ck, t rtp = 6, t rp = 11. 2. do n = data-out from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. t rtp = 6 setting activated by mr0[a11:9 = 001]. 5. the example assumes that t rc (min) is satisfied at the next activate command time (t18). 6. ca parity = disable, cs to ca latency = disable, read dbi = disable. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 213 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 155: read with auto precharge, additive latency, and 1 t ck preamble t0 cl = 11 al = cl - 2 = 9 t rtp t1 t2 t3 des des des des des des des command rda des des des des des dq bc4 opertaion ck_t ck_c dqs_t, dqs_c t26 t27 t10 t11 t12 t13 t24 t25 t22 t23 t21 t20 t19 t16 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n des des des des act bank group address bga bga t rp dq bl8 opertaion dqs_t, dqs_c do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 do n address bank a col n bank a row b notes: 1. rl = 20 (cl = 11, al = cl - 2), preamble = 1 t ck, t rtp = 6, t rp = 11. 2. do n = data-out from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. t rtp = 6 setting activated by mr0[11:9] = 001. 5. the example assumes that t rc (min) is satisfied at the next activate command time (t27). 6. ca parity = disable, cs to ca latency = disable, read dbi = disable. read operation with read data bus inversion (dbi) figure 156: consecutive read (bl8) with 1 t ck preamble and dbi in different bank group t0 t ccd_s = 4 t rpre rl = 11 + 2 (read dbi adder) t16 t1 t2 t3 t4 t9 t10 t11 t12 t13 t14 t15 des des des des des des des command des read des des read des dq ck_t ck_c dqs_t, dqs_c rl = 11 + 2 (read dbi adder) t21 t17 t18 t19 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do b + 1 do b + 2 do b + 7 do n des des des des des bank group address bga bgb address bank col n bank col b t rpst do n + 4 do n + 5 do n + 6 do n + 7 do b do b + 5 do b + 6 do b + 3 do b +4 _ dbi_n dbi n + 1 dbi n + 2 dbi n + 3 dbi b + 1 dbi b + 2 dbi b + 7 dbi n dbi n + 4 dbi n + 5 dbi n + 6 dbi n + 7 dbi b dbi b + 5 dbi b + 6 dbi b + 3 dbi b + 4 notes: 1. bl = 8, al = 0, cl = 11, preamble = 1 t ck, rl = 11 + 2 (read dbi adder). 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 214 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
2. do n (or b) = data-out from column n (or b); dbi n (or b) = data bus inversion from col- umn n (or b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read commands at t0 and t4. 5. ca parity = disable, cs to ca latency = disable, read dbi = enable. read operation with command/address parity (ca parity) figure 157: consecutive read (bl8) with 1 t ck preamble and ca parity in different bank group t0 t ccd_s = 4 t rpre rl = 15 t1 t2 t3 t4 t7 t8 des des des des des des des command des read des des read des dq ck_t ck_c dqs_t, dqs_c rl = 15 t16 t13 t14 t15 t21 t17 t18 t19 t20 t21 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do b + 1 do b + 2 do b + 7 do n des des des des des bank group address bga bgb address parity bank col n bank col b t rpst do n + 4 do n + 5 do n + 6 do n + 7 do b do b + 5 do b + 6 do b + 3 do b +4 _ notes: 1. bl = 8, al = 0, cl = 11, pl = 4, (rl = cl + al + pl = 15), preamble = 1 t ck. 2. do n (or b) = data-out from column n (or b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:a0 = 00] or mr0[a1:a0 = 01] and a12 = 1 during read commands at t0 and t4. 5. ca parity = enable, cs to ca latency = disable, read dbi = disable. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 215 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 158: read (bl8) to write (bl8) with 1 t ck preamble and ca parity in same or different bank group t0 read to write command delay = rl +bl/2 - wl + 2 t ck 4 clocks t rpre rl = 15 t rpst t1 t7 t8 t9 des des des des des des des command des read des write des des dq ck_t ck_c dqs_t, dqs_c wl = 13 t22 t16 t14 t15 t21 t17 t18 t19 t20 t25 t26 t24 t23 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 do n des des des des des bank group address address parity bank col n bank col b bga bga or bgb t wpre t wpst t wtr t wr notes: 1. bl = 8, al = 0, cl = 11, pl = 4, (rl = cl + al + pl = 15), read preamble = 1 t ck, cwl = 9, al = 0, pl = 4, (wl = cl + al + pl = 13), write preamble = 1 t ck. 2. do n = data-out from column n, di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read commands at t0 and write command at t8. 5. ca parity = enable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 216 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
read followed by write with crc enabled figure 159: read (bl8) to write (bl8 or bc4: otf) with 1 t ck preamble and write crc in same or different bank group t0 read to write command delay = rl +bl/2 - wl + 2 t ck 4 clocks t rpre rl = 11 t rpst t1 t7 t8 t9 t10 t11 t12 t13 des des des des des des des command des read des write des des dq x4, bl = 8 ck_t ck_c dqs_t, dqs_c wl = 9 t22 t16 t14 t15 t21 t17 t18 t19 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 crc crc do n des des des des des bank group address address bank col n bank col b bga bga or bgb dq x8/x16, bl = 8 do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 crc do n dq x4, read: bl = 8, write: bc = 4 (otf) dq x8/x16, read: bl = 8, write: bc = 4 (otf) do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di b di b + 1 di b + 2 crc crc do n t wpre t wpst t wtr t wr do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di b di b + 1 di b + 2 di b + 3 crc do n di b + 3 notes: 1. bl = 8 (or bc = 4: otf for write), rl = 11 (cl = 11, al = 0), read preamble = 1 t ck, wl = 9 (cwl = 9, al = 0), write preamble = 1 t ck. 2. do n = data-out from column n, di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read commands at t0 and write commands at t8. 5. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write commands at t8. 6. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = enable. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 217 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 160: read (bc4: fixed) to write (bc4: fixed) with 1 t ck preamble and write crc in same or different bank group t0 read to write command delay = rl +bl/2 - wl + 2 t ck 2 clocks t rpre rl = 11 t rpst t1 t7 t6 t5 t8 t9 t10 t11 t12 t13 des des des des des des des command des read des write des des dq x4, bc = 4 (fixed) ck_t ck_c dqs_t, dqs_c wl = 9 t16 t14 t15 t17 t18 t19 t20 dont care transitioning data time break do n + 1 do n + 2 do n + 3 di b di b + 1 di b + 2 di b + 3 crc crc do n des des des des des bank group address address bank col n bank col b bga bga or bgb dq x8/x16, bc = 4 (fixed) do n + 1 do n + 2 do n + 3 di b di b + 1 di b + 2 di b + 3 crc do n t wpre t wpst t wtr t wr notes: 1. bc = 4 (fixed), rl = 11 (cl = 11, al = 0), read preamble = 1 t ck, wl = 9 (cwl = 9, al = 0), write preamble = 1 t ck. 2. do n = data-out from column n, di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 10. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = enable. read operation with command/address latency (cal) enabled figure 161: consecutive read (bl8) with cal (3 t ck) and 1 t ck preamble in different bank group t0 t cal = 3 t cal = 3 t ccd_s = 4 t rpre rl = 11 t1 t2 t3 t4 des des des des des des command w/o cs_n des des read read des des dq ck_t ck_c dqs_t, dqs_c rl = 11 t5 t6 t7 t8 t22 t23 t13 t17 t14 t15 t18 t19 t21 dont care transitioning data time break di n + 1 di n + 2 di n + 5 di n + 6 di n + 7 di b di b + 1 di b + 2 di b + 5 di b + 6 di b + 7 di n des des des des des bank group address address bank col n bank col b bga bgb t rpst cs_n notes: 1. bl = 8, rl = 11 (cl = 11, al = 0), read preamble = 1 t ck. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 218 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
2. di n (or b) = data-in from column n (or b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read commands at t3 and t7. 5. ca parity = disable, cs to ca latency = enable, read dbi = disable, write dbi = disable, write crc = disable. 6. enabling cal mode does not impact odt control timings. the same timing relationship relative to the command/address bus as when cal is disabled should be maintained. figure 162: consecutive read (bl8) with cal (4 t ck) and 1 t ck preamble in different bank group t0 t cal = 4 t cal = 4 t ccd_s = 4 t rpre rl = 11 t1 t2 t3 t4 des des des des des des command w/o cs_n des des read read des des dq ck_t ck_c dqs_t, dqs_c rl = 11 t5 t6 t7 t8 t24 t22 t23 t16 t14 t15 t18 t19 t21 dont care transitioning data time break di n + 1 di n + 2 di n + 5 di n + 6 di n + 7 di b di b + 1 di b + 2 di b + 5 di b + 6 di b + 7 di n des des des des des bank group address address bank col n bank col b bga bgb t rpst cs_n notes: 1. bl = 8, rl = 11 (cl = 11, al = 0), read preamble = 1 t ck. 2. di n (or b) = data-in from column n (or b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read commands at t3 and t8. 5. ca parity = disable, cs to ca latency = enable, read dbi = disable, write dbi = disable, write crc = disable. 6. enabling cal mode does not impact odt control timings. the same timing relationship relative to the command/address bus as when cal is disabled should be maintained. 8gb: x4, x8, x16 ddr4 sdram read operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 219 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
write operation write timing definitions the write timings shown in the following figures are applicable in normal operation mode, that is, when the dll is enabled and locked. write timing C clock-to-data strobe relationship the clock-to-data strobe relationship is shown below and is applicable in normal oper- ation mode, that is, when the dll is enabled and locked. rising data strobe edge parameters: ? t dqss (min) to t dqss (max) describes the allowed range for a rising data strobe edge relative to ck. ? t dqss is the actual position of a rising strobe edge relative to ck. ? t dqsh describes the data strobe high pulse width. ? t wpst strobe going to high, nondrive level (shown in the postamble section of the graphic below). falling data strobe edge parameters: ? t dqsl describes the data strobe low pulse width. ? t wpre strobe going to low, initial drive level (shown in the preamble section of the graphic below). 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 220 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 163: write timing definition wl = al + cwl t0 t1 t2 t7 t8 t9 t10 t11 t12 t13 t14 dont care time break transitioning data bank, col n des write des des des des des des des des des ck_t ck_c command 3 dq 2 dqs_t, dqs_c dqs_t, dqs_c dqs_t, dqs_c address 4 t wpstaa dm_n t wpst (min) t dqsl t dqss (min) d in n d in n + 2 d in n + 3 dq 2 dq 2 t dqss (max) t dqss (nominal) t dqsl t wpre(1nck) t dqsl t dqss t dqss t dss t dss t dss t dss t dss t dsh t dsh t dsh t dsh t dss t dss t dss t dss t dss t dss t dss t dss t dss t dss t dsh t dsh t dsh t dsh t dsh t dsh t dsh t dsh t dqsl t dqsh t dqsl t dqsh t dqsl t dqsh tdqsh t dqsl t dqsh t dqsl t dqsh t dqsl t dqsh t dqsh t dqsl t dqsh t dqsl t dqsh t dqsl t dqsh t dqsh t wpre(1nck) t wpre(1nck) t dqsh (min) t dqsh (min) t dqsh (min) t wpst (min) t dqsl (min) t dqsl (min) t dqsl (min) d in n + 4 d in n + 6 d in n + 7 d in n d in n + 2 d in n + 3 d in n + 4 d in n + 6 d in n + 7 d in n d in n + 2 d in n + 3 d in n + 4 d in n + 6 d in n + 7 notes: 1. bl8, wl = 9 (al = 0, cwl = 9). 2. d in n = data-in from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write command at t0. 5. t dqss must be met at each rising clock edge. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 221 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
t wpre calculation figure 164: t wpre method for calculating transitions and endpoints '46bw w :35(hqgv w &.bw &.bf 9 '' 5hvxowlqjgliihuhqwldovljqdouhohydqwiru w :35(vshflilfdwlrq 6lqjohhqghgvljqdosurylghgdvedfnjurxqglqirupdwlrq 9 '46bf '46bw'46bf '46bw '46bf '46bw '46bf w :35(ehjlqv w 9 6: 9 6: 9 5()'4 9 5()'4 9 5()'4 9 ,+',))'46 9 ,+',))3hdn notes: 1. v sw1 = (0.1) v ih,diff,dqs . 2. v sw2 = (0.9) v ih,diff,dqs . 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 222 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
t wpst calculation figure 165: t wpst method for calculating transitions and endpoints '46bw'46bf 9 6: 9 6: '46bw w :367hqgv w &.bw &.bf 5hvxowlqjgliihuhqwldovljqdouhohydqwiru w :367vshflilfdwlrq 6lqjohhqghgvljqdosurylghgdvedfnjurxqglqirupdwlrq 9 '46bf '46bw '46bf w :367ehjlqv w 9 '' 9 5()'4 9 5()'4 9 5()'4 9 ,/',))'46 9 ,/',))3hdn notes: 1. v sw1 =(0.9) v il,diff,dqs . 2. v sw2 = (0.1) v il,diff,dqs . write timing C data strobe-to-data relationship the dq input receiver uses a compliance mask (rx) for voltage and timing as shown in the figure below. the receiver mask (rx mask) defines the area where the input signal must not encroach in order for the dram input receiver to be able to successfully cap- ture a valid input signal. the rx mask is not the valid data-eye. tdivw and v divw define the absolute maximum rx mask. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 223 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 166: rx compliance mask tdivw v divw rx mask v centdq,midpoint v centdq,midpoint is defined as the midpoint between the largest v refdq voltage level and the smallest v refdq voltage level across all dq pins for a given dram. each dq pin's v refdq is defined by the center (widest opening) of the cumulative data input eye as de- picted in the following figure. this means a dram's level variation is accounted for within the dram rx mask. the dram v refdq level will be set by the system to account for r on and odt settings. figure 167: v cent_dq v refdq voltage variation v centdqx v centdqy v centdqz v centdq,midpoint dqx dqy (smallest v refdq level) dqz (largest v refdq level) v ref variation (component) the following figure shows the rx mask requirements both from a midpoint-to-mid- point reference (left side) and from an edge-to-edge reference. the intent is not to add any new requirement or specification between the two but rather how to convert the relationship between the two methodologies. the minimum data-eye shown in the composite view is not actually obtainable due to the minimum pulse width require- ment. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 224 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 168: rx mask dq-to-dqs timings dqs, dqs data-in at dram ball dqs, dqs data-in at dram ball rx mask rx mask C alternative view rx mask rx mask rx mask rx mask dqs_t rx mask 0.5 tdivw 0.5 tdivw t dqs2dq +0.5 tdivw t dqs2dq +0.5 tdivw dqy dramc rx mask dqz dramc rx mask dqz dramb rx mask dqy dramb rx mask dqs_c dqs_c dqs_t dqxCz drama dqy dramc dqz dramc dqz dramb dqy dramb dqxCz drama rx mask tdivw tdivw 0.5 tdivw 0.5 tdivw t dqs2dq t dq2dq t dq2dq t dq2dq t dq2dq t dq2dq t dqs2dq t dq2dq v divw v divw v divw v divw v divw v divw v divw v divw v divw v divw t divw t divw t divw t divw notes: 1. dqx represents an optimally centered mask. dqy represents earliest valid mask. dqz represents latest valid mask. 2. drama represents a dram without any dqs/dq skews. dramb represents a dram with early skews (negative t dqs2dq). dramc represents a dram with delayed skews (positive t dqs2dq). 3. this figure shows the skew allowed between dram-to-dram and between dq-to-dq for a dram. signals assume data is center-aligned at dram latch. tdipw is not shown; composite data-eyes shown would violate tdipw. v centdq,midpoint is not shown but is assumed to be midpoint of v divw . the previous figure shows the basic rx mask requirements. converting the rx mask re- quirements to a classical dq-to-dqs relationship is shown in the following figure. it should become apparent that dram write training is required to take full advantage of the rx mask. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 225 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 169: rx mask dq-to-dqs dram-based timings dqs_c dqs_t rx mask dqs, dqs data-in at dram ball v divw v divw v divw v divw v divw v divw dqx , y, z dqs_c dqs_t rx mask dqs, dqs data-in at dram ball t dsx t dhx dqxCz drama drama dramb dramb dramc dramc tdipw tdipw rx mask vs. composite data-eye rx mask vs. ui data-eye tdipw *skew *skew t dsy t dhy dqy rx mask tdivw t dq2dq dqz tdipw tdivw tdivw t dsz t dhz dqy t dq2dq dqz tdipw rx mask tdivw t dq2dq rx mask tdivw rx mask t divw t dq2dq notes: 1. dqx represents an optimally centered mask. dqy represents earliest valid mask. dqz represents latest valid mask. 2. *skew = t dqs2dq + 0.5 tdivw drama represents a dram without any dqs/dq skews. dramb represents a dram with the earliest skews (negative t dqs2dq, t dqsy > *skew). dramc represents a dram with the latest skews (positive t dqs2dq, t dqhz > *skew). 3. t ds/ t dh are traditional data-eye setup/hold edges at dc levels. t ds and t dh are not specified; t dh and t ds may be any value provided the pulse width and rx mask limits are not violated. t dh (min) > tdivw + t ds (min) + t dq2dq. the ddr4 sdram's input receivers are expected to capture the input data with an rx mask of tdivw provided the minimum pulse width is satisfied. the dram controller will have to train the data input buffer to utilize the rx mask specifications to this maxi- 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 226 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
mum benefit. if the dram controller does not train the data input buffers, then the worst case limits have to be used for the rx mask (tdivw + 2 t dqs2dq), which will generally be the classical minimum ( t ds and t dh) and is required as well. figure 170: example of data input requirements without training t ds v divw 0.5 v divw 0.5 v divw t dh 0.5 tdivw + t dqs2dq tdivw + 2 t dqs2dq 0.5 tdivw + t dqs2dq v centdq,midpoint v il(dc) v ih(dc) dqs_c dqs_t rx mask write burst operation the following write timing diagrams are intended to help understand each write pa- rameter's meaning and are only examples. each parameter will be defined in detail sep- arately. in these write timing diagrams, ck and dqs are shown aligned, and dqs and dq are shown center-aligned for the purpose of illustration. ddr4 write command supports bursts of bl8 (fixed), bc4 (fixed), and bl8/bc4 on- the-fly (otf); otf uses address a12 to control otf when otf is enabled: ? a12 = 0, bc4 (bc4 = burst chop) ? a12 = 1, bl8 write commands can issue precharge automatically with a write with auto pre- charge (wra) command, which is enabled by a10 high. ? write command with a10 = 0 (wr) performs standard write, bank remains active af- ter write burst ? write command with a10 = 1 (wra) performs write with auto precharge, bank goes into precharge after write burst the data mask (dm) function is supported for the x8 and x16 configurations only (the dm function is not supported on x4 devices). the dm function shares a common pin with the dbi_n and tdqs functions. the dm function only applies to write opera- tions and cannot be enabled at the same time the dbi function is enabled. ? if dm_n is sampled low on a given byte lane, the dram masks the write data re- ceived on the dq inputs. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 227 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
? if dm_n is sampled high on a given byte lane, the dram does not mask the data and writes this data into the dram core. ? if crc write is enabled, then dm enabled (via mrs) will be selected between write crc nonpersistent mode (dm disabled) and write crc persistent mode (dm ena- bled). figure 171: write burst operation, wl = 9 (al = 0, cwl = 9, bl8) t0 t wpre t1 t7 t2 t8 t9 t10 t11 t12 t13 des des des des des des des command des write des des des des dq ck_t ck_c dqs_t, dqs_c wl = al + cwl = 9 t16 t14 t15 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di n bank group address address bank col n bga t wpst notes: 1. bl8, wl = 0, al = 0, cwl = 9, preamble = 1 t ck. 2. di n = data-in from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write command at t0. 5. ca parity = disable, cs to ca atency = disable, read dbi = disable. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 228 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 172: write burst operation, wl = 19 (al = 10, cwl = 9, bl8) t0 t wpre al = 10 cwl = 9 t1 t2 t9 t10 t11 des des des des des des des command des write des des des des dq ck_t ck_c dqs_t, dqs_c wl = al + cwl = 19 t21 t17 t18 t19 t20 t23 t22 dont care transitioning data time break di n di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 bank group address address bank col n bga t wpst notes: 1. bl8, wl = 19, al = 10 (cl - 1), cwl = 9, preamble = 1 t ck. 2. di n = data-in from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write command at t0. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable. write operation followed by another write operation figure 173: consecutive write (bl8) with 1 t ck preamble in different bank group t0 t ccd_s = 4 4 clocks t wpre wl = al + cwl = 9 t1 t2 t3 t4 des des des des des des des command des write des des write des dq ck_t ck_c dqs_t, dqs_c wl = al + cwl = 9 t7 t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t19 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 di n des des des des des bank group address address bank col n bank col b bga bgb t wpst t wtr t wr notes: 1. bl8, al = 0, cwl = 9, preamble = 1 t ck. 2. di n (or b) = data-in from column n (or column b). 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 229 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write commands at t0 and t4. 5. ca parity = disable, cs to ca latency = disable, write dbi = disable, write crc = disable. 6. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t17. figure 174: consecutive write (bl8) with 2 t ck preamble in different bank group t0 t ccd_s = 4 4 clocks t wpre wl = al + cwl = 10 t1 t2 t3 t4 des des des des des des des command des write des des write des dq ck_t ck_c dqs_t, dqs_c wl = al + cwl = 10 t7 t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t19 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 di n des des des des des bank group address address bank col n bank col b bga bgb t wpst t wtr t wr notes: 1. bl8, al = 0, cwl = 9 + 1 = 10 (see note 7), preamble = 2 t ck. 2. di n (or b) = data-in from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write commands at t0 and t4. 5. ca parity = disable, cs to ca latency = disable, write dbi = disable, write crc = disable. 6. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t17. 7. when operating in 2 t ck write preamble mode, cwl may need to be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range, which means cwl = 9 is not allowed when operating in 2 t ck write pream- ble mode. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 230 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 175: nonconsecutive write (bl8) with 1 t ck preamble in same or different bank group t0 t ccd_s/l = 5 4 clocks t wpre wl = al + cwl = 9 t1 t2 t3 t4 des des des des des des des command des write des des des write dq ck_t ck_c dqs_t, dqs_c wl = al + cwl = 9 t5 t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t19 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 di n des des des des des bank group address address bank col n bank col b bga bga or bgb t wpst t wtr t wr notes: 1. bl8, al = 0, cwl = 9, preamble = 1 t ck, t ccd_s/l = 5 t ck. 2. di n (or b) = data-in from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write commands at t0 and t5. 5. ca parity = disable, cs to ca latency = disable, write dbi = disable, write crc = disable. 6. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t18. figure 176: nonconsecutive write (bl8) with 2 t ck preamble in same or different bank group t0 t ccd_s/l = 6 4 clocks t wpre wl = al + cwl = 10 t1 t2 t6 t7 des des des des des des des command des write des write des des dq ck_t ck_c dqs_t, dqs_c wl = al + cwl = 10 t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t20 t19 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 di n des des des des des bank group address address bank col n bank col b bga bga or bgb t wpre t wpst t wtr t wr notes: 1. bl8, al = 0, cwl = 9 + 1 = 10 (see note 8), preamble = 2 t ck, t ccd_s/l = 6 t ck. 2. di n (or b) = data-in from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write commands at t0 and t6. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 231 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
5. ca parity = disable, cs to ca latency = disable, write dbi = disable, write crc = disable. 6. t ccd_s/l = 5 isnt allowed in 2 t ck preamble mode. 7. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t20. 8. when operating in 2 t ck write preamble mode, cwl may need to be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range, which means cwl = 9 is not allowed when operating in 2 t ck write pream- ble mode. figure 177: write (bc4) otf to write (bc4) otf with 1 t ck preamble in different bank group t0 t ccd_s = 4 4 clocks t wpre wl = al + cwl = 9 t1 t2 t3 t4 des des des des des des des command des write des des write des dq ck_t ck_c dqs_t, dqs_c wl = al + cwl = 9 t7 t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t19 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di b di b + 1 di b + 2 di b + 3 di n des des des des des bank group address address bank col n bank col b bga bgb t wpre t wtr t wr t wpst t wpst notes: 1. bc4, al = 0, cwl = 9, preamble = 1 t ck. 2. di n (or b) = data-in from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write commands at t0 and t4. 5. ca parity = disable, cs to ca latency = disable, write dbi = disable, write crc = disable. 6. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t17. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 232 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 178: write (bc4) otf to write (bc4) otf with 2 t ck preamble in different bank group t0 t ccd_s = 4 4 clocks t wpre wl = al + cwl = 10 t1 t2 t3 t4 des des des des des des des command des write des des write des dq ck_t ck_c dqs_t, dqs_c wl = al + cwl = 10 t7 t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t19 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di b di b + 1 di b + 2 di b + 3 di n des des des des des bank group address address bank col n bank col b bga bgb t wpre t wtr t wr t wpst notes: 1. bc4, al = 0, cwl = 9 + 1 = 10 (see note 7), preamble = 2 t ck. 2. di n (or b) = data-in from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 01 and a12 = 1 during write commands at t0 and t4. 5. ca parity = disable, cs to ca latency = disable, write dbi = disable, write crc = disable. 6. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t18. 7. when operating in 2 t ck write preamble mode, cwl may need to be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range, which means cwl = 9 is not allowed when operating in 2 t ck write pream- ble mode. figure 179: write (bc4) fixed to write (bc4) fixed with 1 t ck preamble in different bank group t0 t ccd_s = 4 2 clocks t wpre wl = al + cwl = 9 t1 t2 t3 t4 des des des des des des des command des write des des write des dq ck_t ck_c dqs_t, dqs_c wl = al + cwl = 9 t7 t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t19 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di b di b + 1 di b + 2 di b + 3 di n des des des des des bank group address address bank col n bank col b bga bgb t wpre t wtr t wr t wpst t wpst notes: 1. bc4, al = 0, cwl = 9, preamble = 1 t ck. 2. di n (or b) = data-in from column n (or column b). 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 233 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 (fixed) setting activated by mr0[1:0] = 10. 5. ca parity = disable, cs to ca latency = disable, write dbi = disable, write crc = disable. 6. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t15. figure 180: write (bl8) to write (bc4) otf with 1 t ck preamble in different bank group t0 t ccd_s = 4 4 clocks t wpre wl = al + cwl = 9 t1 t2 t3 t4 des des des des des des des command des write des des write des dq ck_t ck_c dqs_t, dqs_c wl = al + cwl = 9 t7 t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t19 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di b di b + 1 di b + 2 di b + 3 di n des des des des des bank group address address bank col n bank col b bga bgb t wtr t wr t wpst notes: 1. bl = 8/bc = 4, al = 0, cl = 9, preamble = 1 t ck. 2. di n (or b) = data-in from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0[1:0] = 01 and a12 = 1 during write command at t0. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write command at t4. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write crc = disable. 6. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t17. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 234 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 181: write (bc4) otf to write (bl8) with 1 t ck preamble in different bank group t0 t ccd_s = 4 t wpre t wpre wl = al + cwl = 9 t1 t2 t3 t4 des des des des des des des command des write des des write des dq ck_t ck_c dqs_t, dqs_c wl = al + cwl = 9 t7 t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t19 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 di n des des des des des bank group address address bank col n bank col b bga bgb t wtr t wr t wpst t wpst 4 clocks notes: 1. bl = 8/bc = 4, al = 0, cl = 9, preamble = 1 t ck. 2. di n (or b) = data-in from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write command at t0. bl8 setting activated by mr0[1:0] = 01 and a12 = 1 during write command at t4. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write crc = disable. 6. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t17. write operation followed by read operation figure 182: write (bl8) to read (bl8) with 1 t ck preamble in different bank group di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 t0 t wtr_s = 2 t wpre wl = al + cwl = 9 rl = al + cl = 11 t1 t7 des des des des read des des command des write des des des des dq ck_t ck_c dqs_t, dqs_c t8 t9 t10 t11 t12 t13 t16 t14 t15 t24 t25 t26 t27 t28 t29 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di n des des des des des bank group address address bank col n bank col b bga bgb t rpre t wpst 4 clocks notes: 1. bl = 8, wl = 9 (cwl = 9, al = 0), cl = 11, read preamble = 1 t ck, write preamble = 1 t ck. 2. di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 235 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write command at t0 and read command at t15. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. 6. the write timing parameter ( t wtr_s) is referenced from the first rising clock edge after the last write data shown at t13. figure 183: write (bl8) to read (bl8) with 1 t ck preamble in same bank group t0 t wtr_l = 4 t wpre wl = al + cwl = 9 rl = al + cl = 11 t1 t7 des des des des des des des command des write des des des read dq ck_t ck_c dqs_t, dqs_c t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t26 t27 t28 t29 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di n des des des des des bank group address address bank col n bank col b bga bga t rpre t wpst di b di b + 1 di b + 2 4 clocks notes: 1. bl = 8, wl = 9 (cwl = 9, al = 0), cl = 11, read preamble = 1 t ck, write preamble = 1 t ck. 2. di b = data-in from column b. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write command at t0 and read command at t17. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. 6. the write timing parameter ( t wtr_l) is referenced from the first rising clock edge after the last write data shown at t13. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 236 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 184: write (bc4) otf to read (bc4) otf with 1 t ck preamble in different bank group t0 t wtr_s = 2 t wpre wl = al + cwl = 9 rl = al + cl = 11 t1 t7 des des des des read des des command des write des des des des dq ck_t ck_c dqs_t, dqs_c t8 t9 t10 t11 t12 t13 t16 t14 t15 t24 t25 t26 t27 t28 t29 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n des des des des des bank group address address bank col n bank col b bga bgb t rpre t wpst t rpst di b di b + 1 di b + 2 di b + 3 4 clocks notes: 1. bc = 4, wl = 9 (cwl = 9, al = 0), cl = 11, read preamble = 1 t ck, write preamble = 1 t ck. 2. di b = data-in from column b . 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write command at t0 and read command at t15. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. 6. the write timing parameter ( t wtr_s) is referenced from the first rising clock edge after the last write data shown at t13. figure 185: write (bc4) otf to read (bc4) otf with 1 t ck preamble in same bank group t0 t wtr_l = 4 t wpre wl = al + cwl = 9 rl = al + cl = 11 t1 t7 des des des des des des read command des write des des des des dq ck_t ck_c dqs_t, dqs_c t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t26 t27 t28 t29 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n des des des des des bank group address address bank col n bank col b bga bga t rpre t wpst di b di b + 1 di b + 2 4 clocks notes: 1. bc = 4, wl = 9 (cwl = 9, al = 0), cl = 11, read preamble = 1 t ck, write preamble = 1 t ck. 2. di b = data-in from column b . 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write command at t0 and read command at t17. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 237 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. 6. the write timing parameter ( t wtr_l) is referenced from the first rising clock edge after the last write data shown at t13. figure 186: write (bc4) fixed to read (bc4) fixed with 1 t ck preamble in different bank group t0 t wtr_s = 2 t wpre wl = al + cwl = 9 rl = al + cl = 11 t1 t7 des des des des des des read command des write des des des des dq ck_t ck_c dqs_t, dqs_c t8 t9 t10 t11 t12 t13 t23 t14 t22 t24 t25 t26 t27 t28 t29 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n des des des des des bank group address address bank col n bank col b bga bgb t rpre t wpst t rpst di b di b + 1 di b + 2 di b + 3 2 clocks notes: 1. bc = 4, wl = 9 (cwl = 9, al = 0), cl = 11, read preamble = 1 t ck, write preamble = 1 t ck. 2. di b = data-in from column b . 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 10. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. 6. the write timing parameter ( t wtr_s) is referenced from the first rising clock edge after the last write data shown at t11. figure 187: write (bc4) fixed to read (bc4) fixed with 1 t ck preamble in same bank group t0 t wtr_l = 4 t wpre wl = al + cwl = 9 rl = al + cl = 11 t1 t7 des des des des des des read command des write des des des des dq ck_t ck_c dqs_t, dqs_c t8 t9 t10 t11 t12 t13 t16 t14 t15 t24 t25 t26 t27 t28 t29 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n des des des des des bank group address address bank col n bank col b bga bga t rpre t wpst t rpst di b di b + 1 di b + 2 di b + 3 2 clocks notes: 1. bc = 4, wl = 9 (cwl = 9, al = 0), c l = 11, read preamble = 1 t ck, write preamble = 1 t ck. 2. di b = data-in from column b . 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 238 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 10. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write dbi = disable, write crc = disable. 6. the write timing parameter ( t wtr_l) is referenced from the first rising clock edge after the last write data shown at t11. write operation followed by precharge operation the minimum external write command to precharge command spacing is equal to wl (al + cwl) plus either 4 t ck (bl8/bc4-otf) or 2 t ck (bc4-fixed) plus t wr. the min- imum act to pre timing, t ras, must be satisfied as well. figure 188: write (bl8/bc4-otf) to precharge with 1 t ck preamble t0 wl = al + cwl = 9 t wr = 12 t rp t1 t2 t3 t4 des des des des des des des command des write des des des des dq bc4 (otf) opertaion ck_t ck_c dqs_t, dqs_c t14 t7 t8 t9 t10 t11 t12 t13 t26 t22 t23 t24 t25 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n des des des pre des address bga, bank b col n bga, bank b (or all) dq bl8 opertaion dqs_t, dqs_c di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di n 4 clocks notes: 1. bl = 8 with bc4-otf, wl = 9 (cwl = 9, al = 0 ), preamble = 1 t ck, t wr = 12. 2. di n = data-in from column n . 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write command at t0. bl8 setting activated by mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write command at t0. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, crc = disable. 6. the write recovery time ( t wr) is referenced from the first rising clock edge after the last write data shown at t13. t wr specifies the last burst write cycle until the precharge command can be issued to the same bank. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 239 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 189: write (bc4-fixed) to precharge with 1 t ck preamble t0 wl = al + cwl = 9 t wr = 12 t rp t1 t2 t3 t4 des des des des des des des command des write des des des des dq bc4 (fixed) opertaion ck_t ck_c dqs_t, dqs_c t14 t7 t8 t9 t10 t11 t12 t13 t26 t22 t23 t24 t25 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n des pre des des des address bga, bank b col n bga, bank b (or all) 2 clocks notes: 1. bc4 = fixed, wl = 9 (cwl = 9, al = 0 ), preamble = 1 t ck, t wr = 12. 2. di n = data-in from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 10. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, crc = disable. 6. the write recovery time ( t wr) is referenced from the first rising clock edge after the last write data shown at t11. t wr specifies the last burst write cycle until the precharge command can be issued to the same bank. figure 190: write (bl8/bc4-otf) to auto precharge with 1 t ck preamble t0 wl = al + cwl = 9 t wr = 12 t rp t1 t2 t3 t4 des des des des des des des command des write des des des des dq bc4 (otf) opertaion ck_t ck_c dqs_t, dqs_c t14 t7 t8 t9 t10 t11 t12 t13 t26 t22 t23 t24 t25 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n des des des des des address bga, bank b col n dq bl8 opertaion dqs_t, dqs_c di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di n 4 clocks notes: 1. bl = 8 with bc4-otf, wl = 9 (cwl = 9, al = 0 ), preamble = 1 t ck, t wr = 12. 2. di n = data-in from column n . 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write command at t0. bl8 setting activated by mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write com- mand at t0. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, crc = disable. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 240 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
6. the write recovery time ( t wr) is referenced from the first rising clock edge after the last write data shown at t13. t wr specifies the last burst write cycle until the precharge command can be issued to the same bank. figure 191: write (bc4-fixed) to auto precharge with 1 t ck preamble t0 wl = al + cwl = 9 t wr = 12 t rp t1 t2 t3 t4 des des des des des des des command des write des des des des dq bc4 (fixed) opertaion ck_t ck_c dqs_t, dqs_c t14 t7 t8 t9 t10 t11 t12 t13 t26 t22 t23 t24 t25 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n des des des des des address bga, bank b col n 2 clocks notes: 1. bc4 = fixed, wl = 9 (cwl = 9, al = 0 ), preamble = 1 t ck, t wr = 12. 2. di n = data-in from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 10. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, crc = disable. 6. the write recovery time ( t wr) is referenced from the first rising clock edge after the last write data shown at t11. t wr specifies the last burst write cycle until the precharge command can be issued to the same bank. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 241 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
write operation with write dbi enabled figure 192: write (bl8/bc4-otf) with 1 t ck preamble and dbi t0 wl = al + cwl = 9 t wr t wtr t1 t2 t3 t4 des des des des des des des command des write des des des des dq bc4 (otf) opertaion ck_t ck_c dqs_t, dqs_c t5 t6 t14 t7 t8 t9 t10 t11 t12 t13 t15 t16 t17 dont care transitioning data di n + 1 di n + 2 di n + 3 di n des des des des des address bga address bank, col n dq dbi_n bl8 opertaion dqs_t, dqs_c di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di n di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di n dbi_n di n + 1 di n + 2 di n + 3 di n 4 clocks notes: 1. bl = 8 with bc4-otf, wl = 9 (cwl = 9, al = 0 ), preamble = 1 t ck. 2. di n = data-in from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write command at t0. bl8 setting activated by mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write com- mand at t0. 5. ca parity = disable, cs to ca latency = disable, write dbi = enabled, write crc = disa- bled. 6. the write recovery time ( t wr_dbi) is referenced from the first rising clock edge after the last write data shown at t13. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 242 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 193: write (bc4-fixed) with 1 t ck preamble and dbi t0 wl = al + cwl = 9 t wr t wtr t1 t2 t3 t4 des des des des des des des command des write des des des des dq bc4 (fixed) opertaion ck_t ck_c dqs_t, dqs_c t5 t6 t14 t7 t8 t9 t10 t11 t12 t13 t15 t16 t17 dont care transitioning data di n + 1 di n + 2 di n + 3 di n des des des des des address bga address bank, col n dbi_n di n + 1 di n + 2 di n + 3 di n 2 clocks notes: 1. bc4 = fixed, wl = 9 (cwl = 9, al = 0 ), preamble = 1 t ck. 2. di n = data-in from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 10. 5. ca parity = disable, cs to ca latency = disable, write dbi = enabled, write crc = disa- bled. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 243 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
write operation with ca parity enabled figure 194: consecutive write (bl8) with 1 t ck preamble and ca parity in different bank group t0 t ccd_s = 4 4 clocks t wpre wl = pl + al + cwl = 13 t1 t2 t3 t4 des des des des des des des command des write des des write des dq ck_t ck_c dqs_t, dqs_c wl = pl + al + cwl = 13 t20 t21 t22 t23 t11 t12 t13 t16 t14 t15 t17 t18 t19 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 di n des des des des des bank group address address bank col n bank col b bga bgb t wpst t wtr t wr parity valid valid notes: 1. bl = 8, wl = 9 (cwl = 13, al = 0 ), preamble = 1 t ck. 2. di n = data-in from column n. 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write com- mands at t0 and t4. 5. ca parity = enable, cs to ca latency = disable, write dbi = enabled, write crc = disa- ble. 6. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t21. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 244 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
write operation with write crc enabled figure 195: consecutive write (bl8/bc4-otf) with 1 t ck preamble and write crc in same or differ- ent bank group t0 t ccd_s/l = 5 t wpre wl = al + cwl = 9 t1 t2 t3 t4 des des des des des des des command des write des des des write dq x4, bl = 8 ck_t ck_c dqs_t, dqs_c wl = al + cwl = 9 t5 t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t19 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 crc di n + 7 crc crc crc di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 crc crc di n des des des des des bank group address address bank col n bank col b bga bga or bgb dq x8/x16, bl = 8 di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 crc di n crc dq x4, bc = 4 (otf) dq x8/x16, bc = 4 (otf) di n + 1 di n + 2 di n + 3 di b di b + 1 di b + 2 crc crc di n t wpst t wtr t wr di n + 1 di n + 2 di n + 3 di b di b + 1 di b + 2 di b + 3 crc di n di b + 3 crc 4 clocks notes: 1. bl8/bc4-otf, al = 0, cwl = 9, preamble = 1 t ck, t cdd_s/l = 5 t ck. 2. di n (or b) = data-in from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write commands at t0 and t5. 5. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write commands at t0 and t5. 6. ca parity = disable, cs to ca latency = disable, read dbi = disable, write crc = enable. 7. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t18. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 245 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 196: consecutive write (bc4-fixed) with 1 t ck preamble and write crc in same or different bank group t0 t ccd_s/l = 5 t wpre wl = al + cwl = 9 t1 t2 t3 t4 des des des des des des des command des write des des des write ck_t ck_c dqs_t, dqs_c wl = al + cwl = 9 t5 t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t19 dont care transitioning data time break crc des des des des des bank group address address bank col n bank col b bga bga or bgb crc crc dq x4, bc = 4 (fixed) dq x8/x16, bc = 4 (fixed) di n + 1 di n + 2 di n + 3 di b di b + 1 di b + 2 crc crc di n t wpst t wtr t wr di n + 1 di n + 2 di n + 3 di b di b + 1 di b + 2 di b + 3 crc di n di b + 3 2 clocks notes: 1. bc4-fixed, al = 0, cwl = 9, preamble = 1 t ck, t cdd_s/l = 5 t ck. 2. di n (or b) = data-in from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[1:0] = 10 during write commands at t0 and t5. 5. ca parity = disable, cs to ca latency = disable, read dbi = disable, write crc = enable, dm = disable. 6. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t16. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 246 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 197: nonconsecutive write (bl8/bc4-otf) with 1 t ck preamble and write crc in same or dif- ferent bank group 7 w &&'b6/ w :35( :/ $/&:/ 7 7 7 7 '(6 '(6 '(6 '(6 '(6 '(6 '(6 &rppdqg '(6 :5,7( '(6 '(6 '(6 '(6 :5,7( '4[ %/ &.bw &.bf '46bw '46bf :/ $/&:/ 7 7 7 7 7 7 7 7 7 7 7 7 7 'rq?w&duh 7udqvlwlrqlqj'dwd 7lph%uhdn ', q ', q ', q ', q ', q ', q ', q &5& ', q &5& &5& &5& ', e ', e ', e ', e ', e ', e ', e ', e &5& &5& ', q '(6 '(6 '(6 '(6 '(6 %dqn*urxs $gguhvv $gguhvv %dqn &roq %dqn &roe %*d %*dru %*e '4[; %/ ', q ', q ', q ', q ', q ', q ', e ', e ', e ', e ', e ', e ', e ', e &5& ', q &5& '4[ %& 27) '4[; %& 27) ', q ', q ', q ', e ', e ', e &5& &5& ', q w :367 w :75 w :5 ', q ', q ', q ', e ', e ', e ', e &5& ', q ', e &5& &orfnv notes: 1. bl8/bc4-otf, al = 0, cwl = 9, preamble = 1 t ck, t cdd_s/l = 6 t ck. 2. di n (or b) = data-in from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write commands at t0 and t6. 5. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write commands at t0 and t6. 6. ca parity = disable, cs to ca latency = disable, read dbi = disable, write crc = enable, dm = disable. 7. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t19. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 247 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 198: nonconsecutive write (bl8/bc4-otf) with 2 t ck preamble and write crc in same or dif- ferent bank group t0 t ccd_s/l = 7 t wpre wl = al + cwl = 10 t1 des des des des des des des command des write des des des write dq x4, bl = 8 ck_t ck_c dqs_t, dqs_c wl = al + cwl = 10 t22 t21 t7 t20 t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t19 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 crc di n + 7 crc crc crc di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 crc crc di n des des des des des bank group address address bank col n bank col b bga bga or bgb dq x8/x16, bl = 8 di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 crc di n crc dq x4, bc = 4 (otf) dq x8/x16, bc = 4 (otf) di n + 1 di n + 2 di n + 3 di b di b + 1 di b + 2 crc crc di n t wpre t wpst t wtr t wr di n + 1 di n + 2 di n + 3 di b di b + 1 di b + 2 di b + 3 crc di n di b + 3 crc 4 clocks notes: 1. bl8/bc4-otf, al = 0, cwl = 9 + 1 = 10 (see note 9), preamble = 2 t ck, t cdd_s/l = 7 t ck (see note 7). 2. di n (or b) = data-in from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write commands at t0 and t7. 5. bc4 setting activated by mr0[1:0] = 01 and a12 = 0 during write commands at t0 and t7. 6. ca parity = disable, cs to ca latency = disable, read dbi = disable, write crc = enable, dm = disable. 7. t cdd_s/l = 6 t ck is not allowed in 2 t ck preamble mode if minimum t cdd_s/l allowed in 1 t ck preamble mode would have been 6 clocks. 8. the write recovery time ( t wr) and write timing parameter ( t wtr) are referenced from the first rising clock edge after the last write data shown at t21. 9. when operating in 2 t ck write preamble mode, cwl may need to be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range. that means cwl = 9 is not allowed when operating in 2 t ck write preamble mode. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 248 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 199: write (bl8/bc4-otf/fixed) with 1 t ck preamble and write crc in same or different bank group t0 t wpre wl = al + cwl = 9 t1 t2 t6 t7 des des des des des des des command des write des des des des des dq x4, bl = 8 ck_t ck_c dqs_t, dqs_c t20 t8 t9 t10 t11 t12 t13 t16 t14 t15 t17 t18 t19 dont care transitioning data time break di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 crc di n + 7 crc crc crc di n des des des des des bank group address address bank col n bga dq x8/x16, bl = 8 di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n crc dq x4, bc = 4 (otf/fixed) dq x8/x16, bc = 4 (otf/fixed) di n + 1 di n + 2 di n + 3 di n t wtr_s_crc_dm/ t wtr_l_crc_dm t wr_crc_dm t wpst di n + 1 di n + 2 di n + 3 di n dm n + 7 dmx4/x8/x16 bl = 8 dm n + 1 dm n + 2 dm n + 3 dm n + 4 dm n + 5 dm n + 6 dm n crc dm x4/x8/x16 bc = 4 (otf / fixed) dm n + 1 dm n + 2 dm n + 3 dm n 4 clocks notes: 1. bl8/bc4, al = 0, cwl = 9, preamble = 1 t ck. 2. di n (or b) = data-in from column n (or column b). 3. des commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during write command at t0. 5. bc4 setting activated by either mr0[1:0] = 10 or mr0[1:0] = 01 and a12 = 0 during write command at t0. 6. ca parity = disable, cs to ca latency = disable, read dbi = disable, write crc = enable, dm = enable. 7. the write recovery time ( t wr_crc_dm) and write timing parameter ( t wtr_s_crc_dm/ t wtr_l_crc_dm) are referenced from the first rising clock edge after the last write da- ta shown at t13. 8gb: x4, x8, x16 ddr4 sdram write operation 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 249 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
write timing violations motivation generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure that the device works properly. however, for certain mi- nor violations, it is desirable that the device is guaranteed not to "hang up" and that er- rors are limited to that specific operation. a minor violation does not include a major timing violation (for example, when a dqs strobe misses in the t dqsck window). for the following, it will be assumed that there are no timing violations with regard to the write command itself (including odt, and so on) and that it does satisfy all timing requirements not mentioned below. data setup and hold violations if the data-to-strobe timing requirements ( t ds, t dh) are violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with this write command. in the example, the relevant strobe edges for write burst a are associated with the clock edges: t5, t5.5, t6, t6.5, t7, t7.5, t8, and t8.5. subsequent reads from that location might result in unpredictable read data; however, the device will work properly otherwise. strobe-to-strobe and strobe-to-clock violations if the strobe timing requirements ( t dqsh, t dqsl, t wpre, t wpst) or the strobe to clock timing requirements ( t dss, t dsh, t dqss) are violated, for any of the strobe edges asso- ciated with a write burst, then wrong data might be written to the memory location addressed with the offending write command. subsequent reads from that location might result in unpredictable read data; however, the device will work properly other- wise with the following constraints: ? both write crc and data burst otf are disabled; timing specifications other than t dqsh, t dqsl, t wpre, t wpst, t dss, t dsh, t dqss are not violated. ? the offending write strobe (and preamble) arrive no earlier or later than six dqs tran- sition edges from the write latency position. ? a read command following an offending write command from any open bank is allowed. ? one or more subsequent wr or a subsequent wra (to same bank as offending wr) may be issued t ccd_l later, but incorrect data could be written. subsequent wr and wra can be either offending or non-offending writes. reads from these writes may provide incorrect data. ? one or more subsequent wr or a subsequent wra (to a different bank group) may be issued t ccd_s later, but incorrect data could be written. subsequent wr and wra can be either offending or non-offending writes. reads from these writes may provide incorrect data. ? after one or more precharge commands (pre or prea) are issued to the device after an offending write command and all banks are in precharged state (idle state), a subsequent, non-offending wr or wra to any open bank will be able to write correct data. 8gb: x4, x8, x16 ddr4 sdram write timing violations 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 250 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
zq calibration commands a zq calibration command is used to calibrate dram r on and odt values. the de- vice needs a longer time to calibrate the output driver and on-die termination circuits at initialization and a relatively smaller time to perform periodic calibrations. the zqcl command is used to perform the initial calibration during the power-up ini- tialization sequence. this command may be issued at any time by the controller de- pending on the system environment. the zqcl command triggers the calibration en- gine inside the dram and, after calibration is achieved, the calibrated values are trans- ferred from the calibration engine to dram i/o, which is reflected as an updated out- put driver and odt values. the first zqcl command issued after reset is allowed a timing period of t zqinit to per- form the full calibration and the transfer of values. all other zqcl commands except the first zqcl command issued after reset are allowed a timing period of t zqoper. the zqcs command is used to perform periodic calibrations to account for voltage and temperature variations. a shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter t zqcs. one zqcs command can effectively correct a minimum of 0.5 % (zq correction) of r on and r tt impedance error within 64 nck for all speed bins assuming the maximum sensitivities specified in the output driver and odt voltage and temperature sensitivity tables. the appropriate in- terval between zqcs commands can be determined from these tables and other appli- cation-specific parameters. one method for calculating the interval between zqcs commands, given the temperature (t drift_rate ) and voltage (v drift_rate ) drift rates that the device is subjected to in the application, is illustrated. the interval could be defined by the following formula: zq correction (t sense x t drift_rate ) + (v sense x t drift_rate ) where t sense = max(dr tt dt, dr on dtm) and v sense = max(dr tt dv, dr on dvm) define the temperature and voltage sensitivities. for example, if t sens = 1.5%/c, v sens = 0.15%/mv, t driftrate = 1 c/sec and v driftrate = 15 mv /sec, then the interval between zqcs commands is calculated as: 0.5 = 0.133 128ms (1.5 1) + (0.15 15) no other activities should be performed on the dram channel by the controller for the duration of t zqinit, t zqoper, or t zqcs. the quiet time on the dram channel allows ac- curate calibration of output driver and on-die termination values. after dram calibra- tion is achieved, the device should disable the zq current consumption path to reduce power. all banks must be precharged and t rp met before zqcl or zqcs commands are issued by the controller. zq calibration commands can also be issued in parallel to dll lock time when coming out of self refresh. upon self refresh exit, the device will not perform an i/o cali- 8gb: x4, x8, x16 ddr4 sdram zq calibration commands 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 251 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
bration without an explicit zq calibration command. the earliest possible time for a zq calibration command (short or long) after self refresh exit is t xs, t xs_abort, or t xs_fast depending on operation mode. in systems that share the zq resistor between devices, the controller must not allow any overlap of t zqoper, t zqinit, or t zqcs between the devices. figure 200: zq calibration timing t0 t1 ta0 dq bus t zqinit_ t zqoper dont care ta1 ta2 ta3 tb0 tb1 tc0 tc1 tc2 zqcs des des des valid valid valid valid valid command des zqcl des des valid valid valid valid high-z or r tt(park) activities note 3 note 2 note 1 activities high-z or r tt(park) time break address valid valid valid valid a10 cke valid valid odt ck_t ck_c t zqcs notes: 1. cke must be continuously registered high during the calibration procedure. 2. during zq calibration, the odt signal must be held low and dram continues to pro- vide rtt_park. 3. all devices connected to the dq bus should be high-z during the calibration procedure. 8gb: x4, x8, x16 ddr4 sdram zq calibration commands 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 252 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
on-die termination the on-die termination (odt) feature enables the device to change termination resist- ance for each dq, dqs, and dm_n/dbi_n signal for x4 and x8 configurations (and tdqs for the x8 configuration when enabled via a11 = 1 in mr1) via the odt control pin, write command, or default parking value with mr setting. for the x16 configura- tion, odt is applied to each dqu, dql, dqsu, dqsl, dmu_n/dbiu_n, and dml_n/ dbil_n signal. the odt feature is designed to improve the signal integrity of the mem- ory channel by allowing the dram controller to independently change termination re- sistance for any or all dram devices. if dbi read mode is enabled while the dram is in standby, either dm mode or dbi write mode must also be enabled if r tt(nom) or r tt(park) is desired. more details about odt control modes and odt timing modes can be found further along in this document. the odt feature is turned off and not supported in self refresh mode. figure 201: functional representation of odt odt v ddq r tt switch dq, dqs, dm, tdqs to other circuitry such as rcv, . . . the switch is enabled by the internal odt control logic, which uses the external odt pin and other control information. the value of r tt is determined by the settings of mode register bits (see mode register). the odt pin will be ignored if the mode register mr1 is programmed to disable r tt(nom) [mr1[10,9,8] = 0,0,0] and in self refresh mode. odt mode register and odt state table the odt mode of the ddr4 device has four states: data termination disable, r tt(nom) , r tt(wr) , and r tt(park) . the odt mode is enabled if any of mr1[10:8] (r tt(nom) ), mr2[11:9] (r tt(wr) ), or mr5[8:6] (r tt(park) ) are non-zero. when enabled, the value of r tt is determined by the settings of these bits. r tt control of each r tt condition is possible with a wr or rd command and odt pin. ?r tt(wr) : the dram (rank) that is being written to provide termination regardless of odt pin status (either high or low). ?r tt(nom) : dram turns on r tt(nom) if it sees odt asserted high (except when odt is disabled by mr1). ?r tt(park) : default parked value set via mr5 to be enabled and r tt(nom) is not turned on. ? the termination state table that follows shows various interactions. the r tt values have the following priority: ? data termination disable ?r tt(wr) ?r tt(nom) ?r tt(park) 8gb: x4, x8, x16 ddr4 sdram on-die termination 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 253 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 71: termination state table case r tt(park) r tt(nom) 1 r tt(wr) 2 odt pin odt reads 3 odt standby odt writes a 4 disabled disabled disabled don't care off (high-z) off (high-z) off (high-z) enabled don't care off (high-z) off (high-z) r tt(wr) b 5 enabled disabled disabled don't care off (high-z) r tt(park) r tt(park) enabled don't care off (high-z) r tt(park) r tt(wr) c 6 disabled enabled disabled low off (high-z) off (high-z) off (high-z) high off (high-z) r tt(nom) r tt(nom) enabled low off (high-z) off (high-z) r tt(wr) high off (high-z) r tt(nom) r tt(wr) d 6 enabled enabled disabled low off (high-z) r tt(park) r tt(park) high off (high-z) r tt(nom) r tt(nom) enabled low off (high-z) r tt(park) r tt(wr) high off (high-z) r tt(nom) r tt(wr) notes: 1. if r tt(nom) mr is disabled, power to the odt receiver will be turned off to save power. 2. if r tt(wr) is enabled, r tt(wr) will be activated by a write command for a defined period time independent of the odt pin and mr setting of r tt(park) /r tt(nom) . this is described in the dynamic odt section. 3. when a read command is executed, the dram termination state will be high-z for a defined period independent of the odt pin and mr setting of r tt(park) /r tt(nom) . this is described in the odt during read section. 4. case a is generally best for single-rank memories. 5. case b is generally best for dual-rank, single-slotted memories. 6. case c and case d are generally best for multi-slotted memories. odt read disable state table upon receiving a read command, the dram driving data disables odt after rl - (2 or 3) clock cycles, where 2 = 1 t ck preamble mode and 3 = 2 t ck preamble mode. odt stays off for a duration of bl/2 + (2 or 3) + (0 or 1) clock cycles, where 2 = 1 t ck preamble mode, 3 = 2 t ck preamble mode, 0 = crc disabled, and 1 = crc enabled. table 72: read termination disable window preamble crc start odt disable after read duration of odt disable 1 t ck disabled rl - 2 bl/2 + 2 enabled rl - 2 bl/2 + 3 2 t ck disabled rl - 3 bl/2 + 3 enabled rl - 3 bl/2 + 4 8gb: x4, x8, x16 ddr4 sdram odt mode register and odt state table 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 254 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
synchronous odt mode synchronous odt mode is selected whenever the dll is turned on and locked. based on the power-down definition, these modes include the following: ? any bank active with cke high ? refresh with cke high ? idle mode with cke high ? active power-down mode (regardless of mr1 bit a10) ? precharge power-down mode in synchronous odt mode, r tt(nom) will be turned on dodtlon clock cycles after odt is sampled high by a rising clock edge and turned off dodtloff clock cycles after odt is registered low by a rising clock edge. the odt latency is determined by the programmed values for: cas write latency (cwl), additive latency (al), and parity la- tency (pl), as well as the programmed state of the preamble. odt latency and posted odt the odt latencies for synchronous odt mode are summarized in the table below. for details, refer to the latency definitions. table 73: odt latency at ddr4-1600/-1866/-2133/-2400/-2666/-3200 applicable when write crc is disabled symbol parameter 1 t ck preamble 2 t ck preamble unit dodtlon direct odt turn-on latency cwl + al + pl - 2 cwl + al + pl - 3 t ck dodtloff direct odt turn-off latency cwl + al + pl - 2 cwl + al + pl - 3 rodtloff read command to internal odt turn-off latency cl + al + pl - 2 cl + al + pl - 3 rodtlon4 read command to r tt(park) turn-on la- tency in bc4-fixed rodtloff + 4 rodtloff + 5 rodtlon8 read command to r tt(park) turn-on la- tency in bl8/bc4-otf rodtloff + 6 rodtloff + 7 odth4 odt assertion time, bc4 mode 4 5 odth8 odt assertion time, bl8 mode 6 7 timing parameters in synchronous odt mode, the following parameters apply: ? dodtlon, dodtloff, rodtloff, rodtlon4, rodtlon8, and t adc (min)/(max). ? t adc (min) and t adc (max) are minimum and maximum r tt change timing skew between different termination values. these timing parameters apply to both the syn- chronous odt mode and the data termination disable mode. when odt is asserted, it must remain high until minimum odth4 (bc = 4) or odth8 (bl = 8) is satisfied. if write crc mode or 2 t ck preamble mode is enabled, odth should be adjusted to account for it. odthx is measured from odt first regis- tered high to odt first registered low or from the registration of a write command. 8gb: x4, x8, x16 ddr4 sdram synchronous odt mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 255 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 202: synchronous odt timing with bl8 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 diff_ck dodtlon = wl - 2 dodtloff = wl - 2 command odt dram_r tt r tt(park) r tt(nom) r tt(park) t adc (min) t adc (max) t adc (min) t adc (max) transitioning notes: 1. example for cwl = 9, al = 0, pl = 0; dodtlon = al + pl + cwl - 2 = 7; dodtloff = al + pl + cwl - 2 = 7. 2. odt must be held high for at least odth8 after assertion (t1). figure 203: synchronous odt with bc4 diff_ck dodtlon = cwl - 2 odth4 odtlcwn4 = odtlcnw + 4 dodtloff = wl - 2 command odt dram_r tt r tt(park) r tt(park) r tt(wr) t adc (min) t adc (max) t adc (min) t adc (max) t1 t0 t2 t3 t4 t5 t18 t19 t20 t21 t22 t23 t36 t37 t38 t39 t40 t41 42 t adc (min) t adc (max) t adc (min) t adc (max) wrs4 transitioning odtlcnw = wl - 2 r tt(park) r tt(nom) notes: 1. example for cwl = 9, al = 10, pl = 0; dodtlon/off = al + pl+ cwl - 2 = 17; odtcnw = al + pl+ cwl - 2 = 17. 2. odt must be held high for at least odth4 after assertion (t1). 8gb: x4, x8, x16 ddr4 sdram synchronous odt mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 256 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
odt during reads because the dram cannot terminate with r tt and drive with r on at the same time, r tt may nominally not be enabled until the end of the postamble as shown in the example below. at cycle t25 the device turns on the termination when it stops driving, which is determined by t hz. if the dram stops driving early (that is, t hz is early), then t adc (min) timing may apply. if the dram stops driving late (that is, t hz is late), then the dram complies with t adc (max) timing. using cl = 11 as an example for the figure below: pl = 0, al = cl - 1 = 10, rl = pl + al + cl = 21, cwl= 9; rodtloff = rl - 2 = 19, dodtlon = pl + al + cwl - 2 = 17, 1 t ck preamble. figure 204: odt during reads gliib&. '2'7/rq :/ 5/ $/&/3/ 52'7/rii 5/ &rppdqg 2'7 '46b2'7 w &.3uhdpeoh 5 773dun w $'&0,1 w $'&0$; 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 w $'&0,1 w $'&0$; 5' $gguhvv $ '4 '46glii 7udqvlwlrqlqj 5 77120 '46b2'7 w &.3uhdpeoh 5 773dun w $'&0,1 w $'&0$; w $'&0,1 w $'&0$; 5 77120 '4b2'7 w &.3uhdpeoh 5 773dun w $'&0,1 w $'&0$;q&. w $'&0$;q&. w $'&0,1 w $'&0$; 5 77120 4$ 4$ 4$ 4$ 4$ 4$ 4$ 4$ '4b2'7 w &.3uhdpeoh 5 773dun w $'&0,1 w $'&0,1 w $'&0$; 5 77120 '4 4$ 4$ 4$ 4$ 4$ 4$ 4$ 4$ 8gb: x4, x8, x16 ddr4 sdram synchronous odt mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 257 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
dynamic odt in certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the device can be changed without issuing an mrs command. this requirement is supported by the dynamic odt feature. functional description dynamic odt mode is enabled if bit a9 or a10 of mr2 is set to 1. ? three r tt values are available: r tt(nom) , r tt(wr) , and r tt(park) . C the value for r tt(nom) is preselected via bits mr1[10:8]. C the value for r tt(wr) is preselected via bits mr2[11:9]. C the value for r tt(park) is preselected via bits mr5[8:6]. ? during operation without write commands, the termination is controlled as fol- lows: C nominal termination strength r tt(nom) or r tt(park) is selected. Cr tt(nom) on/off timing is controlled via odt pin and latencies dodtlon and dodtloff, and r tt(park) is on when odt is low. ? when a write command (wr, wra, wrs4, wrs8, wras4, and wras8) is regis- tered, and if dynamic odt is enabled, the termination is controlled as follows: C latency odtlcnw after the write command, termination strength r tt(wr) is se- lected. C latency odtlcwn8 (for bl8, fixed by mrs or selected otf) or odtlcwn4 (for bc4, fixed by mrs or selected otf) after the write command, termination strength r tt(wr) is de-selected. one or two clocks will be added into or subtracted from odtlcwn8 and odtlcwn4, depending on write crc mode and/or 2 t ck preamble enablement. the following table shows latencies and timing parameters relevant to the on-die termi- nation control in dynamic odt mode. the dynamic odt feature is not supported in dll-off mode. an mrs command must be used to set r tt(wr) to disable dynamic odt externally (mr2[11:9] = 000). table 74: dynamic odt latencies and timing (1 t ck preamble mode and crc disabled) name and description abbr. defined from defined to definition for all ddr4 speed bins unit odt latency for change from r tt(park) /r tt(nom) to r tt(wr) odtlcnw registering external write command change r tt strength from r tt(park) /r tt(nom) to r tt(wr) odtlcnw = wl - 2 t ck odt latency for change from r tt(wr) to r tt(park) /r tt(nom) (bc = 4) odtlcwn 4 registering external write command change r tt strength from r tt(wr) to r tt(park) /r tt(nom) odtlcwn4 = 4 + odtlcnw t ck odt latency for change from r tt(wr) to r tt(park) /r tt(nom) (bl = 8) odtlcwn 8 registering external write command change r tt strength from r tt(nom) to r tt(wr) odtlcwn8 = 6 + odtlcnw t ck (avg) r tt change skew t adc odtlcnw odtlcwn r tt valid t adc (min) = 0.3 t adc (max) = 0.7 t ck (avg) 8gb: x4, x8, x16 ddr4 sdram dynamic odt 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 258 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 75: dynamic odt latencies and timing with preamble mode and crc mode matrix symbol 1 t ck parameter 2 t ck parameter unit crc off crc on crc off crc on odtlcnw 1 wl - 2 wl - 2 wl - 3 wl - 3 t ck odtlcwn4 odtlcnw + 4 odtlcnw + 7 odtlcnw + 5 odtlcnw + 8 odtlcwn8 odtlcnw + 6 odtlcnw + 7 odtlcnw + 7 odtlcnw + 8 note: 1. odtlcnw = wl - 2 (1 t ck preamble) or wl - 3 (2 t ck preamble). figure 205: dynamic odt (1 t ck preamble; cl = 14, cwl = 11, bl = 8, al = 0, crc disabled) diff_ck odtlcwn odtlcnw dodtlon = wl - 2 dodtloff = wl - 2 command odt r tt r tt(park) r tt(nom) r tt(park) r tt(wr) t adc (max) t adc (max) t1 t0 t2 t5 t6 t7 t14 t8 t9 t10 t11 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t adc (min) t adc (min) t adc (min) t adc (min) t adc (max) r tt(park) t adc (max) wr transitioning notes: 1. odtlcnw = wl - 2 (1 t ck preamble) or wl - 3 (2 t ck preamble). 2. if bc4, then odtlcwn = wl + 4 if crc disabled or wl + 5 if crc enabled; if bl8, then odtlcwn = wl + 6 if crc disabled or wl + 7 if crc enabled. 8gb: x4, x8, x16 ddr4 sdram dynamic odt 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 259 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 206: dynamic odt overlapped with r tt(nom) (cl = 14, cwl = 11, bl = 8, al = 0, crc disabled) diff_ck command odt t1 t0 t2 t5 t6 t7 t25 t12 t9 t10 t11 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 wr odtlcnw dodtloff = cwl -2 odtlcwn8 r tt r tt_nom r tt_nom r tt_park r tt_wr t adc (max) t adc (max) t adc (min) t adc (min) t adc (min) t adc (max) note: 1. behavior with wr command issued while odt is registered high. 8gb: x4, x8, x16 ddr4 sdram dynamic odt 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 260 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
asynchronous odt mode asynchronous odt mode is selected when the dram runs in dll-off mode. in asyn- chronous odt timing mode, the internal odt command is not delayed by either addi- tive latency (al) or the parity latency (pl) relative to the external odt signal (r tt(nom) ). in asynchronous odt mode, two timing parameters apply: t aonas (min/max), and t aofas (min/max). r tt(nom) turn-on time ? minimum r tt(nom) turn-on time ( t aonas [min]) is when the device termination cir- cuit leaves r tt(park) and odt resistance begins to turn on. ? maximum r tt(nom) turn-on time ( t aonas [max]) is when the odt resistance has reached r tt(nom) . ? t aonas (min) and t aonas (max) are measured from odt being sampled high. r tt(nom) turn-off time ? minimum r tt(nom) turn-off time ( t aofas [min]) is when the device's termination circuit starts to leave r tt(nom) . ? maximum r tt(nom) turn-off time ( t aofas [max]) is when the on-die termination has reached r tt(park) . ? t aofas (min) and t aofas (max) are measured from odt being sampled low. figure 207: asynchronous odt timings with dll off diff_ck t aonas (max) cke odt r tt r tt(park) r tt(nom) t aonas (min) t aonas (max) t aonas (min) t ih t is t ih t is t1 t0 t2 t3 t4 t5 t6 ti ti + 1 ti + 2 ti + 3 ti + 4 ti + 5 ti + 6 ta tb transitioning 8gb: x4, x8, x16 ddr4 sdram asynchronous odt mode 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 261 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
electrical specifications absolute ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions outside those indicated in the operational sections of this specification is not im- plied. exposure to absolute maximum rating conditions for extended periods may ad- versely affect reliability. although "unlimited" row accesses to the same row is allowed within the refresh period; excessive row accesses to the same row over a long term can result in degraded operation. table 76: absolute maximum ratings symbol parameter min max unit notes v dd voltage on v dd pin relative to v ss C0.4 1.5 v 1 v ddq voltage on v ddq pin relative to v ss C0.4 1.5 v 1 v pp voltage on v pp pin relative to v ss C0.4 3.0 v 3 v in , v out voltage on any pin relative to v ss C0.4 1.5 v t stg storage temperature C55 150 c 2 notes: 1. v dd and v ddq must be within 300mv of each other at all times, and v ref must not be greater than 0.6 v ddq . when v dd and v ddq are <500mv, v ref can be 300mv. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to the jesd51-2 standard. 3. v pp must be equal to or greater than v dd /v ddq at all times when powered. dram component operating temperature range operating temperature, t oper , is the case surface temperature on the center/top side of the dram. for measurement conditions, refer to the jedec document jesd51-2. table 77: temperature range symbol parameter min max unit notes t oper normal operating temperature range 0 85 c 1 extended temperature range (optional) >85 95 c 2 notes: 1. the normal temperature range specifies the temperatures at which all dram specifica- tions will be supported. during operation, the dram case temperature must be main- tained between 0c to 85c under all operating conditions for the commercial offering; the industrial temperature offering allows the case temperature to go below 0c to -40c. 2. some applications require operation of the commercial and industrial temperature drams in the extended temperature range (between 85c and 95c case temperature). full specifications are supported in this range, but the following additional conditions apply: ? refresh commands must be doubled in frequency, reducing the refresh interval t refi to 3.9s. it is also possible to specify a component with 1x refresh ( t refi to 7.8s) in the extended temperature range. 8gb: x4, x8, x16 ddr4 sdram electrical specifications 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 262 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
? if self refresh operation is required in the extended temperature range, it is manda- tory to use either the manual self refresh mode with extended temperature range ca- pability (mr2[6] = 0 and mr2 [7] = 1) or enable the optional auto self refresh mode (mr2 [6] = 1 and mr2 [7] = 1). electrical characteristics C ac and dc operating conditions supply operating conditions table 78: recommended supply operating conditions symbol parameter rating unit notes min typ max v dd supply voltage 1.14 1.2 1.26 v 1, 2, 3, 4, 5 v ddq supply voltage for output 1.14 1.2 1.26 v 1, 2, 6 v pp wordline supply voltage 2.375 2.5 2.750 v 7 notes: 1. under all conditions v ddq must be less than or equal to v dd . 2. v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together. 3. v dd slew rate between 300mv and 80% of v dd,min shall be between 0.004 v/ms and 600 v/ms, 20 mhz band-limited measurement. 4. v dd ramp time from 300mv to v dd,min shall be no longer than 200ms. 5. a stable valid v dd level is a set dc level (0 hz to 250 khz) and must be no less than v dd,min and no greater than v dd,max . if the set dc level is altered anytime after initializa- tion, the dll reset and calibrations must be performed again after the new set dc level is final. ac noise of 60mv (greater than 250 khz) is allowed on v dd provided the noise doesn't alter v dd to less than v dd,min or greater than v dd,max . 6. a stable valid v ddq level is a set dc level (0 hz to 250 khz) and must be no less than v ddq,min and no greater than v ddq,max . if the set dc level is altered anytime after initial- ization, the dll reset and calibrations must be performed again after the new set dc level is final. ac noise of 60mv (greater than 250 khz) is allowed on v ddq provided the noise doesn't alter v ddq to less than v ddq,min or greater than v ddq,max . 7. a stable valid v pp level is a set dc level (0 hz to 250 khz) and must be no less than v pp,min and no greater than v pp,max . if the set dc level is altered anytime after initializa- tion, the dll reset and calibrations must be performed again after the new set dc level is final. ac noise of 120mv (greater than 250 khz) is allowed on v pp provided the noise doesn't alter v pp to less than v pp,min or greater than v pp,max . table 79: v dd slew rate symbol min max unit notes v dd_sl 0.004 600 v/ms 1, 2 v dd_on C 200 ms 3 notes: 1. measurement made between 300mv and 80% v dd (minimum level). 2. the dc bandwidth is limited to 20 mhz. 3. maximum time to ramp v dd from 300 mv to v dd minimum. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc operating conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 263 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
leakages table 80: leakages condition symbol min max unit notes input leakage (excluding zq and ten) i in C2 2 a 1 zq leakage i zq C3 3 a 1 ten leakage i ten C6 10 a 1, 2 v refca leakage i vrefca C2 2 a 3 output leakage: v out = v ddq i ozpd C 5 a 4 output leakage: v out = v ssq i ozpu C50 C a 4, 5 notes: 1. input under test 0v < v in < 1.1v. 2. additional leakage due to weak pull-down. 3. v refca = v dd /2, v dd at valid level after initialization. 4. dqs are disabled. 5. odt is disabled with the odt input high. v refca supply v refca is to be supplied to the dram and equal to v dd /2. the v refca is a reference sup- ply input and therefore does not draw biasing current. the dc-tolerance limits and ac-noise limits for the reference voltages v refca are illus- trated in the figure below. the figure shows a valid reference voltage v ref(t) as a function of time (v ref stands for v refca ). v ref(dc) is the linear average of v ref(t) over a very long period of time (1 second). this average has to meet the min/max requirements. fur- thermore, v ref(t) may temporarily deviate from v ref(dc) by no more than 1% v dd for the ac-noise limit. figure 208: v refdq voltage range v ref ac-noise v ref(dc) v ref(dc) max v ref(t) v ref(dc) min v dd /2 v ss time voltage v dd 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc operating conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 264 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
the voltage levels for setup and hold time measurements are dependent on v ref . v ref is understood as v ref(dc) , as defined in the above figure. this clarifies that dc-variations of v ref affect the absolute voltage a signal has to reach to achieve a valid high or low level, and therefore, the time to which setup and hold is measured. system timing and voltage budgets need to account for v ref(dc) deviations from the optimum position within the data-eye of the input signals. this also clarifies that the dram setup/hold specification and derating values need to include time and voltage associated with v ref ac-noise. timing and voltage effects due to ac-noise on v ref up to the specified limit (1% of v dd ) are included in dram timings and their associated deratings. v refdq supply and calibration ranges the device internally generates its own v refdq . dram internal v refdq specification pa- rameters: voltage range, step size, v ref step time, v ref full step time, and v ref valid level are used to help provide estimated values for the internal v refdq and are not pass/fail limits. the voltage operating range specifies the minimum required range for ddr4 sdram devices. the minimum range is defined by v refdq,min and v refdq,max . a cali- bration sequence should be performed by the dram controller to adjust v refdq and optimize the timing and voltage margin of the dram data input receivers. table 81: v refdq specification parameter symbol min typ max unit notes range 1 v refdq operating points v refdq r1 60% C 92% v ddq 1, 2 range 2 v refdq operating points v refdq r2 45% C 77% v ddq 1, 2 v ref step size v ref,step 0.5% 0.65% 0.8% v ddq 3 v ref set tolerance v ref,set_tol C1.625% 0% 1.625% v ddq 4, 5, 6 C0.15% 0% 0.15% v ddq 4, 7, 8 v ref step time v ref,time C C 150 ns 9, 10, 11 v ref valid tolerance v ref_val_tol C0.15% 0% 0.15% v ddq 12 notes: 1. v ref(dc) voltage is referenced to v ddq(dc) . v ddq(dc) is 1.2v. 2. dram range 1 or range 2 is set by the mrs6[6]6. 3. v ref step size increment/decrement range. v ref at dc level. 4. v ref,new = v ref,old n v ref,step ; n = number of steps. if increment, use +, if decrement, use -. 5. for n >4, the minimum value of v ref setting tolerance = v ref,new - 1.625% v ddq . the maximum value of v ref setting tolerance = v ref,new + 1.625% v ddq . 6. measured by recording the min and max values of the v ref output over the range, drawing a straight line between those points, and comparing all other v ref output set- tings to that line. 7. for n 4, the minimum value of v ref setting tolerance = v ref,new - 0.15% v ddq . the maximum value of v ref setting tolerance = v ref,new + 0.15% v ddq . 8. measured by recording the min and max values of the v ref output across four consecu- tive steps (n = 4), drawing a straight line between those points, and comparing all v ref output settings to that line. 9. time from mrs command to increment or decrement one step size for v ref . 10. time from mrs command to increment or decrement more than one step size up to the full range of v ref . 11. if the v ref monitor is enabled, v ref must be derated by +10ns if dq bus load is 0pf and an additional +15 ns/pf of dq bus loading. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc operating conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 265 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
12. only applicable for dram component-level test/characterization purposes. not applica- ble for normal mode of operation. v ref valid qualifies the step times, which will be char- acterized at the component level. v refdq ranges mr6[6] selects range 1 (60% to 92.5% of v ddq ) or range 2 (45% to 77.5% of v ddq ), and mr6[5:0] sets the v refdq level, as listed in the following table. the values in mr6[6:0] will update the v ddq range and level independent of mr6[7] setting. it is recommended mr6[7] be enabled when changing the settings in mr6[6:0], and it is highly recommen- ded mr6[7] be enabled when changing the settings in mr6[6:0] multiple times during a calibration routine. table 82: v refdq range and levels mr6[5:0] mr6[6] 0 = range 1 mr6[6] 1 = range 2 mr6[5:0] mr6[6] 0 = range 1 mr6[6] 1 = range 2 00 0000 60.00% 45.00% 01 1010 76.90% 61.90% 00 0001 60.65% 45.65% 01 1011 77.55% 62.55% 00 0010 61.30% 46.30% 01 1100 78.20% 63.20% 00 0011 61.95% 46.95% 01 1101 78.85% 63.85% 00 0100 62.60% 47.60% 01 1110 79.50% 64.50% 00 0101 63.25% 48.25% 01 1111 80.15% 65.15% 00 0110 63.90% 48.90% 10 0000 80.80% 65.80% 00 0111 64.55% 49.55% 10 0001 81.45% 66.45% 00 1000 65.20% 50.20% 10 0010 82.10% 67.10% 00 1001 65.85% 50.85% 10 0011 82.75% 67.75% 00 1010 66.50% 51.50% 10 0100 83.40% 68.40% 00 1011 67.15% 52.15% 10 0101 84.05% 69.05% 00 1100 67.80% 52.80% 10 0110 84.70% 69.70% 00 1101 68.45% 53.45% 10 0111 85.35% 70.35% 00 1110 69.10% 54.10% 10 1000 86.00% 71.00% 00 1111 69.75% 54.75% 10 1001 86.65% 71.65% 01 0000 70.40% 55.40% 10 1010 87.30% 72.30% 01 0001 71.05% 56.05% 10 1011 87.95% 72.95% 01 0010 71.70% 56.70% 10 1100 88.60% 73.60% 01 0011 72.35% 57.35% 10 1101 89.25% 74.25% 01 0100 73.00% 58.00% 10 1110 89.90% 74.90% 01 0101 73.65% 58.65% 10 1111 90.55% 75.55% 01 0110 74.30% 59.30% 11 0000 91.20% 76.20% 01 0111 74.95% 59.95% 11 0001 91.85% 76.85% 01 1000 75.60% 60.60% 11 0010 92.50% 77.50% 01 1001 76.25% 61.25% 11 0011 to 11 1111 are reserved 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc operating conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 266 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
electrical characteristics C ac and dc single-ended input measurement levels reset_n input levels table 83: reset_n input levels (cmos) parameter symbol min max unit note ac input high voltage v ih(ac)_reset 0.8 v dd v dd v1 dc input high voltage v ih(dc)_reset 0.7 v dd v dd v2 dc input low voltage v il(dc)_reset v ss 0.3 v dd v3 ac input low voltage v il(ac)_reset v ss 0.2 v dd v4 rising time t r_reset C 1 s 5 reset pulse width after power-up t pw_reset_s 1 C s 6, 7 reset pulse width during power-up t pw_reset_l 200 C s 6 notes: 1. overshoot should not exceed the v in shown in the absolute maximum ratings table. 2. after reset_n is registered high, the reset_n level must be maintained above v ih(dc)_reset , otherwise operation will be uncertain until it is reset by asserting reset_n signal low. 3. after reset_n is registered low, the reset_n level must be maintained below v il(dc)_re- set during t pw_reset, otherwise the dram may not be reset. 4. undershoot should not exceed the v in shown in the absolute maximum ratings table. 5. slope reversal (ring-back) during this level transition from low to high should be miti- gated as much as possible. 6. reset is destructive to data contents. 7. see reset procedure at power stable condition figure. figure 209: reset_n input slew rate definition t r_reset t pw_reset v ih(ac)_reset,min v il(ac)_reset,max v ih(dc)_reset,min v il(dc)_reset,max command/address input levels table 84: command and address input levels: ddr4-1600 through ddr4-2400 parameter symbol min max unit note ac input high voltage v ih(ac) v ref + 100 v dd 5 mv 1, 2, 3 dc input high voltage v ih(dc) v ref + 75 v dd mv 1, 2 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc single-ended input measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 267 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 84: command and address input levels: ddr4-1600 through ddr4-2400 (continued) parameter symbol min max unit note dc input low voltage v il(dc) v ss v ref - 75 mv 1, 2 ac input low voltage v il(ac) v ss 5v ref - 100 mv 1, 2, 3 reference voltage for cmd/addr inputs v reffca(dc) 0.49 v dd 0.51 v dd v4 notes: 1. for input except reset_n. v ref = v refca(dc) . 2. v ref = v refca(dc) . 3. input signal must meet v il /v ih(ac) to meet t is timings and v il /v ih(dc) to meet t ih timings. 4. the ac peak noise on v ref may not allow v ref to deviate from v refca(dc) by more than 1% v dd (for reference: approximately 12mv). 5. refer to overshoot and undershoot specifications. table 85: command and address input levels: ddr4-2666 parameter symbol min max unit note ac input high voltage v ih(ac) v ref + 90 v dd 5 mv 1, 2, 3 dc input high voltage v ih(dc) v ref + 65 v dd mv 1, 2 dc input low voltage v il(dc) v ss v ref - 65 mv 1, 2 ac input low voltage v il(ac) v ss 5v ref - 90 mv 1, 2, 3 reference voltage for cmd/addr inputs v reffca(dc) 0.49 v dd 0.51 v dd v4 notes: 1. for input except reset_n. v ref = v refca(dc) . 2. v ref = v refca(dc) . 3. input signal must meet v il /v ih(ac) to meet t is timings and v il /v ih(dc) to meet t ih timings. 4. the ac peak noise on v ref may not allow v ref to deviate from v refca(dc) by more than 1% v dd (for reference: approximately 12mv). 5. refer to overshoot and undershoot specifications. table 86: command and address input levels: ddr4-2933 and ddr4-3200 parameter symbol min max unit note ac input high voltage v ih(ac) v ref + 90 v dd 5 mv 1, 2, 3 dc input high voltage v ih(dc) v ref + 65 v dd mv 1, 2 dc input low voltage v il(dc) v ss v ref - 65 mv 1, 2 ac input low voltage v il(ac) v ss 5v ref - 90 mv 1, 2, 3 reference voltage for cmd/addr inputs v reffca(dc) 0.49 v dd 0.51 v dd v4 notes: 1. for input except reset_n. v ref = v refca(dc) . 2. v ref = v refca(dc) . 3. input signal must meet v il /v ih(ac) to meet t is timings and v il /v ih(dc) to meet t ih timings. 4. the ac peak noise on v ref may not allow v ref to deviate from v refca(dc) by more than 1% v dd (for reference: approximately 12mv). 5. refer to overshoot and undershoot specifications. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc single-ended input measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 268 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 87: single-ended input slew rates parameter symbol min max unit note single-ended input slew rate C ca sr ca 1.0 7.0 v/ns 1, 2, 3, 4 notes: 1. for input except reset_n. 2. v ref = v refca(dc) . 3. t is/ t ih timings assume sr ca = 1v/ns. 4. measured between v ih(ac) and v il(ac) for falling edges and between v il(ac) and v ih(ac) for rising edges figure 210: single-ended input slew rate definition tr se tf se v ih(dc) v ih(ac) v il(ac) v il(dc) v refca command, control, and address setup, hold, and derating the total t is (setup time) and t ih (hold time) required is calculated to account for slew rate variation by adding the data sheet t is (base) values, the v il(ac) /v ih(ac) points, and t ih (base) values, the v il(dc) /v ih(dc) points; to the t is and t ih derating values, re- spectively. the base values are derived with single-end signals at 1v/ns and differential clock at 2 v/ns. example: t is (total setup time) = t is (base) + t is. for a valid transition, the input signal has to remain above/below v ih(ac) /v il(ac) for the time defined by t vac. although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached v ih(ac) /v il(ac) at the time of the rising clock transi- tion), a valid input signal is still required to complete the transition and to reach v ih(ac) /v il(ac) . for slew rates that fall between the values listed in derating tables, the derating values may be obtained by linear interpolation. setup ( t is) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc)max and the first crossing of v ih(ac)min that does not ring back be- low v ih(dc)min . setup ( t is) nominal slew rate for a falling signal is defined as the slew 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc single-ended input measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 269 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
rate between the last crossing of v ih(dc)min and the first crossing of v il(ac)max that does not ring back above v il(dc)max . hold ( t ih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc)max and the first crossing of v ih(ac)min that does not ring back be- low v ih(dc)min . hold ( t ih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc)min and the first crossing of v il(ac)min that does not ring back above v il(dc)max . table 88: command and address setup and hold values referenced C ac/dc-based symbol 1600 1866 2133 2400 2666 2933 3200 unit reference t is(base, ac100) 115 100 80 62 C C C ps v ih(ac) /v il(ac) t ih(base, dc75) 140 125 105 87 C C C ps v ih(dc) /v il(dc) t is(base, ac90) CCCC554840psv ih(ac) /v il(ac) t ih(base, dc65) CCCC807365psv ih(dc) /v il(dc) t is/ t ih(vref) 215 200 180 162 145 138 130 ps v ih(dc) /v il(dc) table 89: derating values for t is/ t ih C ac100dc75-based t is with ac100 threshold, 7.0 76 54 76 55 77 56 79 58 82 60 86 64 94 73 111 89 6.0 73 53 74 53 75 54 77 56 79 58 83 63 92 71 108 88 5.0 70 50 71 51 72 52 74 54 76 56 80 60 88 68 105 85 4.0 65 46 66 47 67 48 69 50 71 52 75 56 83 65 100 81 3.0 57 40 57 41 58 42 60 44 63 46 67 50 75 58 92 75 2.0 40 28 41 28 42 29 44 31 46 33 50 38 58 46 75 63 1.5 23 15 24 16 25 17 27 19 29 21 33 25 42 33 58 50 1.0 C10 C10 C9 C9 C8 C8 C6 C6 C4 C4 00 8 8 25 25 0.9 C17 C14 C16 C14 C15 C13 C13 C10 C11 C8 C7 C4 1 4 18 21 0.8 C26 C19 C25 C19 C24 C18 C22 C16 C20 C14 C16 C9 C7 C1 9 16 0.7 C37 C26 C36 C25 C35 C24 C33 C22 C31 C20 C27 C16 C18 C8 C2 9 0.6 C52 C35 C51 C34 C50 C33 C48 C31 C46 C29 C42 C25 C33 C17 C17 0 0.5 C73 C48 C72 C47 C71 C46 C69 C44 C67 C42 C63 C38 C54 C29 C38 C13 0.4 C104 C66 C103 C66 C102 C65 C100 C63 C98 C60 C94 C56 C85 C48 C69 C31 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc single-ended input measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 270 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 90: derating values for t is/ t ih C ac90/dc65-based t is with ac90 threshold, 7.0 68 47 69 47 70 48 72 50 73 52 77 56 85 63 100 78 6.0 66 45 67 46 68 47 69 49 71 50 75 54 83 62 98 77 5.0 63 43 64 44 65 45 66 46 68 48 72 52 80 60 95 75 4.0 59 40 59 40 60 41 62 43 64 45 68 49 75 56 90 71 3.0 51 34 52 35 53 36 54 38 56 40 60 43 68 51 83 66 2.0 36 24 37 24 38 25 39 27 41 29 45 33 53 40 68 55 1.5 21 13 22 13 23 14 24 16 26 18 30 22 38 29 53 44 1.0 C9 C9 C8 C8 C8 C8 C6 C6 C4 C4 00 8 8 23 23 0.9 C15 C13 C15 C12 C14 C11 C12 C9 C10 C7 C6 C4 1 4 16 19 0.8 C23 C17 C23 C17 C22 C16 C20 C14 C18 C12 C14 C8 C7 C1 8 14 0.7 C34 C23 C33 C22 C32 C21 C30 C20 C28 C18 C25 C14 C17 C6 C2 9 0.6 C47 C31 C47 C30 C46 C29 C44 C27 C42 C25 C38 C22 C31 C14 C16 1 0.5 C67 C42 C66 C41 C65 C40 C63 C38 C61 C36 C58 C33 C50 C25 C35 C10 0.4 C95 C58 C95 C57 C94 C56 C92 C54 C90 C53 C86 C49 C79 C41 C64 C26 data receiver input requirements the following parameters apply to the data receiver rx mask operation detailed in the write timing section, data strobe-to-data relationship. the rising edge slew rates are defined by srr1 and srr2. the slew rate measurement points for a rising edge are shown in the figure below. a low-to-high transition time, tr1, is measured from 0.5 v divw,max below v centdq,midpoint to the last transition through 0.5 v divw,max above v centdq,midpoint ; tr2 is measured from the last transition through 0.5 v divw,max above v centdq,midpoint to the first transition through the 0.5 v ihl(ac)min above v centdq,midpoint . the falling edge slew rates are defined by srf1 and srf2. the slew rate measurement points for a falling edge are shown in the figure below. a high-to-low transition time, tf1, is measured from 0.5 v divw,max above v centdq,midpoint to the last transition through 0.5 v divw,max below v centdq,midpoint ; tf2 is measured from the last transition through 0.5 v divw,max below v centdq,midpoint to the first transition through the 0.5 v ihl(ac)min below v centdq,midpoint . 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc single-ended input measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 271 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 211: dq slew rate definitions v ihl(ac)min 0.5 v ihl(ac)min 0.5 v ihl(ac)min v ihl(ac)min 0.5 v ihl(ac)min 0.5 v ihl(ac)min 0.5 v divw,max 0.5 v divw,max v centdq,midpoint v divw,max 0.5 v divw,max 0.5 v divw,max v divw,max t r1 t r2 v centdq,midpoint t f1 t f2 rx mask rx mask notes: 1. rising edge slew rate equation srr1 = v divw,max /( t r1). 2. rising edge slew rate equation srr2 = (v ihl(ac)min - v divw,max )/(2 t r2). 3. falling edge slew rate equation srf1 = v divw,max /( t f1). 4. falling edge slew rate equation srf2 = (v ihl(ac)min - v divw,max )/(2 t f2). table 91: dq input receiver specifications note 1 applies to the entire table parameter symbol ddr4-1600, 1866, 2133 ddr4-2400 ddr4-2666 ddr4-2933 ddr4-3200 unit not es min max min max min max min max min max v in rx mask input peak-to-peak v divw C 136 C 130 C 120 C 115 C 110 mv 2, 3 dq rx input tim- ing window tdivw C 0.2 C 0.2 C 0.22 C 0.23 C 0.23 ui 2, 3 dq ac input swing peak-to- peak v ihl(ac) 186 C 160 C 150 C 145 C 140 C mv 4, 5 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc single-ended input measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 272 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 91: dq input receiver specifications (continued) note 1 applies to the entire table parameter symbol ddr4-1600, 1866, 2133 ddr4-2400 ddr4-2666 ddr4-2933 ddr4-3200 unit not es min max min max min max min max min max dq input pulse width tdipw 0.58 C 0.58 C 0.58 C 0.58 C 0.58 C ui 6 dqs-to-dq rx mask offset t dqs2d q C0.17 0.17 C0.17 0.17 C0.19 0.19 C0.22 0.22 C0.22 0.22 ui 7 dq-to-dq rx mask offset t dq2dq C 0.1 C 0.1 C 0.105 C 0.115 C 0.125 ui 8 input slew rate over v divw if t ck 0.925ns srr1, srf1 1 9 1 9 1 9 1 9 1 9 v/ns 9 input slew rate over v divw if 0.935ns > t ck 0.625ns srr1, srf1 C C 1.25 9 1.25 9 1.25 9 1.25 9 v/ns 9 rising input slew rate over 1/2 v ihl(ac) srr2 0.2 srr1 9 0.2 srr1 9 0.2 srr1 9 0.2 srr1 9 0.2 srr1 9 v/ns 10 falling input slew rate over 1/2 v ihl(ac) srf2 0.2 srf1 9 0.2 srf1 9 0.2 srf1 9 0.2 srf1 9 0.2 srf1 9 v/ns 10 notes: 1. all rx mask specifications must be satisfied for each ui. for example, if the minimum in- put pulse width is violated when satisfying tdivw (min), v divw,max , and minimum slew rate limits, then either tdivw (min) or minimum slew rates would have to be increased to the point where the minimum input pulse width would no longer be violated. 2. data rx mask voltage and timing total input valid window where v divw is centered around v centdq,midpoint after v refdq training is completed. the data rx mask is applied per bit and should include voltage and temperature drift terms. the input buffer design specification is to achieve at least a ber =1 e- 16 when the rx mask is not violated. 3. defined over the dq internal v ref range 1. 4. overshoot and undershoot specifications apply. 5. dq input pulse signal swing into the receiver must meet or exceed v ihl(ac)min . v ihl(ac)min is to be achieved on an ui basis when a rising and falling edge occur in the same ui (a valid tdipw). 6. dq minimum input pulse width defined at the v centdq,midpoint . 7. dqs-to-dq rx mask offset is skew between dqs and dq within a nibble (x4) or word (x8, x16 [for x16, the upper and lower bytes are treated as separate x8s]) at the sdram balls over process, voltage, and temperature. 8. dq-to-dq rx mask offset is skew between dqs within a nibble (x4) or word (x8, x16) at the sdram balls for a given component over process, voltage, and temperature. 9. input slew rate over v divw mask centered at v centdq,midpoint . slowest dq slew rate to fastest dq slew rate per transition edge must be within 1.7v/ns of each other. 10. input slew rate between v divw mask edge and v ihl(ac)min points. the following figure shows the rx mask relationship to the input timing specifications relative to system t ds and t dh. the classical definition for t ds/ t dh required a dq rising 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc single-ended input measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 273 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
and falling edges to not violate t ds and t dh relative to the dqs strobe at any time; how- ever, with the rx mask t ds and t dh can shift relative to the dqs strobe provided the input pulse width specification is satisfied and the rx mask is not violated. figure 212: rx mask relative to t ds/ t dh t dh = greater of 0.5 tdivw or 0.5 (tdipw + v divw / t r1) t ds = greater of 0.5 tdivw or 0.5 (tdipw + v divw / t f1) v divw 0.5 v divw t f1 t r1 0.5 v divw tdipw tdivw v centdq,pin mean v il(dc) v ih(dc) dqs_c dqs_t rx mask the following figure and table show an example of the worst case rx mask required if the dqs and dq pins do not have dram controller to dram write dq training. the figure and table show that without dram write dq training, the rx mask would in- crease from 0.2ui to essentially 0.54ui. this would also be the minimum t ds and t dh required as well. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc single-ended input measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 274 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 213: rx mask without write training t ds v divw 0.5 v divw 0.5 v divw t dh 0.5 tdivw + t dqs2dq tdivw + 2 t dqs2dq 0.5 tdivw + t dqs2dq v centdq,midpoint v il(dc) v ih(dc) dqs_c dqs_t rx mask table 92: rx mask and t ds/ t dh without write training ddr4 v ihl(ac) (mv) tdipw (ui) v divw (mv) tdivw (ui) t dqs2dq (ui) t dq2dq (ui) rx mask with write train (ps) t ds + t dh (ps) 1600 186 0.58 136 0.2 0.17 0.1 125 338 1866 186 0.58 136 0.2 0.17 0.1 107.1 289 2133 186 0.58 136 0.2 0.17 0.1 94 253 2400 160 0.58 130 0.2 0.17 0.1 83.3 225 2666 150 0.58 120 0.22 0.19 0.105 82.5 225 2933 145 0.58 115 0.23 0.22 0.115 78.4 228 3200 140 0.58 110 0.23 0.22 0.125 71.8 209 note: 1. v ihl(ac) , v divw , and v ilh(dc) referenced to v centdq,midpoint . connectivity test (ct) mode input levels table 93: ten input levels (cmos) parameter symbol min max unit note ten ac input high voltage v ih(ac)_ten 0.8 v dd v dd v1 ten dc input high voltage v ih(dc)_ten 0.7 v dd v dd v ten dc input low voltage v il(dc)_ten v ss 0.3 v dd v ten ac input low voltage v il(ac)_ten v ss 0.2 v dd v2 ten falling time t f_ten C 1 0 ns 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc single-ended input measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 275 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 93: ten input levels (cmos) (continued) parameter symbol min max unit note ten rising time t r_ten C 1 0 ns notes: 1. overshoot should not exceed the v in values in the absolute maximum ratings table. 2. undershoot should not exceed the v in values in the absolute maximum ratings table. figure 214: ten input slew rate definition t r_ten t f_ten v ih(ac)_tenmin v il(ac)_tenmin v ih(dc)_tenmin v il(dc)_tenmin table 94: ct type-a input levels parameter symbol min max unit note ctipa ac input high voltage v ih(ac) v ref + 200 v dd1 1 v 2, 3 ctipa dc input high voltage v ih(dc) v ref + 150 v dd v 2, 3 ctipa dc input low voltage v il(dc) v ss v ref - 150 v 2, 3 ctipa ac input low voltage v il(ac) v ss1 1 v ref - 200 v 2, 3 ctipa falling time t f_ctipa C 5 ns 2 ctipa rising time t r_ctipa C 5 ns 2 notes: 1. refer to overshoot and undershoot specifications. 2. ct type-a inputs: cs_n, bg[1:0], ba[1:0], a[9:0], a10/ap, a11, a12/bc_n, a13, we_n/a14, cas_n/a15, ras_n/a16, cke, act_n, odt, clk_t, clk_c, par. 3. v refca = 0.5 v dd . figure 215: ct type-a input slew rate definition v ih(ac)_ctipamin v il(ac)_ctipamax v ih(dc)_ctipamin v il(dc)_ctipamax t r_ctipa t f_ctipa v refca 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc single-ended input measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 276 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 95: ct type-b input levels parameter symbol min max unit note ctipb ac input high voltage v ih(ac) v ref + 300 v dd1 1 v 2, 3 ctipb dc input high voltage v ih(dc) v ref + 200 v dd v 2, 3 ctipb dc input low voltage v il(dc) v ss v ref - 200 v 2, 3 ctipb ac input low voltage v il(ac) v ss1 1 v ref - 300 v 2, 3 ctipb falling time t f_ctipb C 5 ns 2 ctipb rising time t r_ctipb C 5 ns 2 notes: 1. refer to overshoot and undershoot specifications. 2. ct type-b inputs: dml_n/dbil_n, dmu_n/dbiu_n and dm_n/dbi_n. 3. v refdq should be 0.5 v dd figure 216: ct type-b input slew rate definition v ih(ac)_ctipbmin v il(ac)_ctipbmax v ih(dc)_ctipbmin v il(dc)_ctipbmax t r_ctipb t f_ctipb v refdq table 96: ct type-c input levels (cmos) parameter symbol min max unit note ctipc ac input high voltage v ih(ac)_ctipc 0.8 v dd v dd 1 v2 ctipc dc input high voltage v ih(dc)_ctipc 0.7 v dd v dd v2 ctipc dc input low voltage v il(dc)_ctipc v ss 0.3 v dd v2 ctipc ac input low voltage v il(ac)_ctipc v ss 1 0.2 v dd v2 ctipc falling time t f_ctipc C 1 0 ns 2 ctipc rising time t r_ctipc C 1 0 ns 2 notes: 1. refer to overshoot and undershoot specifications. 2. ct type-c inputs: alert_n. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc single-ended input measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 277 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 217: ct type-c input slew rate definition t r_ten t f_ten v ih(ac)_tenmin v il(ac)_tenmin v ih(dc)_tenmin v il(dc)_tenmin table 97: ct type-d input levels parameter symbol min max unit note ctipd ac input high voltage v ih(ac)_ctipd 0.8 v dd v dd v4 ctipd dc input high voltage v ih(dc)_ctipd 0.7 v dd v dd v2 ctipd dc input low voltage v il(dc)_ctipd v ss 0.3 v dd v1 ctipd ac input low voltage v il(ac)_ctipd v ss 0.2 v dd v5 rising time t r_reset C 1 s 3 reset pulse width - after power-up t pw_reset_s 1 C s reset pulse width - during power-up t pw_reset_l 200 C s notes: 1. after reset_n is registered low, the reset_n level must be maintained below v il(dc)_re- set during t pw_reset, otherwise, the dram may not be reset. 2. after reset_n is registered high, the reset_n level must be maintained above v ih(dc)_reset , otherwise, operation will be uncertain until it is reset by asserting reset_n signal low. 3. slope reversal (ring-back) during this level transition from low to high should be miti- gated as much as possible. 4. overshoot should not exceed the v in values in the absolute maximum ratings table. 5. undershoot should not exceed the v in values in the absolute maximum ratings table. 6. ct type-d inputs: reset_n; same requirements as in normal mode. figure 218: ct type-d input slew rate definition t r_reset t pw_reset v ih(ac)_resetmin v il(ac)_resetmax v ih(dc)_resetmin v il(dc)_resetmax 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc single-ended input measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 278 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
electrical characteristics C ac and dc differential input measurement levels differential inputs figure 219: differential ac swing and time exceeding ac-level t dvac v ih,diff(ac)min 0.0 v il,diff,max t dvac v ih,diff,min v il,diff(ac)max half cycle t dvac ck_t, ck_c notes: 1. differential signal rising edge from v il,diff,max to v ih,diff(ac)min must be monotonic slope. 2. differential signal falling edge from ih,diff,min to v il,diff(ac)max must be monotonic slope. table 98: differential input swing requirements for ck_t, ck_c parameter symbol ddr4-1600 / 1866 / 2133 / 2400 ddr4-2666 / 2933 / 3200 unit notes min max min max differential input high v ihdiff 0.150 note 3 0.120 note 3 v 1 differential input low v ildiff note 3 C0.150 note 3 -0.120 v 1 differential input high (ac) v ihdiff(ac) 2 (v ih(ac) - v ref ) note 3 2 (v ih(ac) - v ref ) note 3 v 2 differential input low (ac) v ildiff(ac) note 3 2 (v il(ac) - v ref ) note 3 2 (v il(ac) - v ref ) v2 notes: 1. used to define a differential signal slew-rate. 2. for ck_t, ck_c use v ih(ac) and v il(ac) of add/cmd and v refca . 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc differential input meas- urement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 279 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
3. these values are not defined; however, the differential signals (ck_t, ck_c) need to be within the respective limits, v ih(dc)max and v il(dc)min for single-ended signals as well as the limitations for overshoot and undershoot. table 99: minimum time ac time t dvac for ck slew rate (v/ns) t dvac (ps) at |v ih,diff(ac) to v il,diff(ac) | 200mv tbdmv >4.0 120 tbd 4.0 115 tbd 3.0 110 tbd 2.0 105 tbd 1.9 100 tbd 1.6 95 tbd 1.4 90 tbd 1.2 85 tbd 1.0 80 tbd <1.0 80 tbd note: 1. below v il(ac) . single-ended requirements for ck differential signals each individual component of a differential signal (ck_t, ck_c) has to comply with cer- tain requirements for single-ended signals. ck_t and ck_c have to reach approximately v sehmin /v sel,max , which are approximately equal to the ac levels v ih(ac) and v il(ac) for add/cmd signals in every half-cycle. the applicable ac levels for add/cmd might differ per speed-bin, and so on. for example, if a value other than 100mv is used for add/cmd v ih(ac) and v il(ac) signals, then these ac levels also apply for the single- ended signals ck_t and ck_c. while add/cmd signal requirements are with respect to v refca , the single-ended com- ponents of differential signals have a requirement with respect to v dd /2; this is nomi- nally the same. the transition of single-ended signals through the ac levels is used to measure setup time. for single-ended components of differential signals the require- ment to reach v sel,max /v seh,min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc differential input meas- urement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 280 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 220: single-ended requirements for ck v ss or v ssq v dd or v ddq v sel,max v seh,min v seh v sel ck v dd /2 or v ddq /2 table 100: single-ended requirements for ck parameter symbol ddr4-1600 / 1866 / 2133 / 2400 ddr4-2666 / 2933 / 3200 unit notes min max min max single-ended high level for ck_t, ck_c v seh v dd /2 + 0.100 note 3 v dd /2 + 0.90 note 3 v 1, 2 single-ended low level for ck_t, ck_c v sel note 3 v dd /2 - 0.100 note 3 v dd /2 - 0.90 v 1, 2 notes: 1. for ck_t, ck_c use v ih(ac) and v il(ac) of add/cmd and v refca . 2. addr/cmd v ih(ac) and v il(ac) based on v refca . 3. these values are not defined; however, the differential signal (ck_t, ck_c) need to be within the respective limits, v ih(dc)max and v il(dc)min for single-ended signals as well as the limitations for overshoot and undershoot. slew rate definitions for ck differential input signals table 101: ck differential input slew rate definition description measured defined by from to differential input slew rate for rising edge v il,diff,max v ih,diff,min |v ih,diff,min - v il,diff,max ??tr diff differential input slew rate for falling edge v ih,diff,min v il,diff,max |v ih,diff,min - v il,diff,max ??tf diff note: 1. the differential signal ck_t, ck_c must be monotonic between these thresholds. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc differential input meas- urement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 281 micron technology, inc. reserves the right to change products or specifications without notice. 2015 micron technology, inc. all rights reserved.
figure 221: differential input slew rate definition for ck_t, ck_c tf diff v ih,diff,min v il,diff,max 0 ck differential input voltage tr diff ck differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signal ck_t, ck_c must meet the requirements shown below. the differential input cross point voltage v ix(ck) is measured from the actual cross point of true and complement signals to the midlevel between v dd and v ss . figure 222: v ix(ck) definition v ix(ck) v seh v sel v ix(ck) v ix(ck) ck_t v ss v dd /2 ck_c v dd 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc differential input meas- urement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 282 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 102: cross point voltage for ck differential input signals at ddr4-1600 through ddr4-2400 parameter sym input level ddr4-1600, 1866, 2133 ddr4-2400 min max min max differential input cross point volt- age relative to v dd /2 for ck_t, ck_c v ix(ck) v seh > v dd /2 + 145mv n/a 120mv n/a 120mv v dd /2 + 100mv v seh v dd /2 + 145mv n/a (v seh - v dd /2) - 25mv n/a (v seh - v dd /2) - 25mv v dd /2 - 145mv v sel v dd /2 - 100mv C(v dd /2-v sel ) +25mv n/a C(v dd /2-v sel ) + 25mv n/a v sel v dd /2 - 145mv C120mv n/a C120mv n/a table 103: cross point voltage for ck differential input signals at ddr4-2666 through ddr4-3200 parameter sym input level ddr4-2666 ddr4-2933, 3200 min max min max differential input cross point volt- age relative to v dd /2 for ck_t, ck_c v ix(ck) v seh > v dd /2 + 135mv n/a 110mv n/a 110mv v dd /2 + 90mv v seh v dd /2 + 135mv n/a (v seh - v dd /2) - 30mv n/a (v seh - v dd /2) - 30mv v dd /2 - 135mv v sel v dd /2 - 90mv C(v dd /2-v sel ) + 30mv n/a C(v dd /2-v sel ) + 30mv n/a v sel v dd /2 - 135mv C110mv n/a C110mv n/a dqs differential input signal definition and swing requirements figure 223: differential input signal definition for dqs_t, dqs_c half cycle v il,diff,peak 0.0v dqs_t, dqs_c: differential input voltage v ih,diff,peak half cycle 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc differential input meas- urement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 283 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 104: ddr4-1600 through ddr4-2400 differential input swing requirements for dqs_t, dqs_c parameter symbol ddr4-1600, 1866, 2133 ddr4-2400 unit notes min max min max peak differential input high voltage v ih,diff,peak 186 v ddq 160 v ddq mv 1 , 2 peak differential input low voltage v il,diff,peak v ssq C186 v ssq C160 mv 1 , 2 notes: 1. minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits. 2. minimum value point is used to determine differential signal slew-rate. table 105: ddr4-2633 through ddr4-3200 differential input swing requirements for dqs_t, dqs_c parameter symbol ddr4-2666 ddr4-2933 ddr4-3200 unit notes min max min max min max peak differential input high volt- age v ih,diff,peak 150 v ddq 145 v ddq 140 v ddq mv 1 , 2 peak differential input low volt- age v il,diff,peak v ssq C150 v ssq C145 v ssq C140 mv 1 , 2 notes: 1. minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits. 2. minimum value point is used to determine differential signal slew-rate. the peak voltage of the dqs signals are calculated using the following equations: v ih,dif,peak voltage = max(f t ) v il,dif,peak voltage = min(f t ) (f t ) = dqs_t, dqs_c. the max(f(t)) or min(f(t)) used to determine the midpoint from which to reference the 35% window of the exempt non-monotonic signaling shall be the smallest peak volt- age observed in all uis. figure 224: dqs_t, dqs_c input peak voltage calculation and range of exempt non-monotonic sig- naling dqs_t min(f t ) max(f t ) dqs_c dqs_t, dqs_c: single-ended input voltages +50% C50% +35% C35% 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc differential input meas- urement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 284 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
dqs differential input cross point voltage to achieve tight rxmask input requirements as well as output skew parameters with re- spect to strobe, the cross point voltage of differential input signals (dqs_t, dqs_c) must meet v ix_dqs,ratio in the table below. the differential input cross point voltage v ix_dqs (v ix_dqs_fr and v ix_dqs_rf ) is measured from the actual cross point of dqs_t, dqs_c relative to the v dqs,mid of the dqs_t and dqs_c signals. v dqs,mid is the midpoint of the minimum levels achieved by the transitioning dqs_t and dqs_c signals, and noted by v dqs_trans . v dqs_trans is the difference between the low- est horizontal tangent above v dqs,mid of the transitioning dqs signals and the highest horizontal tangent below v dqs,mid of the transitioning dqs signals. a non-monotonic transitioning signals ledge is exempt or not used in determination of a horizontal tan- gent provided the said ledge occurs within 35% of the midpoint of either v ih.diff.peak voltage (dqs_t rising) or v il.diff.peak voltage (dqs_c rising), as shown in the figure be- low. a secondary horizontal tangent resulting from a ring-back transition is also exempt in determination of a horizontal tangent. that is, a falling transitions horizontal tangent is derived from its negative slope to zero slope transition (point a in the figure below), and a ring-backs horizontal tangent is derived from its positive slope to zero slope transi- tion (point b in the figure below) and is not a valid horizontal tangent; a rising transi- tions horizontal tangent is derived from its positive slope to zero slope transition (point c in the figure below), and a ring-backs horizontal tangent derived from its negative slope to zero slope transition (point d in the figure below) and is not a valid horizontal tangent. figure 225: v ixdqs definition dqs_t, dqs_c: single-ended input voltages dqs_t v ix_dqs,fr v ix_dqs,fr v ix_dqs,rf v ix_dqs,rf v dqs_trans v dqs_trans /2 lowest horizontal tanget above v dqs,mid of the transitioning signals highest horizontal tanget below v dqs,mid of the transitioning signals v ssq v dqs,mid dqs_c a b c d table 106: cross point voltage for differential input signals dqs parameter symbol ddr4-1600, 1866, 2133, 2400, 2666, 2933, 3200 unit notes min max dqs_t and dqs_c crossing relative to the midpoint of the dqs_t and dqs_c signal swings v ix_dqs,ratio C 25 % 1, 2 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc differential input meas- urement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 285 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 106: cross point voltage for differential input signals dqs (continued) parameter symbol ddr4-1600, 1866, 2133, 2400, 2666, 2933, 3200 unit notes min max v dqs,mid to v cent(midpoint) offset v dqs,mid_to_vcent C note 3 mv 2 notes: 1. v ix_dqs,ratio is dqs v ix crossing (v ix_dqs,fr or v ix_dqs,rf ) divided by v dqs_trans . v dqs_trans is the difference between the lowest horizontal tangent above v dqs,mid d of the transition- ing dqs signals and the highest horizontal tangent below v dqs,mid of the transitioning dqs signals. 2. v dqs,mid will be similar to the v refdq internal setting value (v cent(midpoint) offset) ob- tained during v ref training if the dqs and dqs drivers and paths are matched. 3. the maximum limit shall not exceed the smaller of v ih,diff,dqs minimum limit or 50mv. slew rate definitions for dqs differential input signals table 107: dqs differential input slew rate definition description measured defined by from to differential input slew rate for rising edge v il,diff,dqs v ih,diff,dqs |v ih,diff,dqs - v il,diff,dqs ??tr diff differential input slew rate for falling edge v ih,diff,dqs v il,diff,dqs |v ihdiffdqs - v il,diff,dqs ??tf diff note: 1. the differential signal dqs_t, dqs_c must be monotonic between these thresholds. figure 226: differential input slew rate and input level definition for dqs_t, dqs_c tf diff tr diff v il,diff,peak 0.0v dqs_t, dqs_c: differential input voltage v ih,diff,peak v ih,diff,dqs v il,diff,dqs table 108: ddr4-1600 through ddr4-2400 differential input slew rate and input levels for dqs_t, dqs_c parameter symbol ddr4-1600, 1866, 2133 ddr4-2400 unit notes min max min max peak differential input high voltage v ih,diff,peak 186 v ddq 160 v ddq mv 1 differential input high voltage v ih,diff,dqs 136 C 130 C mv 2, 3 differential input low voltage v il,diff,dqs C C136 C C130 mv 2, 3 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc differential input meas- urement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 286 micron technology, inc. reserves the right to change products or specifications without notice. 2015 micron technology, inc. all rights reserved.
table 108: ddr4-1600 through ddr4-2400 differential input slew rate and input levels for dqs_t, dqs_c (continued) parameter symbol ddr4-1600, 1866, 2133 ddr4-2400 unit notes min max min max peak differential input low voltage v il,diff,peak v ssq C186 v ssq C160 mv 1 dqs differential input slew rate sridiff 3.0 18 3.0 18 v/ns 4, 5 notes: 1. minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits. 2. differential signal rising edge from v il,diff,dqs to v ih,diff,dqs must be monotonic slope. 3. differential signal falling edge from v ih,diff,dqs to v il,diff,dqs must be monotonic slope. 4. differential input slew rate for rising edge from v il,diff,dqs to v ih,diff,dqs is defined by | v il,diff,min - v ih,diff,max ??tr diff . 5. differential input slew rate for falling edge from v ih,diff,dqs to v il,diff,dqs is defined by | v il,diff,min - v ih,diff,max ??tf diff . table 109: ddr4-2666 through ddr4-3200 differential input slew rate and input levels for dqs_t, dqs_c parameter symbol ddr4-2666 ddr4-2933 ddr4-3200 unit notes min max min max min max peak differential input high voltage v ih,diff,peak 150 v ddq 145 v ddq 140 v ddq mv 1 differential input high voltage v ih,diff,dqs 120 C 115 C 110 C mv 2, 3 differential input low voltage v il,diff,dqs C C120 C C115 C C110 mv 2, 3 peak differential input low voltage v il,diff,peak v ssq C150 v ssq C145 v ssq C140 mv 1 dqs differential input slew rate sridiff 3.0 18 3.0 18 3.0 18 v/ns 4, 5 notes: 1. minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits. 2. differential signal rising edge from v il,diff,dqs to v ih,diff,dqs must be monotonic slope. 3. differential signal falling edge from v ih,diff,dqs to v il,diff,dqs must be monotonic slope. 4. differential input slew rate for rising edge from v il,diff,dqs to v ih,diff,dqs is defined by | v il,diff,min - v ih,diff,max ??tr diff . 5. differential input slew rate for falling edge from v ih,diff,dqs to v il,diff,dqs is defined by | v il,diff,min - v ih,diff,max ??tf diff . 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc differential input meas- urement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 287 micron technology, inc. reserves the right to change products or specifications without notice. 2015 micron technology, inc. all rights reserved.
electrical characteristics C overshoot and undershoot specifications address, command, and control overshoot and undershoot specifications table 110: addr, cmd, cntl overshoot and undershoot/specifications description ddr4- 1600 ddr4- 1866 ddr4- 2133 ddr4- 2400 ddr4- 2666 ddr4- 2933 ddr4- 3200 unit address and control pins (a[17:0], bg[1:0], ba[1:0], cs_n, ras_n, cas_n, we_n, cke, odt, c2-0) area a: maximum peak amplitude above v dd absolute max 0.06 0.06 0.06 0.06 0.06 0.06 0.06 v area b: amplitude allowed between v dd and v dd absolute max 0.24 0.24 0.24 0.24 0.24 0.24 0.24 v area c: maximum peak amplitude allowed for undershoot below v ss 0.30 0.30 0.30 0.30 0.30 0.30 0.30 v area a maximum overshoot area per 1 t ck 0.0083 0.0071 0.0062 0.0055 0.0055 0.0055 0.0055 v/ns area b maximum overshoot area per 1 t ck 0.2550 0.2185 0.1914 0.1699 0.1699 0.1699 0.1699 v/ns area c maximum undershoot area per 1 t ck 0.2644 0.2265 0.1984 0.1762 0.1762 0.1762 0.1762 v/ns figure 227: addr, cmd, cntl overshoot and undershoot definition v dd absolute max absolute max overshoot overshoot area above v dd absolute max overshoot area below v dd absolute max and above v dd max undershoot area below v ss 1 t ck volts (v) v dd v ss a b c 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C overshoot and undershoot specifi- cations 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 288 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
clock overshoot and undershoot specifications table 111: ck overshoot and undershoot/ specifications description ddr4- 1600 ddr4- 1866 ddr4- 2133 ddr4- 2400 ddr4- 2666 ddr4- 2933 ddr4- 3200 unit clk_t, clk_n area a: maximum peak amplitude above v dd absolute max 0.06 0.06 0.06 0.06 0.06 0.06 0.06 v area b: amplitude allowed between v dd and v dd absolute max 0.24 0.24 0.24 0.24 0.24 0.24 0.24 v area c: maximum peak amplitude allowed for undershoot below v ss 0.30 0.30 0.30 0.30 0.30 0.30 0.30 v area a maximum overshoot area per 1ui 0.0038 0.0032 0.0028 0.0025 0.0025 0.0025 0.0025 v/ns area b maximum overshoot area per 1ui 0.1125 0.0964 0.0844 0.0750 0.0750 0.0750 0.0750 v/ns area c maximum undershoot area per 1ui 0.1144 0.0980 0.0858 0.0762 0.0762 0.0762 0.0762 v/ns figure 228: ck overshoot and undershoot definition v dd absolute max absolute max overshoot overshoot area above v dd absolute max overshoot area below v dd absolute max and above v dd max undershoot area below v ss 1ui volts (v) v dd v ss a b c 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C overshoot and undershoot specifi- cations 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 289 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
data, strobe, and mask overshoot and undershoot specifications table 112: data, strobe, and mask overshoot and undershoot/ specifications description ddr4- 1600 ddr4- 1866 ddr4- 2133 ddr4- 2400 ddr4- 2666 ddr4- 2933 ddr4- 3200 unit dqs_t, dqs_n, dqsl_t, dqsl_n, dqsu_t, dqsu_n, dq[0:15], dm/dbi, udm/udbi, ldm/ldbi, area a: maximum peak amplitude above v ddq absolute max 0.16 0.16 0.16 0.16 0.16 0.16 0.16 v area b: amplitude allowed between v ddq and v ddq absolute max 0.24 0.24 0.24 0.24 0.24 0.24 0.24 v area c: maximum peak amplitude allowed for undershoot below v ssq 0.30 0.30 0.30 0.30 0.30 0.30 0.30 v area d: maximum peak amplitude below v ssq absolute min 0.10 0.10 0.10 0.10 0.10 0.10 0.10 v area a maximum overshoot area per 1ui 0.0150 0.0129 0.0113 0.0100 0.0129 0.0113 0.0100 v/ns area b maximum overshoot area per 1ui 0.1050 0.0900 0.0788 0.0700 0.0900 0.0788 0.0700 v/ns area c maximum undershoot area per 1ui 0.1050 0.0900 0.0788 0.0700 0.0900 0.0788 0.0700 v/ns area d maximum undershoot area per 1ui 0.0150 0.0129 0.0113 0.0100 0.0129 0.0113 0.0100 v/ns figure 229: data, strobe, and mask overshoot and undershoot definition v ddq absolute max v ssq absolute min a b c absolute max overshoot absolute max undershoot overshoot area above v ddq absolute max undershoot area below v ssq absolute min overshoot area below v ddq absolute max and above v ddq max undershoot area below v ssq min and above v ssq absolute min 1ui volts (v) v ddq v ssq d electrical characteristics C ac and dc output measurement levels single-ended outputs table 113: single-ended output levels parameter symbol ddr4-1600 to ddr4-3200 unit dc output high measurement level (for iv curve linearity) v oh(dc) 1.1 v ddq v dc output mid measurement level (for iv curve linearity) v om(dc) 0.8 v ddq v dc output low measurement level (for iv curve linearity) v ol(dc) 0.5 v ddq v ac output high measurement level (for output slew rate) v oh(ac) (0.7 + 0.15) v ddq v 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc output measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 290 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 113: single-ended output levels (continued) parameter symbol ddr4-1600 to ddr4-3200 unit ac output low measurement level (for output slew rate) v ol(ac) (0.7 - 0.15) v ddq v note: 1. the swing of 0.15 v ddq is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of rzq/7 and an effective test load of 50 to v tt = v ddq . using the same reference load used for timing measurements, output slew rate for fall- ing and rising edges is defined and measured between v ol(ac) and v oh(ac) for single- ended signals. table 114: single-ended output slew rate definition description measured defined by from to single-ended output slew rate for rising edge v ol(ac) v oh(ac) [v oh(ac) - v ol(ac) ??tr se single-ended output slew rate for falling edge v oh(ac) v ol(ac) [v oh(ac) - v ol(ac) ??tf se figure 230: single-ended output slew rate definition tr se tf se v oh(ac) v ol(ac) single-ended output voltage (dq) 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc output measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 291 micron technology, inc. reserves the right to change products or specifications without notice. 2015 micron technology, inc. all rights reserved.
table 115: single-ended output slew rate for r on = r zq /7 parameter symbol ddr4-1600/ 1866 / 2133 / 2400 ddr4-2666 ddr4-2933 / 3200 unit min max min max min max single-ended output slew rate srq se 4 9 4949 v/ns notes: 1. sr = slew rate; q = query output; se = single-ended signals 2. in two cases a maximum slew rate of 12v/ns applies for a single dq signal within a byte lane: ? case 1 is defined for a single dq signal within a byte lane that is switching into a cer- tain direction (either from high-to-low or low-to-high) while all remaining dq sig- nals in the same byte lane are static (they stay at either high or low). ? case 2 is defined for a single dq signal within a byte lane that is switching into a cer- tain direction (either from high-to-low or low-to-high) while all remaining dq sig- nals in the same byte lane are switching into the opposite direction (from low-to- high or high-to-low, respectively). for the remaining dq signal switching into the opposite direction, the standard maximum limit of 9 v/ns applies. differential outputs table 116: differential output levels parameter symbol ddr4-1600 to ddr4-3200 unit ac differential output high measurement level (for output slew rate) v oh,diff(ac) 0.3 v ddq v ac differential output low measurement level (for output slew rate) v ol,diff(ac) C0.3 v ddq v note: 1. the swing of 0.3 v ddq is based on approximately 50% of the static single-ended out- put peak-to-peak swing with a driver impedance of rzq/7 and an effective test load of 50 to v tt = v ddq at each differential output. using the same reference load used for timing measurements, output slew rate for fall- ing and rising edges is defined and measured between v ol,diff(ac) and v oh,diff(ac) for dif- ferential signals. table 117: differential output slew rate definition description measured defined by from to differential output slew rate for rising edge v ol,diff(ac) v oh,diff(ac) [v oh,diff(ac) - v ol,diff(ac) ??tr diff differential output slew rate for falling edge v oh,diff(ac) v ol,diff(ac) [v oh,diff(ac) - v ol,diff(ac) ??tf diff 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc output measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 292 micron technology, inc. reserves the right to change products or specifications without notice. 2015 micron technology, inc. all rights reserved.
figure 231: differential output slew rate definition tr diff tf diff v oh,diff(ac) v ol,diff(ac) differential input voltage (dqs_t, dqs_c) table 118: differential output slew rate for r on = r zq /7 parameter symbol ddr4-1600 / 1866 / 2133 / 2400 ddr4-2666 ddr4-2933 / 3200 unit min max min max min max differential output slew rate srq diff 8 18 8 18 8 18 v/ns note: 1. sr = slew rate; q = query output; diff = differential signals. reference load for ac timing and output slew rate the effective reference load of 50 to v tt = v ddq and driver impedance of r zq /7 for each output was used in defining the relevant ac timing parameters of the device as well as output slew rate measurements. ron nominal of dq, dqs_t and dqs_c drivers uses 34 ohms to specify the relevant ac timing paraeter values of the device. the maximum dc high level of output signal = 1.0 * vddq, the minimum dc low level of output signal = { 34 /( 34 + 50 ) } *vddq = 0.4* vddq the nominal reference level of an output signal can be approximated by the following: the center of maximum dc high and minimum dc low = { ( 1 + 0.4 ) / 2 } * vddq = 0.7 * vddq. the actual reference level of output signal might vary with driver ron and ref- erence load tolerances. thus, the actual reference level or midpoint of an output signal is at the widest part of the output signals eye. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc output measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 293 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 232: reference load for ac timing and output slew rate timing reference point dq, dqs_t, dqs_c, dm, tdqs_t, tdqs_c ck_t, ck_c dut v tt = v ddq v ddq v ssq r tt = 50 connectivity test mode output levels table 119: connectivity test mode output levels parameter symbol ddr4-1600 to ddr4-3200 unit dc output high measurement level (for iv curve linearity) v oh(dc) 1.1 v ddq v dc output mid measurement level (for iv curve linearity) v om(dc) 0.8 v ddq v dc output low measurement level (for iv curve linearity) v ol(dc) 0.5 v ddq v dc output below measurement level (for iv curve linearity) v ob(dc) 0.2 v ddq v ac output high measurement level (for output slew rate) v oh(ac) v tt + (0.1 v ddq )v ac output low measurement level (for output slew rate) v ol(ac) v tt - (0.1 v ddq )v note: 1. driver impedance of r zq /7 and an effective test load of 50 to v tt = v ddq . figure 233: connectivity test mode reference test load timing reference point dqsl_t, dqsl_c, dqsu_t, dqsu_c, dq, dqs_t, dqs_c, dm, dml, dmh, tdqs_t, tdqs_c ct_inputs dut 0.5 v ddq v ddq v ssq r tt = 50 8gb: x4, x8, x16 ddr4 sdram electrical characteristics ? ac and dc output measurement levels 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 294 micron technology, inc. reserves the right to change products or specifications without notice. 2015 micron technology, inc. all rights reserved.
figure 234: connectivity test mode output slew rate definition tf output_ct v oh(ac) v ol(ac) v tt 0.5 x vdd tr output_ct table 120: connectivity test mode output slew rate parameter symbol ddr4-1600 / 1866 / 2133 / 2400 ddr4-2666 ddr4-2933 / 3200 unit min max min max min max output signal falling time tf_output_ct C 10 C 10 C 10 ns/v output signal rising time tr_output_ct C 10 C 10 C 10 ns/v electrical characteristics C ac and dc output driver characteristics connectivity test mode output driver electrical characteristics the ddr4 driver supports special values during connectivity test mode. these r on val- ues are referenced in this section. a functional representation of the output buffer is shown in the figure below. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc output driver charac- teristics 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 295 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 235: output driver during connectivity test mode v ddq v ssq chip in drive mode dq v out i out r onpu_ct r onpd_ct output driver to other circuitry like rcv, ... i pu_ct i pd_ct the output driver impedance, r on , is determined by the value of the external reference resistor r zq as follows: r on = r zq /7. this targets 34 with nominal r zq ????? ; however, connectivity test mode uses uncalibrated drivers and only a maximum target is defined. mismatch between pull up and pull down is undefined. the individual pull-up and pull-down resistors (r onpu_ct and r onpd_ct ) are defined as follows: r onpu_ct when r onpd_ct is off: 5 2138b7 9 ''4 9 287 , 287 r onpd_ct when r onpu_ct is off: 5 213'b7 9 287 , 287 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc output driver charac- teristics 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 296 micron technology, inc. reserves the right to change products or specifications without notice. 2015 micron technology, inc. all rights reserved.
table 121: output driver electrical characteristics during connectivity test mode assumes r zq ?????; zq calibration not required r on,nom_ct resistor v out min nom max unit ?? r onpd_ct v ob(dc) = 0.2 v ddq n/a n/a 1.9 r zq /7 v ol(dc) = 0.5 v ddq n/a n/a 2.0 r zq /7 v om(dc) = 0.8 v ddq n/a n/a 2.2 r zq /7 v oh(dc) = 1.1 v ddq n/a n/a 2.5 r zq /7 r onpu_ct v ob(dc) = 0.2 v ddq n/a n/a 1.9 r zq /7 v ol(dc) = 0.5 v ddq n/a n/a 2.0 r zq /7 v om(dc) = 0.8 v ddq n/a n/a 2.2 r zq /7 v oh(dc) = 1.1 v ddq n/a n/a 2.5 r zq /7 output driver electrical characteristics the ddr4 driver supports two r on values. these r on values are referred to as strong mode (low r on ???? ) and weak mode (high r on ???? ). a functional representation of the output buffer is shown in the figure below. figure 236: output driver: definition of voltages and currents v ddq v ssq chip in drive mode dq v out i out r onpu r onpd output driver to other circuitry like rcv, ... i pu i pd the output driver impedance, r on , is determined by the value of the external reference resistor r zq as follows: r on(34) = r zq /7, or r on(48) = r zq /5. this provides either a nomi- nal 34.3 10% or 48 10% with nominal r zq ?????? the individual pull-up and pull-down resistors (r onpu and r onpd ) are defined as fol- lows: r onpu when r onpd is off: 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc output driver charac- teristics 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 297 micron technology, inc. reserves the right to change products or specifications without notice. 2015 micron technology, inc. all rights reserved.
r onpu = v ddq - v out i out r onpd when r onpu is off: r onpd = v out i out table 122: strong mode (34 ) output driver electrical characteristics assumes r zq ?????; entire operating temperature range after proper zq calibration r on,nom resistor v out min nom max unit notes ?? r on34pd v ol(dc) = 0.5 v ddq 0.8 1.0 1.1 r zq /7 1, 2, 3 v om(dc) = 0.8 v ddq 0.9 1.0 1.1 r zq /7 1, 2, 3 v oh(dc) = 1.1 v ddq 0.9 1.0 1.25 r zq /7 1, 2, 3 r on34pu v ol(dc) = 0.5 v ddq 0.9 1.0 1.25 r zq /7 1, 2, 3 v om(dc) = 0.8 v ddq 0.9 1.0 1.1 r zq /7 1, 2, 3 v oh(dc) = 1.1 v ddq 0.8 1.0 1.1 r zq /7 1, 2, 3 mismatch between dq to dq within byte variation pull-up, mm pudd v om(dc) = 0.8 v ddq C10 C 10 % 1, 2, 3, 4, 5 mismatch between dq to dq within byte variation pull-down, mm pddd v om(dc) = 0.8 v ddq C C 10 % 1, 2, 3, 4, 6, 7 mismatch between pull-up and pull- down, mm pupd v om(dc) = 0.8 v ddq C C 10 % 1, 2, 3, 4, 6, 7 notes: 1. the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibra- tion, see following section on voltage and temperature sensitivity. 2. the tolerance limits are specified under the condition that v ddq = v dd and that v ssq = v ss . 3. micron recommends calibrating pull-down and pull-up output driver impedances at 0.8 v ddq . other calibration schemes may be used to achieve the linearity specification shown above; for example, calibration at 0.5 v ddq and 1.1 v ddq . 4. dq-to-dq mismatch within byte variation for a given component including dqs_t and dqs_c (characterized). 5. measurement definition for mismatch between pull-up and pull-down, mm pupd : measure both r onpu and r onpd at 0.8 v ddq separately; r on,nom is the nominal r on val- ue: mm pupd = 100 r onpu - r onpd r on,nom 6. r on variance range ratio to r on nominal value in a given component, including dqs_t and dqs_c: 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc output driver charac- teristics 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 298 micron technology, inc. reserves the right to change products or specifications without notice. 2015 micron technology, inc. all rights reserved.
mm pudd = 100 r onpu,max - r onpu,min r on,nom mm pddd = 100 r onpd,max - r onpd,min r on,nom 7. the lower and upper bytes of a x16 are each treated on a per byte basis. 8. for it and at devices, the minimum values are derated by 9% when the device operates between C40c and 0c (t c ). table 123: weak mode (48 ) output driver electrical characteristics assumes r zq ?????; entire operating temperature range after proper zq calibration r on,nom resistor v out min nom max unit notes ?? r on34pd v ol(dc) = 0.5 v ddq 0.8 1.0 1.1 r zq /5 1, 2, 3 v om(dc) = 0.8 v ddq 0.9 1.0 1.1 r zq /5 1, 2, 3 v oh(dc) = 1.1 v ddq 0.9 1.0 1.25 r zq /5 1, 2, 3 r on34pu v ol(dc) = 0.5 v ddq 0.9 1.0 1.25 r zq /5 1, 2, 3 v om(dc) = 0.8 v ddq 0.9 1.0 1.1 r zq /5 1, 2, 3 v oh(dc) = 1.1 v ddq 0.8 1.0 1.1 r zq /5 1, 2, 3 mismatch between dq to dq within byte variation pull-up, mm pudd v om(dc) = 0.8 v ddq -10 C 10 % 1, 2, 3, 4, 5 mismatch between dq to dq within byte variation pull-down, mm pddd v om(dc) = 0.8 v ddq C C 10 % 1, 2, 3, 4, 6, 7 mismatch between pull-up and pull-down, mm pupd v om(dc) = 0.8 v ddq C C 10 % 1, 2, 3, 4, 6, 7 notes: 1. the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibra- tion, see following section on voltage and temperature sensitivity. 2. the tolerance limits are specified under the condition that v ddq = v dd and that v ssq = v ss . 3. micron recommends calibrating pull-down and pull-up output driver impedances at 0.8 v ddq . other calibration schemes may be used to achieve the linearity specification shown above; for example, calibration at 0.5 v ddq and 1.1 v ddq . 4. dq-to-dq mismatch within byte variation for a given component including dqs_t and dqs_c (characterized). 5. measurement definition for mismatch between pull-up and pull-down, mm pupd : measure both r onpu and r onpd at 0.8 v ddq separately; r on,nom is the nominal r on val- ue: mm pupd = 100 r onpu - r onpd r on,nom 6. r on variance range ratio to r on nominal value in a given component, including dqs_t and dqs_c: 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc output driver charac- teristics 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 299 micron technology, inc. reserves the right to change products or specifications without notice. 2015 micron technology, inc. all rights reserved.
mm pudd = 100 r onpu,max - r onpu,min r on,nom mm pddd = 100 r onpd,max - r onpd,min r on,nom 7. the lower and upper bytes of a x16 are each treated on a per byte basis. 8. for it and at devices, the minimum values are derated by 9% when the device operates between C40c and 0c (t c ). output driver temperature and voltage sensitivity if temperature and/or voltage change after calibration, the tolerance limits widen ac- cording to the equations and tables below. t = t - t(@calibration); v = v ddq - v ddq (@ calibration); v dd = v ddq table 124: output driver sensitivity definitions symbol min max unit r onpu @ v oh(dc) 0.6 - dr on dth |t| - dr on dvh | v| 1.1 _ dr on dth |t| + dr on dvh | v| r zq /6 r on @ v om(dc) 0.9 - dr on dtm |t| - dr on dvm | v| 1.1 + dr on dtm |t| + dr on dvm | v| r zq /6 r onpd @ v ol(dc) 0.6 - dr on dtl |t| - dr on dvl | v| 1.1 + dr on dtl |t| + dr on dvl | v| r zq /6 table 125: output driver voltage and temperature sensitivity symbol voltage and temperature range unit min max dr on dtm 0 1.5 %/c dr on dvm 0 0.15 %/mv dr on dtl 0 1.5 %/c dr on dvl 0 0.15 %/mv dr on dth 0 1.5 %/c dr on dvm 0 0.15 %/mv alert driver a functional representation of the alert output buffer is shown in the figure below. out- put driver impedance, r on , is defined as follows. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C ac and dc output driver charac- teristics 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 300 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 237: alert driver alert v out r onpd '5$0 alert driver i pd i out v ssq r onpd when r onpu is off: r onpd = v out i out table 126: alert driver voltage r on,nom register v out min nom max unit n/a r onpd v ol(dc) = 0.1 v ddq 0.3 n/a 1.2 r zq /7 v om(dc) = 0.8 v ddq 0.4 n/a 1.12 r zq /7 v oh(dc) = 1.1 v ddq 0.4 n/a 1.4 r zq /7 note: 1. v ddq voltage is at v ddq(dc) . electrical characteristics C on-die termination characteristics odt levels and i-v characteristics on-die termination (odt) effective resistance settings are defined and can be selected by any or all of the following options: ? mr1[10:8] (r tt(nom) ): disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40 ohms, and 34 ohms. ? mr2[11:9] (r tt(wr) ): disable, 240 ohms,120 ohms, and 80 ohms. ? mr5[8:6] (r tt(park) ): disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40 ohms, and 34 ohms. odt is applied to the following inputs: ? x4: dq, dm_n, dqs_t, and dqs_c inputs. ? x8: dq, dm_n, dqs_t, dqs_c, tdqs_t, and tdqs_c inputs. ? x16: dq, ldm_n, udm_n, ldqs_t, ldqs_c, udqs_t, and udqs_c inputs. a functional representation of odt is shown in the figure below. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C on-die termination characteristics 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 301 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 238: odt definition of voltages and currents v ddq v ssq chip in termination mode dq v out i out r tt to other circuitry like rcv, ... odt table 127: odt dc characteristics r tt v out min nom max unit notes 240 ohm v ol(dc) = 0.5 v ddq 0.9 1 1.25 r zq 1, 2, 3 v om(dc) = 0.8 v ddq 0.9 1 1.1 r zq 1, 2, 3 v oh(dc) = 1.1 v ddq 0.8 1 1.1 r zq 1, 2, 3 120 ohm v ol(dc) = 0.5 v ddq 0.9 1 1.25 r zq /2 1, 2, 3 v om(dc) = 0.8 v ddq 0.9 1 1.1 r zq /2 1, 2, 3 v oh(dc) = 1.1 v ddq 0.8 1 1.1 r zq /2 1, 2, 3 80 ohm v ol(dc) = 0.5 v ddq 0.9 1 1.25 r zq /3 1, 2, 3 v om(dc) = 0.8 v ddq 0.9 1 1.1 r zq /3 1, 2, 3 v oh(dc) = 1.1 v ddq 0.8 1 1.1 r zq /3 1, 2, 3 60 ohm v ol(dc) = 0.5 v ddq 0.9 1 1.25 r zq /4 1, 2, 3 v om(dc) = 0.8 v ddq 0.9 1 1.1 r zq /4 1, 2, 3 v oh(dc) = 1.1 v ddq 0.8 1 1.1 r zq /4 1, 2, 3 48 ohm v ol(dc) = 0.5 v ddq 0.9 1 1.25 r zq /5 1, 2, 3 v om(dc) = 0.8 v ddq 0.9 1 1.1 r zq /5 1, 2, 3 v oh(dc) = 1.1 v ddq 0.8 1 1.1 r zq /5 1, 2, 3 40 ohm v ol(dc) = 0.5 v ddq 0.9 1 1.25 r zq /6 1, 2, 3 v om(dc) = 0.8 v ddq 0.9 1 1.1 r zq /6 1, 2, 3 v oh(dc) = 1.1 v ddq 0.8 1 1.1 r zq /6 1, 2, 3 34 ohm v ol(dc) = 0.5 v ddq 0.9 1 1.25 r zq /7 1, 2, 3 v om(dc) = 0.8 v ddq 0.9 1 1.1 r zq /7 1, 2, 3 v oh(dc) = 1.1 v ddq 0.8 1 1.1 r zq /7 1, 2, 3 dq-to-dq mismatch within byte v om(dc) = 0.8 v ddq 0 C 10 % 1, 2, 4, 5, 6 notes: 1. the tolerance limits are specified after calibration to 240 ohm 1% resistor with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see odt temperature and voltage sensitivity. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C on-die termination characteristics 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 302 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
2. micron recommends calibrating pull-up odt resistors at 0.8 v ddq . other calibration schemes may be used to achieve the linearity specification shown here. 3. the tolerance limits are specified under the condition that v ddq = v dd and v ssq = v ss . 4. the dq-to-dq mismatch within byte variation for a given component including dqs_t and dqs_c. 5. r tt variance range ratio to r tt nominal value in a given component, including dqs_t and dqs_c. dq-to-dq mismatch = r tt(max) - r tt(min) r tt(nom) 100 6. dq-to-dq mismatch for a x16 device is treated as two separate bytes. 7. for it, at, and ut devices, the minimum values are derated by 9% when the device op- erates between C40c and 0c (tc). odt temperature and voltage sensitivity if temperature and/or voltage change after calibration, the tolerance limits widen ac- cording to the following equations and tables. t = t - t(@ calibration); v = v ddq - v ddq (@ calibration); v dd = v ddq table 128: odt sensitivity definitions parameter min max unit r tt @ 0.9 - dr tt dt |t| - dr tt dv | v| 1.6 + dr tt dth |t| + dr tt dvh | v| r zq /n table 129: odt voltage and temperature sensitivity parameter min max unit dr tt dt 0 1.5 %/c dr tt dv 0 0.15 %/mv odt timing definitions the reference load for odt timings is different than the reference load used for timing measurements. figure 239: odt timing reference load timing reference point dq, dqs_t, dqs_c, dm, tdqs_t, tdqs_c ck_t, ck_c dut v tt v ddq v ssq v ssq = r tt = 50 odt timing definitions and waveforms 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C on-die termination characteristics 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 303 micron technology, inc. reserves the right to change products or specifications without notice. 2015 micron technology, inc. all rights reserved.
definitions for t adc, t aonas, and t aofas are provided in the table 130 (page 304) and shown in figure 240 (page 305) and figure 242 (page 306). measurement reference set- tings are provided in the subsequent table 131 (page 304). the t adc for the dynamic odt case and read disable odt cases are represented by t adc of direct odt control case. table 130: odt timing definitions parameter begin point definition end point definition figure t adc rising edge of ck_t, ck_c defined by the end point of dodtloff extrapolated point at v rtt,nom figure 240 (page 305) rising edge of ck_t, ck_c defined by the end point of dodtlon extrapolated point at v ssq figure 240 (page 305) rising edge of ck_t, ck_c defined by the end point of odtlcnw extrapolated point at v rtt,nom figure 241 (page 305) rising edge of ck_t, ck_c defined by the end point of odtlcwn4 or odtlcwn8 extrapolated point at v ssq figure 241 (page 305) t aonas rising edge of ck_t, ck_c with odt being first registered high extrapolated point at v ssq figure 242 (page 306) t aofas rising edge of ck_t, ck_c with odt being first registered low extrapolated point at v rtt,nom figure 242 (page 306) table 131: reference settings for odt timing measurements measure parameter r tt(park) r tt(nom) r tt(wr) vsw1 vsw2 note t adc disable r zq ?????? ? C 0.20v 0.40v 1, 2, 4 Cr zq ??????? high-z 0.20v 0.40v 1, 3, 5 t aonas disable r zq ?????? ? C 0.20v 0.40v 1, 2, 6 t aofas disable r zq ??????? C 0.20v 0.40v 1, 2, 6 notes: 1. mr settings are as follows: mr1 has a10 = 1, a9 = 1, a8 = 1 for r tt(nom) setting; mr5 has a8 = 0, a7 = 0, a6 = 0 for r tt(park) setting; and mr2 has a11 = 0, a10 = 1, a9 = 1 for r tt(wr) setting. 2. odt state change is controlled by odt pin. 3. odt state change is controlled by a write command. 4. refer to figure 240 (page 305). 5. refer to figure 241 (page 305). 6. refer to figure 242 (page 306). 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C on-die termination characteristics 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 304 micron technology, inc. reserves the right to change products or specifications without notice. 2015 micron technology, inc. all rights reserved.
figure 240: t adc definition with direct odt control t adc t adc begin point: rising edge of ck_t, ck_c defined by the end point of dodtloff dodtloff begin point: rising edge of ck_t, ck_c defined by the end point of dodtlon dodtlon end point: extrapolated point at v rtt,nom end point: extrapolated point at v ssq v rtt,nom v rtt,nom v ssq v ssq dq, dm dqs_t, dqs_c tdqs_t, tdqs_c ck_c ck_t vsw2 vsw1 figure 241: t adc definition with dynamic odt control t adc t adc begin point: rising edge of ck_t, ck_c defined by the end point of odtlcnw odtlcnw begin point: rising edge of ck_t, ck_c defined by the end point of odtlcnw4 or odtlcnw8 odtlcnw4/8 end point: extrapolated point at v rtt,nom end point: extrapolated point at v ssq v rtt,nom v rtt,nom v ssq v ssq dq, dm dqs_t, dqs_c tdqs_t, tdqs_c ck_c ck_t vsw2 vsw1 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C on-die termination characteristics 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 305 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 242: t aofas and t aonas definitions t aofas t aonas rising edge of ck_t, ck_c with odt being first registered low rising edge of ck_t, ck_c with odt being first registered high end point: extrapolated point at v rtt_nom end point: extrapolated point at v ssq v rtt,nom v rtt,nom v ssq v ssq dq, dm dqs_t, dqs_c tdqs_t, tdqs_c ck_c ck_t vsw2 vsw1 8gb: x4, x8, x16 ddr4 sdram electrical characteristics C on-die termination characteristics 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 306 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
dram package electrical specifications table 132: dram package electrical specifications for x4 and x8 devices parameter symbol 1600/1866/2133/ 2400/2666 2933 3200 unit notes min max min max min max input/ output zpkg z io 45 85 48 85 48 85 ohm 1, 2, 4 package delay td io 14 42 14 40 14 40 ps 1, 3, 4 lpkg l io C 3.3 C 3.3 C 3.3 nh cpkg c io C 0.78 C 0.78 C 0.78 pf dqs_t, dqs_c zpkg z io dqs 45 85 48 85 48 85 ohm 1, 2 package delay td io dqs 14 42 14 40 14 40 ps 1, 3 delta zpkg dz io dqs C 10 C 10 C 10 ohm 1, 2, 6 delta delay dtd io dqs C5C5C5ps1, 3, 6 lpkg l io dqs C 3.3 C 3.3 C 3.3 nh cpkg c io dqs C 0.78 C 0.78 C 0.78 pf input ctrl pins zpkg z i ctrl 50 90 50 90 50 90 ohm 1, 2, 8 package delay td i ctrl 14 42 14 40 14 40 ps 1, 3, 8 lpkg l i ctrl C 3.4 C 3.4 C 3.4 nh cpkg c i ctrl C 0.7 C 0.7 C 0.7 pf input cmd add pins zpkg z i add cmd 50 90 50 90 50 90 ohm 1, 2, 7 package delay td i add cmd 14 45 14 40 14 40 ps 1, 3, 7 lpkg l i add cmd C 3.6 C 3.6 C 3.6 nh cpkg c i add cmd C 0.74 C 0.74 C 0.74 pf ck_t, ck_c zpkg z ck 50 90 50 90 50 90 ohm 1, 2 package delay td ck 14 42 14 42 14 42 ps 1, 3 delta zpkg dz dck C 10 C 10 C 10 ohm 1, 2, 5 delta delay dtd dck C 5 C 5 C 5 ps 1, 3, 5 lpkg l i clk C 3.4 C 3.4 C 3.4 nh cpkg c i clk C 0.7 C 0.7 C 0.7 pf zq zpkg z o zq C 100 C 100 C 100 ohm 1, 2 zq delay td o zq 20 55 20 55 20 55 ps 1, 3 alert zpkg z o alert 40 100 40 100 40 100 ohm 1, 2 alert delay td o alert 20 55 20 55 20 55 ps 1, 3 notes: 1. the package parasitic (l and c) are validated using package only samples. the capaci- tance is measured with v dd , v ddq , v ss , and v ssq shorted with all other signal pins float- ing. the inductance is measured with v dd , v ddq , v ss , and v ssq shorted and all other sig- nal pins shorted at the die, not pin, side. 2. package-only impedance (zpkg) is calculated based on the lpkg and cpkg total for a given pin where: zpkg (total per pin) = sqrt (lpkg/cpkg). 3. package-only delay (tpkg) is calculated based on lpkg and cpkg total for a given pin where: tdpkg (total per pin) = sqrt (lpkg cpkg). 4. z io and td io apply to dq, dm, dqs_c, dqs_t, tdqs_t, and tdqs_c. 8gb: x4, x8, x16 ddr4 sdram dram package electrical specifications 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 307 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
5. absolute value of zck_t, zck_c for impedance (z) or absolute value of tdck_t, tdck_c for delay (td). 6. absolute value of zio (dqs_t), zio (dqs_c) for impedance (z) or absolute value of tdio (dqs_t), tdio (dqs_c) for delay (td). 7. z i add cmd and td i add cmd apply to a[17:0], ba[1:0], bg[1:0], ras_n cas_n, and we_n. 8. z i ctrl and td i ctrl apply to odt, cs_n, and cke. 9. package implementations will meet specification if the zpkg and package delay fall within the ranges shown, and the maximum lpkg and cpkg do not exceed the maxi- mum values shown. 10. it is assumed that lpkg can be approximated as lpkg = z o td. 11. it is assumed that cpkg can be approximated as cpkg = td/z o . table 133: dram package electrical specifications for x16 devices parameter symbol 1600/1866/2133/ 2400/2666 2933 3200 unit notes min max min max min max input/ output zpkg z io 45 85 45 85 45 85 ohm 1, 2, 4 package delay td io 14 45 14 45 14 45 ps 1, 3, 4 lpkg l io C 3.4 C 3.4 C 3.4 nh cpkg c io C 0.82 C 0.82 C 0.82 pf dqsl_t/ dqsl_c/ dqsu_t/ dqsu_c zpkg z io dqs 45 85 45 85 45 85 ohm 1, 2 package delay td io dqs 14 45 14 45 14 45 ps 1, 3 lpkg l io dqs C 3.4 C 3.4 C 3.4 nh cpkg c io dqs C 0.82 C 0.82 C 0.82 pf dqsl_t/ dqsl_c, dqsu_t/ dqsu_c, delta zpkg dz io dqs C 10 C 10 C 10 ohm 1, 2, 6 delta delay dtd io dqs C5C5C5ps1, 3, 6 input ctrl pins zpkg z i ctrl 50 90 50 90 50 90 ohm 1, 2, 8 package delay td i ctrl 14 42 14 42 14 42 ps 1, 3, 8 lpkg l i ctrl C 3.4 C 3.4 C 3.4 nh cpkg c i ctrl C 0.7 C 0.7 C 0.7 pf input cmd add pins zpkg z i add cmd 50 90 50 90 50 90 ohm 1, 2, 7 package delay td i add cmd 14 52 14 52 14 52 ps 1, 3, 7 lpkg l i add cmd C 3.9 C 3.9 C 3.9 nh cpkg c i add cmd C 0.86 C 0.86 C 0.86 pf ck_t, ck_c zpkg z ck 50 90 50 90 50 90 ohm 1, 2 package delay td ck 14 42 14 42 14 42 ps 1, 3 delta zpkg dz dck C 10 C 10 C 10 ohm 1, 2, 5 delta delay dtd dck C 5 C 5 C 5 ps 1, 3, 5 input clk lpkg l i clk C 3.4 C 3.4 C 3.4 nh cpkg c i clk C 0.7 C 0.7 C 0.7 pf zq zpkg z o zq C 100 C 100 C 100 ohm 1, 2 zq delay td o zq 20 90 20 90 20 90 ps 1, 3 8gb: x4, x8, x16 ddr4 sdram dram package electrical specifications 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 308 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 133: dram package electrical specifications for x16 devices (continued) parameter symbol 1600/1866/2133/ 2400/2666 2933 3200 unit notes min max min max min max alert zpkg z o alert 40 100 40 100 40 100 ohm 1, 2 alert delay td o alert 20 55 20 55 20 55 ps 1, 3 notes: 1. the package parasitic (l and c) are validated using package only samples. the capaci- tance is measured with v dd , v ddq , v ss , and v ssq shorted with all other signal pins float- ing. the inductance is measured with v dd , v ddq , v ss , and v ssq shorted and all other sig- nal pins shorted at the die, not pin, side. 2. package-only impedance (zpkg) is calculated based on the lpkg and cpkg total for a given pin where: zpkg (total per pin) = sqrt (lpkg/cpkg). 3. package-only delay (tpkg) is calculated based on lpkg and cpkg total for a given pin where: tdpkg (total per pin) = sqrt (lpkg cpkg). 4. z io and td io apply to dq, dm, dqs_c, dqs_t, tdqs_t, and tdqs_c. 5. absolute value of zck_t, zck_c for impedance (z) or absolute value of tdck_t, tdck_c for delay (td). 6. absolute value of zio (dqs_t), zio (dqs_c) for impedance (z) or absolute value of tdio (dqs_t), tdio (dqs_c) for delay (td). 7. z i add cmd and td i add cmd apply to a[17:0], ba[1:0], bg[1:0], ras_n cas_n, and we_n. 8. z i ctrl and td i ctrl apply to odt, cs_n, and cke. 9. package implementations will meet specification if the zpkg and package delay fall within the ranges shown, and the maximum lpkg and cpkg do not exceed the maxi- mum values shown. 10. it is assumed that lpkg can be approximated as lpkg = z o td. 11. it is assumed that cpkg can be approximated as cpkg = td/z o . 8gb: x4, x8, x16 ddr4 sdram dram package electrical specifications 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 309 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 134: pad input/output capacitance parameter symbol ddr4-1600, 1866, 2133 ddr4-2400, 2666 ddr4-2933 ddr4-3200 unit notes min max min max min max min max input/output capacitance: dq, dm, dqs_t, dqs_c, tdqs_t, tdqs_c c io 0.55 1.4 0.55 1.15 0.55 1.00 0.55 1.00 pf 1, 2, 3 input capacitance: ck_t and ck_c c ck 0.2 0.8 0.2 0.7 0.2 0.7 0.2 0.7 pf 1, 2, 3, 4 input capacitance delta: ck_t and ck_c c dck 0 0.05 0 0.05 0 0.05 0 0.05 pf 1, 2, 3, 5 input/output capacitance del- ta: dqs_t and dqs_c c ddqs 0 0.05 0 0.05 0 0.05 0 0.05 pf 1, 2, 3 input capacitance: ctrl, add, cmd input-only pins c i 0.2 0.8 0.2 0.7 0.2 0.6 0.2 0.55 pf 1, 2, 3, 6 input capacitance delta: all ctrl input-only pins c di_ctrl C0.1 0.1 C0.1 0.1 C0.1 0.1 C0.1 0.1 pf 1, 2, 3, 7 input capacitance delta: all add/cmd input-only pins c di_add_cm d C0.1 0.1 C0.1 0.1 C0.1 0.1 C0.1 0.1 pf 1, 2, 3, 8, 9 input/output capacitance del- ta: dq, dm, dqs_t, dqs_c, tdqs_t, tdqs_c c dio C0.1 0.1 C0.1 0.1 C0.1 0.1 C0.1 0.1 pf 1, 2, 10, 11 input/output capacitance: alert pin c alert 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 pf 1, 2, 2, 3 input/output capacitance: zq pin c zq C 2.3 C 2.3 C 2.3 C 2.3 pf 1, 2, 3, 12 input/output capacitance: ten pin c ten 0.2 2.3 0.2 2.3 0.2 2.3 0.2 2.3 pf 1, 2, 3, 13 notes: 1. although the dm, tdqs_t, and tdqs_c pins have different functions, the loading matches dq and dqs. 2. this parameter is not subject to a production test; it is verified by design and characteri- zation. the capacitance is measured according to the jep147 specification, procedure for measuring input capacitance using a vector network analyzer (vna), with v dd , v ddq , v ss , and v ssq applied and all other pins floating (except the pin under test, cke, reset_n and odt, as necessary). v dd = v ddq = 1.5v, v bias = v dd /2 and on-die termination off. measured data is rounded using industry standard half-rounded up methodology to the nearest hundredth of the msb. 3. this parameter applies to monolithic die, obtained by de-embedding the package l and c parasitics. 4. c dio = c io (dq, dm) - 0.5 (c io (dqs_t) + c io (dqs_c)). 5. absolute value of c io (dqs_t), c io (dqs_c) 6. absolute value of cck_t, cck_c 7. c i applies to odt, cs_n, cke, a[15:0], ba[1:0], ras_n, cas_n, and we_n. 8. c di_ctrl applies to odt, cs_n, and cke. 9. c di_ctrl = c i (ctrl) - 0.5 (c i (clk_t) + c i (clk_c)). 10. c di_add_cmd applies to a[15:0], ba1:0], ras_n, cas_n and we_n. 8gb: x4, x8, x16 ddr4 sdram dram package electrical specifications 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 310 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
11. c di_add_cmd = c i (add_cmd) - 0.5 (c i (clk_t) + c i (clk_c)). 12. maximum external load capacitance on zq pin: 5pf. 13. only applicable if ten pin does not have an internal pull-up. thermal characteristics table 135: thermal characteristics parameter/condition value units symbol notes operating case temperature: commercial 0 to +85 c t c 1, 2, 3 0 to +95 c t c 1, 2, 3, 4 operating case temperature: industrial C40 to +85 c t c 1, 2, 3 C40 to +95 c t c 1, 2, 3, 4 operating case temperature: automotive C40 to +85 c t c 1, 2, 3 C40 to +105 c t c 1, 2, 3, 4 rev a 78-ball pm junction-to-case (top) 3.1 c/w jc 5 junction-to-board 10.6 c/w jb 96-ball ha junction-to-case (top) 3.0 c/w jc 5 junction-to-board 9.9 c/w jb rev b 78-ball we junction-to-case (top) 3.5 c/w jc 5 junction-to-board 21 c/w jb 96-ball jy junction-to-case (top) 4.1 c/w jc 5 junction-to-board 16.2 c/w jb rev c 78-ball sa junction-to-case (top) tbd c/w jc 5 junction-to-board tbd c/w jb 96-ball ly junction-to-case (top) tbd c/w jc 5 junction-to-board tbd c/w jb rev d 78-ball we junction-to-case (top) 3.2 c/w jc 5 junction-to-board 20.2 c/w jb 96-ball jy junction-to-case (top) tbd c/w jc 5 junction-to-board tbd c/w jb rev e 78-ball sa junction-to-case (top) tbd c/w jc 5 junction-to-board tbd c/w jb 96-ball ly junction-to-case (top) tbd c/w jc 5 junction-to-board tbd c/w jb rev g 78-ball we junction-to-case (top) tbd c/w jc 5 junction-to-board tbd c/w jb n/a junction-to-case (top) n/a c/w jc 5 junction-to-board n/a c/w jb 8gb: x4, x8, x16 ddr4 sdram thermal characteristics 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 311 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 135: thermal characteristics (continued) parameter/condition value units symbol notes rev h 78-ball sa junction-to-case (top) tbd c/w jc 5 junction-to-board tbd c/w jb 96-ball ly junction-to-case (top) tbd c/w jc 5 junction-to-board tbd c/w jb notes: 1. max operating case temperature. t c is measured in the center of the package. 2. a thermal solution must be designed to ensure the dram device does not exceed the maximum t c during operation. 3. device functionality is not guaranteed if the dram device exceeds the maximum t c dur- ing operation. 4. if t c exceeds 85c, the dram must be refreshed externally at 2x refresh, which is a 3.9s interval refresh rate. 5. the thermal resistance data is based off of a number of samples from multiple lots and should be viewed as a typical number. figure 243: thermal measurement point (l/2) l w (w/2) t c test point current specifications C measurement conditions i dd , i pp , and i ddq measurement conditions i dd , i pp , and i ddq measurement conditions, such as test load and patterns, are defined in this section. ?i dd currents (i dd0 , i dd1 , i dd2n , i dd2nt , i dd2p , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , i dd5r , i dd6n , i dd6e , i dd6r , i dd7 , and i dd8 ) are measured as time-averaged currents with all v dd balls of the device under test grouped together. i pp and i ddq currents are not in- cluded in i dd currents. ?i pp currents are i ppsb for standby cases (i dd2n , i dd2nt , i dd2p , i dd2q , i dd3n , i dd3p , i dd8 ); i pp0 for active cases (i dd0 ,i dd1 , i dd4r , i dd4w ); i pp5r and i pp6n for self refresh cases 8gb: x4, x8, x16 ddr4 sdram current specifications C measurement conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 312 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
(i dd6n , i dd6e , i dd6r ), and i pp7 . these have the same definitions as the i dd currents ref- erenced but are measured on the v pp supply. ?i ddq currents (i ddq2nt ) are measured as time-averaged currents with v ddq balls of the device under test grouped together. i dd current is not included in i ddq currents. note: i ddq values cannot be directly used to calculate the i/o power of the device. they can be used to support correlation of simulated i/o power to actual i/o power. in dram module application, i ddq cannot be measured separately because v dd and v ddq are using a merged-power layer in the module pcb. the following definitions apply for i dd , i ddp and i ddq measurements. ? 0 and low are defined as v in v il(ac)max ? 1 and high are defined as v in v ih(ac)min ? midlevel is defined as inputs v ref = v dd /2 ? timings used for i dd , i ddp and i ddq measurement-loop patterns are provided in the current test definition and patterns section. ? basic i dd , i pp , and i ddq measurement conditions are described in the current test definition and patterns section. ? detailed i dd , i pp , and i ddq measurement-loop patterns are described in the current test definition and patterns section. ? current measurements are done after properly initializing the device. this includes, but is not limited to, setting: r on = r zq /7 (34 ohm in mr1); qoff = 0b (output buffer enabled in mr1); r tt(nom) = r zq /6 (40 ohm in mr1); r tt(wr) = r zq /2 (120 ohm in mr2); r tt(park) = disabled; tdqs feature disabled in mr1; crc disabled in mr2; ca parity feature disabled in mr3; gear-down mode disabled in mr3; read/write dbi disabled in mr5; dm disa- bled in mr5 ? define d = {cs_n, ras_n, cas_n, we_n}: = {high, low, low, low}; apply bg/ba changes when directed. ? define d_n = {cs_n, ras_n, cas_n, we_n}: = {high, high, high, high}; apply in- vert of bg/ba changes when directed above. note: the measurement-loop patterns must be executed at least once before actual cur- rent measurements can be taken. 8gb: x4, x8, x16 ddr4 sdram current specifications C measurement conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 313 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 244: measurement setup and test load for i ddx , i ddpx , and i ddqx i dd ck_t/ck_c cs_n cke odt v dd v ddq v ss v ssq reset_n act_n, ras_n, cas_n, we_n dqs_t, dqs_c dq dm_n zq a, bg, ba i ddq c i pp v pp ddr4 sdram figure 245: correlation: simulated channel i/o power to actual channel i/o power application-specific memory c ha nne l env ironmen t c hanne l i/o power simulation i dd q test load i dd q simulation i dd q measurement correlation correction c hanne l i/o power number note: 1. supported by i ddq measurement. i dd definitions table 136: basic i dd , i pp , and i ddq measurement conditions symbol description i dd0 operating one bank active-precharge current (al = 0) cke: high; external clock: on; t ck, nrc, nras, cl: see the previous table; bl: 8; 1 al: 0; cs_n: high between act and pre; command, address, bank group address, bank address inputs: partially toggling according to the next table; data i/o: v ddq ; dm_n: stable at 0; bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the i dd0 measurement-loop pattern table); output buffer and r tt : enabled in mode registers; 2 odt signal: stable at 0; pattern details: see the i dd0 measurement-loop pattern table 8gb: x4, x8, x16 ddr4 sdram current specifications C measurement conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 314 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 136: basic i dd , i pp , and i ddq measurement conditions (continued) symbol description i pp0 operating one bank active-precharge i pp current (al = 0) same conditions as i dd0 above i dd1 operating one bank active-read-precharge current (al = 0) cke: high; external clock: on; t ck, nrc, nras, nrcd, cl: see the previous table; bl: 8; 1, 5 al: 0; cs_n: high between act, rd, and pre; command, address, bank group address, bank address inputs, data i/o: partially toggling according to the i dd1 measurement-loop pattern table; dm_n: stable at 0; bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the following table); output buffer and r tt : enabled in mode registers; 2 odt signal: stable at 0; pattern details: see the i dd1 measurement-loop pattern table i dd2n precharge standby current (al = 0) cke: high; external clock: on; t ck, cl: see the previous table; bl: 8; 1 al: 0; cs_n: stable at 1; command, ad- dress, bank group address, bank address inputs: partially toggling according to the i dd2n and i dd3n measure- ment-loop pattern table; data i/o: v ddq ; dm_n: stable at 1; bank activity: all banks closed; output buffer and r tt : enabled in mode registers; 2 odt signal: stable at 0; pattern details: see the i dd2n and i dd3n measurement- loop pattern table i dd2nt precharge standby odt current cke: high; external clock: on; t ck, cl: see the previous table; bl: 8; 1 al: 0; cs_n: stable at 1; command, ad- dress, bank gropup address, bank address inputs: partially toggling according to the i dd2nt and i ddq2nt meas- urement-loop pattern table; data i/o: v ssq ; dm_n: stable at 1; bank activity: all banks closed; output buffer and r tt : enabled in mode registers; 2 odt signal: toggling according to the i dd2nt and i ddq2nt measurement- loop pattern table; pattern details: see the i dd2nt and i ddq2nt measurement-loop pattern table i ddq2nt precharge standby odt i ddq current has the same definition as i dd2nt above, with the exception of measuring i ddq current instead of i dd current i dd2p precharge power-down current cke: low; external clock: on; t ck, cl: see the previous table; bl: 8; 1 al: 0; cs_n: stable at 1; command, ad- dress, bank group address, bank address inputs: stable at 0; data i/o: v ddq ; dm_n: stable at 1; bank activity: all banks closed; output buffer and r tt : enabled in mode registers; 2 odt signal: stable at 0 i dd2q precharge quiet standby current cke: high; external clock: on; t ck, cl: see the previous table; bl: 8; 1 al: 0; cs_n: stable at 1; command, ad- dress, bank group address, bank address inputs: stable at 0; data i/o: v ddq ; dm_n: stable at 1; bank activity: all banks closed; output buffer and r tt : enabled in mode registers; 2 odt signal: stable at 0 i dd3n active standby current (al = 0) cke: high; external clock: on; t ck, cl: see the previous table; bl: 8; 1 al: 0; cs_n: stable at 1; command, ad- dress, bank group address, bank address inputs: partially toggling according to the i dd2n and i dd3n measure- ment-loop pattern table; data i/o: v ddq ; dm_n: stable at 1; bank activity: all banks open; output buffer and r tt : enabled in mode registers; 2 odt signal: stable at 0; pattern details: see the i dd2n and i dd3n measurement- loop pattern table i ppsb active standby i ppsb current (al = 0) same conditions as i dd3n above i dd3p active power-down current (al = 0) cke: low; external clock: on; t ck, cl: see the previous table; bl: 8; 1 al: 0; cs_n: stable at 1; command, ad- dress, bank group address, bank address inputs: stable at 1; data i/o: v ddq ; dm_n: stable at 1; bank activity: all banks open; output buffer and r tt : enabled in mode registers; 2 odt signal: stable at 0 8gb: x4, x8, x16 ddr4 sdram current specifications C measurement conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 315 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 136: basic i dd , i pp , and i ddq measurement conditions (continued) symbol description i dd4r operating burst read current (al = 0) cke: high; external clock: on; t ck, cl: see the previous table; bl: 8; 15 al: 0; cs_n: high between rd; com- mand, address, bank group address, bank address inputs: partially toggling according to the i dd4r measure- ment-loop pattern table; data i/o: seamless read data burst with different data between one burst and the next one according to the i dd4r measurement-loop pattern table; dm_n: stable at 1; bank activity: all banks open, rd commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see the i dd4r measurement-loop pattern table); output buffer and r tt : enabled in mode registers; 2 odt signal: stable at 0; pattern details: see the i dd4r meas- urement-loop pattern table i dd4w operating burst write current (al = 0) cke: high; external clock: on; t ck, cl: see the previous table; bl: 8; 1 al: 0; cs_n: high between wr; com- mand, address, bank group address, bank address inputs: partially toggling according to the i dd4w measure- ment-loop pattern table; data i/o: seamless write data burst with different data between one burst and the next one according to the i dd4w measurement-loop pattern table; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see i dd4w measurement-loop pattern table); output buffer and r tt : enabled in mode registers (see note2); odt signal: stable at high; pattern details: see the i dd4w measurement-loop pattern table i dd5r burst refresh current (1x ref) cke: high; external clock: on; t ck, cl, nrefi: see the previous table; bl: 8; 1 al: 0; cs_n: high between ref; command, address, bank group address, bank address inputs: partially toggling according to the i dd5r meas- urement-loop pattern table; data i/o: v ddq ; dm_n: stable at 1; bank activity: ref command every nrefi (see the i dd5r measurement-loop pattern table); output buffer and r tt : enabled in mode registers 2 ; odt signal: stable at 0; pattern details: see the i dd5r measurement-loop pattern table i pp5r burst refresh current (1x ref) same conditions as i dd5r above i dd6n self refresh current: normal temperature range t c : 0C85c; auto self refresh (asr): disabled; 3 self refresh temperature range (srt): normal; 4 cke: low; exter- nal clock: off; ck_t and ck_c: low; cl: see the table above; bl: 8; 1 al: 0; cs_n, command, address, bank group address, bank address, data i/o: v ddq ; dm_n: stable at 1; bank activity: self refresh operation; output buffer and r tt : enabled in mode registers; 2 odt signal: midlevel i pp6n self refresh i pp current: normal temperature range same conditions as i dd6n above i dd6e self refresh current: extended temperature range 4 t c : 0C95c; auto self refresh (asr): disabled 4 ; self refresh temperature range (srt): extended; 4 cke: low; ex- ternal clock: off; ck_t and ck_c: low; cl: see the previous table; bl: 8; 1 al: 0; cs_n, command, address, group bank address, bank address, data i/o: v ddq ; dm_n: stable at 1; bank activity: extended temperature self refresh operation; output buffer and r tt : enabled in mode registers; 2 odt signal: midlevel i dd6r self refresh current: reduced temperature range t c : 0C45c; auto self refresh (asr): disabled; self refresh temperature range (srt): reduced; 4 cke: low; exter- nal clock: off; ck_t and ck_c: low; cl: see the previous table; bl: 8; 1 al: 0; cs_n, command, address, bank group address, bank address, data i/o: v ddq ; dm_n: stable at 1; bank activity: extended temperature self refresh operation; output buffer and r tt : enabled in mode registers; 2 odt signal: midlevel 8gb: x4, x8, x16 ddr4 sdram current specifications C measurement conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 316 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 136: basic i dd , i pp , and i ddq measurement conditions (continued) symbol description i dd7 operating bank interleave read current cke: high; external clock: on; t ck, nrc, nras, nrcd, nrrd, n faw, cl: see the previous table; bl: 8; 15 al: cl - 1; cs_n: high between act and rda; command, address, group bank adress, bank address inputs: partially toggling according to the i dd7 measurement-loop pattern table; data i/o: read data bursts with different data between one burst and the next one according to the i dd7 measurement-loop pattern table; dm: stable at 1; bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see the i dd7 measurement-loop pattern table; output buffer and r tt : enabled in mode registers; 2 odt signal: stable at 0; pattern details: see the i dd7 measurement-loop pattern table i pp7 operating bank interleave read i pp current same conditions as i dd7 above i dd8 maximum power down current place dram in mpsm then cke: high; external clock: on; t ck, cl: see the previous table; bl: 8; 1 al: 0; cs_n: stable at 1; command, address, bank group address, bank address inputs: stable at 0; data i/o: v ddq ; dm_n: stable at 1; bank activity: all banks closed; output buffer and r tt : enabled in mode registers; 2 odt signal: sta- ble at 0 notes: 1. burst length: bl8 fixed by mrs: set mr0[1:0] 00. 2. output buffer enable: set mr1[12] 0 (output buffer enabled); set mr1[2:1] 00 (r on = r zq /7); r tt(nom) enable: set mr1[10:8] 011 (r zq /6); r tt(wr) enable: set mr2[11:9] 001 (r zq /2), and r tt(park) enable: set mr5[8:6] 000 (disabled). 3. auto self refresh (asr): set mr2[6] 0 to disable or mr2[6] 1 to enable feature. 4. self refresh temperature range (srt): set mr2[7] 0 for normal or mr2[7] 1 for extended temperature range. 5. read burst type: nibble sequential, set mr0[3] 0. 8gb: x4, x8, x16 ddr4 sdram current specifications C measurement conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 317 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
current specifications C patterns and test conditions current test definitions and patterns table 137: i dd0 and i pp0 measurement-loop pattern 1 ck_t, ck_c cke sub-loop cycle number command cs_n act_n ras_n/a16 cas_n/a15 we_n/a14 odt bg[1:0] 2 ba[1:0] a12/bc_n a[17,13,11]] a[10]/ap a[9:7] a[6:3] a[2:0] data 3 toggling static high 0 0 act00000000000000 C 1, 2 d, d10000000000000 C 3, 4 d_n, d_n 111110330007f0 C ... repeat pattern 1...4 until nras - 1; truncate if necessary n ras pre01010000000000 C ... repeat pattern 1...4 until nrc - 1; truncate if necessary 1 1 nrc repeat sub-loop 0, use bg[1:0] = 1, use ba[1:0] = 1 instead 2 2 nrc repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 2 instead 3 3 nrc repeat sub-loop 0, use bg[1:0] = 1, use ba[1:0] = 3 instead 4 4 nrc repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 1 instead 5 5 nrc repeat sub-loop 0, use bg[1:0] = 1, use ba[1:0] = 2 instead 6 6 nrc repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 3 instead 7 7 nrc repeat sub-loop 0, use bg[1:0] = 1, use ba[1:0] = 0 instead 8 8 nrc repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 0 instead 4 9 9 nrc repeat sub-loop 0, use bg[1:0] = 3, use ba[1:0] = 1 instead 4 10 10 nrc repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 2 instead 4 11 11 nrc repeat sub-loop 0, use bg[1:0] = 3, use ba[1:0] = 3 instead 4 12 12 nrc repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 1 instead 4 13 13 nrc repeat sub-loop 0, use bg[1:0] = 3, use ba[1:0] = 2 instead 4 14 14 nrc repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 3 instead 4 15 15 nrc repeat sub-loop 0, use bg[1:0] = 3, use ba[1:0] = 0 instead 4 notes: 1. dqs_t, dqs_c are v ddq . 2. bg1 is a "don't care" for x16 devices. 3. dq signals are v ddq . 4. for x4 and x8 only. 8gb: x4, x8, x16 ddr4 sdram current specifications C patterns and test conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 318 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 138: i dd1 measurement C loop pattern 1 ck_c, ck_t, cke sub-loop cycle number command cs_n act_n ras_n/a16 cas_n/a15 we_n/a14 odt bg[1:0] 2 ba[1:0] a12/bc_n a[17,13,11]] a[10]/ap a[9:7] a[6:3] a[2:0] data 3 toggling static high 0 0 act 00000000000000 C 1, 2 d, d 10000000000000 C 3, 4 d_n, d_n 1 1 1 1 1 0 3 3 0 0 0 7 f 0 C ... repeat pattern 1...4 until nrcd - al - 1; truncate if necessary n rcd - al rd 0 1 1 0 1 0 0 0 0 0 0 0 0 0 d0 = 00, d1 = ff, d2 = ff, d3 = 00, d4 = ff, d5 = 00, d5 = 00, d7 = ff ... repeat pattern 1...4 until nras - 1; truncate if necessary n ras pre 01010000000000 ... repeat pattern 1...4 until nrc - 1; truncate if necessary 1 1 n rc + 0 act 00011011000000 C 1 nrc + 1, 2 d, d 10000000000000 C 1 nrc + 3, 4 d_n, d_n 1 1 1 1 1 0 3 3 0 0 0 7 f 0 C ... repeat pattern nrc + 1...4 until 1 nrc + nras - 1; truncate if necessary 1 nrc +nrcd - al rd 0 1 1 0 1 0 1 1 0 0 0 0 0 0 d0 = ff, d1 = 00, d2 = 00, d3 = ff, d4 = 00, d5 = ff, d5 = ff, d7 = 00 ... repeat pattern 1...4 until nras - 1; truncate if necessary 1 nrc + nras pre 01010011000000 ... repeat pattern nrc + 1...4 until 2 nrc - 1; truncate if necessary 2 2 nrc repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 2 instead 3 3 nrc repeat sub-loop 0, use bg[1:0] = 1, use ba[1:0] = 3 instead 4 4 nrc repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 1 instead 5 5 nrc repeat sub-loop 0, use bg[1:0] = 1, use ba[1:0] = 2 instead 6 6 nrc repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 3 instead 7 7 nrc repeat sub-loop 0, use bg[1:0] = 1, use ba[1:0] = 0 instead 8 9 nrc repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 0 instead 4 9 10 nrc repeat sub-loop 0, use bg[1:0] = 3, use ba[1:0] = 1 instead 4 10 11 nrc repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 2 instead 4 11 12 nrc repeat sub-loop 0, use bg[1:0] = 3, use ba[1:0] = 3 instead 4 12 13 nrc repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 1 instead 4 13 14 nrc repeat sub-loop 0, use bg[1:0] = 3, use ba[1:0] = 2 instead 4 14 15 nrc repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 3 instead 4 15 16 nrc repeat sub-loop 0, use bg[1:0] = 3, use ba[1:0] = 0 instead 4 notes: 1. dqs_t, dqs_c are v ddq when not toggling. 8gb: x4, x8, x16 ddr4 sdram current specifications C patterns and test conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 319 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
2. bg1 is a "don't care" for x16 devices. 3. dq signals are v ddq except when burst sequence drives each dq signal by a read com- mand. 4. for x4 and x8 only. table 139: i dd2n , i dd3n , and i pp3p measurement C loop pattern 1 ck_c, ck_t, cke sub-loop cycle number command cs_n act_n ras_n/a16 cas_n/a15 we_n/a14 odt bg[1:0] 2 ba[1:0] a12/bc_n a[17,13,11]] a[10]/ap a[9:7] a[6:3] a[2:0] data 3 toggling static high 0 0 d 10000000000000 C 1 d 10000000000000 C 2 d_n111110330007f0 C 3 d_n111110330007f0 C 1 4C7 repeat sub-loop 0, use bg[1:0] = 1, use ba[1:0] = 1 instead 2 8C11 repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 2 instead 3 12C15 repeat sub-loop 0, use bg[1:0] = 1, use ba[1:0] = 3 instead 4 16C19 repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 1 instead 5 20C23 repeat sub-loop 0, use bg[1:0] = 1, use ba[1:0] = 2 instead 6 24C27 repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 3 instead 7 28C31 repeat sub-loop 0, use bg[1:0] = 1, use ba[1:0] = 0 instead 8 32C35 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 0 instead 4 9 36C39 repeat sub-loop 0, use bg[1:0] = 3, use ba[1:0] = 1 instead 4 10 40C43 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 2 instead 4 11 44C47 repeat sub-loop 0, use bg[1:0] = 3, use ba[1:0] = 3 instead 4 12 48C51 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 1 instead 4 13 52C55 repeat sub-loop 0, use bg[1:0] = 3, use ba[1:0] = 2 instead 4 14 56C59 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 3 instead 4 15 60C63 repeat sub-loop 0, use bg[1:0] = 3, use ba[1:0] = 0 instead 4 notes: 1. dqs_t, dqs_c are v ddq . 2. bg1 is a "don't care" for x16 devices. 3. dq signals are v ddq . 4. for x4 and x8 only. 8gb: x4, x8, x16 ddr4 sdram current specifications C patterns and test conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 320 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 140: i dd2nt and i ddq2nt measurement C loop pattern 1 ck_c, ck_t, cke sub-loop cycle number command cs_n act_n ras_n/a16 cas_n/a15 we_n/a14 odt bg[1:0] 2 ba[1:0] a12/bc_n a[17,13,11]] a[10]/ap a[9:7] a[6:3] a[2:0] data 3 toggling static high 0 0 d 10000000000000 C 1 d 10000000000000 C 2 d_n111110330007f0 C 3 d_n111110330007f0 C 1 4C7 repeat sub-loop 0 with odt = 1, use bg[1:0] = 1, use ba[1:0] = 1 instead 2 8C11 repeat sub-loop 0 with odt = 0, use bg[1:0] = 0, use ba[1:0] = 2 instead 3 12C15 repeat sub-loop 0 with odt = 1, use bg[1:0] = 1, use ba[1:0] = 3 instead 4 16C19 repeat sub-loop 0 with odt = 0, use bg[1:0] = 0, use ba[1:0] = 1 instead 5 20C23 repeat sub-loop 0 with odt = 1, use bg[1:0] = 1, use ba[1:0] = 2 instead 6 24C27 repeat sub-loop 0 with odt = 0, use bg[1:0] = 0, use ba[1:0] = 3 instead 7 28C31 repeat sub-loop 0 with odt = 1, use bg[1:0] = 1, use ba[1:0] = 0 instead 8 32C35 repeat sub-loop 0 with odt = 0, use bg[1:0] = 2, use ba[1:0] = 0 instead 4 9 36C39 repeat sub-loop 0 with odt = 1, use bg[1:0] = 3, use ba[1:0] = 1 instead 4 10 40C43 repeat sub-loop 0 with odt = 0, use bg[1:0] = 2, use ba[1:0] = 2 instead 4 11 44C47 repeat sub-loop 0 with odt = 1, use bg[1:0] = 3, use ba[1:0] = 3 instead 4 12 48C51 repeat sub-loop 0 with odt = 0, use bg[1:0] = 2, use ba[1:0] = 1 instead 4 13 52C55 repeat sub-loop 0 with odt = 1, use bg[1:0] = 3, use ba[1:0] = 2 instead 4 14 56C59 repeat sub-loop 0 with odt = 0, use bg[1:0] = 2, use ba[1:0] = 3 instead 4 15 60C63 repeat sub-loop 0 with odt = 1, use bg[1:0] = 3, use ba[1:0] = 0 instead 4 notes: 1. dqs_t, dqs_c are v ssq . 2. bg1 is a "don't care" for x16 devices. 3. dq signals are v ssq . 4. for x4 and x8 only. 8gb: x4, x8, x16 ddr4 sdram current specifications C patterns and test conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 321 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 141: i dd4r measurement C loop pattern 1 ck_c, ck_t, cke sub-loop cycle number command cs_n act_n ras_n/a16 cas_n/a15 we_n/a14 odt bg[1:0] 2 ba[1:0] a12/bc_n a[17,13,11]] a[10]/ap a[9:7] a[6:3] a[2:0] data 3 toggling static high 0 0 rd 0 1 1 0 1 0 0 0 0 0 0 0 0 0 d0 = 00, d1 = ff, d2 = ff, d3 = 00, d4 = ff, d5 = 00, d5 = 00, d7 = ff 1 d 10000000000000 2, 3 d_n, d_n 111110330007f0 1 4 rd 0 1 1 0 1 0 1 1 0 0 0 7 f 0 d0 = ff, d1 = 00 d2 = 00, d3 = ff d4 = 00, d5 = ff d5 = ff, d7 = 00 5 d 10000000000000 6, 7 d_n, d_n 111110330007f0 2 8C11 repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 2 instead 3 12C15 repeat sub-loop 1, use bg[1:0] = 1, use ba[1:0] = 3 instead 4 16C19 repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 1 instead 5 20C23 repeat sub-loop 1, use bg[1:0] = 1, use ba[1:0] = 2 instead 6 24C27 repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 3 instead 7 28C31 repeat sub-loop 1, use bg[1:0] = 1, use ba[1:0] = 0 instead 8 32C35 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 0 instead 4 9 36C39 repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 1 instead 4 10 40C43 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 2 instead 4 11 44C47 repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 3 instead 4 12 48C51 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 1 instead 4 13 52C55 repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 2 instead 4 14 56C59 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 3 instead 4 15 60C63 repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 0 instead 4 notes: 1. dqs_t, dqs_c are v ddq when not toggling. 2. bg1 is a "don't care" for x16 devices. 3. burst sequence driven on each dq signal by a read command. outside burst operation, dq signals are v ddq . 4. for x4 and x8 only. 8gb: x4, x8, x16 ddr4 sdram current specifications C patterns and test conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 322 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 142: i dd4w measurement C loop pattern 1 ck_c, ck_t, cke sub-loop cycle number com- mand cs_n act_n ras_n/a1 6 cas_n/a1 5 we_n/a14 odt bg[1:0] 2 ba[1:0] a12/bc_n a[17,13,1 1]] a[10]/ap a[9:7] a[6:3] a[2:0] data 3 toggling static high 0 0 wr01100100000000d0 = 00, d1 = ff, d2 = ff, d3 = 00, d4 = ff, d5 = 00, d5 = 00, d7 = ff 1 d 10000100000000 2, 3 d_n, d_n 111101330007f0 1 4 wr011001110007f0d0 = ff, d1 = 00 d2 = 00, d3 = ff d4 = 00, d5 = ff d5 = ff, d7 = 00 5 d 10000100000000 6, 7 d_n, d_n 111101330007f0 2 8C11 repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 2 instead 3 12C15 repeat sub-loop 1, use bg[1:0] = 1, use ba[1:0] = 3 instead 4 16C19 repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 1 instead 5 20C23 repeat sub-loop 1, use bg[1:0] = 1, use ba[1:0] = 2 instead 6 24C27 repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 3 instead 7 28C31 repeat sub-loop 1, use bg[1:0] = 1, use ba[1:0] = 0 instead 8 32C35 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 0 instead 4 9 36C39 repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 1 instead 4 10 40C43 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 2 instead 4 11 44C47 repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 3 instead 4 12 48C51 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 1 instead 4 13 52C55 repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 2 instead 4 14 56C59 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 3 instead 4 15 60C63 repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 0 instead 4 notes: 1. dqs_t, dqs_c are v ddq when not toggling. 2. bg1 is a "don't care" for x16 devices. 3. burst sequence driven on each dq signal by write command. outside burst operation, dq signals are v ddq . 4. for x4 and x8 only. 8gb: x4, x8, x16 ddr4 sdram current specifications C patterns and test conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 323 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 143: i dd4wc measurement C loop pattern 1 ck_c, ck_t, cke sub-loop cycle number command cs_n act_n ras_n/a16 cas_n/a15 we_n/a14 odt bg[1:0] 3 ba[1:0] a12/bc_n a[17,13,11]] a[10]/ap a[9:7] a[6:3] a[2:0] data 4 toggling static high 0 0 wr01100100000000d0 = 00, d1 = ff, d2 = ff, d3 = 00, d4 = ff, d5 = 00, d8 = crc 1, 2 d, d10000100000000 3, 4 d_n, d_n 111101330007f0 1 5 wr011001110007f0d0 = ff, d1 = 00, d2 = 00, d3 = ff, d4 = 00, d5 = ff, d5 = ff, d7 = 00 d8 = crc 6, 7 d, d10000100000000 8, 9 d_n, d_n 111101330007f0 2 10C14 repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 2 instead 3 15C19 repeat sub-loop 1, use bg[1:0] = 1, use ba[1:0] = 3 instead 4 20C24 repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 1 instead 5 25C29 repeat sub-loop 1, use bg[1:0] = 1, use ba[1:0] = 2 instead 6 30C34 repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 3 instead 7 35C39 repeat sub-loop 1, use bg[1:0] = 1, use ba[1:0] = 0 instead 8 40C44 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 0 instead 4 9 45C49 repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 1 instead 4 10 50C54 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 2 instead 4 11 55C59 repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 3 instead 4 12 60C64 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 1 instead 4 13 65C69 repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 2 instead 4 14 70C74 repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 3 instead 4 15 75C79 repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 0 instead 4 notes: 1. pattern provided for reference only. 2. dqs_t, dqs_c are v ddq when not toggling. 3. bg1 is a "don't care" for x16 devices. 4. burst sequence driven on each dq signal by write command. outside burst operation, dq signals are v ddq . 5. for x4 and x8 only. 8gb: x4, x8, x16 ddr4 sdram current specifications C patterns and test conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 324 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 144: i dd5r measurement C loop pattern 1 ck_c, ck_t, cke sub-loop cycle number command cs_n act_n ras_n/a16 cas_n/a15 we_n/a14 odt bg[1:0] 2 ba[1:0] a12/bc_n a[17,13,11]] a[10]/ap a[9:7] a[6:3] a[2:0] data 3 toggling static high 0 0 ref01001000000000 C 1 1 d 10000000000000 C 2 d 10000000000000 C 3 d_n111110330007f0 C 4 d_n111110330007f0 C 5C8 repeat pattern 1...4, use bg[1:0] = 1, use ba[1:0] = 1 instead 9C12 repeat pattern 1...4, use bg[1:0] = 0, use ba[1:0] = 2 instead 13C16 repeat pattern 1...4, use bg[1:0] = 1, use ba[1:0] = 3 instead 17C20 repeat pattern 1...4, use bg[1:0] = 0, use ba[1:0] = 1 instead 21C24 repeat pattern 1...4, use bg[1:0] = 1, use ba[1:0] = 2 instead 25C28 repeat pattern 1...4, use bg[1:0] = 0, use ba[1:0] = 3 instead 29C32 repeat pattern 1...4, use bg[1:0] = 1, use ba[1:0] = 0 instead 33C36 repeat pattern 1...4, use bg[1:0] = 2, use ba[1:0] = 0 instead 4 37C40 repeat pattern 1...4, use bg[1:0] = 3, use ba[1:0] = 1 instead 4 41C44 repeat pattern 1...4, use bg[1:0] = 2, use ba[1:0] = 2 instead 4 45C48 repeat pattern 1...4, use bg[1:0] = 3, use ba[1:0] = 3 instead 4 49C52 repeat pattern 1...4, use bg[1:0] = 2, use ba[1:0] = 1 instead 4 53C56 repeat pattern 1...4, use bg[1:0] = 3, use ba[1:0] = 2 instead 4 57C60 repeat pattern 1...4, use bg[1:0] = 2, use ba[1:0] = 3 instead 4 61C64 repeat pattern 1...4, use bg[1:0] = 3, use ba[1:0] = 0 instead 4 2 65... nrefi - 1 repeat sub-loop 1; truncate if necessary notes: 1. dqs_t, dqs_c are v ddq . 2. bg1 is a "don't care" for x16 devices. 3. dq signals are v ddq . 4. for x4 and x8 only. 8gb: x4, x8, x16 ddr4 sdram current specifications C patterns and test conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 325 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 145: i dd7 measurement C loop pattern 1 ck_t, ck_c cke sub-loop cycle number command cs_n act_n ras_n/a16 cas_n/a15 we_n/a14 odt bg[1:0] 2 ba[1:0] a12/bc_n a[17,13,11]] a[10]/ap a[9:7] a[6:3] a[2:0] data 3 toggling static high 0 0 act00000000000000 C 1 rda01101000001000 2 d 10000000000000 C 3 d_n111110330007f0 C ... repeat pattern 2...3 until nrrd - 1, if n rrd > 4. truncate if necessary 1 n rrd act00000011000000 C n rrd+1 rda 0 1 1 0 1 0 1 1 0 0 1 0 0 0 ... repeat pattern 2...3 until 2 nrrd - 1, if n rrd > 4. truncate if necessary 2 2 nrrd repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 2 instead 3 3 nrrd repeat sub-loop 1, use bg[1:0] = 1, use ba[1:0] = 3 instead 4 4 n rrd repeat pattern 2...3 until n faw - 1, if n faw > 4 n rrd. truncate if necessary 5 n faw repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 1 instead 6 n faw + nrrd repeat sub-loop 1, use bg[1:0] = 1, use ba[1:0] = 2 instead 7 n faw + 2 nrrd repeat sub-loop 0, use bg[1:0] = 0, use ba[1:0] = 3 instead 8 n faw + 3 nrrd repeat sub-loop 1, use bg[1:0] = 1, use ba[1:0] = 0 instead 9 n faw + 4 nrrd repeat sub-loop 4 10 2 n faw repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 0 instead 11 2 n faw + nrrd repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 1 instead 12 2 n faw + 2 nrrd repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 2 instead 13 2 n faw + 3 nrrd repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 3 instead 14 2 n faw + 4 nrrd repeat sub-loop 4 15 3 n faw repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 1 instead 16 3 n faw + nrrd repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 2 instead 17 3 n faw + 2 nrrd repeat sub-loop 0, use bg[1:0] = 2, use ba[1:0] = 3 instead 18 3 n faw + 3 nrrd repeat sub-loop 1, use bg[1:0] = 3, use ba[1:0] = 0 instead 19 3 nf aw + 4 nrrd repeat sub-loop 4 20 4 n faw repeat pattern 2...3 until nrc - 1, if nrc > 4 n faw. truncate if necessary notes: 1. dqs_t, dqs_c are v ddq . 2. bg1 is a "don't care" for x16 devices. 3. dq signals are v ddq except when burst sequence drives each dq signal by a read com- mand. 8gb: x4, x8, x16 ddr4 sdram current specifications C patterns and test conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 326 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
4. for x4 and x8 only. i dd specifications table 146: timings used for i dd , i pp , and i ddq measurement C loop patterns symbol ddr4-1600 ddr4-1866 ddr4-2133 ddr4-2400 ddr4-2666 ddr4-2933 ddr4-3200 uni t 10-10-10 11-11-11 12-12-12 12-12-12 13-13-13 14-14-14 14-14-14 15-15-15 16-16-16 15-15-15 16-16-16 17-17-17 17-17-17 18-18-18 19-19-19 20-20-20 21-21-21 22-22-22 20-20-20 22-22-22 24-24-24 t ck 1.25 1.071 0.937 0.833 0.75 0.682 0.625 ns cl 10 11 12 12 13 14 14 15 16 15 16 17 17 18 19 20 21 22 20 22 24 ck cwl 9 111110121211141412161614 18 18 14 18 18 16 20 20ck n rcd 10 11 12 12 13 14 14 15 16 15 16 17 17 18 19 19 20 21 20 22 24 ck n rc 38 39 40 44 45 46 50 51 52 54 55 57 60 61 62 66 67 68 72 74 76 ck n rp 10 11 12 12 13 14 14 15 16 15 16 17 17 18 19 19 20 21 20 22 24 ck n ras 28 32 36 39 43 47 52 ck nfa w x4 1 16 16 16 16 16 16 16 ck x8 20 22 23 26 28 31 34 ck x1 6 28 28 32 36 40 44 48 ck nrrd _s x4 4 4 4 4 4 4 4 ck x8 4 4 4 4 4 4 4 ck x1 6 5567 7 8 9c k nrrd _l x4 5 5 6 6 7 8 8 ck x8 5 5 6 6 7 8 8 ck x1 6 6678 9 1 01 1c k n ccd_s 4 4 4 4 4 4 4 ck n ccd_l 5 5 6 6 7 8 8 ck n wtr_s 2 3 3 3 4 4 4 ck n wtr_l 6 7 8 9 10 11 12 ck n refi 6,240 7,283 8,324 9,364 10,400 11,437 12,480 ck n rfc 2gb 128 150 171 193 214 235 256 ck n rfc 4gb 208 243 278 313 347 382 416 ck n rfc 8gb 280 327 374 421 467 514 560 ck nrfc 16gb 440 514 587 660 734 807 880 ck note: 1. 1kb based x4 use same numbers of clocks for n faw as the x8. 8gb: x4, x8, x16 ddr4 sdram current specifications C patterns and test conditions 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 327 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
current specifications C limits table 147: i dd , i pp , and i ddq current limits; die rev. a symbol width ddr4-2133 ddr4-2400 ddr4-2666 ddr4-2933 unit i dd0 : one bank activate-to-pre- charge current x4, x8 55 60 65 tbd ma x16 85 90 95 tbd ma i pp0 : one bank activate-to-precharge i pp current x4, x8 3 3 3 tbd ma x16 4 4 4 tbd ma i dd1 : one bank activate-to-readto- precharge current x4, x8 70 75 80 tbd ma x16 105 110 115 tbd ma i dd2n : precharge standby current x4, x8 45 50 55 tbd ma x16 65 70 75 tbd ma i dd2nt : precharge standby odt current x4, x8 55 60 65 tbd ma x16 75 80 90 tbd ma i dd2p : precharge power-down current x4, x8 25 30 35 tbd ma x16 45 50 55 tbd ma i dd2q : precharge quiet standby current x4, x8 45 45 50 tbd ma x16 65 65 70 tbd ma i dd3n : active standby current x4, x8 55 55 60 tbd ma x16 75 75 85 tbd ma i pp3n : active standby i pp current all 3 3 3 tbd ma i dd3p : active power-down current x4, x8 35 40 40 tbd ma x16 55 60 65 tbd ma i dd4r : burst read current x4 135 145 160 tbd ma x8 150 150 175 tbd ma x16 210 230 250 tbd ma i dd4w : burst write current x4 135 145 160 tbd ma x8 150 160 175 tbd ma x16 210 230 250 tbd ma i dd5r : burst refresh current (1x ref) x4, x8 64 64 68 tbd ma x16 84 84 94 tbd ma i pp5r : burst refresh i pp current (1x ref) x4, x8 5 5 5 tbd ma x16 5 5 5 tbd ma i dd6n : self refresh current; 0C85c 1 x4, x8 30 30 30 tbd ma x16 30 30 30 ma i dd6e : self refresh current; 0C95c 2 x4, x8 35 35 35 tbd ma x16 50 50 50 ma i dd6r : self refresh current; 0C45c 3,4 x4, x8 25 25 25 tbd ma x16 25 25 25 ma i dd6a : auto self refresh current (25c) 4 x4, x8 20 20 20 tbd ma x16 20 20 20 ma 8gb: x4, x8, x16 ddr4 sdram current specifications C limits 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 328 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 147: i dd , i pp , and i ddq current limits; die rev. a (continued) symbol width ddr4-2133 ddr4-2400 ddr4-2666 ddr4-2933 unit i dd6a : auto self refresh current (45c) 4 x4, x8 25 25 25 tbd ma x16 25 25 25 ma i dd6a : auto self refresh current (75c) 4 x4, x8 35 35 35 tbd ma x16 50 50 50 ma i pp6x : auto self refresh i pp current 25 all 5 5 5 ma i dd7 : bank interleave read current x4 250 255 265 tbd ma x8 200 205 215 tbd ma x16 265 270 280 ma i pp7 : bank interleave read i pp current x4 25 25 25 tbd ma x8 15 15 15 tbd x16 20 20 20 tbd ma i dd8 : maximum power-down current all 20 20 20 tbd ma notes: 1. applicable for mr2 settings a7 = 0 and a6 = 0; manual mode with normal temperature range of operation (0C85c). 2. applicable for mr2 settings a7 = 1 and a7 = 0; manual mode with extended tempera- ture range of operation (0C95c). 3. applicable for mr2 settings a7 = 0 and a7 = 1; manual mode with reduced temperature range of operation (0C45c). 4. i dd6r and i dd6a values are typical. 5. when additive latency is enabled for i dd0 , current changes by approximately 0%. 6. when additive latency is enabled for i dd1 , current changes by approximately +5%(x4/x8), +4%(x16). 7. when additive latency is enabled for i dd2n , current changes by approximately +0%. 8. when dll is disabled for i dd2n , current changes by approximately C23%. 9. when cal is enabled for i dd2n , current changes by approximately C25%. 10. when gear-down is enabled for i dd2n , current changes by approximately 0%. 11. when ca parity is enabled for i dd2n , current changes by approximately +7%. 12. when additive latency is enabled for i dd3n , current changes by approximately +0.6%. 13. when additive latency is enabled for i dd4r , current changes by approximately +5%. 14. when read dbi is enabled for i dd4r , current changes by approximately 0%. 15. when additive latency is enabled for i dd4w , current changes by approximately +3%(x4/ x8), +4%(x16). 16. when write dbi is enabled for i dd4w , current changes by approximately 0%. 17. when write crc is enabled for i dd4w , current changes by approximately +10%(x4/x8), +10%(x16). 18. when ca parity is enabled for i dd4w , current changes by approximately +12% (x8), +12% (x16). 19. when 2x ref is enabled for i dd5r , current changes by approximately C14%. 20. when 4x ref is enabled for i dd5r , current changes by approximately C33%. 21. i pp0 test and limit is applicable for i dd0 and i dd1 conditions. 22. i pp3n test and limit is applicable for all i dd2x , i dd3x , i dd4x and i dd8 conditions; that is, test- ing i pp3n should satisfy the i pp s for the noted i dd tests. 23. ddr4-1600 and ddr4-1866 use the same i dd limits as ddr4-2133. 8gb: x4, x8, x16 ddr4 sdram current specifications C limits 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 329 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
24. the i dd values must be derated (increased) when operated outside of the range 0c t c 85c: when t c < 0c: i dd2p0 , i dd2p1 , and i dd3p must be derated by 6%; i dd4r and i dd4w must be derated by 4%; i dd6 , i dd6et , and i dd7 must be derated by 11%. when t c > 85c: i dd0 , i dd1 , i dd2n , i dd2nt , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , and i dd5r must be derated by 3%; i dd2px must be derated by 40%. 25. i pp6x is applicable to i dd6n , i dd6e , i dd6r and i dd6a conditions. table 148: i dd , i pp , and i ddq current limits; die rev. b symbol width ddr4-2133 ddr4-2400 ddr4-2666 ddr4-2933 ddr4-3200 unit i dd0 : one bank activate-to- precharge current x4 40 43 46 49 52 ma x8 45 48 51 54 57 ma x16 75 80 85 90 95 ma i pp0 : one bank activate-to- precharge i pp current x4, x8 3 3 3 3 3 ma x16 4 4 4 4 4 ma i dd1 : one bank activate-to- readto- precharge current x4 52 55 58 61 64 ma x8 57 60 63 66 69 ma x16 95 100 105 110 115 ma i dd2n : precharge standby current x4, x8 33 34 35 36 37 ma x16 33 34 35 36 37 ma i dd2nt : precharge standby odt current x4, x8 45 50 50 55 60 ma x16 67 75 75 78 81 ma i dd2p : precharge power- down current x4, x8 25 25 25 25 25 ma x16 25 25 25 25 25 ma i dd2q : precharge quiet stand- by current x4, x8 30 30 30 30 30 ma x16 30 30 30 30 30 ma i dd3n : active standby current x4 35 38 41 44 47 ma x8 40 43 46 49 52 ma x16 44 47 50 53 56 ma i pp3n : active standby i pp cur- rent all 3 3 3 3 3 ma i dd3p : active power-down current x4 30 32 34 36 38 ma x8 35 37 39 41 43 ma x16 39 41 43 45 47 ma i dd4r : burst read current x4 100 110 121 132 143 ma x8 125 135 146 157 168 ma x16 225 243 263 283 302 ma i dd4w : burst write current x4 95 103 112 121 130 ma x8 115 123 132 141 150 ma x16 213 228 244 261 278 ma i dd5r : burst refresh current (1x ref) x4, x8 50 53 56 59 62 ma x16 56 59 61 64 67 ma 8gb: x4, x8, x16 ddr4 sdram current specifications C limits 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 330 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 148: i dd , i pp , and i ddq current limits; die rev. b (continued) symbol width ddr4-2133 ddr4-2400 ddr4-2666 ddr4-2933 ddr4-3200 unit i pp5r : burst refresh i pp cur- rent (1x ref) x4, x8 5 5 5 5 28 ma x16 5 5 5 5 28 ma i dd6n : self refresh current; 0C 85c 1 x4, x8 30 30 30 30 30 ma x16 30 30 30 30 30 ma i dd6e : self refresh current; 0C 95c 2 x4, x8 35 35 35 35 35 ma x16 35 35 35 35 35 ma i dd6r : self refresh current; 0C 45c 3,4 x4, x8 20 20 20 20 20 ma x16 20 20 20 20 20 ma i dd6a : auto self refresh cur- rent (25c) 4 x4, x8 8.6 8.6 8.6 8.6 8.6 ma x16 8.6 8.6 8.6 8.6 8.6 ma i dd6a : auto self refresh cur- rent (45c) 4 x4, x8 20 20 20 20 20 ma x16 20 20 20 20 20 ma i dd6a : auto self refresh cur- rent (75c) 4 x4, x8 30 30 30 30 30 ma x16 30 30 30 30 30 ma i pp6x : auto self refresh i pp current 25 all 5 5 5 5 5 ma i dd7 : bank interleave read current x4 175 185 200 215 230 ma x8 170 175 180 185 190 ma x16 239 249 259 269 279 ma i pp7 : bank interleave read i pp current x4 16 17 18 19 20 ma x8 15 15 15 15 15 ma x16 20 20 20 20 20 ma i dd8 : maximum power-down current all 25 25 25 25 25 ma notes: 1. applicable for mr2 settings a7 = 0 and a6 = 0; manual mode with normal temperature range of operation (0C85c). 2. applicable for mr2 settings a7 = 1 and a7 = 0; manual mode with extended tempera- ture range of operation (0C95c). 3. applicable for mr2 settings a7 = 0 and a7 = 1; manual mode with reduced temperature range of operation (0C45c). 4. i dd6r and i dd6a values are typical. 5. when additive latency is enabled for i dd0 , current changes by approximately 0%. 6. when additive latency is enabled for i dd1 , current changes by approximately +5%(x4/x8), +4%(x16). 7. when additive latency is enabled for i dd2n , current changes by approximately +0%. 8. when dll is disabled for i dd2n , current changes by approximately C23%. 9. when cal is enabled for i dd2n , current changes by approximately C25%. 10. when gear-down is enabled for i dd2n , current changes by approximately 0%. 11. when ca parity is enabled for i dd2n , current changes by approximately +7%. 12. when additive latency is enabled for i dd3n , current changes by approximately +0.6%. 13. when additive latency is enabled for i dd4r , current changes by approximately +5%. 14. when read dbi is enabled for i dd4r , current changes by approximately 0%. 8gb: x4, x8, x16 ddr4 sdram current specifications C limits 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 331 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
15. when additive latency is enabled for i dd4w , current changes by approximately +3%(x4/ x8), +4%(x16). 16. when write dbi is enabled for i dd4w , current changes by approximately 0%. 17. when write crc is enabled for i dd4w , current changes by approximately +10%(x4/x8), +10%(x16). 18. when ca parity is enabled for i dd4w , current changes by approximately +12% (x8), +12% (x16). 19. when 2x ref is enabled for i dd5r , current changes by approximately C14%. 20. when 4x ref is enabled for i dd5r , current changes by approximately C33%. 21. i pp0 test and limit is applicable for i dd0 and i dd1 conditions. 22. i pp3n test and limit is applicable for all i dd2x , i dd3x , i dd4x and i dd8 conditions; that is, test- ing i pp3n should satisfy the i pp s for the noted i dd tests. 23. ddr4-1600 and ddr4-1866 use the same i dd limits as ddr4-2133. 24. the i dd values must be derated (increased) when operated outside of the range 0c t c 85c: when t c < 0c: i dd2p0 , i dd2p1 , and i dd3p must be derated by 6%; i dd4r and i dd4w must be derated by 4%; i dd6 , i dd6et , and i dd7 must be derated by 11%. when t c > 85c: i dd0 , i dd1 , i dd2n , i dd2nt , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , and i dd5r must be derated by 3%; i dd2px must be derated by 40%. 25. i pp6x is applicable to i dd6n , i dd6e , i dd6r and i dd6a conditions. table 149: i dd , i pp , and i ddq current limits; die rev. d symbol width ddr4-2133 ddr4-2400 ddr4-2666 ddr4-2933 ddr4-3200 unit i dd0 : one bank activate-to- precharge current x4 40 43 46 49 52 ma x8 45 48 51 54 57 ma x16 75 80 85 90 95 ma i pp0 : one bank activate-to- precharge i pp current x4, x8 3 3 3 3 3 ma x16 4 4 4 4 4 ma i dd1 : one bank activate-to- readto- precharge current x4 52 55 58 61 64 ma x8 57 60 63 66 69 ma x16 95 100 105 110 115 ma i dd2n : precharge standby current x4, x8 33 34 35 36 37 ma x16 33 34 35 36 37 ma i dd2nt : precharge standby odt current x4, x8 45 50 50 55 60 ma x16 67 75 75 78 81 ma i dd2p : precharge power- down current x4, x8 25 25 25 25 25 ma x16 25 25 25 25 25 ma i dd2q : precharge quiet stand- by current x4, x8 30 30 30 30 30 ma x16 30 30 30 30 30 ma i dd3n : active standby current x4 40 43 46 49 52 ma x8 45 48 51 54 56 ma x16 49 52 55 58 61 ma i pp3n : active standby i pp cur- rent all 3 3 3 3 3 ma 8gb: x4, x8, x16 ddr4 sdram current specifications C limits 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 332 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 149: i dd , i pp , and i ddq current limits; die rev. d (continued) symbol width ddr4-2133 ddr4-2400 ddr4-2666 ddr4-2933 ddr4-3200 unit i dd3p : active power-down current x4 30 32 34 36 38 ma x8 35 37 39 41 43 ma x16 39 41 43 45 47 ma i dd4r : burst read current x4 100 110 121 132 143 ma x8 125 135 146 157 168 ma x16 225 243 263 283 302 ma i dd4w : burst write current x4 105 113 122 130 140 ma x8 125 132 142 150 160 ma x16 225 240 255 270 290 ma i dd5r : burst refresh current (1x ref) x4, x8 56 58 61 64 66 ma x16 61 64 67 69 72 ma i pp5r : burst refresh i pp cur- rent (1x ref) x4, x8 5 5 5 5 5 ma x16 5 5 5 5 5 ma i dd6n : self refresh current; 0C 85c 1 x4, x8 31 31 31 31 31 ma x16 31 31 31 31 31 ma i dd6e : self refresh current; 0C 95c 2 x4, x8 36 36 36 36 36 ma x16 36 36 36 36 36 ma i dd6r : self refresh current; 0C 45c 3,4 x4, x8 21 21 21 21 21 ma x16 21 21 21 21 21 ma i dd6a : auto self refresh cur- rent (25c) 4 x4, x8 8.6 8.6 8.6 8.6 8.6 ma x16 8.6 8.6 8.6 8.6 8.6 ma i dd6a : auto self refresh cur- rent (45c) 4 x4, x8 21 21 21 21 21 ma x16 21 21 21 21 21 ma i dd6a : auto self refresh cur- rent (75c) 4 x4, x8 31 31 31 31 31 ma x16 31 31 31 31 31 ma i pp6x : auto self refresh i pp current 26 all 5 5 5 5 5 ma i dd7 : bank interleave read current x4 175 185 200 215 230 ma x8 170 175 180 185 190 ma x16 239 249 259 269 279 ma i pp7 : bank interleave read i pp current x4 16 17 18 19 20 ma x8 15 15 15 15 15 ma x16 20 20 20 20 20 ma i dd8 : maximum power-down current all 25 25 25 25 25 ma notes: 1. until production data is obtain for these die revisions to derive more accurate limits, the targets set forth which are from die rev b, should be used temporarily. 2. applicable for mr2 settings a7 = 0 and a6 = 0; manual mode with normal temperature range of operation (0C85c). 8gb: x4, x8, x16 ddr4 sdram current specifications C limits 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 333 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
3. applicable for mr2 settings a7 = 1 and a7 = 0; manual mode with extended tempera- ture range of operation (0C95c). 4. applicable for mr2 settings a7 = 0 and a7 = 1; manual mode with reduced temperature range of operation (0C45c). 5. i dd6r and i dd6a values are typical. 6. when additive latency is enabled for i dd0 , current changes by approximately 0%. 7. when additive latency is enabled for i dd1 , current changes by approximately +5%(x4/x8), +4%(x16). 8. when additive latency is enabled for i dd2n , current changes by approximately +0%. 9. when dll is disabled for i dd2n , current changes by approximately C23%. 10. when cal is enabled for i dd2n , current changes by approximately C25%. 11. when gear-down is enabled for i dd2n , current changes by approximately 0%. 12. when ca parity is enabled for i dd2n , current changes by approximately +7%. 13. when additive latency is enabled for i dd3n , current changes by approximately +0.6%. 14. when additive latency is enabled for i dd4r , current changes by approximately +5%. 15. when read dbi is enabled for i dd4r , current changes by approximately 0%. 16. when additive latency is enabled for i dd4w , current changes by approximately +3%(x4/ x8), +4%(x16). 17. when write dbi is enabled for i dd4w , current changes by approximately 0%. 18. when write crc is enabled for i dd4w , current changes by approximately +10%(x4/x8), +10%(x16). 19. when ca parity is enabled for i dd4w , current changes by approximately +12% (x8), +12% (x16). 20. when 2x ref is enabled for i dd5r , current changes by approximately C14%. 21. when 4x ref is enabled for i dd5r , current changes by approximately C33%. 22. i pp0 test and limit is applicable for i dd0 and i dd1 conditions. 23. i pp3n test and limit is applicable for all i dd2x , i dd3x , i dd4x and i dd8 conditions; that is, test- ing i pp3n should satisfy the i pp s for the noted i dd tests. 24. ddr4-1600 and ddr4-1866 use the same i dd limits as ddr4-2133. 25. the i dd values must be derated (increased) when operated outside of the range 0c t c 85c: when t c < 0c: i dd2p0 , i dd2p1 , and i dd3p must be derated by 6%; i dd4r and i dd4w must be derated by 4%; i dd6 , i dd6et , and i dd7 must be derated by 11%. when t c > 85c: i dd0 , i dd1 , i dd2n , i dd2nt , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , and i dd5r must be derated by 3%; i dd2px must be derated by 40%. 26. i pp6x is applicable to i dd6n , i dd6e , i dd6r and i dd6a conditions. table 150: i dd , i pp , and i ddq current limits; die rev. e, g, h symbol width ddr4-2133 ddr4-2400 ddr4-2666 ddr4-2933 ddr4-3200 unit i dd0 : one bank activate-to- precharge current x4 40 43 46 49 52 ma x8 45 48 51 54 57 ma x16 75 80 85 90 95 ma i pp0 : one bank activate-to- precharge i pp current x4, x8 3 3 3 3 3 ma x16 4 4 4 4 4 ma i dd1 : one bank activate-to- readto- precharge current x4 52 55 58 61 64 ma x8 57 60 63 66 69 ma x16 95 100 105 110 115 ma 8gb: x4, x8, x16 ddr4 sdram current specifications C limits 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 334 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 150: i dd , i pp , and i ddq current limits; die rev. e, g, h (continued) symbol width ddr4-2133 ddr4-2400 ddr4-2666 ddr4-2933 ddr4-3200 unit i dd2n : precharge standby current x4, x8 33 34 35 36 37 ma x16 33 34 35 36 37 ma i dd2nt : precharge standby odt current x4, x8 45 50 50 55 60 ma x16 67 75 75 78 81 ma i dd2p : precharge power- down current x4, x8 25 25 25 25 25 ma x16 25 25 25 25 25 ma i dd2q : precharge quiet stand- by current x4, x8 30 30 30 30 30 ma x16 30 30 30 30 30 ma i dd3n : active standby current x4 40 43 46 49 52 ma x8 45 48 51 54 56 ma x16 49 52 55 58 61 ma i pp3n : active standby i pp cur- rent all 3 3 3 3 3 ma i dd3p : active power-down current x4 30 32 34 36 38 ma x8 35 37 39 41 43 ma x16 39 41 43 45 47 ma i dd4r : burst read current x4 100 110 121 132 143 ma x8 125 135 146 157 168 ma x16 225 243 263 283 302 ma i dd4w : burst write current x4 100 108 117 126 135 ma x8 120 128 137 146 155 ma x16 218 233 249 266 283 ma i dd5r : burst refresh current (1x ref) x4, x8 56 58 61 64 66 ma x16 61 64 67 69 72 ma i pp5r : burst refresh i pp cur- rent (1x ref) x4, x8 5 5 5 5 5 ma x16 5 5 5 5 5 ma i dd6n : self refresh current; 0C 85c 1 x4, x8 31 31 31 31 31 ma x16 31 31 31 31 31 ma i dd6e : self refresh current; 0C 95c 2 x4, x8 36 36 36 36 36 ma x16 36 36 36 36 36 ma i dd6r : self refresh current; 0C 45c 3,4 x4, x8 21 21 21 21 21 ma x16 21 21 21 21 21 ma i dd6a : auto self refresh cur- rent (25c) 4 x4, x8 8.6 8.6 8.6 8.6 8.6 ma x16 8.6 8.6 8.6 8.6 8.6 ma i dd6a : auto self refresh cur- rent (45c) 4 x4, x8 21 21 21 21 21 ma x16 21 21 21 21 21 ma i dd6a : auto self refresh cur- rent (75c) 4 x4, x8 31 31 31 31 31 ma x16 31 31 31 31 31 ma 8gb: x4, x8, x16 ddr4 sdram current specifications C limits 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 335 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 150: i dd , i pp , and i ddq current limits; die rev. e, g, h (continued) symbol width ddr4-2133 ddr4-2400 ddr4-2666 ddr4-2933 ddr4-3200 unit i pp6x : auto self refresh i pp current 26 all 5 5 5 5 5 ma i dd7 : bank interleave read current x4 175 185 200 215 230 ma x8 170 175 180 185 190 ma x16 239 249 259 269 279 ma i pp7 : bank interleave read i pp current x4 16 17 18 19 20 ma x8 15 15 15 15 15 ma x16 20 20 20 20 20 ma i dd8 : maximum power-down current all 25 25 25 25 25 ma notes: 1. until production data is obtain for these die revisions to derive more accurate limits, the targets set forth which are from die rev b, should be used temporarily. 2. applicable for mr2 settings a7 = 0 and a6 = 0; manual mode with normal temperature range of operation (0C85c). 3. applicable for mr2 settings a7 = 1 and a7 = 0; manual mode with extended tempera- ture range of operation (0C95c). 4. applicable for mr2 settings a7 = 0 and a7 = 1; manual mode with reduced temperature range of operation (0C45c). 5. i dd6r and i dd6a values are typical. 6. when additive latency is enabled for i dd0 , current changes by approximately 0%. 7. when additive latency is enabled for i dd1 , current changes by approximately +5%(x4/x8), +4%(x16). 8. when additive latency is enabled for i dd2n , current changes by approximately +0%. 9. when dll is disabled for i dd2n , current changes by approximately C23%. 10. when cal is enabled for i dd2n , current changes by approximately C25%. 11. when gear-down is enabled for i dd2n , current changes by approximately 0%. 12. when ca parity is enabled for i dd2n , current changes by approximately +7%. 13. when additive latency is enabled for i dd3n , current changes by approximately +0.6%. 14. when additive latency is enabled for i dd4r , current changes by approximately +5%. 15. when read dbi is enabled for i dd4r , current changes by approximately 0%. 16. when additive latency is enabled for i dd4w , current changes by approximately +3%(x4/ x8), +4%(x16). 17. when write dbi is enabled for i dd4w , current changes by approximately 0%. 18. when write crc is enabled for i dd4w , current changes by approximately +10%(x4/x8), +10%(x16). 19. when ca parity is enabled for i dd4w , current changes by approximately +12% (x8), +12% (x16). 20. when 2x ref is enabled for i dd5r , current changes by approximately C14%. 21. when 4x ref is enabled for i dd5r , current changes by approximately C33%. 22. i pp0 test and limit is applicable for i dd0 and i dd1 conditions. 23. i pp3n test and limit is applicable for all i dd2x , i dd3x , i dd4x and i dd8 conditions; that is, test- ing i pp3n should satisfy the i pp s for the noted i dd tests. 24. ddr4-1600 and ddr4-1866 use the same i dd limits as ddr4-2133. 25. the i dd values must be derated (increased) when operated outside of the range 0c t c 85c: 8gb: x4, x8, x16 ddr4 sdram current specifications C limits 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 336 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
when t c < 0c: i dd2p0 , i dd2p1 , and i dd3p must be derated by 6%; i dd4r and i dd4w must be derated by 4%; i dd6 , i dd6et , and i dd7 must be derated by 11%. when t c > 85c: i dd0 , i dd1 , i dd2n , i dd2nt , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , and i dd5r must be derated by 3%; i dd2px must be derated by 40%. 26. i pp6x is applicable to i dd6n , i dd6e , i dd6r and i dd6a conditions. 8gb: x4, x8, x16 ddr4 sdram current specifications C limits 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 337 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
speed bin tables ddr4 dram timing is primarily covered by two types of tables: the speed bin tables in this section and those tables found in the electrical characteristics and ac timing pa- rameters section. the timing parameter tables define the applicable timing specifica- tions based on the speed rating. the speed bin tables below list the t aa, t rcd, t rp, t ras and t rc limits of a given speed mark and are applicable to the cl settings in the lower half of the table provided they are applied in the correct clock range, which is noted. table 151: ddr4-1600 speed bins and operating conditions ddr4-1600 speed bin -125f -125e -125 unit cl-nrcd-nrp 10-10-10 11-11-11 12-12-12 parameter symbol min max min max min max internal read command to first data t aa 12.50 19.00 13.75 5 19.00 15.00 19.00 ns internal read command to first data with read dbi enabled t aa_dbi t aa (min) + 2nck t aa (max) + 2nck t aa (min) + 2nck t aa (max) + 2nck t aa (min) + 2nck t aa (max) + 2nck ns activate to internal read or write delay time t rcd 12.50 C 13.75 5 C 15.00 C ns precharge command period t rp 12.50 C 13.75 5 C 15.00 C ns activate-to-precharge command period t ras 35 9 t refi 35 9 t refi 35 9 t refi ns activate-to-activate or refresh command period t rc 6t ras + t rp C t ras + t rp C t ras + t rp Cns read: non- dbi read: dbi write symbol min max min max min max unit cl = 9 cl = 11 cwl = 9 t ck 4 1.5 1.9 1.5 1.9 reserved ns cl = 10 cl = 12 cwl = 9 t ck 4 1.5 1.9 1.5 1.9 1.5 1.9 ns cl = 10 cl = 12 cwl = 9, 11 t ck 4 1.25 <1.5 reserved reserved ns cl = 11 cl = 13 cwl = 9, 11 t ck 4 1.25 <1.5 1.25 <1.5 reserved ns cl = 12 cl = 14 cwl = 9, 11 t ck 4 1.25 <1.5 1.25 <1.5 1.25 <1.5 ns supported cl settings 9C12 9, 11, 12 10, 12 nck supported cl settings with read dbi 11C14 11, 13, 14 12, 14 nck supported cwl settings 9, 11 9, 11 9, 11 nck notes: 1. speed bin table is only valid with dll enabled and gear-down mode disabled. 2. when operating in 2 t ck write preamble mode, cwl must be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range. 3. the programmed value of cwl must be less than or equal to programmed value of cl. 4. t ck (avg) min. 5. the dram supports 13.5ns with cl9 operation at defined clock rates. 6. when calculating t rc and t rp in clocks, values may not be used in a combination that would violate t ras. 8gb: x4, x8, x16 ddr4 sdram speed bin tables 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 338 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 152: ddr4-1866 speed bins and operating conditions ddr4-1866 speed bin -107f -107e -107 unit cl-nrcd-nrp 12-12-12 13-13-13 14-14-14 parameter symbol min max min max min max internal read command to first data t aa 12.85 19.00 13.92 7 19.00 15.00 19.00 ns internal read command to first data with read dbi enabled t aa_dbi t aa (min) + 2nck t aa (max) + 2nck t aa (min) + 2nck t aa (max) + 2nck t aa (min) + 2nck t aa (max) + 2nck ns activate to internal read or write delay time t rcd 12.85 C 13.92 7 C 15.00 C ns precharge command period t rp 12.85 C 13.92 7 C 15.00 C ns activate-to-precharge command period t ras 34 9 t refi 34 9 t refi 34 9 t refi ns activate-to-activate or refresh command period t rc 8t ras + t rp C t ras + t rp C t ras + t rp Cns read: nondbi read: dbi write symbol min max min max min max unit cl = 9 cl = 11 cwl = 9 t ck 6 1.5 1.9 1.5 1.9 reserved ns cl = 10 cl = 12 cwl = 9 t ck 6 1.5 1.9 1.5 1.9 1.5 1.9 ns cl = 10 cl = 12 cwl = 11 t ck 6 reserved reserved reserved ns cl = 11 cl = 13 cwl = 9, 11 t ck 6 reserved 1.25 <1.5 reserved ns cl = 12 cl = 14 cwl = 9, 11 t ck 6 1.25 <1.5 1.25 <1.5 1.25 <1.5 ns cl = 12 cl = 14 cwl = 10, 12 t ck 6 1.071 <1.25 reserved reserved ns cl = 13 cl = 15 cwl = 10, 12 t ck 6 1.071 <1.25 1.071 <1.25 reserved ns cl = 14 cl = 16 cwl = 10, 12 t ck 6 1.071 <1.25 1.071 <1.25 1.071 <1.25 ns supported cl settings 9, 10, 12C14 9, 11C14 10, 12, 14 nck supported cl settings with read dbi 11,12,14-16 11, 13C16 12, 14, 16 nck supported cwl settings 9C12 9C12 9C12 nck notes: 1. speed bin table is only valid with dll enabled and gear-down mode disabled. 2. when operating in 2 t ck write preamble mode, cwl must be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range. 3. the programmed value of cwl must be less than or equal to programmed value of cl. 4. 12.85ns is the minimum value of t aa and t rp when operating at ddr4-1866 at t ck (avg) min = 1.071ns and is only a reference that does not consider the down binning strategy that 12.5ns supports. 5. 13.92ns is the minimum value of t aa and t rp when operating at ddr4-1866 at t ck (avg) min = 1.071ns and is only a reference that does not consider the down binning strategy that 13.75ns supports. 6. t ck (avg) min. 7. the dram supports 13.5ns with cl9 operation and 13.75ns with cl11 operation at de- fined clock rates. 8. when calculating t rc and t rp in clocks, values may not be used in a combination that would violate t ras. 8gb: x4, x8, x16 ddr4 sdram speed bin tables 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 339 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 153: ddr4-2133 speed bins and operating conditions ddr4-2133 speed bin -093f -093e -093 unit cl-nrcd-nrp 14-14-14 15-15-15 16-16-16 parameter symbol min max min max min max internal read command to first data t aa 13.13 19.00 14.06 5 19.00 15.00 19.00 ns internal read command to first data with read dbi enabled t aa_dbi t aa (min) + 2nck t aa (max) + 2nck t aa (min) + 2nck t aa (max) + 2nck t aa (min) + 2nck t aa (max) + 2nck ns activate to internal read or write delay time t rcd 13.13 C 14.06 5 C 15.00 C ns precharge command period t rp 13.13 C 14.06 5 C 15.00 C ns activate-to-precharge command period t ras 33 9 t refi 33 9 t refi 33 9 t refi ns activate-to-activate or refresh command period t rc 7t ras + t rp C t ras + t rp C t ras + t rp Cns read: nondbi read: dbi write symbol min max min max min max unit cl = 9 cl = 11 cwl = 9 t ck 4 1.5 1.9 1.5 1.9 reserved ns cl = 10 cl = 12 cwl = 9 t ck 4 1.5 1.9 1.5 1.9 1.5 1.9 cl = 11 cl = 13 cwl = 9 , 11 t ck 4 reserved 1.25 <1.5 reserved ns cl = 12 cl = 14 cwl = 9, 11 t ck 4 1.25 <1.5 1.25 <1.5 1.25 <1.5 ns cl = 13 cl = 15 cwl = 10, 12 t ck 4 reserved 1.071 <1.25 reserved ns cl = 14 cl = 16 cwl = 10, 12 t ck 4 1.071 <1.25 1.071 <1.25 1.071 <1.25 ns cl = 14 cl = 17 cwl = 11, 14 t ck 4 0.937 6 <1.071 reserved reserved ns cl = 15 cl = 18 cwl = 11, 14 t ck 4 0.937 <1.071 0.937 <1.071 reserved ns cl = 16 cl = 19 cwl = 11, 14 t ck 4 0.937 <1.071 0.937 <1.071 0.937 <1.071 ns supported cl settings 9, 10, 12, 14C16 9C16 10, 12, 14, 16 nck supported cl settings with read dbi 11, 12, 14, 16C19 11, 13C16,18,19 12, 14, 16, 19 nck supported cwl settings 9, 10, 11, 12, 14 9, 10, 11, 12, 14 9, 10, 11, 12, 14 nck notes: 1. speed bin table is only valid with dll enabled and gear-down mode disabled. 2. when operating in 2 t ck write preamble mode, cwl must be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range. 3. the programmed value of cwl must be less than or equal to programmed value of cl. 4. t ck (avg) min. 5. the dram supports 13.5ns with cl9 operation and 13.75ns with cl11 operation 13.92ns with cl13 operation at defined clock rates. 6. if the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing pa- rameters that are derived off the clock will use 0.938ns as its reference. for example, if t ck (min) = 0.938ns and t rp = 14.06ns, then t rp would require 15ncks (14.06ns/ 0.938ns), but if t ck (min) = 0.937ns and t rp = 14.06ns, then t rp would still require 15ncks (14.06ns/ 0.938ns) and not 16ncks (14.06ns/ 0.937ns). 7. when calculating t rc and t rp in clocks, values may not be used in a combination that would violate t ras. 8gb: x4, x8, x16 ddr4 sdram speed bin tables 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 340 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 154: ddr4-2400 speed bins and operating conditions ddr4-2400 speed bin -083f -083e -083 unit cl-nrcd-nrp 15-15-15 16-16-16 17-17-17 parameter symbol min max min max min max internal read command to first data t aa 12.5 19.00 13.32 19.00 14.16 19.00 ns internal read command to first data with read dbi enabled t aa_dbi t aa (min) + 3nck t aa (max) + 3nck t aa (min) + 3nck t aa (max) + 3nck t aa (min) + 3nck t aa (max) + 3nck ns activate to internal read or write delay time t rcd 12.5 C 13.32 C 14.16 C ns precharge command period t rp 12.5 C 13.32 C 14.16 C ns activate-to-precharge command period t ras 32 9 t refi 32 9 t refi 32 9 t refi ns activate-to-activate or refresh command period t rc 6t ras + t rp C t ras + t rp C t ras + t rp Cns read: nondbi read: dbi write symbol min max min max min max unit cl = 9 cl = 11 cwl = 9 t ck 4 1.5 1.9 1.5 1.9 reserved ns cl = 10 cl = 12 cwl = 9 t ck 4 1.5 1.9 1.5 1.9 1.5 1.9 ns cl = 10 cl = 12 cwl = 9, 11 t ck 4 reserved reserved reserved ns cl = 11 cl = 13 cwl = 9, 11 t ck 4 reserved 1.25 <1.5 1.25 <1.5 ns cl = 12 cl = 14 cwl = 9, 11 t ck 4 1.25 <1.5 1.25 <1.5 1.25 <1.5 ns cl = 12 cl = 14 cwl = 10, 12 t ck 4 reserved reserved reserved ns cl = 13 cl = 15 cwl = 10, 12 t ck 4 reserved 1.071 <1.25 1.071 <1.25 ns cl = 14 cl = 16 cwl = 10, 12 t ck 4 1.071 <1.25 1.071 <1.25 1.071 <1.25 ns cl = 14 cl =17 cwl = 11, 14 t ck 4 reserved reserved reserved ns cl = 15 cl = 18 cwl = 11, 14 t ck 4 reserved 0.937 5 <1.071 0.937 <1.071 ns cl = 16 cl = 19 cwl = 11, 14 t ck 4 0.937 <1.071 0.937 <1.071 0.937 <1.071 ns cl = 15 cl = 18 cwl = 12, 16 t ck 4 0.833 <0.937 reserved reserved ns cl = 16 cl = 19 cwl = 12, 16 t ck 4 0.833 <0.937 0.833 <0.937 reserved ns cl = 17 cl = 20 cwl = 12, 16 t ck 4 0.833 <0.937 0.833 <0.937 0.833 <0.937 ns cl = 18 cl = 21 cwl = 12, 16 t ck 4 0.833 <0.937 0.833 <0.937 0.833 <0.937 ns supported cl settings 9, 10, 12, 14C18 9C18 10C18 nck supported cl settings with read dbi 11, 12, 14, 16, 18-21 11, 13C16, 18C21 12C16, 18C21 nck supported cwl settings 9, 10, 11, 12, 14, 16 9, 10, 11, 12, 14, 16 9, 10, 11, 12, 14, 16 nck notes: 1. speed bin table is only valid with dll enabled and gear-down mode disabled. 2. when operating in 2 t ck write preamble mode, cwl must be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range. 3. the programmed value of cwl must be less than or equal to programmed value of cl. 4. t ck (avg) min. 8gb: x4, x8, x16 ddr4 sdram speed bin tables 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 341 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
5. if the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing pa- rameters that are derived off the clock will use 0.938ns as its reference. for example, if t ck (min) = 0.938ns and t rp = 14.06ns, then t rp would require 15ncks (14.06ns/ 0.938ns), but if t ck (min) = 0.937ns and t rp = 14.06ns, then t rp would still require 15ncks (14.06ns/ 0.938ns) and not 16ncks (14.06ns/ 0.937ns). 6. when calculating t rc and t rp in clocks, values may not be used in a combination that would violate t ras. table 155: ddr4-2666 speed bins and operating conditions ddr4-2666 speed bin -075f -075e -075 unit cl-nrcd-nrp 17-17-17 18-18-18 19-19-19 parameter symbol min max min max min max internal read command to first data t aa 12.75 19.00 13.5 19.00 14.25 5 19.00 ns internal read command to first data with read dbi enabled t aa_dbi t aa (min) + 3nck t aa (max) + 3nck t aa (min) + 3nck t aa (max) + 3nck t aa (min) + 3nck t aa (max) + 3nck ns activate to internal read or write delay time t rcd 12.75 C 13.5 C 14.25 5 Cns precharge command period t rp 12.75 C 13.5 C 14.25 5 Cns activate-to-precharge command period t ras 32 9 t refi 32 9 t refi 32 9 t refi ns activate-to-activate or refresh command period t rc 7t ras + t rp C t ras + t rp C t ras + t rp Cns read: nondbi read: dbi write symbol min max min max min max unit cl = 9 cl = 11 cwl = 9 t ck 4 1.5 1.9 1.5 1.9 reserved ns cl = 10 cl = 12 cwl = 9 t ck 4 1.5 1.9 1.5 1.9 1.5 1.9 ns cl = 10 cl = 12 cwl = 9, 11 t ck 4 reserved reserved reserved ns cl = 11 cl = 13 cwl = 9, 11 t ck 4 1.25 <1.5 1.25 <1.5 1.25 <1.5 ns cl = 12 cl = 14 cwl = 9, 11 t ck 4 1.25 <1.5 1.25 <1.5 1.25 <1.5 ns cl = 12 cl = 14 cwl = 10, 12 t ck 4 reserved reserved reserved ns cl = 13 cl = 15 cwl = 10, 12 t ck 4 1.071 <1.25 1.071 <1.25 1.071 <1.25 ns cl = 14 cl = 16 cwl = 10, 12 t ck 4 1.071 <1.25 1.071 <1.25 1.071 <1.25 ns cl = 14 cl =17 cwl = 11, 14 t ck 4 reserved reserved reserved ns cl = 15 cl = 18 cwl = 11, 14 t ck 4 0.937 6 <1.071 0.937 <1.071 0.937 <1.071 ns cl = 16 cl = 19 cwl = 11, 14 t ck 4 0.937 <1.071 0.937 <1.071 0.937 <1.071 ns cl = 15 cl = 18 cwl = 12, 16 t ck 4 reserved reserved reserved ns cl = 16 cl = 19 cwl = 12, 16 t ck 4 0.833 <0.937 reserved reserved ns cl = 17 cl = 20 cwl = 12, 16 t ck 4 0.833 <0.937 0.833 <0.937 0.833 <0.937 ns cl = 18 cl = 21 cwl = 12, 16 t ck 4 0.833 <0.937 0.833 <0.937 0.833 <0.937 ns cl = 17 cl = 20 cwl = 14, 18 t ck 4 0.750 <0.833 reserved reserved ns cl = 18 cl = 21 cwl = 14, 18 t ck 4 0.750 <0.833 0.750 <0.833 reserved ns cl = 19 cl = 22 cwl = 14, 18 t ck 4 0.750 <0.833 0.750 <0.833 0.750 <0.833 ns cl = 20 cl = 23 cwl = 14, 18 t ck 4 0.750 <0.833 0.750 <0.833 0.750 <0.833 ns 8gb: x4, x8, x16 ddr4 sdram speed bin tables 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 342 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 155: ddr4-2666 speed bins and operating conditions (continued) ddr4-2666 speed bin -075f -075e -075 unit cl-nrcd-nrp 17-17-17 18-18-18 19-19-19 parameter symbol min max min max min max supported cl settings 9C20 9C20 10,12-C20 nck supported cl settings with read dbi 11C16, 18C23 11C16, 18C23 12, 14C16, 18C23 nck supported cwl settings 9, 10, 11, 12, 14, 16, 18 9, 10, 11, 12, 14, 16, 18 9, 10, 11, 12, 14, 16, 18 nck notes: 1. speed bin table is only valid with dll enabled and gear-down mode disabled. 2. when operating in 2 t ck write preamble mode, cwl must be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range. 3. the programmed value of cwl must be less than or equal to programmed value of cl. 4. t ck (avg) min. 5. the dram supports 13.92ns with cl13 operation, 14.07ns with cl15 operation, and 14.16ns with cl17 operation at defined clock rates. 6. if the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing pa- rameters that are derived off the clock will use 0.938ns as its reference. for example, if t ck (min) = 0.938ns and t rp = 14.06ns, then t rp would require 15ncks (14.06ns/ 0.938ns), but if t ck (min) = 0.937ns and t rp = 14.06ns, then t rp would still require 15ncks (14.06ns/ 0.938ns) and not 16ncks (14.06ns/ 0.937ns). 7. when calculating t rc and t rp in clocks, values may not be used in a combination that would violate t ras. table 156: ddr4-2933 speed bins and operating conditions ddr4-2933 speed bin -068e -068 -068d unit cl-nrcd-nrp 20-20-20 21-21-21 22-22-22 parameter symbol min max min max min max internal read command to first data t aa 13.64 5 19.00 14.32 19.00 15 19.00 ns internal read command to first data with read dbi enabled t aa_dbi t aa (min) + 4nck t aa (max) + 4nck t aa (min) + 4nck t aa (max) + 4nck t aa (min) + 4nck t aa (max) + 4nck ns activate to internal read or write delay time t rcd 13.64 C 14.32 C 15 C ns precharge command period t rp 13.64 C 14.32 C 15 C ns activate-to-precharge command period t ras 32 9 t refi 32 9 t refi 32 9 t refi ns activate-to-activate or refresh command period t rc 6t ras + t rp C t ras + t rp C t ras + t rp Cns read: nondbi read: dbi write symbol min max min max min max unit cl = 9 cl = 11 cwl = 9 t ck 4 1.5 1.9 reserved reserved ns cl = 10 cl = 12 cwl = 9 t ck 4 1.5 1.9 1.5 1.9 1.5 1.9 ns cl = 10 cl = 12 cwl = 9, 11 t ck 4 reserved reserved reserved ns 8gb: x4, x8, x16 ddr4 sdram speed bin tables 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 343 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 156: ddr4-2933 speed bins and operating conditions (continued) ddr4-2933 speed bin -068e -068 -068d unit cl-nrcd-nrp 20-20-20 21-21-21 22-22-22 parameter symbol min max min max min max cl = 11 cl = 13 cwl = 9, 11 t ck 4 1.25 <1.5 1.25 <1.5 reserved ns cl = 12 cl = 14 cwl = 9, 11 t ck 4 1.25 <1.5 1.25 <1.5 1.25 <1.5 ns cl = 12 cl = 14 cwl = 10, 12 t ck 4 reserved reserved reserved ns cl = 13 cl = 15 cwl = 10, 12 t ck 4 1.071 <1.25 1.071 <1.25 reserved ns cl = 14 cl = 16 cwl = 10, 12 t ck 4 1.071 <1.25 1.071 <1.25 1.071 <1.25 ns cl = 14 cl =17 cwl = 11, 14 t ck 4 reserved reserved reserved ns cl = 15 cl = 18 cwl = 11, 14 t ck 4 0.937 6 <1.071 0.937 <1.071 reserved ns cl = 16 cl = 19 cwl = 11, 14 t ck 4 0.937 <1.071 0.937 <1.071 0.937 <1.071 ns cl = 15 cl = 18 cwl = 12, 16 t ck 4 reserved reserved reserved ns cl = 16 cl = 19 cwl = 12, 16 t ck 4 reserved reserved reserved ns cl = 17 cl = 20 cwl = 12, 16 t ck 4 0.833 <0.937 0.833 <0.937 reserved ns cl = 18 cl = 21 cwl = 12, 16 t ck 4 0.833 <0.937 0.833 <0.937 0.833 <0.937 ns cl = 17 cl = 20 cwl = 14, 18 t ck 4 reserved reserved reserved ns cl = 18 cl = 21 cwl = 14, 18 t ck 4 reserved reserved reserved ns cl = 19 cl = 22 cwl = 14, 18 t ck 4 0.750 <0.833 0.750 <0.833 0.750 <0.833 ns cl = 20 cl = 23 cwl = 14, 18 t ck 4 0.750 <0.833 0.750 <0.833 0.750 <0.833 ns cl = 19 cl = 23 cwl = 16, 20 t ck 4 reserved reserved reserved ns cl = 20 cl = 24 cwl = 16, 20 t ck 4 0.682 <0.750 reserved reserved ns cl = 21 cl = 26 cwl = 16, 20 t ck 4 0.682 <0.750 0.682 <0.750 reserved ns cl = 22 cl = 26 cwl = 16, 20 t ck 4 0.682 <0.750 0.682 <0.750 0.682 <0.750 ns supported cl settings 9-22 10-22 10, 12, 14, 16, 18, 20 nck supported cl settings with read dbi 11-24, 26 12-24, 26 12, 14, 16, 19, 21, 23, 26 nck supported cwl settings 9, 10, 11, 12, 14, 16, 18, 20 9, 10, 11, 12, 14, 16, 18, 20 9, 10, 11, 12, 14, 16, 18, 20 nck notes: 1. speed bin table is only valid with dll enabled and gear-down mode disabled. 2. when operating in 2 t ck write preamble mode, cwl must be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range. 3. the programmed value of cwl must be less than or equal to programmed value of cl. 4. t ck (avg) min. 5. the dram supports 13.5ns with cl9 operation. 6. if the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing pa- rameters that are derived off the clock will use 0.938ns as its reference. for example, if t ck (min) = 0.938ns and t rp = 14.06ns, then t rp would require 15ncks (14.06ns/ 0.938ns), but if t ck (min) = 0.937ns and t rp = 14.06ns, then t rp would still require 15ncks (14.06ns/ 0.938ns) and not 16ncks (14.06ns/ 0.937ns). 7. when calculating t rc and t rp in clocks, values may not be used in a combination that would violate t ras. 8gb: x4, x8, x16 ddr4 sdram speed bin tables 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 344 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 157: ddr4-3200 speed bins and operating conditions ddr4-3200 speed bin -062f -062e -062 unit cl-nrcd-nrp 20-20-20 22-22-22 24-24-24 parameter symbol min max min max min max internal read command to first data t aa 12.5 19.00 13.75 5 19.00 15 19.00 ns internal read command to first data with read dbi enabled t aa_dbi t aa (min) + 4nck t aa (max) + 4nck t aa (min) + 4nck t aa (max) + 4nck t aa (min) + 4nck t aa (max) + 4nck ns activate to internal read or write delay time t rcd 12.5 C 13.75 5 C15Cns precharge command period t rp 12.5 C 13.75 5 C15Cns activate-to-precharge command period t ras 32 9 t refi 32 9 t refi 32 9 t refi ns activate-to-activate or refresh command period t rc 6t ras + t rp C t ras + t rp C t ras + t rp Cns read: nondbi read: dbi write symbol min max min max min max unit cl = 9 cl = 11 cwl = 9 t ck 4 1.5 1.9 reserved reserved ns cl = 10 cl = 12 cwl = 9 t ck 4 1.5 1.9 1.5 1.9 1.5 1.9 ns cl = 10 cl = 12 cwl = 9, 11 t ck 4 reserved reserved reserved ns cl = 11 cl = 13 cwl = 9, 11 t ck 4 1.25 <1.5 1.25 <1.5 reserved ns cl = 12 cl = 14 cwl = 9, 11 t ck 4 1.25 <1.5 1.25 <1.5 1.25 <1.5 ns cl = 12 cl = 14 cwl = 10, 12 t ck 4 reserved reserved reserved ns cl = 13 cl = 15 cwl = 10, 12 t ck 4 1.071 <1.25 1.071 <1.25 reserved ns cl = 14 cl = 16 cwl = 10, 12 t ck 4 1.071 <1.25 1.071 <1.25 1.071 <1.25 ns cl = 14 cl =17 cwl = 11, 14 t ck 4 reserved reserved reserved ns cl = 15 cl = 18 cwl = 11, 14 t ck 4 0.937 6 <1.071 0.937 <1.071 reserved ns cl = 16 cl = 19 cwl = 11, 14 t ck 4 0.937 <1.071 0.937 <1.071 0.937 <1.071 ns cl = 15 cl = 18 cwl = 12, 16 t ck 4 reserved reserved reserved ns cl = 16 cl = 19 cwl = 12, 16 t ck 4 0.833 <0.937 reserved reserved ns cl = 17 cl = 20 cwl = 12, 16 t ck 4 0.833 <0.937 0.833 <0.937 reserved ns cl = 18 cl = 21 cwl = 12, 16 t ck 4 0.833 <0.937 0.833 <0.937 0.833 <0.937 ns cl = 17 cl = 20 cwl = 14, 18 t ck 4 reserved reserved reserved ns cl = 18 cl = 21 cwl = 14, 18 t ck 4 0.750 <0.833 reserved reserved ns cl = 19 cl = 22 cwl = 14, 18 t ck 4 0.750 <0.833 0.750 <0.833 reserved ns cl = 20 cl = 23 cwl = 14, 18 t ck 4 0.750 <0.833 0.750 <0.833 0.750 <0.833 ns cl = 20 cl = 24 cwl = 16, 20 t ck 4 0.625 <0.750 reserved reserved ns cl = 22 cl = 26 cwl = 16, 20 t ck 4 0.625 <0.750 0.625 <0.750 reserved ns cl = 24 cl = 28 cwl = 16, 20 t ck 4 0.625 <0.750 0.625 <0.750 0.625 <0.750 ns supported cl settings 9C20, 22, 24 10C20, 22, 24 10C20, 22, 24 nck supported cl settings with read dbi 11C24, 26, 28 12C16, 18C24, 26, 28 12, 14, 16, 19, 21, 23, 28 nck 8gb: x4, x8, x16 ddr4 sdram speed bin tables 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 345 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 157: ddr4-3200 speed bins and operating conditions (continued) ddr4-3200 speed bin -062f -062e -062 unit cl-nrcd-nrp 20-20-20 22-22-22 24-24-24 parameter symbol min max min max min max supported cwl settings 9, 10, 11, 12, 14, 16, 18, 20 9, 10, 11, 12, 14, 16, 18, 20 9, 10, 11, 12, 14, 16, 18, 20 nck notes: 1. speed bin table is only valid with dll enabled and gear-down mode disabled. 2. when operating in 2 t ck write preamble mode, cwl must be programmed to a value at least 1 clock greater than the lowest cwl setting supported in the applicable t ck range. 3. the programmed value of cwl must be less than or equal to programmed value of cl. 4. t ck (avg) min. 5. the dram requires 13.5ns for cl9 operation; jedec doesn't require cl9 support for a cl22 device. 6. if the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing pa- rameters that are derived off the clock will use 0.938ns as its reference. for example, if t ck (min) = 0.938ns and t rp = 14.06ns, then t rp would require 15ncks (14.06ns/ 0.938ns), but if t ck (min) = 0.937ns and t rp = 14.06ns, then t rp would still require 15ncks (14.06ns/ 0.938ns) and not 16ncks (14.06ns/ 0.937ns). 7. when calculating t rc and t rp in clocks, values may not be used in such a combination that would violate t ras. refresh parameters by device density table 158: refresh parameters by device density parameter symbol 2gb 4gb 8gb 16gb unit notes ref command to act or ref com- mand time t rfc (all bank groups) 160 260 350 550 ns average periodic refresh interval t refi 0c t c 85c 7.8 7.8 7.8 7.8 s 0c < t c 95c 3.9 3.9 3.9 3.9 s 1 note: 1. users should refer to the dram supplier data sheet and/or the dimm spd to determine if the devices support these options or requirements. 8gb: x4, x8, x16 ddr4 sdram refresh parameters by device density 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 346 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
electrical characteristics and ac timing parameters table 159: electrical characteristics and ac timing parameters: ddr4-1600 through ddr4-2400 parameter symbol ddr4-1600 ddr4-1866 ddr4-2133 ddr4-2400 unit notes min max min max min max min max clock timing clock period average (dll off mode) t ck (dll_off) 8 20 8 20 8 20 8 20 ns clock period average t ck (avg, dll_on) 1.25 1.9 1.071 1.9 0.937 1.9 0.833 1.9 ns 14 high pulse width average t ch (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t ck (avg) low pulse width average t cl (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t ck (avg) clock period jitter total t jitper_tot C63 63 C54 54 C47 47 C42 42 ps 18 , 19 deterministic t jitper_dj C31 31 C27 27 C23 23 C21 21 ps 18 dll locking t jitper,lck C50 50 C43 43 C38 38 -33 33 ps clock absolute period t ck (abs) min = t ck (avg) min + t jitper_tot min; max = t ck (avg) max + t jitper_tot max ps clock absolute high pulse width (includes duty cycle jitter) t ch (abs) 0.45 C 0.45 C 0.45 C 0.45 C t ck (avg) clock absolute low pulse width (includes duty cycle jitter) t cl (abs) 0.45 C 0.45 C 0.45 C 0.45 C t ck (avg) cycle-to-cycle jitter total t jitcc _tot C 125 C 107 C 94 C 83 ps dll locking t jitcc,lck C 100 C 86 C 75 C 67 ps 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 347 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 159: electrical characteristics and ac timing parameters: ddr4-1600 through ddr4-2400 (continued) parameter symbol ddr4-1600 ddr4-1866 ddr4-2133 ddr4-2400 unit notes min max min max min max min max cumulative error across 2 cycles t err2per C92 92 C79 79 C69 69 C61 61 ps 3 cycles t err3per C109 109 C94 94 C82 82 C73 73 ps 4 cycles t err4per C121 121 C104 104 C91 91 C81 81 ps 5 cycles t err5per C131 131 C112 112 C98 98 C87 87 ps 6 cycles t err6per C139 139 C119 119 C104 104 C92 92 ps 7 cycles t err7per C145 145 C124 124 C109 109 C97 97 ps 8 cycles t err8per C151 151 C129 129 C113 113 C101 101 ps 9 cycles t err9per C156 156 C134 134 C117 117 C104 104 ps 10 cycles t err10per C160 160 C137 137 C120 120 C107 107 ps 11 cycles t err11per C164 164 C141 141 C123 123 C110 110 ps 12 cycles t err12per C168 168 C144 144 C126 126 C112 112 ps n = 13, 14 . . . 49, 50 cycles t errnper t errnper min = (1 + 0.68ln[n]) t jitper_tot min t errnper max = (1 + 0.68ln[n]) t jitper_tot max ps dq input timing data setup time to dqs_t, dqs_c base (calibrated v ref ) t ds refer to dq input receiver specification section (approximately 0.15 t ck to 0.28 t ck ) C noncalibrated v ref t pda_s minimum of 0.5ui ui data hold time from dqs_t, dqs_c base (calibrated v ref ) t dh refer to dq input receiver specification section (approximately 0.15 t ck to 0.28 t ck ) C noncalibrated v ref t pda_h minimum of 0.5ui ui dq and dm minimum data pulse width for each input t dipw 0.58 C 0.58 C 0.58 C 0.58 C ui dq output timing (dll enabled) dqs_t, dqs_c to dq skew, per group, per access t dqsq C 0.16 C 0.16 C 0.16 C 0.17 ui dq output hold time from dqs_t, dqs_c t qh 0.76 C 0.76 C 0.76 C 0.74 C ui data valid window per device: t qh - t dqsq each devices output per ui t dvw d 0.63 0.63 0.64 0.64 ui data valid window per device, per pin: t qh - t dqsq each devices output per ui t dvw p 0.66 C 0.66 C 0.69 C 0.72 C ui 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 348 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 159: electrical characteristics and ac timing parameters: ddr4-1600 through ddr4-2400 (continued) parameter symbol ddr4-1600 ddr4-1866 ddr4-2133 ddr4-2400 unit notes min max min max min max min max dq low-z time from ck_t, ck_c t lzdq C450 225 C390 195 C360 180 C330 175 ps dq high-z time from ck_t, ck_c t hzdq C 225 C 195 C 180 C 175 ps dq strobe input timing dqs_t, dqs_c rising edge to ck_t, ck_c rising edge for 1 t ckpreamble t dqss 1ck C0.27 0.27 C0.27 0.27 C0.27 0.27 C0.27 0.27 ck dqs_t, dqs_c rising edge to ck_t, ck_c rising edge for 2 t ckpreamble t dqss 2ck C0.50 0.50 C0.50 0.50 C0.50 0.50 C0.50 0.50 ck dqs_t, dqs_c differential input low pulse width t dqsl 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 ck dqs_t, dqs_c differential input high pulse width t dqsh 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 ck dqs_t, dqs_c falling edge setup to ck_t, ck_c rising edge t dss 0.18 C 0.18 C 0.18 C 0.18 C ck dqs_t, dqs_c falling edge hold from ck_t, ck_c rising edge t dsh 0.18 C 0.18 C 0.18 C 0.18 C ck dqs_t, dqs_c differential write pream- ble for 1 t ckpreamble t wpre 1ck 0.9 C 0.9 C 0.9 C 0.9 C ck dqs_t, dqs_c differential write pream- ble for 2 t ckpreamble t wpre 2ck 1.8 C 1.8 C 1.8 C 1.8 C ck dqs_t, dqs_c differential write postam- ble t wpst 0.33 C 0.33 C 0.33 C 0.33 C ck dqs strobe output timing (dll enabled) dqs_t, dqs_c rising edge output access time from rising ck_t, ck_c t dqsck C225 225 C195 195 C180 180 C175 175 ps dqs_t, dqs_c rising edge output var- iance window per dram t dqscki C 370 C 330 C 310 C 290 ps dqs_t, dqs_c differential output high time t qsh 0.4 C 0.4 C 0.4 C 0.4 C ck dqs_t, dqs_c differential output low time t qsl 0.4 C 0.4 C 0.4 C 0.4 C ck dqs_t, dqs_c low-z time (rl - 1) t lzdqs C450 225 C390 195 C360 180 C330 175 ps dqs_t, dqs_c high-z time (rl + bl/2) t hzdqs C 225 C 195 C 180 C 175 ps 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 349 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 159: electrical characteristics and ac timing parameters: ddr4-1600 through ddr4-2400 (continued) parameter symbol ddr4-1600 ddr4-1866 ddr4-2133 ddr4-2400 unit notes min max min max min max min max dqs_t, dqs_c differential read pream- ble for 1 t ckpreamble t rpre 1ck 0.9 C 0.9 C 0.9 C 0.9 C ck 21 dqs_t, dqs_c differential read pream- ble for 2 t ck preamble t rpre 2ck 1.8 C 1.8 C 1.8 C 1.8 C ck 21 dqs_t, dqs_c differential read postam- ble t rpst 0.33 C 0.33 C 0.33 C 0.33 C ck 22 command and address timing dll locking time t dllk 597 C 597 C 768 C 768 C ck 2, 4 cmd, addr setup time to ck_t, ck_c base ref- erenced to v ih(ac) and vil(ac) levels base t is 115 C 100 C 80 C 62 C ps v refca t is vref 215 C 200 C 180 C 162 C ps cmd, addr hold time to ck_t, ck_c base ref- erenced to v ih(dc) and vil(dc) levels base t ih 140 C 125 C 105 C 87 C ps v refca t ih vref 215 C 200 C 180 C 162 C ps ctrl, addr pulse width for each input t ipw 600 C 525 C 460 C 410 C ps activate to internal read or write de- lay t rcd see speed bin tables for t rcd ns precharge command period t rp see speed bin tables for t rp ns activate-to-precharge command peri- od t ras see speed bin tables for t ras ns 13 activate-to-activate or ref command period t rc see speed bin tables for t rc ns 13 activate-to-activate command period to different bank groups for 1/2kb page size t rrd_s (1/2kb) min = greater of 4ck or 5ns min = greater of 4ck or 4.2ns min = greater of 4ck or 3.7ns min = greater of 4ck or 3.3ns ck 1 activate-to-activate command period to different bank groups for 1kb page size t rrd_s (1kb) min = greater of 4ck or 5ns min = greater of 4ck or 4.2ns min = greater of 4ck or 3.7ns min = greater of 4ck or 3.3ns ck 1 activate-to-activate command period to different bank groups for 2kb page size t rrd_s (2kb) min = greater of 4ck or 6ns min = greater of 4ck or 5.3ns min = greater of 4ck or 5.3ns min = greater of 4ck or 5.3ns ck 1 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 350 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 159: electrical characteristics and ac timing parameters: ddr4-1600 through ddr4-2400 (continued) parameter symbol ddr4-1600 ddr4-1866 ddr4-2133 ddr4-2400 unit notes min max min max min max min max activate-to-activate command period to same bank groups for 1/2kb page size t rrd_l (1/2kb) min = greater of 4ck or 6ns min = greater of 4ck or 5.3ns min = greater of 4ck or 5.3ns min = greater of 4ck or 4.9ns ck 1 activate-to-activate command period to same bank groups for 1kb page size t rrd_l (1kb) min = greater of 4ck or 6ns min = greater of 4ck or 5.3ns min = greater of 4ck or 5.3ns min = greater of 4ck or 4.9ns ck 1 activate-to-activate command period to same bank groups for 2kb page size t rrd_l (2kb) min = greater of 4ck or 7.5ns min = greater of 4ck or 6.4ns min = greater of 4ck or 6.4ns min = greater of 4ck or 6.4ns ck 1 four activate windows for 1/2kb page size t faw (1/2kb) min = greater of 16ck or 20ns min = greater of 16ck or 17ns min = greater of 16ck or 15ns min = greater of 16ck or 13ns ns four activate windows for 1kb page size t faw (1kb) min = greater of 20ck or 25ns min = greater of 20ck or 23ns min = greater of 20ck or 21ns min = greater of 20ck or 21ns ns four activate windows for 2kb page size t faw (2kb) min = greater of 28ck or 35ns min = greater of 28ck or 30ns min = greater of 28ck or 30ns min = greater of 28ck or 30ns ns write recovery time t wr min = 15ns ns 6, 10, 1 t wr 2 min = 1ck + t wr ck 6, 11, 1 write recovery time when crc and dm are both enabled t wr_crc_dm min = t wr + greater of (4ck or 3.75ns) min = t wr + greater of (5ck or 3.75ns) ck 7, 10, 1 t wr_crc_dm 2 min = 1ck + t wr_crc_dm ck 7, 11, 1 delay from start of internal write trans- action to internal read command C same bank group t wtr_l min = greater of 4ck or 7.5ns ck 6, 10, 1 t wtr_l 2 min = 1ck + t wtr_l ck 6, 11, 1 delay from start of internal write trans- action to internal read command C same bank group when crc and dm are both enabled t wtr_l_crc_d m min = t wtr_l + greater of (4ck or 3.75ns) min = t wtr_l + greater of (5ck or 3.75ns) ck 7, 10, 1 t wtr_l_crc_d m 2 min = 1ck + t wtr_l_crc_dm ck 7, 11, 1 delay from start of internal write trans- action to internal read command C dif- ferent bank group t wtr_s min = greater of (2ck or 2.5ns) ck 6, 8, 9, 10, 1 t wtr_s 2 min = 1ck + t wtr_s ck 6, 8, 9, 11, 1 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 351 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 159: electrical characteristics and ac timing parameters: ddr4-1600 through ddr4-2400 (continued) parameter symbol ddr4-1600 ddr4-1866 ddr4-2133 ddr4-2400 unit notes min max min max min max min max delay from start of internal write trans- action to internal read command C dif- ferent bank group when crc and dm are both enabled t wtr_s_crc_d m min = t wtr_s + greater of (4ck or 3.75ns) min = t wtr_s + greater of (5ck or 3.75ns) ck 7, 8, 9, 10, 1 t wtr_s_crc_d m 2 min = 1ck + t wtr_s_crc_dm ck 7, 8, 9, 11, 1 read-to-precharge time t rtp min = greater of 4ck or 7.5ns ck 1 cas_n-to-cas_n command delay to dif- ferent bank group t ccd_s 4 C 4 C 4 C 4 C ck cas_n-to-cas_n command delay to same bank group t ccd_l min = greater of 4ck or 6.25ns C min = greater of 4ck or 5.355ns C min = greater of 4ck or 5.355ns C min = greater of 4ck or 5ns Cck15 auto precharge write recovery + pre- charge time t dal (min) min = wr + roundup t rp/ t ck (avg); max = n/a ck mrs command timing mrs command cycle time t mrd 8 C 8 C 8 C 8 C ck mrs command cycle time in pda mode t mrd_pda min = greater of (16nck, 10ns) ck 1 mrs command cycle time in cal mode t mrd_cal min = t mod + t cal ck mrs command update delay t mod min = greater of (24nck, 15ns) ck 1 mrs command update delay in pda mode t mod_pda min = t mod ck mrs command update delay in cal mode t mod_cal min = t mod + t cal ck mrs command to dqs drive in preamble training t sdo min = t mod + 9ns mpr command timing multipurpose register recovery time t mprr min = 1ck ck multipurpose register write recovery time t wr_mprr min = t mod + al + pl crc error reporting timing crc error to alert_n latency t crc_alert 3 13 3 13 3 13 3 13 ns crc alert_n pulse width t crc_alert_p w 6 10 6 10 6 10 6 10 ck 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 352 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 159: electrical characteristics and ac timing parameters: ddr4-1600 through ddr4-2400 (continued) parameter symbol ddr4-1600 ddr4-1866 ddr4-2133 ddr4-2400 unit notes min max min max min max min max ca parity timing parity latency pl 4 C 4 C 4 C 5 C ck commands uncertain to be executed dur- ing this time t par_un- known C pl C pl C pl C pl ck delay from errant command to alert_n assertion t par_alert_o n C pl + 6ns C p l + 6ns C pl + 6ns C pl + 6ns ck pulse width of alert_n signal when as- serted t par_alert_p w 48 96 56 112 64 128 72 144 ck time from alert asserted until des com- mands required in persistent ca parity mode t par_alert_rs p C 43 C 50 C 57 C 64 ck cal timing cs_n to command address latency t cal 3 C 4 C 4 C 5 C ck 20 cs_n to command address latency in gear-down mode t calg n/a C n/a C n/a C n/a C ck mpsm timing command path disable delay upopn mpsm entry t mped min = t mod (min) + t cpded (min) ck 1 valid clock requirement after mpsm entry t ckmpe min = t mod (min) + t cpded (min) ck 1 valid clock requirement before mpsm exit t ckmpx min = t cksrx (min) ck 1 exit mpsm to commands not requiring a locked dll t xmp t xs (min) ck exit mpsm to commands requiring a locked dll t xmpdll min = t xmp (min) + t xsdll (min) ck 1 cs setup time to cke t mpx_s min = t is (min) + t ih (min) ns cs_n high hold time to cke rising edge t mpx_hh min = t xp ns cs_n low hold time to cke rising edge t mpx_lh 12 t xmp-1 0ns 12 t xmp-1 0ns 12 t xmp-1 0ns 12 t xmp-1 0ns ns connectivity test timing ten pin high to cs_n low C enter ct mode t ct_enable 200 C 200 C 200 C 200 C ns 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 353 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 159: electrical characteristics and ac timing parameters: ddr4-1600 through ddr4-2400 (continued) parameter symbol ddr4-1600 ddr4-1866 ddr4-2133 ddr4-2400 unit notes min max min max min max min max cs_n low and valid input to valid output t ct_valid C 200 C 200 C 200 C 200 ns ck_t, ck_c valid and cke high after ten goes high t ctcke_valid 10 C 10 C 10 C 10 C ns calibration and v refdq train timing zqcl command: long calibration time power-up and reset operation t zqinit 1024 C 1024 C 1024 C 1024 C ck normal opera- tion t zqoper 512 C 512 C 512 C 512 C ck zqcs command: short calibration time t zqcs 128 C 128 C 128 C 128 C ck the v ref increment/decrement step time v ref_time min = 150ns enter v refdq training mode to the first write or v refdq mrs command delay t vrefdqe min = 150ns ns 1 exit v refdq training mode to the first write command delay t vrefdqx min = 150ns ns 1 initialization and reset timing exit reset from cke high to a valid com- mand t xpr min = greater of 5ck or t rfc (min) + 10ns ck 1 reset_l pulse low after power stable t pw_rest_s 0.1 C 0.1 C 0.1 C 0.1 C s reset_l pulse low at power-up t pw_rest_l 200 C 200 C 200 C 200 C s begin power supply ramp to power sup- plies stable t vddpr min = n/a; max = 200 ms reset_n low to power supplies stable t rps min = 0; max = 0 ns reset_n low to i/o and r tt high-z t ioz min = n/a; max = undefined ns refresh timing 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 354 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 159: electrical characteristics and ac timing parameters: ddr4-1600 through ddr4-2400 (continued) parameter symbol ddr4-1600 ddr4-1866 ddr4-2133 ddr4-2400 unit notes min max min max min max min max refresh-to-activate or refresh command period (all bank groups) 4gb t rfc1 min = 260 ns 1, 12 t rfc2 min = 160 ns 1, 12 t rfc4 min = 110 ns 1, 12 8gb t rfc1 min = 350 ns 1, 12 t rfc2 min = 260 ns 1, 12 t rfc4 min = 160 ns 1, 12 16gb t rfc1 min = 550 ns 1, 12 t rfc2 min = 350 ns 1, 12 t rfc4 min = 260 ns 1, 12 average periodic re- fresh interval 0c t c 85c t refi min = n/a; max = 7.8 s 12 85c < t c 95c t refi min = n/a; max = 3.9 s 12 self refresh timing exit self refresh to commands not requir- ing a locked dll srx to commands not requiring a locked dll in self refresh abort t xs min = t rfc + 10ns ns 1 t xs_abort min = t rfc4 + 10ns ns 1 exit self refresh to zqcl, zqcs and mrs (cl, cwl, wr, rtp and gear-down) t xs_fast min = t rfc4 + 10ns ns 1 exit self refresh to commands requiring a locked dll t xsdll min = t dllk (min) ck 1 minimum cke low pulse width for self re- fresh entry to self refresh exit timing t ckesr min = t cke (min) + 1nck ck 1 minimum cke low pulse width for self re- fresh entry to self refresh exit timing when ca parity is enabled t ckesr_par min = t cke (min) + 1nck + pl ck 1 valid clocks after self refresh entry (sre) or power-down entry (pde) t cksre min = greater of (5ck, 10ns) ck 1 valid clock requirement after self refresh entry or power-down when ca parity is enabled t cksre_par min = greater of (5ck, 10ns) + pl ck 1 valid clocks before self refresh exit (srx) or power-down exit (pdx), or reset exit t cksrx min = greater of (5ck, 10ns) ck 1 power-down timing 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 355 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 159: electrical characteristics and ac timing parameters: ddr4-1600 through ddr4-2400 (continued) parameter symbol ddr4-1600 ddr4-1866 ddr4-2133 ddr4-2400 unit notes min max min max min max min max exit power-down with dll on to any val- id command t xp min = greater of 4ck or 6ns ck 1 exit power-down with dll on to any val- id command when ca parity is enabled. t xp _par min = (greater of 4ck or 6ns) + pl ck 1 cke min pulse width t cke (min) min = greater of 3ck or 5ns ck 1 command pass disable delay t cpded 4 C 4 C 4 C 4 C ck power-down entry to power-down exit timing t pd min = t cke (min); max = 9 t refi ck begin power-down period prior to cke registered high t anpd wl - 1ck ck power-down entry period: odt either synchronous or asynchronous pde greater of t anpd or t rfc - refresh command to cke low time ck power-down exit period: odt either syn- chronous or asynchronous pdx t anpd + t xsdll ck power-down entry minimum timing activate command to power-down en- try t actpden 1 C 1 C 2 C 2 C ck precharge/precharge all command to power-down entry t prpden 1 C 1 C 2 C 2 C ck refresh command to power-down entry t refpden 1 C 1 C 2 C 2 C ck mrs command to power-down entry t mrspden min = t mod (min) ck 1 read/read with auto precharge com- mand to power-down entry t rdpden min = rl + 4 + 1 ck 1 write command to power-down entry (bl8otf, bl8mrs, bc4otf) t wrpden min = wl + 4 + t wr/ t ck (avg) ck 1 write command to power-down entry (bc4mrs) t wrpbc4den min = wl + 2 + t wr/ t ck (avg) ck 1 write with auto precharge command to power-down entry (bl8otf, bl8mrs,bc4otf) t wrapden min = wl + 4 + wr + 1 ck 1 write with auto precharge command to power-down entry (bc4mrs) t wrapbc4den min = wl + 2 + wr + 1 ck 1 odt timing 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 356 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 159: electrical characteristics and ac timing parameters: ddr4-1600 through ddr4-2400 (continued) parameter symbol ddr4-1600 ddr4-1866 ddr4-2133 ddr4-2400 unit notes min max min max min max min max direct odt turn-on latency dodtlon wl - 2 = cwl + al + pl - 2 ck direct odt turn-off latency dodtloff wl - 2 = cwl + al + pl - 2 ck r tt dynamic change skew t adc 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 ck asynchronous r tt(nom) turn-on delay (dll off) t aonas 1 9 1 9 1 9 1 9 ns asynchronous r tt(nom) turn-off delay (dll off) t aofas 1 9 1 9 1 9 1 9 ns odt high time with write command and bl8 odth8 1 t ck 6 C 6 C 6 C 6 C ck odth8 2 t ck7C7C7C7C odt high time without write command or with write command and bc4 odth4 1 t ck 4 C 4 C 4 C 4 C ck odth4 2 t ck5C5C5C5C write leveling timing first dqs_t, dqs_c rising edge after write leveling mode is programmed t wlmrd 40 C 40 C 40 C 40 C ck dqs_t, dqs_c delay after write leveling mode is programmed t wldqsen 25 C 25 C 25 C 25 C ck write leveling setup from rising ck_t, ck_c crossing to rising dqs_t, dqs_c crossing t wls 0.13 C 0.13 C 0.13 C 0.13 C t ck (avg) write leveling hold from rising dqs_t, dqs_c crossing to rising ck_t, ck_c cross- ing t wlh 0.13 C 0.13 C 0.13 C 0.13 C t ck (avg) write leveling output delay t wlo 0 9.5 0 9.5 0 9.5 0 9.5 ns write leveling output error t wloe 0 2 0 2 0 2 0 2 ns gear-down timing (not supported below ddr4-2666) exit reset from cke high to a valid mrs gear-down t xpr_gear n/a n/a n/a n/a ck cke high assert to gear-down enable time) t xs_gear n/a n/a n/a n/a ck mrs command to sync pulse time t sync_gear n/a n/a n/a n/a ck sync pulse to first valid command t cmd_gear n/a n/a n/a n/a ck gear-down setup time t gear_setup n/a C n/a C n/a C n/a C ck gear-down hold time t gear_hold n/a C n/a C n/a C n/a C ck 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 357 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
notes: 1. maximum limit not applicable. 2. t ccd_l and t dllk should be programmed according to the value defined per operating frequency. 3. although unlimited row accesses to the same row is allowed within the refresh period, excessive row accesses to the same row over a long term can result in degraded opera- tion. 4. data rate is greater than or equal to 1066 mb/s. 5. rfucorr 6. write-to-read when crc and dm are both not enabled. 7. write-to-read delay when crc and dm are both enabled. 8. the start of internal write transactions is defined as follows: ? for bl8 (fixed by mrs and on-the-fly): rising clock edge four clock cycles after wl ? for bc4 (on-the-fly): rising clock edge four clock cycles after wl ? for bc4 (fixed by mrs): rising clock edge two clock cycles after wl 9. for these parameters, the device supports t n param [nck] = ru{ t param [ns]/ t ck (avg) [ns]}, in clock cycles, assuming all input clock jitter specifications are satisfied. 10. when operating in 1 t ck write preamble mode. 11. when operating in 2 t ck write preamble mode. 12. when ca parity mode is selected and the dlloff mode is used, each ref command re- quires an additional "pl" added to t rfc refresh time. 13. dram devices should be evenly addressed when being accessed. disproportionate ac- cesses to a particular row address may result in reduction of the product lifetime and/or reduction in data retention ability. 14. applicable from t ck (avg) min to t ck (avg) max as stated in the speed bin tables. 15. jedec specifies a minimum of five clocks. 16. the maximum read postamble is bound by t dqsck (min) plus t qsh (min) on the left side and t hz(dqs) max on the right side. 17. the reference level of dq output signal is specified with a midpoint as a widest part of output signal eye, which should be approximately 0.7 v ddq as a center level of the static single-ended output peak-to-peak swing with a driver impedance of 34 ohms and an effective test load of 50 ohms to v tt = v ddq . 18. jedec hasn't agreed upon the definition of the deterministic jitter; the user should fo- cus on meeting the total limit. 19. spread spectrum is not included in the jitter specification values. however, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20C60 khz with an additional 1% of t ck (avg) as a long-term jitter component; however, the spread spectrum may not use a clock rate below t ck (avg) min. 20. the actual t cal minimum is the larger of 3 clocks or 3.748ns/ t ck; the table lists the ap- plicable clocks required at targeted speed bin. 21. the maximum read preamble is bounded by t lz(dqs) min on the left side and t dqsck (max) on the right side. see figure in the clock to data strobe relationship section. boundary of dqs low-z occur one cycle earlier in 2 t ck toggle mode, which is illustrated in the read preamble section. 22. dq falling signal middle-point of transferring from high to low to first rising edge of dqs differential signal cross-point. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 358 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
electrical characteristics and ac timing parameters: 2666 through 3200 table 160: electrical characteristics and ac timing parameters parameter symbol ddr4-2666 ddr4-2933 ddr4-3200 reserved unit notes min max min max min max min max clock timing clock period average (dll off mode) t ck (dll_off) 8 20 8 20 8 20 ns clock period average t ck (avg, dll_on) 0.75 1.9 0.682 1.9 0.625 1.9 ns 14 high pulse width average t ch (avg) 0.48 0.52 0.48 0.52 0.48 0.52 t ck (avg) low pulse width average t cl (avg) 0.48 0.52 0.48 0.52 0.48 0.52 t ck (avg) clock period jitter total t jitper_tot C38 38 -34 34 C32 32 ps 18 , 19 deterministic t jitper_dj C19 19 -17 17 C16 16 ps 18 dll locking t jitper,lck C30 30 -27 27 C25 25 ps clock absolute period t ck (abs) min = t ck (avg) min + t jitper_tot min; max = t ck (avg) max + t jitper_tot max ps clock absolute high pulse width (includes duty cycle jitter) t ch (abs) 0.45 C 0.45 C 0.45 C t ck (avg) clock absolute low pulse width (includes duty cycle jitter) t cl (abs) 0.45 C 0.45 C 0.45 C t ck (avg) cycle-to-cycle jitter total t jitcc _tot C 75 C 68 C 62 ps dll locking t jitcc,lck C 60 C 55 C 62 ps 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters: 2666 through 3200 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 359 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 160: electrical characteristics and ac timing parameters (continued) parameter symbol ddr4-2666 ddr4-2933 ddr4-3200 reserved unit notes min max min max min max min max cumulative error across 2 cycles t err2per C55 55 -50 50 C46 46 ps 3 cycles t err3per C66 66 -60 60 C55 55 ps 4 cycles t err4per C73 73 -66 66 C61 61 ps 5 cycles t err5per C78 78 -71 71 C65 65 ps 6 cycles t err6per C83 83 -75 75 C69 69 ps 7 cycles t err7per C87 87 -79 79 C73 73 ps 8 cycles t err8per C91 91 -83 83 C76 76 ps 9 cycles t err9per C94 94 -85 85 C78 78 ps 10 cycles t err10per C96 96 -88 88 C80 80 ps 11 cycles t err11per C99 99 -90 90 C83 83 ps 12 cycles t err12per C101 101 -92 92 C84 84 ps n = 13, 14 . . . 49, 50 cycles t errnper t errnper min = (1 + 0.68ln[n]) t jitper_tot min t errnper max = (1 + 0.68ln[n]) t jitper_tot max ps dq input timing data setup time to dqs_t, dqs_c base (calibrated v ref ) t ds refer to dq input receiver specification section (approximately 0.15 t ck to 0.28 t ck ) C non-calibrated v ref t pda_s minimum of 0.5ui ui data hold time from dqs_t, dqs_c base (calibrated v ref ) t dh refer to dq input receiver specification section (approximately 0.15 t ck to 0.28 t ck ) C non-calibrated v ref t pda_h minimum of 0.5ui ui dq and dm minimum data pulse width for each input t dipw 0.58 C 0.58 C 0.58 C ui dq output timing (dll enabled) dqs_t, dqs_c to dq skew, per group, per access t dqsq C 0.18 C 0.19 C 0.22 ui dq output hold time from dqs_t, dqs_c t qh 0.74 C 0.74 C 0.74 C ui data valid window per device: t qh - t dqsq each devices output per iu t dvw d 0.64 C 0.64 C 0.64 C ui data valid window per device, per pin: t qh - t dqsq each devices output per iu t dvw p 0.72 C 0.72 C 0.72 C ui 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters: 2666 through 3200 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 360 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 160: electrical characteristics and ac timing parameters (continued) parameter symbol ddr4-2666 ddr4-2933 ddr4-3200 reserved unit notes min max min max min max min max dq low-z time from ck_t, ck_c t lzdq C310 170 C280 165 C250 160 ps dq high-z time from ck_t, ck_c t hzdq C 170 C 165 C 160 ps dq strobe input timing dqs_t, dqs_c rising edge to ck_t, ck_c rising edge for 1 t ckpreamble t dqss 1ck C0.27 0.27 C0.27 0.27 C0.27 0.27 ck dqs_t, dqs_c rising edge to ck_t, ck_c rising edge for 2 t ckpreamble t dqss 2ck C0.50 0.50 C0.50 0.50 C0.50 0.50 ck dqs_t, dqs_c differential input low pulse width t dqsl 0.46 0.54 0.46 0.54 0.46 0.54 ck dqs_t, dqs_c differential input high pulse width t dqsh 0.46 0.54 0.46 0.54 0.46 0.54 ck dqs_t, dqs_c falling edge setup to ck_t, ck_c rising edge t dss 0.18 C 0.18 C 0.18 C ck dqs_t, dqs_c falling edge hold from ck_t, ck_c rising edge t dsh 0.18 C 0.18 C 0.18 C ck dqs_t, dqs_c differential write pream- ble for 1 t ckpreamble t wpre 1ck 0.9 C 0.9 C 0.9 C ck dqs_t, dqs_c differential write pream- ble for 2 t ckpreamble t wpre 2ck 1.8 C 1.8 C 1.8 C ck dqs_t, dqs_c differential write postam- ble t wpst 0.33 C 0.33 C 0.33 C ck dqs strobe output timing (dll enabled) dqs_t, dqs_c rising edge output access time from rising ck_t, ck_c t dqsck C170 170 C165 165 C160 160 ps dqs_t, dqs_c rising edge output var- iance window per dram t dqscki C 270 C 265 C 260 ps dqs_t, dqs_c differential output high time t qsh 0.40 C 0.40 C 0.40 C ck dqs_t, dqs_c differential output low time t qsl 0.40 C 0.40 C 0.40 C ck dqs_t, dqs_c low-z time (rl - 1) t lzdqs C310 170 C280 165 C250 160 ps dqs_t, dqs_c high-z time (rl + bl/2) t hzdqs C 170 C 165 C 160 ps 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters: 2666 through 3200 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 361 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 160: electrical characteristics and ac timing parameters (continued) parameter symbol ddr4-2666 ddr4-2933 ddr4-3200 reserved unit notes min max min max min max min max dqs_t, dqs_c differential read pream- ble for 1 t ckpreamble t rpre 1ck 0.9 C 0.9 C 0.9 C ck 21 dqs_t, dqs_c differential read pream- ble for 2 t ckpreamble t rpre 2ck 1.8 C 1.8 C 1.8 C ck 21 dqs_t, dqs_c differential read postam- ble t rpst 0.33 C 0.33 C 0.33 C ck 22 command and address timing dll locking time t dllk 854 C 940 C 1024 C ck 2, 3 cmd, addr setup time to ck_t, ck_c refer- enced to v ih(ac) and vil(ac) levels base t is 55 C 48 C 40 C ps v refca t is vref 145 C 138 C 130 C ps cmd, addr hold time to ck_t, ck_c refer- enced to v ih(dc) and vil(dc) levels base t ih 80 C 73 C 65 C ps v refca t ih vref 145 C 138 C 130 C ps ctrl, addr pulse width for each input t ipw 385 C 365 C 350 C ps activate to internal read or write de- lay t rcd see speed bin tables for t rcd ns precharge command period t rp see speed bin tables for t rp ns activate-to-precharge command peri- od t ras see speed bin tables for t ras ns 13 activate-to-activate or ref command period t rc see speed bin tables for t rc ns 13 activate-to-activate command period to different bank groups for 1/2kb page size t rrd_s (1/2kb) min = greater of 4ck or 3.0ns min = greater of 4ck or 2.7ns min = greater of 4ck or 2.5ns ck 1 activate-to-activate command period to different bank groups for 1kb page size t rrd_s (1kb) min = greater of 4ck or 3.0ns min = greater of 4ck or 2.7ns min = greater of 4ck or 2.5ns ck 1 activate-to-activate command period to different bank groups for 2kb page size t rrd_s (2kb) min = greater of 4ck or 5.3ns min = greater of 4ck or 5.3ns min = greater of 4ck or 5.3ns ck 1 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters: 2666 through 3200 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 362 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 160: electrical characteristics and ac timing parameters (continued) parameter symbol ddr4-2666 ddr4-2933 ddr4-3200 reserved unit notes min max min max min max min max activate-to-activate command period to same bank groups for 1/2kb page size t rrd_l (1/2kb) min = greater of 4ck or 4.9ns min = greater of 4ck or 4.9ns min = greater of 4ck or 4.9ns ck 1 activate-to-activate command period to same bank groups for 1kb page size t rrd_l (1kb) min = greater of 4ck or 4.9ns min = greater of 4ck or 4.9ns min = greater of 4ck or 4.9ns ck 1 activate-to-activate command period to same bank groups for 2kb page size t rrd_l (2kb) min = greater of 4ck or 6.4ns min = greater of 4ck or 6.4ns min = greater of 4ck or 6.4ns ck 1 four activate windows for 1/2kb page size t faw (1/2kb) min = greater of 16ck or 12ns min = greater of 16ck or 10.875ns min = greater of 16ck or 10ns ns four activate windows for 1kb page size t faw (1kb) min = greater of 20ck or 21ns min = greater of 20ck or 21ns min = greater of 20ck or 21ns ns four activate windows for 2kb page size t faw (2kb) min = greater of 28ck or 30ns min = greater of 28ck or 30ns min = greater of 28ck or 30ns ns write recovery time t wr min = 15ns ns 5, 10, 1 t wr 2 min = 1ck + t wr ck 5, 11, 1 write recovery time when crc and dm are both enabled t wr_crc_dm min = t wr + greater of (5ck or 3.75ns) ck 6, 10, 1 write recovery time when crc and dm are both enabled t wr_crc_dm 2 min = 1ck + t wr_crc_dm ck 6, 11, 1 delay from start of internal write trans- action to internal read command C same bank group t wtr_l min = greater of 4ck or 7.5ns ck 5, 10, 1 t wtr_l 2 min = 1ck + t wtr_l ck 5, 11, 1 delay from start of internal write trans- action to internal read command C same bank group when crc and dm are both enabled t wtr_l_crc_d m min = t wtr_l + greater of (5ck or 3.75ns) ck 6, 10, 1 t wtr_l_crc_d m 2 min = 1ck + t wtr_l_crc_dm ck 6, 11, 1 delay from start of internal write trans- action to internal read command C dif- ferent bank group t wtr_s min = greater of (2ck or 2.5ns) ck 5, 7, 8, 10, 1 t wtr_s 2 min = 1ck + t wtr_s ck 5, 7, 8, 11, 1 delay from start of internal write trans- action to internal read command C dif- ferent bank group when crc and dm are both enabled t wtr_s_crc_d m min = t wtr_s + greater of (5ck or 3.75ns) ck 6, 7, 8, 10, 1 t wtr_s_crc_d m 2 min = 1ck + t wtr_s_crc_dm ck 6, 7, 8, 11, 1 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters: 2666 through 3200 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 363 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 160: electrical characteristics and ac timing parameters (continued) parameter symbol ddr4-2666 ddr4-2933 ddr4-3200 reserved unit notes min max min max min max min max read-to-precharge time t rtp min = greater of 4ck or 7.5ns ck 1 cas_n-to-cas_n command delay to dif- ferent bank group t ccd_s 4 C 4 C 4 C ck cas_n-to-cas_n command delay to same bank group t ccd_l min = greater of 4ck or 5ns C min = greater of 4ck or 5ns C min = greater of 4ck or 5ns C ck 15 auto precharge write recovery + pre- charge time t dal (min) min = wr + roundup t rp/ t ck (avg); max = n/a ck mrs command timing mrs command cycle time t mrd 8 C 8 C 8 C ck mrs command cycle time in pda mode t mrd_pda min = greater of (16nck, 10ns) 1 mrs command cycle time in cal mode t mrd_cal min = t mod + t cal ck mrs command update delay t mod min = greater of (24nck, 15ns) ck 1 mrs command update delay in pda mode t mod_pda min = t mod ck mrs command update delay in cal mode t mod_cal min = t mod + t cal ck mrs command to dqs drive in preamble training t sdo min = t mod + 9ns mpr command timing multipurpose register recovery time t mprr min = 1nck ck multipurpose register write recovery time t wr_mprr min = t mod + al + pl crc error reporting timing crc error to alert_n latency t crc_alert 3 13 3 13 3 13 ns crc alert_n pulse width t crc_alert_p w 6 10 6 10 6 10 ck ca parity timing parity latency pl 5 C 6 C 6 C ck commands uncertain to be executed dur- ing this time t par_un- known C pl C pl C pl ck delay from errant command to alert_n assertion t par_alert_o n C pl + 6ns C pl + 6ns C pl + 6ns ck 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters: 2666 through 3200 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 364 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 160: electrical characteristics and ac timing parameters (continued) parameter symbol ddr4-2666 ddr4-2933 ddr4-3200 reserved unit notes min max min max min max min max pulse width of alert_n signal when as- serted t par_alert_p w 80 160 88 176 96 192 ck time from alert asserted until des com- mands required in persistent ca parity mode t par_alert_rs p C 71 C 78 C 85 ck cal timing cs_n to command address latency t cal 5 C 6 C 6 C ck 20 cs_n to command address latency in gear-down mode t calg 6 C 8 C 8 C ck mpsm timing command path disable delay upopn mpsm entry t mped min = t mod (min) + t cpded (min) ck 1 valid clock requirement after mpsm entry t ckmpe min = t mod (min) + t cpded (min) ck 1 valid clock requirement before mpsm exit t ckmpx min = t cksrx (min) ck 1 exit mpsm to commands not requiring a locked dll t xmp t xs (min) ck exit mpsm to commands requiring a locked dll t xmpdll min = t xmp (min) + t xsdll (min) ck 1 cs setup time to cke t mpx_s min = t is (min) + t ih (min) ns cs_n high hold time to cke rising edge t mpx_hh min = t xp ns cs_n low hold time to cke rising edge t mpx_lh 12 t xmp-1 0ns 12 t xmp-1 0ns 12 t xmp-1 0ns ns connectivity test timing ten pin high to cs_n low C enter ct mode t ct_enable 200 C 200 C 200 C ns cs_n low and valid input to valid output t ct_valid C 200 C 200 C 200 ns ck_t, ck_c valid and cke high after ten goes high t ctcke_valid 10 C 10 C 10 C ns calibration and v refdq train timing 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters: 2666 through 3200 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 365 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 160: electrical characteristics and ac timing parameters (continued) parameter symbol ddr4-2666 ddr4-2933 ddr4-3200 reserved unit notes min max min max min max min max zqcl command: long calibration time power-up and reset operation t zqinit 1024 C 1024 C 1024 C ck normal opera- tion t zqoper 512 C 512 C 512 C ck zqcs command: short calibration time t zqcs 128 C 128 C 128 C ck the v ref increment/decrement step time v ref_time min = 150ns enter v refdq training mode to the first write or v refdq mrs command delay t vrefdqe min = 150ns ns 1 exit v refdq training mode to the first write command delay t vrefdqx min = 150ns ns 1 initialization and reset timing exit reset from cke high to a valid com- mand t xpr min = greater of 5ck or t rfc (min) + 10ns ck 1 reset_l pulse low after power stable t pw_rest_s 0.1 C 0.1 C 0.1 C s reset_l pulse low at power-up t pw_rest_l 200 C 200 C 200 C s begin power supply ramp to power sup- plies stable t vddpr min = n/a; max = 200 ms reset_n low to power supplies stable t rps min = 0; max = 0 ns reset_n low to i/o and r tt high-z t ioz min = n/a; max = undefined ns refresh timing refresh-to-activate or refresh command period (all bank groups) 4gb t rfc1 min = 260 ns 1, 12 t rfc2 min = 160 ns 1, 12 t rfc4 min = 110 ns 1, 12 8gb t rfc1 min = 350 ns 1, 12 t rfc2 min = 260 ns 1, 12 t rfc4 min = 160 ns 1, 12 16gb t rfc1 min = 550 ns 1, 12 t rfc2 min = 350 ns 1, 12 t rfc4 min = 260 ns 1, 12 average periodic re- fresh interval 0c t c 85c t refi min = n/a; max = 7.8 s 12 85c < t c 95c t refi min = n/a; max = 3.9 s 12 self refresh timing 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters: 2666 through 3200 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 366 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 160: electrical characteristics and ac timing parameters (continued) parameter symbol ddr4-2666 ddr4-2933 ddr4-3200 reserved unit notes min max min max min max min max exit self refresh to commands not requir- ing a locked dll srx to commands not requiring a locked dll in self refresh abort t xs min = t rfc + 10ns ns 1 t xs_abort min = t rfc4 + 10ns ns 1 exit self refresh to zqcl, zqcs and mrs (cl, cwl, wr, rtp and gear-down) t xs_fast min = t rfc4 + 10ns ns 1 exit self refresh to commands requiring a locked dll t xsdll min = t dllk (min) ck 1 minimum cke low pulse width for self re- fresh entry to self refresh exit timing t ckesr min = t cke (min) + 1nck ck 1 minimum cke low pulse width for self re- fresh entry to self refresh exit timing when ca parity is enabled t ckesr_par min = t cke (min) + 1nck + pl ck 1 valid clocks after self refresh entry (sre) or power-down entry (pde) t cksre min = greater of (5ck, 10ns) ck 1 valid clock requirement after self refresh entry or power-down when ca parity is enabled t cksre_par min = greater of (5ck, 10ns) + pl ck 1 valid clocks before self refresh exit (srx) or power-down exit (pdx), or reset exit t cksrx min = greater of (5ck, 10ns) ck 1 power-down timing exit power-down with dll on to any val- id command t xp min = greater of 4ck or 6ns ck 1 exit precharge power-down with dll fro- zen to commands not requiring a locked dll when ca parity is enabled. t xp _par min = (greater of 4ck or 6ns) + pl ck 1 cke min pulse width t cke (min) min = greater of 3ck or 5ns ck 1 command pass disable delay t cpded 4 C 4 C 4 C ck power-down entry to power-down exit timing t pd min = t cke (min); max = 9 t refi ck begin power-down period prior to cke registered high t anpd wl - 1ck ck power-down entry period: odt either synchronous or asynchronous pde greater of t anpd or t rfc - refresh command to cke low time ck 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters: 2666 through 3200 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 367 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 160: electrical characteristics and ac timing parameters (continued) parameter symbol ddr4-2666 ddr4-2933 ddr4-3200 reserved unit notes min max min max min max min max power-down exit period: odt either syn- chronous or asynchronous pdx t anpd + t xsdll ck power-down entry minimum timing activate command to power-down en- try t actpden 2 C 2 C 2 C ck precharge/precharge all command to power-down entry t prpden 2 C 2 C 2 C ck refresh command to power-down entry t refpden 2 C 2 C 2 C ck mrs command to power-down entry t mrspden min = t mod (min) ck 1 read/read with auto precharge com- mand to power-down entry t rdpden min = rl + 4 + 1 ck 1 write command to power-down entry (bl8otf, bl8mrs, bc4otf) t wrpden min = wl + 4 + t wr/ t ck (avg) ck 1 write command to power-down entry (bc4mrs) t wrpbc4den min = wl + 2 + t wr/ t ck (avg) ck 1 write with auto precharge command to power-down entry (bl8otf, bl8mrs,bc4otf) t wrapden min = wl + 4 + wr + 1 ck 1 write with auto precharge command to power-down entry (bc4mrs) t wrapbc4den min = wl + 2 + wr + 1 ck 1 odt timing direct odt turn-on latency dodtlon wl - 2 = cwl + al + pl - 2 ck direct odt turn-off latency dodtloff wl - 2 = cwl + al + pl - 2 ck r tt dynamic change skew t adc 0.3 0.7 0.28 0.72 0.28 0.72 ck asynchronous r tt(nom) turn-on delay (dll off) t aonas 1 9 1 9 1 9 ns asynchronous r tt(nom) turn-off delay (dll off) t aofas 1 9 1 9 1 9 ns odt high time with write command and bl8 odth8 1 t ck 6 C 6 C 6 C ck odth8 2 t ck 7 C 7 C 7 C odt high time without write command or with write command and bc4 odth4 1 t ck 4 C 4 C 4 C ck odth4 2 t ck 5 C 5 C 5 C write leveling timing 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters: 2666 through 3200 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 368 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 160: electrical characteristics and ac timing parameters (continued) parameter symbol ddr4-2666 ddr4-2933 ddr4-3200 reserved unit notes min max min max min max min max first dqs_t, dqs_c rising edge after write leveling mode is programmed t wlmrd 40 C 40 C 40 C ck dqs_t, dqs_c delay after write leveling mode is programmed t wldqsen 25 C 25 C 25 C ck write leveling setup from rising ck_t, ck_c crossing to rising dqs_t, dqs_c crossing t wls 0.13 C 0.13 C 0.13 C ck write leveling hold from rising dqs_t, dqs_c crossing to rising ck_t, ck_c cross- ing t wlh 0.13 C 0.13 C 0.13 C ck write leveling output delay t wlo 0 9.5 0 9.5 0 9.5 ns write leveling output error t wloe 0 2 0 2 0 2 ns gear-down timing exit reset from cke high to a valid mrs gear-down t xpr_gear t xpr t xpr t xpr ck cke high assert to gear-down enable time) t xs_gear t xs t xs t xs ck mrs command to sync pulse time t sync_gear t mod + 4ck t mod + 4ck t mod + 4ck ck sync pulse to first valid command t cmd_gear t mod t mod t mod ck gear-down setup time t gear_setup 2ck C 2ck C 2ck C ck gear-down hold time t gear_hold 2ck C 2ck C 2ck C ck 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters: 2666 through 3200 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 369 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
notes: 1. maximum limit not applicable. 2. t ccd_l and t dllk should be programmed according to the value defined per operating frequency. 3. data rate is greater than or equal to 1066 mb/s. 4. rfu. 5. write-to-read when crc and dm are both not enabled. 6. write-to-read delay when crc and dm are both enabled. 7. the start of internal write transactions is defined as follows: ? for bl8 (fixed by mrs and on-the-fly): rising clock edge four clock cycles after wl ? for bc4 (on-the-fly): rising clock edge four clock cycles after wl ? for bc4 (fixed by mrs): rising clock edge two clock cycles after wl 8. for these parameters, the device supports t n param [nck] = ru{ t param [ns]/ t ck (avg) [ns]}, in clock cycles, assuming all input clock jitter specifications are satisfied. 9. although unlimited row accesses to the same row is allowed within the refresh period, excessive row accesses to the same row over a long term can result in degraded opera- tion. 10. when operating in 1 t ck write preamble mode. 11. when operating in 2 t ck write preamble mode. 12. when ca parity mode is selected and the dlloff mode is used, each ref command re- quires an additional "pl" added to t rfc refresh time. 13. dram devices should be evenly addressed when being accessed. disproportionate ac- cesses to a particular row address may result in reduction of the product lifetime and/or reduction in data retention ability. 14. applicable from t ck (avg) min to t ck (avg) max as stated in the speed bin tables. 15. jedec specifies a minimum of five clocks. 16. the maximum read postamble is bound by t dqsck (min) plus t qsh (min) on the left side and t hz(dqs) max on the right side. 17. the reference level of dq output signal is specified with a midpoint as a widest part of output signal eye, which should be approximately 0.7 v ddq as a center level of the static single-ended output peak-to-peak swing with a driver impedance of 34 ohms and an effective test load of 50 ohms to v tt = v ddq . 18. jedec hasn't agreed upon the definition of the deterministic jitter; the user should fo- cus on meeting the total limit. 19. spread spectrum is not included in the jitter specification values. however, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20C60 khz with an additional 1% of t ck (avg) as a long-term jitter component; however, the spread spectrum may not use a clock rate below t ck (avg) min. 20. the actual t cal minimum is the larger of 3 clocks or 3.748ns/ t ck; the table lists the ap- plicable clocks required at targeted speed bin. 21. the maximum read preamble is bounded by t lz(dqs) min on the left side and t dqsck (max) on the right side. see figure in clock to data strobe relationship. boundary of dqs low-z occur one cycle earlier in 2 t ck toggle mode which is illustrated in read pre- amble. 22. dq falling signal middle-point of transferring from high to low to first rising edge of dqs differential signal cross-point. 8gb: x4, x8, x16 ddr4 sdram electrical characteristics and ac timing parameters: 2666 through 3200 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 370 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
converting time-based specifications to clock-based requirements software algorithms for calculation of timing parameters are subject to potential round- ing errors when converting dram timing requirements to system clocks; for example, a memory clock with a nominal frequency of 933.33...3 mhz, or a clock period of 1.071428571429...ns. similarly, a system with a memory clock frequency of 1066.66...6 mhz mathematically yields a clock period of 0.9375ns. it is unrealistic to represent all digits after the decimal point exactly and some sort of rounding needs to be done. ddr4 sdram spd-based specifications use a minimum granularity for spd-associated timing parameters of 1ps. clock periods such as t ck (avg) min are defined to the near- est picosecond. for example, 0.9375ns is stated as 937ps and 1.0714ns is stated as 1071ps. parameters such as t aa min, and t rcd min are specified in units of time (nanoseconds) and require mathematical computation to convert to system clocks (n ck). rules for rounding allows optimization of device performance without violating device parameters. these spd algorithms rely on results that are within adjustment fac- tors on device testing and specification to avoid losing performance due to rounding er- rors when using spd-based parameters. guidance converting spd associated timing parameters to system clock requirements: ? divide the time base specification (in ns) by the clock period (in ns). ? subtract an adjustment factor of 0.025. this is results in a C2.5% t ck adjustment fac- tor. ? the resultant is set to the next higher integer number of clocks. ? n ck = ceiling [ (parameter in ns / application t ck in ns) - 0.025 ]. alternatively, the following algorithm provides the same results as above: ? use integer math expressing timing specification and application clock period in pi- coseconds; scaling a nanosecond-based parameter value by 1000. ? divide the picosecond-based parameter by the picoseconds based application clock period. ? add an inverse adjustment factor of 97.4%. ? divide the result by 1000. ? truncate down to the next lower integer value. ? n ck = truncate [ {(parameter in ps 1000) / (application t ck in ps) + 974} / 1000 ]. guidance converting nonspd associated timing parameters to system clock require- ments: ? divide the time base specification (in ns) and divided by the clock period (in ns). ? the resultant is set to the next higher integer number of clocks. ? n ck = ceiling [ (parameter in ns / application t ck in ns) ]. 8gb: x4, x8, x16 ddr4 sdram converting time-based specifications to clock-based require- ments 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 371 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
options tables table 161: options - speed based function acronym data rate 1600 1866 2133 2400 2666 2933 3200 write leveling wl yes yes yes yes yes yes yes temperature controlled refresh tcr yes yes yes yes yes yes yes low-power auto self refresh lpasr yes yes yes yes yes yes yes fine granularity refresh fgr yes yes yes yes yes yes yes multipurpose register mr yes yes yes yes yes yes yes data mask dm yes yes yes yes yes yes yes data bus inversion dbi yes yes yes yes yes yes yes tdqs C yes yes yes yes yes yes yes zq calibration zq cal yes yes yes yes yes yes yes v refdq calibration C yes yes yes yes yes yes yes per-dram addressability per dram yes yes yes yes yes yes yes mode register readout C yes yes yes yes yes yes yes command/address latency cal yes yes yes yes yes yes yes write crc crc yes yes yes yes yes yes yes ca parity - yes yes yes yes yes yes yes gear-down mode - no no no no yes yes yes programmable preamble C no no no yes yes yes yes maximum power saving mode mpsm yes yes yes yes yes yes yes additive latency al yes yes yes yes yes yes yes connectivity test mode ct yes yes yes yes yes yes yes hard post package repair mode hppr yes yes yes yes yes yes yes soft post package repair mode sppr yes yes yes yes yes yes yes 8gb: x4, x8, x16 ddr4 sdram options tables 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 372 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 162: options - width based function acronym width x4 x8 x16 write leveling wl yes yes yes temperature controlled refresh tcr yes yes yes low-power auto self refresh lpasr yes yes yes fine granularity refresh fgr yes yes yes multipurpose register mr yes yes yes data mask dm no yes yes data bus inversion dbi no yes yes tdqs C no yes no zq calibration zq cal yes yes yes v refdq calibration C yes yes yes per-dram addressability per dram yes yes yes mode regsiter readout C yes yes yes command/address latency cal yes yes yes write crc crc yes yes yes ca parity C yes yes yes gear-down mode C yes yes yes programmable preamble C yes yes yes maximum power-down mode mpsm yes yes no additive latency al yes yes yes connectivity test mode ct jedec optional on 8gb and larger densities micron supports on all densities yes hard post package repair mode hppr jedec optional on 4gb micron supports on all densities soft post package repair mode sppr jedec optional on 4gb and 8gb micron supports on all densities 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-4000 www.micron.com/products/support sales inquiries: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 8gb: x4, x8, x16 ddr4 sdram options tables 09005aef861d1d4a 8gb_ddr4_dram.pdf - rev. g 1/17 en 373 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.

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