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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. tps7b70-q1 slvsek5 ? august 2018 tps7b70-q1 automotive, 300-ma, 40-v, low-i q ldo with power good 1 1 features 1 ? qualified for automotive applications ? aec-q100 qualified with the following results: ? device temperature grade 1: ? 40 c to 125 c ambient operating temperature range ? device hbm esd classification level 2 ? device cdm esd classification level c4b ? device junction temperature range: ? 40 c to +150 c ? maximum output current: 300 ma ? 4-v to 40-v wide v in input-voltage range with up to 45-v transients ? fixed 3.3-v and 5-v outputs ? maximum dropout voltage: 400 mv at 300 ma ? stable with output capacitor in wide range of capacitance (4.7 f to 500 f) and esr (0.001 to 20 ) ? low quiescent current (i (q) ) ? < 4 a when en is low (shutdown mode) ? 19 a typical at light loads with vint high ? fully adjustable power-good threshold and power-good delay timing ? low input-voltage tracking to uvlo ? integrated fault protection ? overload current-limit protection ? thermal shutdown ? 16-pin htssop powerpad ? package ? thermal resistance (r ja ): 39.7 c/w 2 applications ? body control modules (bcm) ? ev and hev battery management systems ? transmission control units (tcu) ? head units ? electrical power steering (eps) 3 description the tps7b70-q1 is a 300-ma, low-dropout linear regulator (ldo) that operates from an automotive battery. the device has only 19 a of quiescent current at light loads. thus, the tps7b70-q1 is an excellent selection to supply power to always-on components, such as microcontrollers (mcus) and controller area network (can) transceivers. the input voltage range of the tps7b70-q1 extends thru 40 v. this voltage helps the device withstand transient conditions, such as load-dump. the device also has a power good (pg) pin to tell the system when the output voltage is in regulation. to achieve the necessary operation, you can adjust the pg threshold voltage and delay. the threshold voltage of the pg signal is adjusted through external resistors. adjust the delay with an external capacitor. this device operates in ambient temperatures from ? 40 c to +125 c, and with junction temperatures from ? 40 c to +150 c. this device also has a thermally conductive package that enables sustained operation despite significant dissipation across the device, a typical property of off-battery operation. these features, along with included current limit and thermal shutdown protection, make the tps7b70-q1 an excellent selection to supply power to automotive system components. device information (1) part number output voltage package tps7b70-q1 3.3 v or 5 v htssop (16) (1) for all available packages, see the package option addendum at the end of the data sheet. typical application out in tps7b7033-q1 tps7b7050-q1 v reg pg en delay gnd v bat pgadj vint v in v out advance information tools & software technical documents ordernow productfolder support &community
2 tps7b70-q1 slvsek5 ? august 2018 www.ti.com product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 switching characteristics .......................................... 6 6.7 typical characteristics .............................................. 6 7 detailed description ............................................ 10 7.1 overview ................................................................. 10 7.2 functional block diagram ....................................... 10 7.3 feature description ................................................. 10 7.4 device functional modes ........................................ 12 8 application and implementation ........................ 13 8.1 application information ............................................ 13 8.2 typical application .................................................. 13 9 power supply recommendations ...................... 15 10 layout ................................................................... 15 10.1 layout guidelines ................................................. 15 10.2 layout example .................................................... 15 11 device and documentation support ................. 16 11.1 documentation support ........................................ 16 11.2 receiving notification of documentation updates 16 11.3 community resources .......................................... 16 11.4 trademarks ........................................................... 16 11.5 electrostatic discharge caution ............................ 16 11.6 glossary ................................................................ 16 12 mechanical, packaging, and orderable information ........................................................... 16 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes august 2018 * initial release. advance information
3 tps7b70-q1 www.ti.com slvsek5 ? august 2018 product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions pwp package 16-pin htssop with powerpad top view pin functions pin i/o description name no. delay 8 o power-good delay adjustment pin. connect this pin through a capacitor to ground to adjust the power-good delay time. en 2 i device enable pin. pull this pin down to low-level voltage to disable the device. pull this pin up to high-level voltage to enable the device. gnd 3, 4, 5, 6, 7, 9, 10, 12, 13 ? ground reference in 1 i device input power supply pin out 16 o device 3.3-v or 5-v regulated output-voltage pin pg 14 o power-good pin. open-drain output pin. pull this pin up to v out or to a reference through a resistor. when the output voltage is not ready, this pin is pulled down to ground. pgadj 15 o power-good threshold-adjustment pin. connect a resistor divider between the pgadj and out pins to set the power-good threshold. connect this pin to ground to set the threshold to 91.6% of output voltage v out . vint 11 i internal voltage rail. tie this pin above 2 v for lowest i gnd . powerpad ? ? solder thermal pad to board to improve the thermal performance. advance information 1 in 16 out 2 en 15 pgadj 3 gnd 14 pg 4 gnd 13 gnd 5 gnd 12 gnd 6 gnd 11 vint 7 gnd 10 gnd 8 delay 9 gnd not to scale 3rzhu3$'?
4 tps7b70-q1 slvsek5 ? august 2018 www.ti.com product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to ground. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) min max unit unregulated input in, en ? 0.3 45 v power-good delay-timer output delay ? 0.3 7 v regulated output out ? 0.3 7 v power-good output voltage pg ? 0.3 7 v v-internal vint ? 0.3 7 v power-good threshold-adjustment voltage pgadj ? 0.3 7 v t j operating junction temperature ? 40 150 c t stg storage temperature ? 65 150 c (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per aec q100-002 (1) 2000 v charged-device model (cdm), per aec q100-011 all pins 500 corner pins (1, 14, 15, and 28) 750 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit unregulated input in 4 40 v 40-v pins en 0 v in v regulated output out 0 5.5 v power good pg 0 5.5 v low voltage pins pgadj, delay 0 5.5 v i out output current 0 300 ma t a ambient temperature ? 40 125 c t j junction temperature ? 40 150 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report . 6.4 thermal information thermal metric (1) tps7b70-q1 unit pwp (htssop) 16 pins r ja junction-to-ambient thermal resistance 39.7 c/w r jc(top) junction-to-case (top) thermal resistance 28.9 c/w r jb junction-to-board thermal resistance 23.8 c/w jt junction-to-top characterization parameter 1.3 c/w jb junction-to-board characterization parameter 23.7 c/w r jc(bot) junction-to-case (bottom) thermal resistance 3.1 c/w advance information
5 tps7b70-q1 www.ti.com slvsek5 ? august 2018 product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) this test is done with v out in regulation, measuring the v in ? v out when v out drops by 100 mv from the rated output voltage at the specified load. (2) design information ? not tested, determined by characterization. 6.5 electrical characteristics v in = 14 v, c out 4.7 f, 1 m < esr < 20 , t j = ? 40 c to 150 c unless otherwise noted parameter test conditions min typ max unit supply voltage and current (in) i (sleep) input sleep current en = off 4 a i (gnd) input quiescent current v in = v out + 0.7 v ; en = on, vint > 2 v, i out < 1 ma, t j < 80 c 19 29.6 a v (uvlo) undervoltage lockout, falling ramp v in down until output is turned off 2.6 v v (uvlo_hyst) uvlo hysteresis 0.5 v enable input (en) v il low-level input voltage 0.7 v v ih high-level input voltage 2 v v hys hysteresis 150 mv regulated output (out) v out regulated output v in = v out + 0.7 v, i out = 0 ma to 300 ma ? 2% 2% v out( vin) line regulation v in = 5.6 v to 40 v 10 mv v out( iout) load regulation i out = 1 ma to 300 ma 20 mv v (dropout) dropout voltage (v in ? v out ) i out = 300 ma (1) 300 400 mv i out = 200 ma (1) 170 260 i (lim) output current limit v out shorted to ground, v in = 5.6 v to 40 v 301 680 1000 ma psrr power supply ripple rejection (2) i out = 100 ma, c out = 10 f, frequency (f) = 100 hz 60 db i out = 100 ma, c out = 10 f, frequency (f) = 100 khz 40 power good (pg, pgadj) v ol(pg) pg output, low voltage i ol = 5 ma, pg pulled low 0.4 v i lkg(pg) pg pin leakage current pg pulled to v out through a 10 ? k resistor 1 a v (pg_th) default power-good threshold v out powered above the internally set tolerance, pgadj pin shorted to ground 89.6 91.6 93.6 % of v out v (pg_hyst) power-good hysteresis v out falling below the internally set tolerance hysteresis 2 % of v out advance information
6 tps7b70-q1 slvsek5 ? august 2018 www.ti.com product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) v in = 14 v, c out 4.7 f, 1 m < esr < 20 , t j = ? 40 c to 150 c unless otherwise noted parameter test conditions min typ max unit pgadj v (pgadj_th) switching voltage for the power- good adjust pin v out is falling 1.067 1.1 1.133 v power-good delay i (dly_chg) delay capacitor charging current 3 5 10 a v (dly_th) delay pin threshold to release pg high voltage at delay pin is ramped up 0.95 1 1.05 v i (dly_dis) delay capacitor discharging current v delay = 1 v 0.5 ma current voltage reference (rosc) v rosc voltage reference 0.95 1 1.05 v temperature t (sd) junction shutdown temperature 175 c t (hyst) hysteresis of thermal shutdown 25 c 6.6 switching characteristics v i = 14 v, c o 4.7 f, 1 m < esr < 20 , t j = ? 40 c to 150 c unless otherwise noted parameter test conditions min typ max unit power-good delay (delay) t (deglitch) power-good deglitch time 100 180 250 s t (dly_fix) fixed power-good delay no capacitor connect at delay pin 100 248 550 s t (dly) power-good delay delay capacitor value: c (delay) = 100 nf 20 ms 6.7 typical characteristics v in = 14 v, v en 2 v, t j = ? 40 o c to 150 o c unless otherwise noted figure 1. ground current vs output current figure 2. ground current vs input voltage input voltage (v) quiescent current ( p a) 0 5 10 15 20 25 30 35 40 0 50 100 150 200 250 300 350 400 d002 i out = 1 ma i out = 100 ma i out = 200 ma advance information output current (ma) quiescent current ( p a) 0 50 100 150 200 250 300 0 10 20 30 40 50 60 70 80 d001 40 c 25 c 125 c
7 tps7b70-q1 www.ti.com slvsek5 ? august 2018 product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) v in = 14 v, v en 2 v, t j = ? 40 o c to 150 o c unless otherwise noted en = 0 v figure 3. shutdown current vs ambient temperature figure 4. ground current vs ambient temperature figure 5. dropout voltage vs output current i out = 200 ma figure 6. dropout voltage vs ambient temperature v out = 5 v figure 7. output voltage vs ambient temperature v out = 5 v figure 8. output voltage vs input voltage ambient temperature (c) dropout voltage (mv) -40 -25 -10 5 20 35 50 65 80 95 110 125 0 50 100 150 200 250 300 d006 ambient temperature ( q c) shudown current ( p a) -40 -25 -10 5 20 35 50 65 80 95 110 125 0 1 2 3 4 d003 input voltage (v) output voltage (v) 0 5 10 15 20 25 30 35 40 0 1 2 3 4 5 6 d008 -40 q c 25 q c 125 q c output current (ma) dropout voltage (mv) 0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 350 d005 40 c 25 c 125 c advance information ambient temperature (c) output voltage (v) -40 -25 -10 5 20 35 50 65 80 95 110 125 4.94 4.97 5 5.03 5.06 d007 ambient temperature (c) quiescent current ( p a) -40 -25 -10 5 20 35 50 65 80 95 110 125 0 5 10 15 20 25 30 35 d004 i out = 1 ma i out = 100 ma
8 tps7b70-q1 slvsek5 ? august 2018 www.ti.com product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) v in = 14 v, v en 2 v, t j = ? 40 o c to 150 o c unless otherwise noted v in = 5.6 v figure 9. output current limit (i lim ) vs ambient temperature figure 10. load regulation figure 11. line regulation c out = 10 f i out = 1 ma t a = 25 c figure 12. psrr vs frequency c out = 10 f i out = 100 ma t a = 25 c figure 13. psrr vs frequency figure 14. esr stability vs output capacitance output current (ma) line regulation (%) 0 50 100 150 200 250 300 350 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 d010 40 c 25 c 125 c frequency (hz) psrr (db) 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m 10m d012 ambient temperature (c) current limit (ma) -40 -25 -10 5 20 35 50 65 80 95 110 125 500 600 700 800 900 d009 input voltage (v) line regulation (%) 0 5 10 15 20 25 30 35 40 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 d011 -40 q c 25 q c 125 q c advance information esr ( w) output capacitance (f) 1 4.7 10 100 500 1k 0.001 0.01 0.1 1 10 20 d014 table region s unstable region table region uns frequency (hz) psrr (db) 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m 10m d013
9 tps7b70-q1 www.ti.com slvsek5 ? august 2018 product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) v in = 14 v, v en 2 v, t j = ? 40 o c to 150 o c unless otherwise noted v in = 6 v to 40 v v out = 5 v c out = 10 f i out = 1 ma figure 15. line transient v in = 40 v to 6 v v out = 5 v c out = 10 f i out = 1 ma figure 16. line transient v in = 6 v to 40 v v out = 5 v c out = 10 f i out = 200 ma figure 17. line transient v in = 40 v to 6 v v out = 5 v c out = 10 f i out = 200 ma figure 18. line transient v out = 5 v c out = 10 f i out = 1 ma to 200 ma figure 19. load transient v out = 5 v c out = 10 f i out = 200 ma to 1 ma figure 20. load transient v (5 v/div) in v (1 v/div) out v (50 mv/div) out(ac) i (200 ma/div) out v out (1 v/div) v in (10 v/div) v out(ac) (100 mv/div) i out (10 ma/div) v (10 v/div) in v (1 v/div) out v (100 mv/div) out(ac) i (10 ma/div) out advance information v (5 v/div) in v (1 v/div) out i (200 ma/div) out v (500 mv/div) out(ac) v (5 v/div) in v (1 v/div) out i (200 ma/div) out v (500 mv/div) out(ac) v (5 v/div) in v (1 v/div) out v (50 mv/div) out(ac) i (200 ma/div) out
10 tps7b70-q1 slvsek5 ? august 2018 www.ti.com product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the tps7b70-q1 device is a 300-ma, 40-v monolithic low-dropout linear voltage regulator with adjustable power-good threshold functionality. these voltage regulators consume only 19- a quiescent current in light-load applications. because of the adjustable power-good delay (also called power-on-reset delay) and the adjustable power-good threshold, these devices are an excellent choice as power supplies for microprocessors and microcontrollers in automotive applications. 7.2 functional block diagram 7.3 feature description 7.3.1 device enable (en) the en pin is a high-voltage-tolerant pin. a high input activates the device and turns the regulator on. connect this input pin to an external microcontroller or a digital control circuit to enable and disable the device, or connect to the in pin for self-bias applications. in v ref overcurrent protection out delay en pg v (pg_ref) pgadj regulator control thermal shutdown undervoltage lockout band gap filter power good control with delay amp gnd vint + error amp + gnd advance information
11 tps7b70-q1 www.ti.com slvsek5 ? august 2018 product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 7.3.2 adjustable power-good threshold (pg, pgadj) the pg pin is an open-drain output with an external pullup resistor to the regulated supply, and the pgadj pin is a power-good threshold adjustment pin. connecting the pgadj pin to gnd sets the power-good threshold value to the default, v (pg_th) . when v out exceeds the default power-good threshold, the pg output turns high after the power-good delay has expired. when v out falls below v (pg_th) ? v (pg_hyst) , the pg output turns low after a short deglitch time. the power-good threshold is also adjustable from 1.1 v to 5 v by using an external resistor divider between pgadj and out. the threshold can be calculated using equation 1 : where ? v (pg_adj) is the adjustable power-good threshold ? v (pg_ref) is the internal comparator reference voltage of the pgadj pin, 1.1 v typical, 2% accuracy specified under all conditions (1) by setting the power-good threshold v (pg_adj) , when v out exceeds this threshold, the pg output turns high after the power-good delay has expired. when v out falls below v (pg_adj) ? v (pg_hyst) , the pg output turns low after a short deglitch time. figure 21. adjustable power-good threshold 7.3.3 adjustable power-good delay timer (delay) the power-good delay, t (dly) , is the time from when pgadj is greater than v (pg,ref) until the pg pin goes high. the power-good delay is a function of the value of the external capacitor that is connected to the delay pin (c delay ). connecting an external capacitor from this pin to gnd sets the power-good delay. the constant current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator, and equation 2 determines the power-good delay: where ? t (dly) is the adjustable power-good delay ? c delay is the value of the power-good delay capacitor (2) delay (dly) c 1 v t 5 a = m advance information v (pg_ref) pgadj power-good control amp pg out delay v reg adjustable power-good threshold r1 r2 pg _ adj falling pgadj _ th falling pg _ adj risng pgadj _ th falling r1 r2 v v r2 r1 r2 v v 26 mv typ r2 u a o u ? ?
12 tps7b70-q1 slvsek5 ? august 2018 www.ti.com product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) figure 22. power up and conditions for activation of power good if the delay pin is open, the default delay time is t (dly_fix) . 7.3.4 undervoltage shutdown these devices have an integrated undervoltage lockout (uvlo) circuit that shuts down the output if the input voltage falls below an internal uvlo threshold, v (uvlo) . the uvlo circuit makes sure that the regulator does not latch into an unknown state during low-input-voltage conditions. if the input voltage has a negative transient that drops below the uvlo threshold and recovers, the regulator shuts down and powers up with a normal power-up sequence after the input voltage rises above the required level. 7.3.5 current limit these devices have current-limit protection to keep the device in a safe operating area when an overload or output short-to-ground condition occurs. this feature protects devices from excessive power dissipation. for example, during a short-circuit condition on the output, fault protection limits the current through the pass element to i (lim) to protect the device from excessive power dissipation. 7.3.6 thermal shutdown these devices incorporate a thermal shutdown (tsd) circuit as a protection from overheating. for continuous normal operation, the junction temperature must not exceed the tsd trip point. if the junction temperature exceeds the tsd trip point, the output turns off. when the junction temperature falls below the t (sd) ? t (hyst) , the output turns on again. 7.4 device functional modes 7.4.1 operation with input voltage less than 4 v the devices normally operate with input voltages above 4 v. the devices can also operate at lower input voltages; the maximum uvlo voltage is 2.6 v. at input voltages below the actual uvlo voltage, the devices do not operate. 7.4.2 operation with input voltage greater than 4 v when the input voltage is greater than 4 v, if the input voltage is greater than the output set value plus the device dropout voltage, then the output voltage is equal to the set value. otherwise, the output voltage is equal to the input voltage minus the dropout voltage. advance information v in pg v (pg_th) falling (pg_adj) falling v v (pg_th ) rising v (pg_adj ) rising t < t (deglitch) t (deglitch) t (deglitch) delay t (dly ) input voltage drop undervoltage power up power down v (uvlo) v( pg_hyst) v out t (dly ) v (dly _th)
13 tps7b70-q1 www.ti.com slvsek5 ? august 2018 product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the tps7b70-q1 device is a 300-ma low-dropout linear regulator with ultra-low quiescent current. the pspice transient model is available for download on the product folder and can be used to evaluate the basic function of the device. 8.2 typical application figure 23 shows a typical application circuit for the tps7b70-q1 device. different values of external components can be used, depending on the end application. an application may require a larger output capacitor during fast load steps to prevent a large drop on the output voltage. use a low-esr ceramic capacitor with a dielectric of type x7r. figure 23. supply power to an mcu advance information in en delay out pgadj pg gnd vint 100 nf 10 ? f 10 k 10 k 31.6 k 10 ? f can mcu tps7b70-q1 v in i/o
14 tps7b70-q1 slvsek5 ? august 2018 www.ti.com product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) 8.2.1 design requirements for this design, the tps7b70-q1 must be able to supply a can transceiver and an mcu from a 12-v automotive battery. to provide good mcu operation, the pg pin must trip when the output is at 95% of the nominal value. the pg pin must have a 20-ms delay in order to avoid shutting down as a result of temporary glitches. 8.2.2 detailed design procedure 8.2.2.1 input capacitor a 10- f capacitor in parallel with a 0.1 f ceramic bypass capacitor is placed at the input in order to keep the input voltage stable. the input can tolerate transients up to 40 v, so the input capacitors have a 50-v voltage rating. 8.2.2.2 output capacitor for this application, a 10- f x7r ceramic capacitor is used to provide good output transient performance and good loop stability. 8.2.2.3 power-good threshold the power-good threshold is set by connecting pgadj to gnd, or by connecting pgadj to a resistor divider from out to gnd. the adjustable power-good threshold (pg, pgadj) section provides the method to setup the power-good threshold. rearranging equation 1 yields equation 3 , and solves the values of r1 and r2 that are needed to get the 95% falling threshold. in this design, r2 is a 10-k resistor. solving equation 3 for r1 gives a value of 33.18 k . this is not a standard 1% resistor value, so a 31.6-k resistor is chosen for r1. (3) 8.2.2.4 power-good delay, t (dly) set the power-good delay with an external capacitor (c delay ) to ground. calculate the correct capacitance with equation 2 . this application requires a delay of 20 ms, so solve for the correct capacitance required to get this delay. rearrange equation 2 to solve for c delay , as shown in equation 4 (4) 8.2.3 application curves figure 24. power-up waveform (pgadj)falling (ptgadj _ th)falling v r1 r2 v ? ? ? 1 delay dly c = t 5 $ v in (5 v/div) v out (2 v/div) v pg (2 v/div) i (10 ma/div) out advance information
15 tps7b70-q1 www.ti.com slvsek5 ? august 2018 product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 power supply recommendations the device is designed to operate from an input-voltage supply range from 4 v to 40 v. this input supply must be well regulated. if the input supply is located more than a few inches from the tps7b70-q1 device, add a capacitor with a value of 10 f with a 0.1 f ceramic bypass capacitor in parallel at the input. 10 layout 10.1 layout guidelines for ldo power supplies, especially high-voltage and high-current supplies, layout is an important step. if the layout is not carefully designed, the regulator cannot deliver enough output current because of thermal limitations. to improve the thermal performance of the device and maximize the current output at high ambient temperature, spread out the thermal pad as much as possible, and put enough thermal vias on the thermal pad. figure 25 shows an example layout. 10.2 layout example figure 25. layout example in en gnd gnd gnd gnd gnd delay out pgadj pg gnd gnd vint gnd gnd 19 12 3 4 5 6 7 8 13 14 15 16 17 18 20 denotes a via advance information
16 tps7b70-q1 slvsek5 ? august 2018 www.ti.com product folder links: tps7b70-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 device and documentation support 11.1 documentation support 11.1.1 related documentation for related documentation see the following: tps7b70evm-008 evaluation module user ' s guide 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks powerpad, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most- current data available for the designated devices. this data is subject to change without notice and without revision of this document. for browser-based versions of this data sheet, see the left-hand navigation pane. advance information
package option addendum www.ti.com 7-sep-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples PTPS7B7033QPWPRQ1 active htssop pwp 16 2000 tbd call ti call ti -40 to 125 ptps7b7050qpwprq1 active htssop pwp 16 2000 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

www.ti.com package outline c 14x 0.65 2x 4.55 16x 0.30 0.19 typ 6.6 6.2 0.15 0.05 0.25 gage plane -8 0 1.2 max 3.55 2.68 2.46 1.75 b 4.5 4.3 a note 3 5.1 4.9 0.75 0.50 (0.15) typ powerpad tssop - 1.2 mm max height pwp0016j small outline package 4223595/a 03/2017 1 8 9 16 0.1 c a b pin 1 index area see detail a 0.1 c notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. reference jedec registration mo-153. seating plane tm powerpad is a trademark of texas instruments. a 20 detail a typical scale 2.500 thermal pad 1 8 9 16
www.ti.com example board layout 0.05 max all around 0.05 min all around 16x (1.5) 16x (0.45) 14x (0.65) (5.8) (r0.05) typ (3.4) note 8 (5) note 8 (1.35) typ (0.65) (1.3) typ ( 0.2) typ via (2.46) (3.55) powerpad tssop - 1.2 mm max height pwp0016j small outline package 4223595/a 03/2017 notes: (continued) 5. publication ipc-7351 may have alternate designs. 6. solder mask tolerances between and around signal pads can vary based on board fabrication site. 7. this package is designed to be soldered to a thermal pad on the board. for more information, see texas instruments literature numbers slma002 (www.ti.com/lit/slma002) and slma004 (www.ti.com/lit/slma004). 8. size of metal pad may vary due to creepage requirement. 9. vias are optional depending on application, refer to device data sheet. it is recommended that vias under paste be filled, plugged or tented. tm see details land pattern example exposed metal shown scale: 10x symm symm 1 8 9 16 metal covered by solder mask solder mask defined pad 15.000 metal solder mask opening metal under solder mask solder mask opening exposed metal exposed metal solder mask details non-solder mask defined solder mask defined
www.ti.com example stencil design 16x (1.5) 16x (0.45) 14x (0.65) (5.8) (r0.05) typ (3.55) based on 0.125 thick stencil (2.46) based on 0.125 thick stencil powerpad tssop - 1.2 mm max height pwp0016j small outline package 4223595/a 03/2017 2.08 x 3.00 0.175 2.25 x 3.24 0.15 2.46 x 3.55 (shown) 0.125 2.75 x 3.97 0.1 solder stencil opening stencil thickness notes: (continued) 10. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 11. board assembly site may have different recommendations for stencil design. tm solder paste example based on 0.125 mm thick stencil scale: 10x symm symm 1 8 9 16 metal covered by solder mask see table for different openings for other stencil thicknesses
important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ? as is ? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti ? s products are provided subject to ti ? s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti ? s provision of these resources does not expand or otherwise alter ti ? s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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