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nxp semiconductors data sheet: technical data document number: IMX6SLLIEC rev. 0.2, 11/2017 ordering information see table 1 on page 2 ? 2017 nxp b.v. mcimx6v2cvm08ab package information plastic package 14 x 14 mm, 0.65 mm pitch bga 1 introduction the i.mx 6sll processor represents nxp?s latest achievement in integrated multimedia applications processors, which are part of a growing family of multimedia-focused products that offer high performance processing and are optimized for lowest power consumption. the processor features nxp?s advanced implementation of a single arm ? cortex ? -a9, which operates at speeds up to 800 mhz. the processor provides a 32-bit ddr interface that supports lpddr2 and lpddr3. in addition, there are a number of other interfaces for connecting peripherals, such as wlan, bluetooth?, gps, hard drive, displays, and camera sensors. the i.mx 6sll processor is specifically useful for applications, such as: ? color and monochrome ereaders ? barcode scanners ? connectivity ? iot devices i.mx 6sll applications processors for industrial products 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. ordering information . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1. special signal considerations . . . . . . . . . . . . . . . 11 3.2. recommended connections for unused analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1. chip-level conditions . . . . . . . . . . . . . . . . . . . . . 15 4.2. power supplies requirements and restrictions . 23 4.3. integrated ldo voltage regulator parameters . . 24 4.4. pll?s electrical characteristics . . . . . . . . . . . . . . . 25 4.5. on-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . 26 4.6. i/o dc parameters . . . . . . . . . . . . . . . . . . . . . . . . 27 4.7. i/o ac parameters . . . . . . . . . . . . . . . . . . . . . . . . 31 4.8. output buffer impedance parameters . . . . . . . . . 33 4.9. system modules timing . . . . . . . . . . . . . . . . . . . . 36 4.10. external peripheral interface parameters . . . . . . . 39 5. boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 65 5.1. boot mode configuration pins . . . . . . . . . . . . . . . 65 5.2. boot devices interfaces allocation . . . . . . . . . . . . 66 6. package information and contact assignments . . . . . . 67 6.1. 14 x 14 mm package information . . . . . . . . . . . . . 67 7. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 2 nxp semiconductors introduction the i.mx 6sll processor features: ? applications processor?the i.mx 6sll incorporates a 1 ghz cort ex a9 with the neon simd engine and a floating point engine that is opt imized for low power c onsumption and includes hardware that allows dynamic vol tage and frequency scaling (dv fs). this optimizes the voltage to the processor as the frequency change s with the demands of the application. ? multilevel memory system?the multilevel memory system for the processor is based on the l1 instruction and data caches, l2 cache, and intern al and external memory. the processor supports many types of external memory device s, including lpddr2, lpddr3, and emmc. ? powerful graphics acceleration? the processor has a 2d graphics processor called the pixel processor (pxp) that can support csc, dithering, rotation, resize, and overlay. ? interface flexibility?the processor supports conn ections to a variety of interfaces: high-speed usb on-the-go with phy, high-speed usb host ph y, multiple expansion card ports (high-speed mmc/sdio host and other), and a variety of other popular interfaces (such as uart, i 2 c, and i 2 s). ? electronic paper display contro ller?the processor integrates epd controller that supports e-ink color and monochrome with up to 2332 x 1650 resolution and 5-bit grayscale. ? advanced security?the processor de livers hardware-enabled security features that enable secure information encryption, secure boot, and secure so ftware downloads. the se curity features are discussed in the i.mx 6sll security reference manual (imx6sllsrm). cont act your local nxp representative for more information. ? gpio with interrupt capabiliti es?the gpio pad design supports configurable dua l voltage rails at 1.8 v and 3.3 v supplies. the pad is configur able to interface at either voltage level. 1.1 ordering information table 1 shows the orderable part numbers covered by this data sheet. table 1. example orderable part numbers part number feature temperature (tj) package mcimx6v2cvm08ab features supports: ? 800 mhz, industrial grade for general purpose ? basic security ? with lcd/csi ? pxp ? no epdc ? emmc 5.0/sd 3.0 x3 ? usb otg x2 ?uart x5 ? ssi x3 ?timer x3 ?pwm x4 ?i2c x4 ? spi x4 -40 to +105 ? c 14x14 mm, 0.65 mm pitch bga
introduction i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 3 figure 1 describes the part number nomencl ature so that characteristics of a specific part number can be identified (for example, cores, frequency, te mperature grade, fuse opt ions, silicon revision). ? the i.mx 6sll applications processors for industrial pr oducts data sheet (IMX6SLLIEC) covers parts listed with a ?c (industrial temp)? ensure to have the right data sheet for specific pa rt by checking the temperature grade (junction) field and matching it to the right data sheet. if there are any questions, visit the web page nxp.com/imx6series or contact a nxp representative. figure 1. part number nomenclature?i.mx 6sll 1.2 features the i.mx 6sll processor is based on arm cortex-a 9 processor, which has the following features: ? arm cortex-a9 mpcore cpu processor (with trustzone) ? the core configuration is symmetric, where each core includes: ? 32 kbyte l1 instruction cache ? 32 kbyte l1 data cache ? private timer and watchdog ? cortex-a9 neon mpe (media processing engine) co-processor junction temperature (tj) + consumer: 0 to + 95 c d industrial: -40 to +105 c c arm cortex-a9 frequency $$ 1 ghz 10 800 mhz 08 package type rohs 13 x 13 0.5 mm bga vn 14 x 14 0.65 mm bga vm qualification level mc prototype samples pc mass production mc special sc part # series x i.mx 6sll v silicon rev a rev 1.0 a rev 1.1 b fusing % reserved a mc imx6 x @ + vv $$ % a part differentiator @ with epdc 7 reserved for gpu option in the future 6 5 4 security 3 general purpose 2 (full feature) 2 general purpose 1 (reduced feature) 1 baseline, consumer 0
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 4 nxp semiconductors introduction the arm cortex-a9 includes: ? general interrupt controller (gic) with 128 interrupt support ? global timer ? 256 kb unified i/d l2 cache ? two master axi (64-bit) bus interfaces output of l2 cache ? frequency of the core (includi ng neon and l1 cache) as per table 9, "operating ranges," on page 19 ? neon mpe coprocessor ? simd media processing architecture ? neon register file with 32x64- bit general-purpose registers ? neon integer execute pipe line (alu, shift, mac) ? neon dual, single-precision floating poi nt execute pipeli ne (fadd, fmul) ? neon load/store and permute pipeline the soc-level memory system consists of the following a dditional components: ? boot rom, including hab (96 kb) ? internal multimedia / shared, fast access ram (ocram, 128 kb) ? external memory interfaces: ? 32-bit lpddr2/lpddr3 each i.mx 6sll processor enables the following interfac es to external devices (some of them are muxed and not available simultaneously): ? display: ? epdc, color, and monochrome e-ink, up to 2332x1650 resolution and 5-bit grayscale ? 24-bit parallel lcd ? expansion cards: ? three mmc/sd/sdio card ports all supporting: ? sd 3.0 support ? emmc 5.0 support in hs400 mode ?usb: ? two high speed (hs) usb 2.0 otg (up to 480 mbps), with inte grated hs usb phy ? miscellaneous ips and interfaces: ? ssi block?capable of supporting audio sample frequencies up to 192 khz stereo inputs and outputs with i 2 s mode ? five uarts, up to 5.0 mbps each: ? providing rs232 interface ? supporting 9-bit rs485 multidrop mode ? one of the five uarts supports 8-wire, while others four supports 4-wire. this is due to the soc iomux limitation, since all uart ips are identical.
introduction i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 5 ? four ecspi (enhanced cspi) ? three i 2 c, supporting 400 kbps ? four pulse width modulators (pwm) ? system jtag controller (sjc) ? gpio with interrupt capabilities ? sony philips digital inte rface (spdif), rx and tx ? two watchdog timers (wdog) ? audio mux (audmux) the i.mx 6sll processor integrates power management uni t and controllers: ? provide pmu, including ldo su pplies, for on-chip resources ? use temperature sensor for monitoring the die temperature ? support dvfs techniques for low power modes ? use software state retention and power gating for arm and neon ? support various levels of system power modes ? use flexible clock gating control scheme the i.mx 6sll processor uses dedicat ed hardware accelerators to meet needs of e-ink di splays. the use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers, while having the cpu core relatively free for performing other tasks. the i.mx 6sll processor incorporates the following hardware accelerators: ? pxp?pixel processing pipeline. off loading ke y pixel processing operations are required to support the epd disp lay applications. security functions are enabled and accelerated by the following hardware: ? arm trustzone including the tz architecture (s eparation of interrupts, memory mapping, etc.) ? sjc?system jtag controller. protecting jt ag from debug port attacks by regulating or blocking the access to th e system debug features. ? snvs?secure non-volatile storage, including secure real time clock. ? csu?central security unit. enhancement for the ic identification module (iim). will be configured during boot and by efus es and will determine the secu rity level operation mode as well as the tz policy. ? a-hab?advanced high assurance boot?hab v4 with the new embedded enhancements. the actual feature set depends on th e part numbers as described in table 1, "example orderable part numbers," on page 2 . functions, such as 2d hardware graphics accelerat ion or e-ink may not be en abled for specific part numbers.
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 6 nxp semiconductors architectural overview 2 architectural overview the following subsections provide an architectural overview of the i.mx 6sll processor system. 2.1 block diagram figure 2 shows the functional modules in the i.mx 6sll processor system. figure 2. i.mx 6sll system block diagram note the numbers in brackets indicate numbe r of module instances. for example, pwm (x4) indicates four separate pwm peripherals. cpu platform system control arm cortex-a9 secure jtag pll, osc rtc and reset neon watch dog x2 timer x3 pwm x4 smart dma 256 kb l2-cache 32 kb d-cache multimedia connectivity emmc 5.0 / sd 3.0 x3 uart x5 power management ldo iomux temp monitor etm 32 kb i-cache external memory internal memory 96 kb rom 128 kb ram 32-bit dram controller 400 mhz lpddr2/lpddr3 i2c x3 usb2 otg with phy x2 i 2 s/ssi x3 s/pdif tx/rx gpio spi x4 pxp csc/rotation/resize/overlay e- /e modules list i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 7 3 modules list the i.mx 6sll processor contains a variety of digital and analog modules. table 2 describes these modules in alphabetical order. table 2. i.mx 6sll modules list block mnemonic block name subsystem brief description fuse box electrical fuse array security electrical fuse array. enables to setup boot modes, security levels, security keys, and many other system parameters. arm arm platform arm the arm cortex-a9 platform consists of a cortex-a9 core and associated sub-blocks, including level 2 cache controller, gic (general interrupt controller), private timers, watchdog, and coresight debug modules. audmux digital audio mux multimedia peripherals the digital audio multiplexer (audmux) provides a programmable interconnect device for voice, audio, and synchronous data routing between synchronous serial interface controller (ssi) and audio/voice codec?s (also known as coder-decoders) peripheral serial interfaces. ccm gpc src clock control module, general power controller, system reset controller clocks, resets, and power control these modules are responsible for cloc k and reset distribu tion in the system, and also for the syst em power management. csi parallel csi multimedia peripherals the csi ip provides parallel csi standard camera interface port. the csi parallel data ports are up to 24 bits. it is designed to support 24-bit rgb888/yuv444, ccir656 video interface, 8-bit ycbcr, yuv or rgb, and 8-bit/10-bit/16-bit bayer data input. csu central security unit security the central security unit (csu) is responsible for setting comprehensive security policy within the i.mx 6sll pl atform. the security control registers (scr) of the csu are set during boot time by the hab and are locked to prevent further writing. cti-1 cti-2 cross trigger interfaces debug / trace cross trigger interfaces allows cross-triggering based on inputs from masters attached to ctis. the cti module is internal to the cortex-a9 core platform. ctm cross trigger matrix debug / trace cross trigger matrix ip is used to route triggering events between ctis. the ctm module is internal to the cortex-a9 core platform. dap debug access port system control peripherals the dap provides real-time access for the debugger without halting the core to: ? system memory and peripheral registers ? all debug configuration registers the dap also provides debugger access to jtag scan chains. the dap module is internal to the cortex-a9 core platform. dcp data co-processor security this module provides support for general encryption and hashing functions typically used for security functions. because its basic job is moving data from memory to memory, it also incorporates a memory-copy (memcopy) function for both debugging and as a more efficient method of copying data between memory blocks than the dma-based approach.
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 8 nxp semiconductors modules list ecspi-1 ecspi-2 ecspi-3 ecspi-4 configurable spi connectivity peripherals full-duplex enhanced synchronous serial interface. it is configurable to support master/slave modes, four chip selects to support multiple peripherals. epdc electrophoretic display controller peripherals the epdc is a feature-rich, low power, and high-performance direct-drive, active matrix epd controller. it is specifically designed to drive e-ink ? epd panels, supporting a wide variety of tft backplanes. epit-1 epit-2 enhanced periodic interrupt timer timer peripherals each epit is a 32-bit ?set and forget? ti mer that starts counting after the epit is enabled by software. it is capable of providing precise interrupts at regular intervals with minimal processor intervention. it has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter value can be programmed on the fly. gpio-1 gpio-2 gpio-3 gpio-4 gpio-5 gpio-6 general purpose i/o modules system control peripherals used for general purpose input/output to external ics. gpio module (1 - 5) supports 32 bits of i/o and gpio6 supports 5 bits of i/o. gpt general purpose timer timer peripherals each gpt is a 32-bit ?free-running? or ?set and forget? mode timer with programmable prescaler and compare an d capture register. a timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. when the timer is configured to operate in ?set and forget? mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. the counter has output co mpare logic to provide the status and interrupt at comparison. this timer can be configured to run either on an external clock or on an internal clock. i 2 c-1 i 2 c-2 i 2 c-3 i 2 c interface connectivity peripherals i 2 c provide serial interface for external devices. data rates of up to 400 kbps are supported. iomuxc iomux control system control peripherals this module enables flexible io multiplexing. each io pad has default and several alternate functions. the alternate functions are software configurable. lcdif lcd interface connectivity peripherals the lcdif is a general purpose display controller used to drive a wide range of display devices varying in size and capability. the lcdif is designed to support dumb (synchronous 24-bit parallel rgb interface) and smart (asynchronous parallel mpu interface) lcd devices. mmdc multi-mode ddr controller connectivity peripherals ddr controller has the following features: ? support 32-bit lpddr2/lpddr3 ? supports up to 2 gbyte ddr memory space table 2. i.mx 6sll modules list (continued) block mnemonic block name subsystem brief description
modules list i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 9 ocotp_ ctrl otp controller security the on-chip otp controller (ocotp_ctrl) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. the module supports electrically-programmable poly fuse s (efuses). the ocotp_ctrl also provides a set of volatile software-accessible signals that can be used for software control of hardware elemen ts, not requiring non-volatility. the ocotp_ctrl provides the primary user-visible mechanism for interfacing with on-chip fuse elements. among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, jtag secure mode, boot characteristics, and various control signals, requiring permanent non-volatility. ocram on-chip memory controller data path the on-chip memory controller (ocram) module is designed as an interface between system?s axi bus and internal (on-chip) sram memory module. in i.mx 6sll processor, the ocram is used for controlling the 128 kb multimedia ram through a 64-bit axi bus. ocram_l 2 on-chip memory controller for l2 cache data path the on-chip memory controlle r for l2 cache (ocram_l2) module is designed as an interface between system?s axi bus and internal (on-chip) l2 cache memory module during boot mode. osc 32 khz osc 32 khz clocking generates 32.768 khz clock from external crystal. pmu power- management functions data path integrated power management unit. used to provide power to various soc domains. pwm-1 pwm-2 pwm-3 pwm-4 pulse width modulation connectivity peripherals the pulse-width modulator (pwm) has a 16-bit counter and is optimized to generate sound from stored sample au dio images and it can also generate tones. it uses 16-bit resolution and a 4x16 data fifo to generate sound. pxp pixel processing pipeline display peripherals a high-performance pixel processor capable of 1 pixel/clock performance for combined operations, such as color-space conversion, alpha blending, gamma-mapping, and rotation. the pxp is enhanced with features specifically for gray scale applicat ions. in addition , the pxp supports traditional pixel/frame processing paths for still-image and video processing applications, allowing it to interface with either of the integrated epd controllers. ram 128 kb internal ram internal memory internal ram, which is accessed through ocram memory controller. rngb random number generator security random number generating module. rom 96kb boot rom internal memory supports secure and regular boot modes. includes read protection on 4k region for content protection. romcp rom controller with patch data path rom controller with rom patch support sdma smart direct memory access system control peripherals the sdma is multi-channel flexible dma engine. it helps in maximizing system performance by off-loading the va rious cores in dyna mic data routing. table 2. i.mx 6sll modules list (continued) block mnemonic block name subsystem brief description
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 10 nxp semiconductors modules list sjc system jtag controller system control peripherals the sjc provides jtag interface, which complies with jtag tap standards, to internal logic. the i.mx 6sll processor uses jtag port for production, testing, and system debugging. in addition, the sjc provides bsr (boundary scan register) standard support, which complies with ieee1149.1 and ieee1149.6 standards. the jtag port must be accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. t he i.mx 6sll sjc incorporates three security modes for protecting against unauthorized accesses. modes are selected through efuse configuration. snvs secure non-volatile storage security secure non-volatile storage, including secure real time clock, security state machine, master key control, and violation/tamper detection and reporting. spdif sony phillips digital interface multimedia peripherals a standard audio file transfer format, developed jointly by the sony and phillips corporations. has transmitter and receiver functionality. ssi-1 ssi-2 ssi-3 i2s/ssi/ac97 interface connectivity peripherals the ssi is a full-duplex synchronous interface, which is used on the ap to provide connectivity with off-chip audio peripherals. the ssi supports a wide variety of protocols (ssi normal, ssi network, i2s, and ac-97), bit depths (up to 24 bits per word), and clock / frame sync options. tempmon temperature monitor system control peripherals the temperature monitor/sensor ip, for detecting high temperature conditions. the temperature sensor ip for detecting die temper ature. the temperature read out does not reflect case or ambient temperature, but the proximity of the temperature sensor location on the die. temperature distribution may not be uniformly distributed, therefore the read out value may not be the reflection of the temperature value of the entire die. tzasc trust-zone address space controller security the tzasc (tzc-380 by arm) pr ovides security address region control functions required for intended application. it is used on the path to the dram controller. uart-1 uart-2 uart-3 uart-4 uart-5 uart interface connectivity peripherals each of the uartv2 modules support the following serial data transmit/receive protoc ols and configurations: ? 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or none) ? programmable baud rates up to 5 mbps. ? 32-byte fifo on tx and 32 half-w ord fifo on rx supporting auto-baud ? irda 1.0 support (up to sir speed of 115200 bps) ? only one can operate as 8-pins full uart, dce, or dte usbo2 2x usb 2.0 high speed otg connectivity peripherals usbo2 contains: ? two high-speed otg module with integrated hs usb phy table 2. i.mx 6sll modules list (continued) block mnemonic block name subsystem brief description
modules list i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 11 3.1 special signal considerations table 3 lists special signal considerati ons for the i.mx 6sll processor. the signal names are listed in alphabetical order. the package contact assign ments can be found in section 6, ?package information and contact assignments " .? signal descriptions are provided in the i.mx 6sll reference manual . usdhc-1 usdhc-2 usdhc-3 sd/mmc and sdxc enhanced multi-media card / secure digital host controller connectivity peripherals i.mx 6sll specific soc characteristics: all three mmc/sd/sdio controller ips are identical and are based on the usdhc ip. they are: ? fully compliant with mmc command/response sets and physical layer as defined in the multimedia card system specification, v5.0 including high-capacity (size > 2 gb) cards hc mmc. ? fully compliant with sd command/response sets and physical layer as defined in the sd memory card specifications, v3.0 including high-capacity sdhc cards up to 32 gb and sdxc cards up to 2 tb. ? fully compliant with sdio command/re sponse sets and interrupt/read-wait mode as defined in the sdio card specification, part e1, v1.10 wdog-1 watchdog timer peripherals the watchdog timer supports two comparison points during each counting period. each of the comparison points is configurable to evoke an interrupt to the arm core, and a second point evokes an external event on the wdog line. wdog-2 (tz) watchdog (trustzone) timer peripherals the trustzone watchdog (tz wdog) timer module protects against trustzone starvation by providing a method of escaping normal mode and forcing a switch to the tz mode. tz star vation is a situation where the normal os prevents switching to the tz mode. su ch situation is undesirable as it can compromise the system?s se curity. once the tz wdog module is activated, it must be serviced by tz software on a periodic basis. if servicing does not take place, the timer times out. upon a time-out, the tz wdog asserts a tz mapped interrupt that forces switching to the tz mode. if it is still not served, the tz wdog asserts a security violation signal to the csu. the tz wdog module cannot be programmed or deactivated by a normal mode software. xtalosc crystal oscillator i/f clocking the xtalosc module enables connectivity to external crystal oscillator device. in a typical application use-case, it is used for 24 mhz oscillator. table 2. i.mx 6sll modules list (continued) block mnemonic block name subsystem brief description
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 12 nxp semiconductors modules list table 3. special signal considerations signal name remarks clk1_p/ clk1_n one general purpose differential high speed clock input/output is provided. it could be used to: ? to feed external reference clock to the plls and further to the modules inside soc, for example as alternate reference clock for audio interfaces, etc. ? to output internal soc clock to be used outside th e soc as either reference clock or as a functional clock for peripherals. see the i.mx 6sll reference manual for details on the respective clock trees. the clock inputs/outputs are lvds differential pa irs compatible with tia/eia-644 standard. the corresponding clk1_n input should be tied to the constant voltage level equal 1/2 of the input signal swing. termination should be provided in case of high frequency signals. see lvds pad electrical specification for further details. after initialization, the clk1 inpu t/output could be disabled (if not used). if unused, the clk1_n/p pair may remain unconnected. dram_vref when using dram_vref with ddr i/o, the nominal reference voltage must be half of the nvcc_dram supply. the user must tie dram_vref to a precision external resistor divider. use a 1 k ? 0.5% resistor to gnd and a 1 k ? 0.5% resistor to nvcc_dram. shunt eac h resistor with a closely-mounted 0.1 f capacitor. to reduce supply current, a pair of 1.5 k ? 0.1% resistors can be used. using resistors with recommended tolerances ensures the 2% dram_vref tolerance ( per the ddr3 specification) is maintained when four ddr3 ics plus the i.mx 6sll are dr awing current on the resistor divider. it is recommended to use regulated power supply for ?big? memory configurations (more that eight devices). jtag_ nnnn the jtag interface is summarized in ta bl e 4 . use of external resistors is unnecessary. however, if external resistors are used, the user must ensure th at the on-chip pull-up/down configuration is followed. for example, do not use an external pull down on an input that has on-chip pull-up. jtag_tdo is configured wit h a keeper circuit such that the non-connected condition is eliminated if an external pull resistor is not present. an external pul l resistor on jtag_tdo is detrimental and should be avoided. jtag_mode must be externally connected to gnd fo r normal operation. termination to gnd through an external pull-down resistor (such as 1 k ? ) is allowed. jtag_mode set to high configures the jtag interface to mode compliant with ieee1149.1 standar d. jtag_mode set to low configures the jtag interface for common software debug adding all the system taps to the chain. nc these signals are no connect (nc) and should be disconnected by the user. onoff in normal mode may be connected to onoff button ( de-bouncing provided at this input). internally this pad is pulled up. a short duration (<5s) connection to gnd in off mode causes the internal power management state machine to change the state to on. in on mode, a short duration connection to gnd generates interrupt (intended to initiate a software co ntrollable power down). a long duration (above ~5s) connection to gnd causes ?forced? off. por_b this cold reset negative logic input resets all modules and logic in the ic. may be used in addition to internally generated power on reset signal (logical and, both internal and external signals are considered active low)
modules list i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 13 3.2 recommended connections for unused analog interfaces table 5 shows the recommended connecti ons for unused analog interfaces. rtc_xtali/ rtc_xtalo if the user wishes to configure rtc_xtali and rt c_xtalo as an rtc oscillator, a 32.768 khz crystal ( ? 100 k ? esr, 10 pf load) should be connected between rtc_xtali and rtc_xtalo. keep in mind the capacitors implemented on either side of the cryst al are about twice the crystal load capacitor. to hit the exact oscillation frequency, the board capacitors need to be reduced to account for board and chip parasitics. the integrated oscillation amplifier is self biasing, but relatively weak. care must be taken to limit parasitic leakage from rtc_xtali and rtc_xtalo to either power or ground (>100 m ? ). this will debias the amplifier and cause a reduction of startup margin. typically rtc_xtali and rtc_xtalo should bias to approximately 0.5 v. if it is desired to feed an external low frequency clock into rtc_xtali, the rtc_xtalo pin must remain unconnected or driven with a complimentary signal. th e logic level of this forcing clock should not exceed vdd_snvs_cap level and the frequency should be <100 khz under typical conditions. in the case when a high accuracy real time clock is not required, the system may use an internal low frequency ring oscillator. it is recommended to connect rtc_xtali to gnd and keep rtc_xtalo unconnected. test_mode test_mode is for nxp factory use. this signal is internally connected to an on-chip pull-down device. the user must either disconnect this signal or tie it to gnd. xtali/xtalo a 24.0 mhz crystal should be connected between xtali and xtalo. level and the frequency should be <32 mhz under typical conditions. the crystal must be rated for a maximum drive level of 250 ? w. an esr (equivalent series resistance) of typically 80 ? is recommended. nxp bsp (board support package) software requires 24 mhz on xtali/xtalo. the crystal can be eliminated if an external 24 mhz o scillator is available in the system. in this case, xtali must be directly driven by the external o scillator and xtalo is disconnected. the xtali signal level must swing from ~0.8 x nvcc_pll to ~0.2 v. this clock is used as a reference for usb, so there are strict frequency tolerance and jitter requirements. see the xtalosc chapter and relevant inte rface specifications chapters of the i.mx 6sll reference manual for details. zqpad dram calibration resistor 240 ? 1 % used as reference during dram output buffer driver calibration should be connected between this pad and gnd. table 4. jtag controller interface summary jtag i/o type on-chip termination jtag_tck input 47 k ? ? pull-up jtag_tms input 47 k ? ? pull-up jtag_tdi input 47 k ? ? pull-up jtag_tdo 3-state output keeper jtag_trst_b input 47 k ? ? pull-up jtag_mode input 100 k ? ? pull-up table 3. special signal considerations (continued) signal name remarks
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 14 nxp semiconductors modules list table 5. recommended connections for unused analog interfaces module pad name recommendations if unused xtalosc clk1_n, clk1_p not connected usb usb_otgx_dn, usb_otgx_dp, usb_otgx_vbus, usb_otg_chd_b not connected
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 15 4 electrical characteristics this section provides the device and module-level electrical char acteristics for the i.mx 6sll. 4.1 chip-level conditions this section provides the device-level el ectrical characteristics for the ic. see table 6 for a quick reference to the individual tables and sections. 4.1.1 absolute maximum ratings caution stresses beyond those listed under table 7 may cause permanent damage to the device. these are stress ratings onl y. functional operation of the device at these or any other conditi ons beyond those indicated under ?recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods ma y affect device reliability. table 7 shows the absolute maximum operating ratings. table 6. i.mx 6sll chip-level conditions for these characteristi cs ? topic appears ? absolute maximum ratings on page 15 thermal resistance on page 17 operating ranges on page 19 external clock sources on page 20 maximum supply currents on page 21 low power mode supply currents on page 22 usb phy current consumption on page 23 table 7. absolute maximum ratings parameter description symbol min max 1 unit core supply voltages vdd_arm_in vdd_soc_in -0.3 1.4 v gpio supply voltage supplies denoted as i/o supply -0.5 3.6 v ddr i/o supply voltage supplies denoted as i/o supply -0.4 1.975 (see note 2) v vdd_high_in supply voltage vdd_high_in -0.3 3.6 v usb_otg1_vbus, usb_otg2_vbus usb_otg1_vbus usb_otg2_vbus ?5.5v input voltage on usb_otg1_dp, usb_otg1_dn, and usb_otg2_dp, usb_otg2_dn pins usb_otg1_dp/usb_otg1_dn usb_otg2_dp/usb_otg2_dn -0.3 3.63 v
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 16 nxp semiconductors electrical characteristics input/output voltage range v in /v out -0.5 ovdd 3 +0.3 v esd immunity (hbm) all pins except vdd_snvs_cap and vdd_arm_in pins vesd_hbm ? 2000 v esd immunity (hbm) vdd_snvs_cap and vdd_arm_in pins vesd_hbm ? 1000 v esd immunity (cdm) vesd_cdm ? 500 v storage temperature range t storage -40 150 o c 1 exceeding maximum may result in breakdown, or reduction in ic life time, performance, and/or reliability. 2 the absolute maximum voltage includes an allowance for 400 mv of overshoot on the io pins. per jedec standards, the allowed signal overshoot must be derated if nvcc_dram exceeds 1.575 v. 3 ovdd is the i/o supply voltage. the following documents relating to esd design and robustness are available upon request. these documents do not comprise a part of this datasheet, information contained therei n is not a part of the nxp component specification, and nxp does not warrant the accuracy or completeness of such information. nxp?s customers ar e solely responsible for determining the suitability of nxp components for their purposes and for validating and testing their design implementation to confirm system functionality. ? an10853 ? esd and emc sensitivity of ic ? an2764 ? improving the transient immunity performance of microcontroller-based applications ? amf-des-t2360 ? pcb design techniques to improve esd robustness table 7. absolute maximum ratings (continued) parameter description symbol min max 1 unit
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 17 4.1.2 thermal resistance 4.1.2.1 14 x 14 mm (vm) package thermal resistance table 8 provides the 14 x 14 mm package thermal resistance data. 4.1.3 operating ranges figure 3 shows major power systems blocks and inte rnal/external connections for the i.mx 6sll processor. table 8. package thermal resistance data rating board symbol value unit junction to ambient 1,2 (natural convection) 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipa tion of other components on the board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. single layer board (1s) r ? ja 50.6 c/w junction to ambient 1,2,3 (natural convection) 3 per jedec jesd51-6 with the board horizontal. four layer board (2s2p) r ? ja 31.7 c/w junction to ambient 1,3 (at 200 ft/min) single layer board (1s) r ? jma 39.4 c/w four layer board (2s2p) r ? jma 27.5 c/w junction to board 4 4 thermal resistance between the die and the printed circuit b oard per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. ?r ? jb 16.7 c/w junction to case 5 5 thermal resistance between the die and the case top surface as measured by the cold plat e method (mil spec-883 method 1012.1). ?r ? jc 12.0 c/w junction to package top 6 6 the thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. natural convection ? jt 0.2 c/w junction to package bottom 7 7 thermal resistance between the die and the central solder balls on the bottom of the package based on simulation. natural convection r ? jb_csb 13.9 c/w
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 18 nxp semiconductors electrical characteristics figure 3. i.mx 6sll soc power block diagram 91rp 96we\ 9 ([whuqdo6xssolhv &rlq &hoo 9''b$50b,1 9''b+,*+b,1 9''b6196b,1 $50&ruh /&dfkh /'2b3 9''b+,*+b&$3 9''b62&b,1 *1' 3//v /'2b3 9''b3//b&$3 /'2b6196 86% h)xvh *1' 0 26& *1' 9''b6196b&$3 6196 . 26& 86%b27*b9%86 /'2b86% *1' 9''b86%b&$3 86%b27*b9%86 l0;6// 62&/rjlf $ozd\v21'rpdlq 9 19&&b'5$0 '5$0,2 19&&b'5$0b3 'xdo9rowdjh *3,2 19&&b,2 19&&b,2 9 91rp 96we\ 86%b27*b9%86 62&/rjlf 3rzhu'rzq'rpdlq /&dfkh 3* 3* 86%b27*b9%86 3* 9 3*
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 19 table 9 provides the operating ranges of the i.mx 6sll processor. 4.1.4 external clock sources each i.mx 6sll processor has two external input system clocks: a low frequency (rtc_xtali) and a high frequency (xtali). table 9. operating ranges parameter description symbol min typ max 1 1 applying the maximum voltage results in maximum power co nsumption and heat generation. nxp recommends a voltage set point = (vmin + the supply tolerance). this results in an optimized power/speed ratio. unit comment run mode vdd_arm_in 1.150 ? 1.26 v for operation up to 792 mhz. 1.05 ? 1.26 v for operation up to 396 mhz. 0.950 ? 1.26 v for operation up to 198 mhz 0.925 ? 1.26 v for operation up to 24 mhz vdd_soc_in 1.15 ? 1.26 v ? low power run mode vdd_arm_in 0.925 ? 1.26 v all pll bypassed, all clocks running at 24 mhz or below. vdd_soc_in 0.925 ? 1.26 v standby/dsm mode vdd_arm_in 0.9 ? 1.26 v see table 12, "low power mode current and power consumption," on page 22 . vddhigh internal regulator vdd_high_in 2 2 applying the maximum voltage results in shor ten lifetime. 3.6 v usage limit ed to < 1% of the use profile. rest of profile limit ed to below 3.49 v. 2.8 ? 3.6 v must match the range of voltages that the rechargeable backup battery supports. backup battery supply range vdd_snvs_in 2 2.4 ? 3.6 v should be supplied from the same supply as vdd_high_in if the system does not require keeping real time and other data on off state. usb supply voltages usb_otg1_vbus usb_otg2_vbus 4.4 ? 5.5 v ? ddr i/o supply nvcc_dram 1.14 1.2 1.26 v lpddr2, lpddr3 nvcc_dram_2p5 2.25 2.5 2.75 v ? gpio supplies 3 3 all digital i/o supplies (nvcc_xxxx) must be powered under norma l conditions whether the associated i/o pins are in use or not, and associated i/o pins need to have a pull-up or pull-do wn resistor applied to limit any non-connected gate current. nvcc33_io 2 3.0 3.3 3.6 v worst case, assuming all soc i/o operating at 1.8v. nvcc33_io must always be greater than nvcc18_io. nvcc18_io 2 1.65 1.8 1.95 v ? junction temperature t j -40 ? 105 ? industrial see i.mx 6sll product lifetime usage estimates application note for information on product lifetime (power-on years) for this processor.
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 20 nxp semiconductors electrical characteristics the rtc_xtali is used for low-frequency functio ns. it supplies the clock for wake-up circuit, power-down real time clock operation, and slow syst em and watchdog counters. the clock input can be connected to either an external osci llator or a crystal using the internal oscillator amplif ier. additionally, there is an internal ring oscillator, which can substitute the rtc_xtali, in case accuracy is not important. the system clock input xtali is used to generate the main system cl ock. it supplies th e plls and other peripherals. the system clock input can be connected to either an external oscillator or a crystal using the internal oscillator amplifier. note the internal rtc oscillator does not provide an accurate frequency and is affected by process, voltage, and te mperature variations. nxp strongly recommends using an external crystal as the rtc_xtali reference. if the internal oscillator is used instead, careful considerat ion must be given to the timing implications on all of the so c modules dependent on this clock. table 10 shows the interface frequency requirements. the typical values shown in table 10 are required for use with nxp bsps to ensure precise time keeping and usb operation. for rtc_xtali operati on, two clock sources are available: ? on-chip 40 khz ring oscillator: this clock source has the following characteristics: ? approximately 25 ? a more idd than crystal oscillator ? approximately 50% tolerance ? no external component required ? starts up quicker than 32 khz crystal oscillator ? external crystal os cillator with on-chip support circuit ? at power up, ring oscillator is utilized. after crystal oscill ator is stable, the clock circuit switches over to the crystal oscillator automatically. ? higher accuracy th an ring oscillator ? if no external crystal is present, then the ring oscillator is utilized the decision to choose a cl ock source should be take n based on real-time clock us e and precision time-out. table 10. external input clock frequency parameter description symbol min typ max unit rtc_xtali oscillator 1, 2 1 external oscillator or a crystal with internal oscillator amplifier. 2 the required frequency stability of this clock source is application dependent. f ckil ? 32.768 (see 3 ) / 32.0 3 recommended nominal frequency 32.768 khz. ?khz xtali oscillator 4, 2 4 external oscillator or a fundamental frequency crystal with internal oscillator amplifier. f xtal ?24?mhz
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 21 4.1.5 maximum supply currents the numbers shown in table 11 represent the maximum cu rrent consumption possible. see the i.mx 6sll power consumpti on measurement application note fo r more details on typical power consumption under various use case definitions. table 11. maximum supply currents power line conditions max current unit vdd_arm_in 800 mhz arm clock based on power virus operation 1100 ma vdd_soc_in 800 mhz arm clock 650 ma vdd_high_in ? 100 1 1 the actual maximum current drawn from vdd_high_in will be as shown plus any additional current drawn from the vdd_high_cap outputs, depending upon actual applicatio n configuration (for example, nvcc_dram_2p5 supplies). ma vdd_snvs_in ? 250 2 2 the maximum vdd_snvs_in current may be higher depending on specific operating configurations, such as boot_mode[1:0] not equal to 00, or use of the tamper feature. during initial power on, vdd_snvs_in can draw up to 1 ma, if available. vdd_snvs_cap charge time will increase if less than 1 ma is available. ?? a usb_otg1_vbus usb_otg2_vbus ?25 3 3 this is the maximum current pe r active usb physical interface. ma primary interface (io) supplies nvcc_dram ? (see 4 ) 4 the dram power consumption is dependent on several factors, such as external signal termination. dram power calculators are typically available from the memory vendors. they take in account factors, such as signal termination. see the i.mx 6sll power consumption m easurement application note or exampl es of dram power consumption during specific use case scenarios. nvcc33_io n=156 use maximum io equation 5 5 general equation for estimated, maximum power consumption of an io power supply: imax = n x c x v x (0.5 x f) where: n?number of io pins supplied by the power line c?equivalent external capacitive load v?io voltage (0.5 x f)?data change rate. up to 0.5 of the clock rate (f) in this equation, imax is in amps, c in farads, v in volts, and f in hertz. nvcc18_io n=156 use maximum io equation 5 ma misc dram_vref ? 1 ma
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 22 nxp semiconductors electrical characteristics 4.1.6 low power mode supply currents table 12 shows the current core consumpt ion (not including i/o) of i.mx 6sll processor in selected low power modes. 4.1.7 usb phy current consumption 4.1.7.1 power down mode in power down mode, everything is powered down, including the usb_otgx_vbus valid detectors, typical condition. table 13 shows the usb interface current consumption in power down mode. table 12. low power mode current and power consumption mode test conditions supply typical 1 1 the typical values shown here are for information only and are not guaranteed. these values are average values measured on a typical process wafer at 25 ? c. unit system idle (wait) ? cpu is in wfi state, cpu clock is gated ? ddr enters self refresh automatically when no access ? high-speed peripherals are clock gated, but remain powered ? ldo-2p5 set to 2.5 v, ldo_1p1 set to 1.1 v ? 24 mhz xtal is on ? 528 pll active, other plls are power down vdd_arm_in (1.15 v) 5.00 ma vdd_soc_in (1.15 v) 8.00 vdd_high_in (3.0 v) 7.00 vdd_snvs_in(3.0 v) 0.05 total 36.1 mw low power idle (standby) ? cpu is power gated ? ddr is put in self refresh by sw, ddr io is disabled ? high-speed peripherals are clock gated, but remain powered ? ldo_2p5 and ldo_1p1 are set to weak mode ? 24 mhz xtal is off, 24 mhz hz rcosc used as clock source ? all pll are power down vdd_arm_in (0.9 v) ? ma vdd_soc_in (0.9 v) 1.60 vdd_high_in (3.0 v) 0.30 vdd_snvs_in (3.0 v) 0.04 total 2.46 mw suspend (dsm) ? cpu is power gated ? ddr is put in self refresh by sw, ddr io is disabled ? high-speed peripherals are power gated ? ldo_2p5 and ldo_1p1 are shut off ? 24 mhz xtal is off, 24 mhz rcosc is off ? all pll are power down ? all clocks are shut off, only except 32 khz rtc vdd_arm_in (0 v) ? ma vdd_soc_in (0.9 v) 0.20 vdd_high_in (3.0 v) 0.03 vdd_snvs_in (3.0 v) 0.02 total 0.33 mw snvs (rtc) ? cpu is power down ? all soc digital logic is power down ? all analog circuit is power down except 32k rtc vdd_arm_in (0 v) ? ma vdd_soc_in (0 v) ? vdd_high_in (0 v) ? vdd_snvs_in (3.0 v) 0.02 total 0.06 mw
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 23 note the currents on the vdd_high_ cap and vdd_usb_cap were identified to be the voltage divider circuits in the usb-specific level shifters. 4.2 power supplies requir ements and restrictions the system design must comply with power-up sequence, power-down seque nce, and steady state guidelines as described in this section to guarantee the reliable operation of the device. any deviation from these sequences may result in the following situations: ? excessive current during power-up phase ? prevention of the device from booting ? irreversible damage to the pr ocessor (worst-case scenario) 4.2.1 power-up sequence for power-up sequence, the re strictions are as follows: ? vdd_snvs_in supply must be tu rned on before any other power supply. it may be connected (shorted) with vdd_high_in supply. ? if a coin cell is used to power vdd_snvs_in, then ensure it is connected before any other supply is switched on. ? vdd_soc_in must be turned on befo re any other digital io power supply. ? por_b signal must be im mediately asserted at pow er-up and remain asserted after the last power rail reaches its working voltage. ? vdd_arm_in may be applie d with no restrictions. ? nvcc33_io must be appl ied before nvcc18_io. note see the i.mx 6sll reference manual (imx6sllrm) for further details and to ensure that all necessa ry requirements are being met. note ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 v supply (for example, from the external components that use both the 1.8 v and 3.3 v supplies). note usb_otg1_vbus and usb_otg2_vbu s are not part of the power supply sequence and can be powered at any time. table 13. usb phy current consumption in power down mode vdd_usb_cap (3.0 v) vddhigh_ca p (2.5 v) nvcc_pll (1.1 v) current 5.1 ? a1.7 ? a <0.5 ? a
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 24 nxp semiconductors electrical characteristics 4.2.2 power-down sequence for power-down sequence, the re strictions are as follows: ? vdd_snvs_in supply must be tu rned off after all other power supply. it may be connected (shorted) with vdd_high_in supply. ? if a coin cell is used to power vdd_snvs_in, then ensure that it is removed afte r all other supply are switched off. 4.2.3 power supplies usage all i/o pins should not be exte rnally driven while the i/o power supply for the pin (nvcc33_io and nvcc18_io) is off. this can cause internal latch-up and malfunctions due to reverse current flows. for information about i/o power supply of each pin, see ?power group? column of table 64, "14 x 14 mm functional contact assignments," on page 71 . 4.3 integrated ldo voltage regulator parameters various internal supplies can be powered on from inte rnal ldo voltage regulators. all the supply pins named *_cap must be connected to external capaci tors. the onboard ldos are intended for internal use only and should not be used to power any external circuitry. see the i.mx 6sll reference manual for details on the power tree sc heme recommended operation. note the *_cap signals should not be power ed externally. these signals are intended for internal ldo or ldo bypass operation only. 4.3.1 regulators for analog modules 4.3.1.1 ldo_1p1 the ldo_1p1 regulator implements a programmable linear-regulator function from vdd_high_in (see table 9 for min and max input require ments). typical programming operating range is 1.0 v to 1.2 v with the nominal default setting as 1.1 v. ldo_1p1 supplies the us b phy and the plls. a programmable brown-out detector is include d in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded to take the necessary steps. current-limiting can be enabled to allow for in-rush curren t requirements during start- up, if needed. active-pull- down can also be enabled for systems requiring this feature. for information on external capacitor re quirements for this regulator, see the hardware development guide for i.mx 6sll applications processors (imx6sllhdg). for additi onal information, see the i.mx 6sll reference manual . 4.3.1.2 ldo_2p5 the ldo_2p5 module implements a programmable linear-regulator f unction from vdd_high_in (see table 9 for min and max input require ments). typical programming opera ting range is 2.25 v to 2.75 v
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 25 with the nominal default setting as 2.5 v. ldo _2p5 supplies the usb phy, lvds phy and plls. a programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being ex ceeded, to take the necessary steps. current-limiting can be enabled to allow for in-rus h current requirements during start- up, if needed. active-pull-down can also be enabled for systems requiring this feature. an alternate self-biased lo w-precision weak-regulator is included that can be enabled for applications needing to keep the output voltage alive during low-power modes where the main regulator driver and its asso ciated global bandgap refe rence module are disabled. the output of the weak-regul ator is not programmable an d is a function of the input supply as well as the load current. typically, with a 3 v input suppl y the weak-regulator output is 2.525 v and its output impedance is approximately 40 ? . for information on external capacitor re quirements for this regulator, see the hardware development guide for i.mx 6sll applications processors (imx6sllhdg). for additional information, see the i.mx 6sll reference manual (imx6sllrm). 4.3.1.3 ldo_usb the ldo_usb module implements a program mable linear-regulator function from the usb_otg1_vbus and usb_otg2_vbus voltages ( 4.4 v?5.5 v) to produce a nominal 3.0 v output voltage. a programmable brown-out det ector is included in the regulator that can be used by the system to determine when the load capability of the regulator is be ing exceeded, to take the necessary steps. this regulator has a built in power-mux that allows the user to select to run the re gulator from either vbus supply, when both are present. if only one of th e vbus voltages is presen t, then, the regulator automatically selects this supply. current limit is al so included to help the system meet in-rush current targets. if no vbus voltage is present, then the vbusvalid threshold setting will prevent the regulator from being enabled. for information on external capacitor re quirements for this regulator, see the hardware development guide for i.mx 6sll applications processors (imx6sllhdg). for additional information, see the i.mx 6sll reference manual (imx6sllrm). 4.4 pll?s electrical characteristics 4.4.1 audio/video pll?s electrical parameters table 14. audio/video pll?s electrical parameters parameter value clock output range 650 mhz ~1.3 ghz reference clock 24 mhz lock time <11250 reference cycles (450 ? s)
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 26 nxp semiconductors electrical characteristics 4.4.2 528 mhz pll 4.4.3 480 mhz pll 4.4.4 arm pll 4.5 on-chip oscillators 4.5.1 osc24m this block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implements an oscillator. it also implem ents a power mux such that the oscillator can be powered from vdd_soc. if the osci llator is required to run in stop mode then it is necessary to run from vdd_soc, which is 0.9 v in stop mode . the system crystal oscillator consists of a pierce-t ype structure running off the digital supply. a straight forward biased-inverter implementation is used. table 15. 528 mhz pll?s electrical parameters parameter value clock output range 528 mhz pll output reference clock 24 mhz lock time <11250 reference cycles (15 ? s) table 16. 480 mhz pll?s electrical parameters parameter value clock output range 480 mhz pll output reference clock 24 mhz lock time <383 reference cycles ( ?? ? ? s) table 17. arm pll?s electrical parameters parameter value clock output range 650 mhz~1.3 ghz reference clock 24 mhz lock time <2250 reference cycles (50 ? s)
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 27 4.5.2 osc32k this block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implements a low power oscillator. it also implements a power mux such that it can be powered from either a ~3 v backup battery (vdd_snvs_in) or vdd_high_in such as the oscillator consumes power from vdd_high_in when that supply is available and transitions to the back up battery when vdd_high_in is lost. in addition, if the clock monitor dete rmines that the osc32k is not pres ent, then the source of the 32 khz clock will automatically switch to the internal ring oscillator. caution the internal rtc oscillator does not provide an accurate frequency and is affected by process, voltage and te mperature variations. nxp strongly recommends using an external crystal as the rtc_xtali reference. if the internal oscillator is used instead, careful considerat ion must be given to the timing implications on all of the so c modules dependent on this clock. 4.6 i/o dc parameters this section includes the dc parame ters of the following i/o types: ? dual voltage general purpos e i/o cell set (dvgpio) ? single voltage general purpose i/o cell set (gpio) ? double data rate i/o (ddr) for lpddr2 and lpddr3 modes table 18. osc32k main characteristics parameter min typ max comments fosc ? 32.768 khz ? this frequency is nominal and determined mainly by the crystal selected. 32.0 k would work as well. current consumption ?4 ? a ? the typical value shown is only for the oscillator, driven by an external crystal. if the internal ring oscillator is used instead of an external crystal, then approximately 25 ? a should be added to this value. bias resistor ? 14 m ? ? this the integrated bias resistor that sets the amplifier into a high gain state. any leakage through the esd network, external board leakage, or even a scope probe that is significant relative to this value will debias the amp. the debiasing will result in low gain, and will impact the circuit's ability to start up and maintain oscillations. target crystal properties cload ? 10 pf ? usually crystals can be purchased tuned for different cloads. this cload value is typically 1/2 of the capacitanc es realized on the pcb on either side of the quartz. a higher cload will decr ease oscillation margin, but increases current oscillating through the crystal. esr ? 50 k ? ? equivalent series resistance of the crystal. choosing a crystal with a higher value will decrease the oscillating margin.
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 28 nxp semiconductors electrical characteristics note the term ovdd in this section refers to the associated supply rail of an input or output. figure 4. circuit for parameters voh and vol for i/o cells 4.6.1 xtali and rtc_xtali (clock inputs) dc parameters table 19 shows the dc parameters for the clock inputs. 4.6.2 dual voltage general purpose io cell set (dvgpio) dc parameters table 20 shows dc parameters for gp io pads. the parameters in table 21 are guaranteed per the operating ranges in table 9 , unless otherwise noted. table 19. xtali and rtc_xtali dc parameters 1 1 the dc parameters are for external clock input only. parameter symbol test conditions min max unit xtali high-level dc input voltage vih ? 0.8 x nvcc_pll nvcc_pll v xtali low-level dc input voltage vil ? 0 0.2 v rtc_xtali high-level dc input voltage vih ? 0.8 1.1 v rtc_xtali low-level dc input voltage vil ? 0 0.2 v table 20. dvgpio i/o dc parameters parameter symbol test conditions min max unit high-level output voltage 1 voh ioh = -0.1 ma (dse 2 = 001, 010) ioh = -1 ma (dse = 011, 100, 101, 110, 111) ovdd ? 0.15 ? v low-level output voltage 1 vol iol = 0.1 ma (dse 2 = 001, 010) iol = 1ma (dse = 011, 100, 101, 110, 111) ?0.15v high-level dc input voltage 1, 3 vih ? 0.7 ? ovdd ovdd v low-level dc input voltage 1, 3 vil ? 0 0.3 ? ovdd v input hysteresis vhys ovdd = 1.8 v ovdd = 3.3 v 0.25 ? v 0 or 1 predriver pdat ovdd pad nmos (rpd) ovss voh min vol max pmos (rpu)
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 29 4.6.3 single voltage general purp ose i/o (gpio) dc parameters table 21 shows dc parameters for gp io pads. the parameters in table 21 are guaranteed per the operating ranges in table 9 , unless otherwise noted. schmitt trigger vt+ 3, 4 vt+ ? 0.5 ? ovdd ? v schmitt trigger vt? 3, 4 vt? ? ? 0.5 ? ovdd v input current (no pull-up/down) iin vin = ovdd or 0 -1.25 1.25 ? a input current (22 k ? pull-up) iin vin = 0 v vin = ovdd ?212 1 ? a input current (47 k ? pull-up) iin vin = 0 v vin = ovdd ?100 1 ? a input current (100 k ? pull-up) iin vin = 0 v vin= ovdd ?48 1 ? a input current (100 k ? pull-down) iin vin = 0 v vin = ovdd ?1 48 ? a keeper circuit resistance rkeep vin = 0.3 x ovdd vin = 0.7 x ovdd 105 205 k ? 1 overshoot and undershoot conditions (transitions above ovdd and below gnd) on switching pads must be held below 0.6 v, and the duration of the overshoot /undershoot must not exceed 10% of the system clock cycle. overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other method s. non-compliance to this specification may affect device reliability or cause permanent damage to the device. 2 dse is the drive strength field setting in the associated iomux control register. 3 to maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current dc level through to the target dc level, vil or vih. monotonic input transition time is from 0.1 ns to 1 s. 4 hysteresis of 250 mv is guaranteed over all operating conditions when hysteresis is enabled. table 21. gpio i/o dc parameters parameter symbol test conditions min max unit high-level output voltage 1 voh ioh = -0.1 ma (dse 2 = 001, 010) ioh = -1 ma (dse = 011, 100, 101, 110, 111) ovdd ? 0.15 ? v low-level output voltage 1 vol iol = 0.1 ma (dse 2 = 001, 010) iol = 1ma (dse = 011, 100, 101, 110, 111) ?0.15v high-level dc input voltage 1, 3 vih ? 0.7 ? ovdd ovdd v low-level dc input voltage 1, 3 vil ? 0 0.3 ? ovdd v input hysteresis vhys ovdd = 3.3 v 0.25 ? v schmitt trigger vt+ 3, 4 vt+ ? 0.5 ? ovdd ? v schmitt trigger vt? 3, 4 vt? ? ? 0.5 ? ovdd v input current (no pull-up/down ) iin vin = ovdd or 0 -1.25 1.25 ? a table 20. dvgpio i/o dc parameters (continued) parameter symbol test conditions min max unit
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 30 nxp semiconductors electrical characteristics 4.6.4 ddr i/o dc parameters the ddr i/o pads support lpddr2 and lpddr3 operational modes. the multi-mode ddr controller (mmdc) is compatible with jedec-compliant sdrams. the i.mx 6sll mmdc supports the following memory types: ? lpddr2 sdram compliant to jesd209-2b lp ddr2 jedec standard release june, 2009 ? lpddr3 sdram compliant to jesd209-3b lp ddr3 jedec standard release august, 2013 mmdc operation with the standards stated above is contingent upon th e board ddr design adherence to the ddr design and layout requirements stated in the hardware development guide for the i.mx 6sll applications processor (imx6sllhdg). 4.6.4.1 lpddr2/lpddr3 i/o dc parameters table 22 shows the dc parameters for ddr i/ o operating in lpddr2 and lpddr3 mode. input current (22 k ? pull-up) iin vin = 0 v vin = ovdd ?212 1 ? a input current (47 k ? pull-up) iin vin = 0 v vin = ovdd ?100 1 ? a input current (100 k ? pull-up) iin vin = 0 v vin= ovdd ?48 1 ? a input current (100 k ? pull-down) iin vin = 0 v vin = ovdd ?1 48 ? a keeper circuit resistance rkeep vin = 0.3 x ovdd vin = 0.7 x ovdd 105 205 k ? 1 overshoot and undershoot conditions (transitions above ovdd an d below gnd) on switching pads must be held below 0.6 v, and the duration of the overshoot/undershoot must not exce ed 10% of the system clock cycle. overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other method s. non-compliance to this specification may affect device reliability or cause permanent damage to the device. 2 dse is the drive strength field setting in the associated iomux control register. 3 to maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current dc level through to the target dc level, vil or vih. m onotonic input transition time is from 0.1 ns to 1 s. 4 hysteresis of 250 mv is guaranteed over all o perating conditions when hysteresis is enabled. table 22. lpddr2/lpddr3 i/o dc electrical parameters 1 parameters symbol test conditions min max unit high-level output voltage voh ioh = -0.1 ma 0.9 ? ovdd ? v low-level output voltage vol iol = 0.1 ma ? 0.1 ? ovdd v input reference voltage vref ? 0.49 ? ovdd 0.51 ? ovdd dc input high voltage vih(dc) ? vref+0.13v ovdd v table 21. gpio i/o dc parameters (continued) parameter symbol test conditions min max unit
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 31 4.7 i/o ac parameters this section includes the ac parame ters of the following i/o types: ? general purpose i/o (gpio) ? dual voltage general purpose i/o (dvgpio) ? double data rate i/o (ddr) for lpddr2 and lpddr3 modes the gpio and ddr i/o load circuit and out put transition time waveforms are shown in figure 5 and figure 6 . figure 5. load circuit for output figure 6. output transition time waveform dc input low voltage vil(dc) ? ovss vref-0.13v v differential input logic high vih(diff) ? 0.26 see note 2 differential input logic low vil(diff) ? see note 2 -0.26 input current (no pull-up/down) iin vin = 0 or ovdd -2.5 2.5 ? a pull-up/pull-down impedance mismatch mmpupd ? -15 +15 % 240 ? unit calibration resolution rres ? ? 10 ? keeper circuit resistance rkeep ? 110 175 k ? 1 note that the jedec lpddr2 and lpddr3 specification (jesd 209_2b and jesd209-3) supers edes any specification in this document. 2 the single-ended signals need to be within the respective limits (vih(dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot (see ta b l e 2 5 ). table 22. lpddr2/lpddr3 i/o dc electrical parameters 1 (continued) parameters symbol test conditions min max unit test point from output cl cl includes package, probe and fixture capacitance under test 0v ovdd 20% 80% 80% 20% tr tf output (at pad)
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 32 nxp semiconductors electrical characteristics 4.7.1 general purpose i/o ac parameters the i/o ac parameters for gpio in slow and fast modes are presented in the table 23 and table 24 , respectively. note that the fast or slow i/o behavior is determined by the appropriate control bits in the iomuxc control registers. table 23. general purpose i/o ac parameters 1.8 v mode parameter symbol test condition min typ max unit output pad transition times, rise/fall (max drive, ipp_dse=111) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ? ? 2.72/2.79 1.51/1.54 ns output pad transition times, rise/fall (high drive, ipp_dse=101) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ? ? 3.20/3.36 1.96/2.07 output pad transition times, rise/fall (medium drive, ipp_dse=100) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ? ? 3.64/3.88 2.27/2.53 output pad transition times, rise/fall (low drive. ipp_dse=011) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ? ? 4.32/4.50 3.16/3.17 input transition times 1 1 hysteresis mode is recommended for input s with transition times greater than 25 ns. trm ? ? ? 25 ns table 24. general purpose i/o ac parameters 3.3 v mode parameter symbol test condition min typ max unit output pad transition times, rise/fall (max drive, ipp_dse=101) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ? ? 1.70/1.79 1.06/1.15 ns output pad transition times, rise/fall (high drive, ipp_dse=011) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ? ? 2.35/2.43 1.74/1.77 output pad transition times, rise/fall (medium drive, ipp_dse=010) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ? ? 3.13/3.29 2.46/2.60 output pad transition times, rise/fall (low drive. ipp_dse=001) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ? ? 5.14/5.57 4.77/5.15 input transition times 1 1 hysteresis mode is recommended for inputs with transition times greater than 25 ns. trm ? ? ? 25 ns
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 33 4.7.2 ddr i/o ac parameters the multi-mode ddr controller (mmdc) is compatible with jedec-compliant sdrams. the i.mx 6sll mmdc supports the following memory types: ? lpddr2 sdram compliant to jesd209-2b lp ddr2 jedec standard release june, 2009 ? lpddr3 sdram compliant to jesd209-3b lp ddr3 jedec standard release august, 2013 mmdc operation with the standards stated above is contingent upon th e board ddr design adherence to the ddr design and layout requirements stated in the hardware development guide for the i.mx 6sll applications processor (imx6sllhdg). table 25 shows the ac parameters for ddr i/ o operating in lpddr2 and lpddr3 mode. 4.8 output buffer impedance parameters this section defines the i/o imped ance parameters of the i.mx 6sll processor for the following i/o types: ? dual voltage general purpose i/o cell set (dvgpio) ? single voltage general purpose i/o cell set (gpio) table 25. ddr i/o ac parameters 1 1 note that the jedec lpddr2 and lpddr3 specification (jesd 209_2b and jesd209-3b) supersedes any specification in this document. parameter symbol test condition min typ max unit ac input logic high vih(ac) ? vref + 0.22 ? ovdd v ac input logic low vil(ac) ? 0 ? vref ? 0.22 v ac differential input high voltage 2 2 vid(ac) specifies the input differential voltage |vtr ? vcp| requir ed for switching, where vtr is t he ?true? input signal and vcp is the ?complementary? input signal. the mini mum value is equal to vih(ac) ? vil(ac). vidh(ac) ? 0.44 ? ? v ac differential input low voltage vidl(ac) ? ? ? 0.44 v input ac differential cross point voltage 3 3 the typical value of vix(ac) is expected to be about 0.5 ? ovdd. and vix(ac) is expected to track variation of ovdd. vix(ac) indicates the voltage at which diff erential input signal must cross. vix(ac) relative to vref -0.12 ? 0.12 v over/undershoot peak vpeak ? ? ? 0.35 v over/undershoot area (above ovdd or below ovss) varea 400 mhz ? ? 0.3 v-ns single output slew rate, measured between vol (ac) and voh (ac) tsr 50 ?? to vref. 5 pf load. drive impedance = 4 0 ??? 30% 1.5 ? 3.5 v/ns 50 ?? to vref. 5pf load. drive impedance = 60 ??? 30% 1?2.5 skew between pad rise/fall asymmetry + skew caused by ssn t skd clk = 400 mhz ? ? 0.1 ns
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 34 nxp semiconductors electrical characteristics ? double data rate i/o (ddr) note gpio and ddr i/o output driver imp edance is measured with ?long? transmission line of impeda nce ztl attached to i/o pad and incident wave launched into transmission line. rpu/rpd and ztl form a volta ge divider that defines specific voltage of incident wave relative to ovdd. output driver impedance is calculated from this voltage divider (see figure 7 ). figure 7. impedance matching load for measurement 4.8.1 dual voltage gpio output buffer impedance table 26 shows the gpio output buffer impedance (ovdd 1.8 v). ipp_do cload = 1p ztl ? , l = 20 inches predriver pmos (rpu) nmos (rpd) pad ovdd ovss t,(ns) u,(v) ovdd t,(ns) 0 vdd vin (do) vout (pad) u,(v) vref rpu = vovdd?vref1 vref1 ? ztl rpd = ? ztl vref2 vovdd?vref2 vref1 vref2 0
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 35 table 27 shows the gpio output buffer impedance (ovdd 3.3 v). 4.8.2 single voltage gpio output buffer impedance table 28 shows the gpio output buffer impedance (ovdd 3.3 v). 4.8.3 ddr i/o output buffer impedance table 29 shows ddr i/o output buffer impe dance of i.mx 6sll processor. table 26. dvgpio output buffer average impedance (ovdd 1.8 v) parameter symbol drive streng th (ipp_dse) typ value unit output driver impedance rdrv 001 010 011 100 101 110 111 260 130 90 60 50 40 33 ? table 27. dvgpio output buffer average impedance (ovdd 3.3 v) parameter symbol drive streng th (ipp_dse) typ value unit output driver impedance rdrv 001 010 011 100 101 110 111 150 75 50 37 30 25 20 ? table 28. gpio output buffer average impedance (ovdd 3.3 v) parameter symbol drive streng th (ipp_dse) typ value unit output driver impedance rdrv 001 010 011 100 101 110 111 150 75 50 37 30 25 20 ?
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 36 nxp semiconductors electrical characteristics note: 1. output driver impedanc e is controlled across pvts using zq calibration procedure. 2. calibration is done against 240 ?? external reference resistor. 3. output driver impedance devi ation (calibration accuracy) is 5% (max/min impedance) across pvts. 4.9 system modules timing this section contains the timing a nd electrical parameters for the modul es in each i.mx 6sll processor. 4.9.1 reset timings parameters figure 8 shows the reset timing and table 30 lists the timing parameters. figure 8. reset timing diagram 4.9.2 wdog reset timing parameters figure 9 shows the wdog reset timing and table 31 lists the timing parameters. figure 9. wdog_b timing diagram table 29. ddr i/o output buffer impedance parameter symbol test conditions typical unit nvcc_dram=1.2 v (lpddr2/lpddr3) ddr_sel=10 output driver impedance rdrv drive strength (dse) = 000 001 010 011 100 101 110 111 hi-z 240 120 80 60 48 40 34 ? table 30. reset timing parameters id parameter min max unit cc1 duration of por_b to be qualified as valid. 1 ? xtalosc_rtc_xtali cycle por_b cc1 (input) wdog_b cc3 (output)
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 37 note xtalosc_rtc_xtali is approximately 32 khz. xtalosc_rtc_xtali cycle is one period or approximately 30 ? s. note wdog_b output signals (for each one of the watchdog modules) do not have dedicated bins, but are muxe d out through the iomux. see the iomux manual for detailed information. 4.9.3 ddr sdram specific para meters (lpddr2 and lpddr3) 4.9.3.1 lpddr2 and lpddr3 parameters figure 10 shows the lpddr2 and lpddr3 ba sic timing diagram. the timing parameters for this diagram appear in table 32 . figure 10. lpddr2 and lpddr3 command and address timing diagram 1 all measurements are in reference to vref level. table 31. wdog_b timing parameters id parameter min max unit cc3 duration of wdog_b assertion 1 ? xtalosc_rtc_xtali cycle table 32. lpddr2 and lpddr3 timing parameters id parameter symbol ck = 400 mhz unit min max lp1 sdram clock high-level width t ch 0.45 0.55 t ck lp2 sdram clock low-level width t cl 0.45 0.55 t ck lp3 dram_csx_b, dram_sdckex setup time t is 380 ? ps lp4 dram_csx_b, dram_sdckex hold time t ih 380 ? ps dram_sdclkx_p dram_csx_b dram_sdckex dram_addrxx lp4 lp4 lp3 lp4 lp3 lp2 lp3 lp3 lp1
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 38 nxp semiconductors electrical characteristics 2 measurements were done using balanced load and 25 ? resistor from outputs to dram_vref. figure 11 shows the lpddr2 and lpddr3 wr ite timing diagram. the timing parameters for this diagram appear in table 33 . figure 11. lpddr2 and lpddr3 write cycle 1 to receive the reported setup and hold values, write calibrat ion should be performed in order to locate the dram_sdqs in the middle of dram_dataxx window. 2 all measurements are in reference to vref level. 3 measurements were done using balanced load and 25 ? resistor from outputs to dram_vref. table 33. lpddr2 and lpddr3 write cycle id parameter symbol ck = 400 mhz unit min max lp17 dram_dataxx and dram_dqmx setup time to dram_sdqsx_p (differential strobe) t ds 375 ? ps lp18 dram_dataxx and dram_dqmx hold time to dram_sdqsx_p (differential strobe) t dh 375 ? ps lp21 dram_sdqsx_p latching rising transitions to associated clock edges t dqss -0.25 +0.25 tck lp22 dram_sdqsx_p high level width t dqsh 0.4 ? tck lp23 dram_sdqsx_p low level width t dqsl 0.4 ? tck dram_sdclkx_p dram_sdclkx_n dram_sdclkx_p dram_dataxx dram_dqmx data data data data data data data data dm dm dm dm dm dm dm dm lp17 lp17 lp17 lp17 lp18 lp18 lp18 lp18 lp21 lp23 lp22 (output) (output) (output)
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 39 figure 12 shows the lpddr2 and lpddr3 read timing di agram. the timing parameters for this diagram appear in table 34 . figure 12. lpddr2 and lpddr3 read cycle 1 to receive the reported setup and hold values, read calibration should be performed in order to locate the dram_sdqsx_p in the middle of dram_data_xx window. 2 all measurements are in reference to vref level. 3 measurements were done using balanced load and 25 ? resistor from outputs to dram_vref. 4.10 external peripheral interface parameters the following subsections provide inform ation on external peripheral interfaces. 4.10.1 audmux timing parameters the audmux provides a programmable interconnect logic for voice, a udio, and data routing between internal serial interfaces (ssis) and external serial interfaces (audio and voice codecs). the ac timing of audmux external pins is governed by the ssi module. for more information, see the respective ssi electrical specifications f ound within this document. 4.10.2 cmos sensor interface (csi) timing parameters 4.10.2.1 gated clock mode timing figure 13 and figure 14 shows the gated clock mode timings for csi, and table 35 describes the timing parameters (p1?p7) shown in the figures. a fram e starts with a rising/ falling edge on csi_vsync table 34. lpddr2 and lpddr3 read cycle id parameter symbol ck = 400 mhz unit min max lp26 minimum required dram_dataxx valid window width for lpddr2 and lpddr3 ? 270 ? ps dram_sdclkx_p dram_sdclkx_n dram_sdqsx_p dram_dataxx data data data data data data data data lp26 (input) (input)
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 40 nxp semiconductors electrical characteristics (vsync), then csi_hsync (hsync) is asserted and holds for th e entire line. the pixel clock, csi_pixclk (pixclk), is valid as long as hsync is asserted. figure 13. csi gated clock mode?sensor data at falling edge, latch data at rising edge figure 14. csi gated clock mode?sensor data at rising edge, latch data at falling edge table 35. csi gated clock mode timing parameters id parameter symbol min. max. units p1 csi_vsync to csi_hsync time tv2h 33.5 ? ns p2 csi_hsync setup time thsu 1 ? ns p3 csi data setup time tdsu 1 ? ns p4 csi data hold time tdh 1 ? ns p5 csi pixel clock high time tclkh 3.75 ? ns csi_pixclk csi_vsync csi_data[15:00] p5 p1 p3 p4 csi_hsync p2 p6 p7 csi_pixclk csi_vsync csi_data[15:00] p6 p1 p3 p4 csi_hsync p2 p5 p7
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 41 4.10.2.2 ungated clock mode timing figure 15 shows the ungated clock m ode timings of csi, and table 36 describes the timing parameters (p1?p6) that are shown in the figure. in ungated mode the csi_vsync and csi_pixclk signals are used, and the csi_hsync signal is ignored. figure 15. csi ungated clock mode?sensor data at falling edge, latch data at rising edge the csi enables the chip to connect directly to exte rnal cmos image sensors, which are classified as dumb or smart as follows: ? dumb sensors only support traditi onal sensor timing (vertical sync (vsync) and horizontal sync (hsync)) and output-only bayer and statistics data. ? smart sensors support ccir656 vi deo decoder formats and perfor m additional processing of the image (for example, image compression, image pr e-filtering, and various data output formats). p6 csi pixel clock low time tclkl 3.75 ? ns p7 csi pixel clock frequency fclk ? 133.3 mhz table 36. csi ungated clock mode timing parameters id parameter symbol min. max. units p1 csi_vsync to pixel clock time tvsync 33.5 ? ns p2 csi data setup time tdsu 1 ? ns p3 csi data hold time tdh 1 ? ns p4 csi pixel clock high time tclkh 3.75 ? ns p5 csi pixel clock low time tclkl 3.75 ? ns p6 csi pixel clock frequency fclk ? 133.3 mhz table 35. csi gated clock mode timing parameters (continued) id parameter symbol min. max. units csi_pixclk csi_vsync csi_data[15:00] p4 p1 p2 p3 p5 p6
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 42 nxp semiconductors electrical characteristics 4.10.3 ecspi timing parameters this section describes the timi ng parameters of the ecspi bloc k. the ecspi has separate timing parameters for master and slave modes. 4.10.3.1 ecspi master mode timing figure 16 depicts the timing of ec spi in master mode and table 37 lists the ecspi master mode timing characteristics. figure 16. ecspi master mode timing diagram table 37. ecspi master mode timing parameters id parameter symbol min max unit cs1 ecspix_sclk cycle time?read ?slow group 1 ? fast group 2 ecspix_sclk cycle time?write t clk 46 40 15 ?ns cs2 ecspix_sclk high or low time?read ?slow group 1 ? fast group 2 ecspix_sclk high or low time?write t sw 22 20 7 ?ns cs3 ecspix_sclk rise or fall 3 t rise/fall ??ns cs4 ecspix_ssx pulse width t cslh half ecspix period ? ns cs5 ecspix_ssx lead time (cs setup time) t scs half ecspix_sclk period - 4 ? ns cs6 ecspix_ssx lag ti me (cs hold time) t hcs half ecspi_sclk period - 2 ? ns cs7 ecspix_mosi propagation delay (c load =20pf) t pdmosi -0.5 2 ns cs8 ecspix_miso setup time ?slow group 1 ? fast group 2 t smiso ? 14 12 ?ns cs1 cs7 cs2 cs2 cs4 cs6 cs5 cs8 cs9 ecspix_sclk ecspix_ssx ecspix_mosi ecspix_miso ecspix_rdy cs10 cs3 cs3
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 43 4.10.3.2 ecspi slave mode timing figure 17 depicts the timing of ec spi in slave mode and table 38 lists the ecspi slave mode timing characteristics. figure 17. ecspi slave mode timing diagram cs9 ecspix_miso hold time t hmiso 0?ns cs10 ecspix_rdy to ecspix_ssx time 4 t sdry 5?ns 1 ecspi slow group includes: ecspi2/epdc_sdle, ecspi3/ epdc_d9, ecspi4/epdc_d1 2 ecspi fast group includes: ecspi1/lcd_data01, ecspi1/ecspi1_m iso, ecspi2/lcd_data10, ecspi 2/ecspi2_miso, ecspi3/audx_txc, ecspi3/sd2_dat1, ecspi4/key_row1, ecspi4 3 see specific i/o ac parameters section 4.7, ?i/o ac parameters " .? 4 ecspix_rdy is sampled internally by ipg_clk and is asynchronous to all other ecspi signals. table 38. ecspi slave mo de timing parameters id parameter symbol min max unit cs1 ecspix_sclk cycle time?read ecspix_sclk cycle time?write t clk 40 15 ?ns cs2 ecspix_sclk high or low time?read ecspix_sclk high or low time?write t sw 20 7 ?ns cs4 ecspix_ssx pulse width t cslh half sclk period ? ns cs5 ecspix_ssx lead time (cs setup time) t scs 5?ns cs6 ecspix_ssx lag time (cs hold time) t hcs 5?ns cs7 ecspix_mosi setup time t smosi 4?ns cs8 ecspix_mosi hold time t hmosi 4?ns cs9 ecspix_miso propagation delay (c load =20pf) t pdmiso 417ns table 37. ecspi master mode timing parameters (continued) id parameter symbol min max unit cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 ecspix_sclk ecspix_ssx ecspix_miso ecspix_mosi
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 44 nxp semiconductors electrical characteristics 4.10.4 ultra high speed sd/sdio/ mmc host interface (usdhc) ac timing this section describes the electrical informat ion of the usdhc, which includes sd/emmc4.3 (single data rate) timing and emmc4.4/ 4.41/5.0 (dual date rate) timing. 4.10.4.1 sd/emmc4.3 (singl e data rate) ac timing figure 18 depicts the timing of sd/emmc4.3, and table 39 lists the sd/emmc4.3 timing characteristics. figure 18. sd/emmc4.3 timing table 39. sd/emmc4.3 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (low speed) f pp 1 0 400 khz clock frequency (sd/sdio full speed/high speed) f pp 2 0 25/50 mhz clock frequency (mmc full speed/high speed) f pp 3 0 20/52 4 mhz clock frequency (identification mode) f od 100 400 khz sd2 clock low time t wl 7?ns sd3 clock high time t wh 7?ns sd4 clock rise time t tlh ?3ns sd5 clock fall time t thl ?3ns esdhc output/card inputs sdx_cmd, sdx_datax (reference to clk) sd6 esdhc output delay t od ?6.6 3.6 ns esdhc input/card outputs sdx_cmd, sdx_datax (reference to clk) sd1 sd3 sd5 sd4 sd7 sdx_clk sd2 sd8 sd6 output from usdhc to card input from card to usdhc sdx_data[7:0] sdx_data[7:0]
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 45 4.10.4.2 emmc4.4/4.41 (dual data rate) esdhcv3 ac timing figure 19 depicts the timi ng of emmc4.4/4.41. table 40 lists the emmc4.4/4.41 ti ming characteristics. be aware that only sdx_datax is sampled on both e dges of the clock (not applicable to sdx_cmd). figure 19. emmc4.4/4.41 timing sd7 esdhc input setup time t isu 2.5 ? ns sd8 esdhc input hold time 5 t ih 1.5 ? ns 1 in low speed mode, card clock must be lower than 400 khz, voltage ranges from 2.7 to 3.6 v. 2 in normal (full) speed mode for sd/sdio ca rd, clock frequency can be any value between 0 ? 25 mhz. in high-speed mode, clock frequency can be any value between 0 ? 50 mhz. 3 in normal (full) speed mode for mmc card, clock frequency can be any value between 0 ? 20 mhz. in high-speed mode, clock frequency can be any value between 0 ? 52 mhz. 4 usdhc3 dat4 ~ dat7 have two pad groups. the first group use sd2 pad and run at 52 mhz for output. the second group use key pad and only run at 50 mhz for output. 5 to satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. table 40. emmc4.4/4.41 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (emmc4.4/4.41 ddr) f pp 052mhz sd1 clock frequency (sd3.0 ddr) f pp 050mhz usdhc output / card inputs sd_c md, sd_datax (reference to clk) sd2 usdhc output delay t od 2.5 7.1 ns usdhc input / card outputs sd_c md, sd_datax (reference to clk) sd3 usdhc input setup time t isu 1.7 ? ns sd4 usdhc input hold time t ih 1.5 ? ns table 39. sd/emmc4.3 interface timing specification (continued) id parameter symbols min max unit sd1 sd3 output from esdhcv3 to card input from card to esdhcv3 sdx_data[7:0] sdx_clk sd4 sd2 ...... ...... sdx_data[7:0] sd2
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 46 nxp semiconductors electrical characteristics 4.10.4.3 sdr50/sdr104 ac timing figure 20 depicts the timing of sdr50/sdr104, and table 39 lists the sdr50/sdr104 timing characteristics. figure 20. sdr50/sdr104 timing table 41. sdr50/sdr104 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency period t clk 5.0 ? ns sd2 clock low time t cl 0.46 x t clk 0.54 x t clk ns sd3 clock high time t ch 0.46 x t clk 0.54 x t clk ns usdhc output/card inputs sd_cmd, sdx_datax in sdr50 (reference to clk) sd4 usdhc output delay t od ?3 1 ns usdhc output/card inputs sd_cmd, sdx_datax in sdr104 (reference to clk) sd5 usdhc output delay t od ?1.6 0.74 ns usdhc input/card outputs sd_cmd, sdx_datax in sdr50 (reference to clk) sd6 usdhc input setup time t isu 2.5 ? ns sd7 usdhc input hold time t ih 1.5 ? ns usdhc input/card outputs sd_cmd, sdx_datax in sdr104 (reference to clk) 1 1 data window in sdr104 mode is variable. sd8 card output data window t odw 0.5 x t clk ?ns 6&. elwrxwsxwiurpx6'+&wrfdug elwlqsxwiurpfdugwrx6'+& 6' 6' 6' 6'6' 6' 6' 6'
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 47 4.10.4.4 hs200 mode timing figure 21 depicts the timing of hs200 mode, and table 42 lists the hs200 timing characteristics. figure 21. hs200 mode timing 4.10.4.5 hs400 ddr ac timing ? emmc5.0 only figure 22 depicts the timing of hs400 mode, and table 43 lists the hs400 timing characteristics. be aware that only data is sampled on both edges of the clock (not applicable to cmd). the cmd input/output timing for hs400 mode is the same as cmd input/output timing for sdr104 mode. check table 42. hs200 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency period t clk 5.0 ? ns sd2 clock low time t cl 0.46 ? t clk 0.54 ? t clk ns sd3 clock high time t ch 0.46 ? t clk 0.54 ? t clk ns usdhc output/card inputs sd_cmd, sdx_datax in hs200 (reference to clk) sd5 usdhc output delay 1 1 if using key_col1, key_row1, key_col2 and key_row2 for sd3_data4?sd3_data7, note the difference in timing: t od minimum is -1.8 and t od maximum is 0.5. t od ?1.6 0.74 ns usdhc input/card outputs sd_cmd, sdx_datax in hs200 (reference to clk) 2 2 hs200 is for 8 bits while sdr104 is for 4 bits. sd8 card output data window t odw 0.5 ? t clk ?ns 6&. elwrxwsxwiurpx6'+&wrh00& elwlqsxwiurph00&wrx6'+& 6' 6'6' 6' 6' 6'
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 48 nxp semiconductors electrical characteristics sd5, sd6, and sd7 parameters in table 41 sdr50/sdr104 interface timi ng specification for cmd input/output timing for hs400 mode. figure 22. hs400 mode timing 4.10.5 i 2 c bus characteristics the inter-integrated circuit (i 2 c) provides functionality of a standard i 2 c slave and master. the i 2 c is designed to be compatible with the i 2 c bus specification, version 2.1, by philips semiconductor. table 43. hs400 interface timing specification 1 1 do not support hs400 mode if using key pad for sd3_data4 ~ sd3data7. id parameter symbols min max unit card input clock sd1 clock frequency f pp 0 150 mhz sd2 clock low time t cl 0.46 ? t clk 0.54 ? t clk ns sd3 clock high time t ch 0.46 ? t clk 0.54 ? t clk ns usdhc output/card inputs dat (reference to sck) sd4 output skew from data of edge of sck t oskew1 0.45 ns sd5 output skew from edge of sck to data t oskew2 0.45 ns usdhc input/card outputs dat (reference to strobe) sd6 usdhc input skew t rq 0.45 ns sd7 usdhc hold skew t rqh 0.45 ns 6' 6' 6' 6' 6' 6&. 2xwsxwiurp 6wureh ,qsxwiurp x6'+&wrh00& h00&wrx6'+& '$7 '$7 '$7 '$7 '$7 '$7 6' 6' 6' 6'
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 49 4.10.6 pulse width modulator (pwm) timing parameters this section describes the electrical information of the pwm. the pwm can be programmed to select one of three clock signals as its source frequency. the selected clock signal is passed through a prescaler before being input to the counter. the out put is available at the pulse-w idth modulator output (pwmn_out) external pin (see external signals table in the i.mx 6sll reference manual for pwm pin assignments). figure 23 depicts the timing of the pwm, and table 44 lists the pwm timing parameters. figure 23. pwm timing 4.10.7 lcd controller (lcdif) parameters figure 24 shows the lcdif timing and table 45 lists the timing parameters. figure 24. lcd timing table 44. pwm output timing parameters reference number parameter min max unit pwm module clock frequency 0 66 mhz p1 pwm output pulse width high 15 ? ns p2 pwm output pulse width low 9.1591 ? ns 07-n?/54 0 0 / / / / /&'qb&/. idoolqjhgjhfdswxuh /&'qb&/. ulvlqjhgjhfdswxuh /&'qb'$7$>@ /&'q&rqwuro6ljqdov / / /
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 50 nxp semiconductors electrical characteristics 4.10.7.1 lcdif signal mapping table 46 lists the details about the mapping signals. table 45. lcd timing parameters id parameter symbol min max unit l1 lcd pixel clock frequency tclk(lcd) ? 150 mhz l2 lcd pixel clock high (falling edge capture) tclkh(lcd) 3 ? ns l3 lcd pixel clock low (rising edge capture) tclkl(lcd) 3 ? ns l4 lcd pixel clock high to data valid (falling edge capture) td(clkh-dv) -1 1 ns l5 lcd pixel clock low to data valid (rising edge capture) td(clkl-dv) -1 1 ns l6 lcd pixel clock high to control signal valid (falling edge capture) td(clkh-ctrlv) -1 1 ns l7 lcd pixel clock low to control signal valid (rising edge capture) td(clkl-ctrlv) -1 1 ns table 46. lcd signal parameters pin name 8-bit dotclk lcd if 16-bit dotclk lcd if 18-bit dotclk lcd if 24-bit dotclk lcd if 8-bit dvi lcd if lcd_rs ? ? ? ? ccir_clk lcd_vsync* (two options) lcd_vsync lcd_vsync lcd_vsync lcd_vsync ? lcd_hsync lcd_hsync lcd_hsync lcd_hsync lcd_hsync ? lcd_dotclk lcd_dotclk lcd_dotclk lcd_dotclk lcd_dotclk ? lcd_enable lcd_enable lcd_en able lcd_enable lcd_enable ? lcd_d23 ? ? ? r[7] ? lcd_d22 ? ? ? r[6] ? lcd_d21 ? ? ? r[5] ? lcd_d20 ? ? ? r[4] ? lcd_d19 ? ? ? r[3] ? lcd_d18 ? ? ? r[2] ? lcd_d17 ? ? r[5] r[1] ? lcd_d16 ? ? r[4] r[0] ? lcd_d15 / vsync* ? r[4] r[3] g[7] ? lcd_d14 / hsync** ? r[3] r[2] g[6] ? lcd_d13 / lcd_dotclk ** ? r21] r[1] g[5] ?
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 51 4.10.8 scan jtag controller (sjc) timing parameters figure 25 depicts the sjc test clock input timing. figure 26 depicts the sjc boundary scan timing. figure 27 depicts the sjc test access port. signal parameters are listed in table 47 . figure 25. test clock input timing diagram lcd_d12 / enable** ? r[1] r[0] g[4] ? lcd_d11 ? r[0] g[5] g[3] ? lcd_d10 ? g[5] g[4] g[2] ? lcd_d9 ? g[4] g[3] g[1] ? lcd_d8 ? g[3] g[2] g[0] ? lcd_d8 ? g[3] g[2] g[0] ? lcd_d7 r[2] g[2] g[1] b[7] y/c[7] lcd_d6 r[1] g[1] g[0] b[6] y/c[6] lcd_d5 r[0] g[0] b[5] b[5] y/c[5] lcd_d4 g[2] b[4] b[4] b[4] y/c[4] lcd_d3 g[1] b[3] b[3] b[3] y/c[3] lcd_d2 g[0] b[2] b[2] b[2] y/c[2] lcd_d1 b[1] b[1] b[1] b[1] y/c[1] lcd_d0 b[0] b[0] b[0] b[0] y/c[0] lcd_reset lcd_reset lcd_re set lcd_reset lcd_reset ? lcd_busy / lcd_vsync lcd_busy (or optional lcd_vsync) lcd_busy (or optional lcd_vsync) lcd_busy (or optional lcd_vsync) lcd_busy (or optional lcd_vsync) ? table 46. lcd signal parameters (continued) jtag_tck (input) vm vm vih vil sj1 sj2 sj2 sj3 sj3
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 52 nxp semiconductors electrical characteristics figure 26. boundary scan (jtag) timing diagram figure 27. test access port timing diagram jtag_tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid sj4 sj5 sj6 sj7 sj6 jtag_tck (input) jtag_tdi (input) jtag_tdo (output) jtag_tdo (output) jtag_tdo (output) vih vil input data valid output data valid output data valid jtag_tms sj8 sj9 sj10 sj11 sj10
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 53 figure 28. trst timing diagram 4.10.9 spdif timing parameters the sony/philips digital interconnect format (spdif) data is sent usi ng the bi-phase marking code. when encoding, the spdif data signal is modulated by a clock that is twice the bit ra te of the data signal. table 48 and figure 29 and figure 30 show spdif timing parameters for the sony/philips digital interconnect format (spdif), including the timing of the modulating rx clock (spdif_sr_clk) for spdif in rx mode and the timing of the modulating tx clock (spdif _st_clk) for spdif in tx mode. table 47. jtag timing id parameter 1,2 all frequencies unit min max sj0 jtag_tck frequency of operation 1/(3?t dc ) 1 1 t dc = target frequency of sjc 0.001 22 mhz sj1 jtag_tck cycle time in crystal mode 45 ? ns sj2 jtag_tck clock pulse width measured at v m 2 2 v m = mid-point voltage 22.5 ? ns sj3 jtag_tck rise and fall times ? 3 ns sj4 boundary scan input data set-up time 5 ? ns sj5 boundary scan input data hold time 24 ? ns sj6 jtag_tck low to output data valid ? 40 ns sj7 jtag_tck low to output high impedance ? 40 ns sj8 jtag_tms, jtag_tdi data set-up time 5 ? ns sj9 jtag_tms, jtag_tdi data hold time 25 ? ns sj10 jtag_tck low to jtag_tdo data valid ? 44 ns sj11 jtag_tck low to jtag_tdo high impedance ? 44 ns sj12 jtag_trstb assert time 100 ? ns sj13 jtag_trstb set-up time to jtag_tck low 40 ? ns jtag_tck (input) jtag_trstb (input) sj13 sj12
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 54 nxp semiconductors electrical characteristics figure 29. srck timing diagram figure 30. stclk timing diagram 4.10.10 ssi timing parameters this section describes the timing pa rameters of the ssi module. the c onnectivity of the serial synchronous interfaces are summarized in table 49 . table 48. spdif timing parameters characteristics symbol timing parameter range unit min max spdif_in skew: asynchronous inputs, no specs apply ? ? 0.7 ns spdif_out output (load = 50pf) ?skew ? transition rising ? transition falling ? ? ? ? ? ? 1.5 24.2 31.3 ns spdif_out output (load = 30pf) ?skew ? transition rising ? transition falling ? ? ? ? ? ? 1.5 13.6 18.0 ns modulating rx clock (spdif_sr_clk) period srckp 40.0 ? ns spdif_sr_clk high period srckph 16.0 ? ns spdif_sr_clk low period srckpl 16.0 ? ns modulating tx clock (spdif_st_clk) period stclkp 40.0 ? ns spdif_st_clk high period stclkph 16.0 ? ns spdif_st_clk low pe riod stclkpl 16.0 ? ns spdif_sr_clk (output) v m v m srckp srckph srckpl spdif_st_clk (input) v m v m stclkp stclkph stclkpl
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 55 note the terms wl and bl used in the timi ng diagrams and tables refer to word length (wl) and bit length (bl). 4.10.10.1 ssi transmitter timing with internal clock figure 31 depicts the ssi transmitte r internal clock timing and table 50 lists the timing parameters for the ssi transmitter internal clock. . figure 31. ssi transmitter internal clock timing diagram table 49. audmux port allocation port signal nomenclature type and access audmux port 1 ssi 1 internal audmux port 2 ssi 2 internal audmux port 3 aud3 external ? aud3 i/o audmux port 4 aud4 external ? i2c2 and lcd, or ecspi1, or sd2 i/o through iomuxc audmux port 5 aud5 external ? epdc or sd3 i/o through iomuxc audmux port 6 aud6 external ? key_row and key_col through iomuxc audmux port 7 ssi 3 internal ss19 ss1 ss2 ss4 ss3 ss5 ss6 ss8 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss43 ss42 ote: audx_rxd input in synchronous mode only udx_txc dx_txfs (wl) utput) audx_txfs (bl) output) audx_rxd audx_txd
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 56 nxp semiconductors electrical characteristics note ? all the timings for the ssi are give n for a non-inverted serial clock polarity (txc/rxc = 0) and a non-i nverted frame sync (txfs/rxfs = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains va lid by inverting the clock signal txc/rxc and/or the fra me sync txfs/rxfs show n in the tables and in the figures. ? all timings are on audiomux pads when ssi is used for data transfer. ? the terms, wl and bl, refer to word length(wl) and bit length(bl). ? for internal frame sync operation us ing external clock, the fs timing is same as that of txd (for exampl e, during ac97 mode of operation). table 50. ssi transmitter timing with internal clock id parameter min max unit internal clock operation ss1 audx_txc/audx_rxc clock period 81.4 ? ns ss2 audx_txc/audx_rxc clock high period 36.0 ? ns ss4 audx_txc/audx_rxc clock low period 36.0 ? ns ss6 audx_txc high to audx_txfs (bl) high ? 15.0 ns ss8 audx_txc high to audx_txfs (bl) low ? 15.0 ns ss10 audx_txc high to audx_txfs (wl) high ? 15.0 ns ss12 audx_txc high to audx_txfs (wl) low ? 15.0 ns ss14 audx_txc/audx_rxc internal audx_txfs rise time ? 6.0 ns ss15 audx_txc/audx_rxc internal audx_txfs fall time ? 6.0 ns ss16 audx_txc high to audx_txd valid from high impedance ? 15.0 ns ss17 audx_txc high to audx_txd high/low ? 15.0 ns ss18 audx_txc high to audx_txd high impedance ? 15.0 ns synchronous internal clock operation ss42 audx_rxd setup before audx_txc falling 10.0 ? ns ss43 audx_rxd hold after audx_txc falling 0.0 ? ns
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 57 4.10.10.2 ssi receiver timing with internal clock figure 32 depicts the ssi receiver internal clock timing and table 51 lists the timing parameters for the receiver timing with the internal clock. figure 32. ssi receiver internal clock timing diagram table 51. ssi receiver timing with internal clock id parameter min max unit internal clock operation ss1 audx_txc/audx_rxc clock period 81.4 ? ns ss2 audx_txc/audx_rxc clock high period 36.0 ? ns ss3 audx_txc/audx_rxc clock rise time ? 6.0 ns ss4 audx_txc/audx_rxc clock low period 36.0 ? ns ss5 audx_txc/audx_rxc clock fall time ? 6.0 ns ss7 audx_rxc high to audx_txfs (bl) high ? 15.0 ns ss9 audx_rxc high to audx_txfs (bl) low ? 15.0 ns ss11 audx_rxc high to audx_txfs (wl) high ? 15.0 ns ss13 audx_rxc high to audx_txfs (wl) low ? 15.0 ns ss20 audx_rxd setup time before audx_rxc low 10.0 ? ns ss21 audx_rxd hold time after audx_rxc low 0.0 ? ns ss50 ss48 ss1 ss4 ss2 ss51 ss20 ss21 ss49 ss7 ss9 ss11 ss13 ss47 ss3 ss5 audx_txc (output) audx_txfs (bl) output) udx_txfs (wl) output) audx_rxd audx_rxc
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 58 nxp semiconductors electrical characteristics note ? all the timings for the ssi are give n for a non-inverted serial clock polarity (txc/rxc = 0) and a non-i nverted frame sync (txfs/rxfs = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains va lid by inverting the clock signal txc/rxc and/or the fra me sync txfs/rxfs show n in the tables and in the figures. ? all timings are on audiomux pads wh en ssi is being used for data transfer. ? the terms, wl and bl, refer to word length(wl) and bit length(bl). ? for internal frame sync operation us ing external clock, the fs timing is same as that of txd (for exampl e, during ac97 mode of operation). 4.10.10.3 ssi transmitter timing with external clock figure 33 depicts the ssi transmitter external clock timing and table 52 lists the timing parameters for the transmitter timing with the external clock. oversampling cl ock operation ss47 oversampling clock period 15.04 ? ns ss48 oversampling clock high period 6.0 ? ns ss49 oversampling clock rise time ? 3.0 ns ss50 oversampling clock low period 6.0 ? ns ss51 oversampling clock fall time ? 3.0 ns table 51. ssi receiver timing with internal clock (continued) id parameter min max unit
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 59 figure 33. ssi transmitter exte rnal clock timing diagram table 52. ssi transmitter timing with external clock id parameter min max unit external clock operation ss22 audx_txc/audx_rxc clock period 81.4 ? ns ss23 audx_txc/audx_rxc clock high period 36.0 ? ns ss24 audx_txc/audx_rxc clock rise time ? 6.0 ns ss25 audx_txc/audx_rxc clock low period 36.0 ? ns ss26 audx_txc/audx_rxc clock fall time ? 6.0 ns ss27 audx_txc high to audx_txfs (bl) high ?10.0 15.0 ns ss29 audx_txc high to audx_txfs (bl) low 10.0 ? ns ss31 audx_txc high to audx_txfs (wl) high ?10.0 15.0 ns ss33 audx_txc high to audx_txfs (wl) low 10.0 ? ns ss37 audx_txc high to audx_txd valid from high impedance ? 15.0 ns ss38 audx_txc high to audx_txd high/low ? 15.0 ns ss39 audx_txc high to audx_txd high impedance ? 15.0 ns synchronous external clock operation ss44 audx_rxd setup before audx_txc falling 10.0 ? ns ss45 audx_rxd hold after audx_txc falling 2.0 ? ns ss46 audx_rxd rise/fall time ? 6.0 ns ss45 ss33 ss24 ss26 ss25 ss23 ote: audx_rxd input in synchronous mode only ss31 ss29 ss27 ss22 ss44 ss39 ss38 ss37 ss46 audx_txc (input) audx_txfs (bl) (input) audx_txfs (wl) (input) audx_txd (output) audx_rxd (input)
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 60 nxp semiconductors electrical characteristics note ? all the timings for the ssi are give n for a non-inverted serial clock polarity (txc/rxc = 0) and a non-i nverted frame sync (txfs/rxfs = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains va lid by inverting the clock signal txc/rxc and/or the fra me sync txfs/rxfs show n in the tables and in the figures. ? all timings are on audmux pads when ssi is used for data transfer. ? the terms wl and bl refer to wo rd length (wl) and bit length (bl). ? for internal frame sync operation us ing external clock, the fs timing is same as that of txd (for exampl e, during ac97 mode of operation). 4.10.10.4 ssi receiver timing with external clock figure 34 depicts the ssi receiver external clock timing and table 53 lists the timing parameters for the receiver timing with the external clock. figure 34. ssi receiver exte rnal clock timing diagram table 53. ssi receiver timing with external clock id parameter min max unit external clock operation ss22 audx_txc/audx_rxc clock period 81.4 ? ns ss23 audx_txc/audx_rxc clock high period 36 ? ns ss24 audx_txc/audx_rxc clock rise time ? 6.0 ns ss25 audx_txc/audx_rxc clock low period 36 ? ns ss26 audx_txc/audx_rxc clock fall time ? 6.0 ns ss28 audx_rxc high to audx_txfs (bl) high ?10 15.0 ns ss30 audx_rxc high to audx_txfs (bl) low 10 ? ns ss24 ss34 ss35 ss30 ss28 ss26 ss25 ss23 ss40 ss22 ss32 ss36 ss41 audx_txc (input) audx_txfs (bl) (input) audx_txfs (wl) (input) audx_rxd (input)
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 61 note ? all the timings for the ssi are give n for a non-inverted serial clock polarity (txc/rxc=0) and a non-inverted frame sync (txfs/rxfs=0). if the polarity of th e clock and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal txc/rxc and/or the fra me sync txfs/rxfs show n in the tables and in the figures. ? all timings are on audmux pads wh en ssi is being used for data transfer. ? the terms, wl and bl, refer to word length(wl) and bit length(bl). ? for internal frame sync operation us ing external clock, the fs timing is same as that of txd (for exampl e, during ac97 mode of operation). 4.10.11 uart i/o configurat ion and timing parameters 4.10.11.1 uart rs-232 i/o configuration in different modes the i.mx 6sll uart interfaces can serve both as d te or dce device. this can be configured by the dcedte control bit (def ault 0 ? dce mode). table 54 shows the uart i/o conf iguration based on the enabled mode. ss32 audx_rxc high to audx _txfs (wl) high ?10 15.0 ns ss34 audx_rxc high to audx_txfs (wl) low 10 ? ns ss35 audx_txc/audx_rxc external audx_txfs rise time ? 6.0 ns ss36 audx_txc/audx_rxc external audx_txfs fall time ? 6.0 ns ss40 audx_rxd setup time before audx_rxc low 10 ? ns ss41 audx_rxd hold time after audx_rxc low 2 ? ns table 54. uart i/o configuration vs. mode port dte mode dce mode direction description direction description uart_rts_b output rts from dte to dce input rts from dte to dce uart_cts_b input cts from dce to dte output cts from dce to dte uart_dtr_b output dtr from dte to dce input dtr from dte to dce uart_dsr_b input dsr from dce to dte output dsr from dce to dte uart_dcd_b input dcd from dce to dte output dcd from dce to dte uart_ri_b input ring from dce to dte output ring from dce to dte table 53. ssi receiver timing with external clock (continued) id parameter min max unit
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 62 nxp semiconductors electrical characteristics 4.10.11.2 uart rs-232 serial mode timing the following sections describe the electrical information of the uart module in the rs-232 mode. 4.10.11.2.1 uart transmitter figure 35 depicts the transmit timing of uart in the rs- 232 serial mode, with 8 data bit/1 stop bit format. table 55 lists the uart rs-232 serial m ode transmit timing characteristics. figure 35. uart rs-232 serial mode transmit timing diagram uart receiver figure 36 depicts the rs-232 serial m ode receive timing with 8 da ta bit/1 stop bit format. table 56 lists serial mode receive timing characteristics. figure 36. uart rs-232 serial mode receive timing diagram uart_tx_data input serial data from dce to dte output serial data from dce to dte uart_rx_data output serial data from dte to dce input serial data from dte to dce table 55. rs-232 serial mode transmit timing parameters id parameter symbol min max unit ua1 transmit bit time t tbit 1/f baud_rate 1 ? t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate + t ref_clk ? table 56. rs-232 serial mode receive timing parameters id parameter symbol min max unit ua2 receive bit time 1 t rbit 1/f baud_rate 2 ? 1/(16 ? f baud_rate )1/f baud_rate + 1/(16 ? f baud_rate )? table 54. uart i/o configuration vs. mode (continued) port dte mode dce mode direction description direction description next start bit par bit ua1 ua1 ua1 ua1 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_ tx_data (output) bit 3 start bit stop bit possible parity bit bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_ rx_data (input) bit 3 start bit stop bit next start bit possible pa r i t y bit par bit ua2 ua2 ua2 ua2
electrical characteristics i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 63 4.10.11.2.2 uart irda mode timing the following subsections give the uart transmit and receive ti mings in irda mode. uart irda mode transmitter figure 37 depicts the uart irda mode transmit timing, with 8 data bit/1 stop bit format. table 57 lists the transmit timin g characteristics. figure 37. uart irda mode transmit timing diagram uart irda mode receiver figure 38 depicts the uart irda m ode receive timing, with 8 da ta bit/1 stop bit format. table 58 lists the receive timing characteristics. figure 38. uart irda mode receive timing diagram 1 the uart receiver can tolerate 1/(16 ? f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 ? f baud_rate ). 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. table 57. irda mode transmit timing parameters id parameter symbol min max unit ua3 transmit bit time in irda mode t tirbit 1/f baud_rate 1 ? t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate + t ref_clk ? ua4 transmit ir pulse duration t tirpulse (3/16) ? (1/f baud_rate ) ? t ref_clk (3/16) ? (1/f baud_rate ) + t ref_clk ? table 58. irda mode receive timing parameters id parameter symbol min max unit ua5 receive bit time 1 in irda mode t rirbit 1/f baud_rate 2 ? 1/(16 ? f baud_rate )1/f baud_rate + 1/(16 ? f baud_rate )? ua6 receive ir pulse duration t rirpulse 1.41 ? s (5/16) ? (1/f baud_rate )? ua3 ua3 ua3 ua3 ua4 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_ tx_data (output) bit 3 start bit stop bit possible parity bit bit 6 uartx_rx_data (input) ua5 ua5 ua5 ua5 ua6 bit 7 stop bit possible parity bit bit 6 bit 1 bit 2 bit 0 bit 4 bit 5 bit 3 start bit
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 64 nxp semiconductors electrical characteristics 4.10.12 usb phy parameters this section describes the usb-otg phy parameters. the usb phy meets the electrical compliance requireme nts defined in the univer sal serial bus revision 2.0 otg. 1 the uart receiver can tolerate 1/(16 ? f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 ? f baud_rate ). 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16.
boot mode configuration i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 65 5 boot mode configuration this section provides information on boot mode configuration pins allo cation and boot devices interfaces allocation. 5.1 boot mode configuration pins table 59 provides boot options, func tionality, fuse values, and associated pins. several input pins are also sampled at reset and can be used to override fuse values, depending on the va lue of bt_fuse_sel fuse. the boot option pins are in effect when bt_fuse_sel fuse is ?0? (cleared, which is the case for an unblown fuse). for detailed boot mode options configured by the boot m ode pins, see the i.mx 6sll fuse map document and the system boot chapter of the i.mx 6sll reference manual . table 59. fuses and associated pins used for boot ball name direction at reset efuse name boot mode selection boot_mode1 input boot mode selection boot_mode0 input boot mode selection boot options 1 lcd_dat0 input boot_cfg1[0] lcd_dat1 input boot_cfg1[1] lcd_dat2 input boot_cfg1[2] lcd_dat3 input boot_cfg1[3] lcd_dat4 input boot_cfg1[4] lcd_dat5 input boot_cfg1[5] lcd_dat6 input boot_cfg1[6] lcd_dat7 input boot_cfg1[7] lcd_dat8 input boot_cfg2[0] lcd_dat09 input boot_cfg2[1] lcd_dat10 input boot_cfg2[2] lcd_dat11 input boot_cfg2[3] lcd_dat12 input boot_cfg2[4] lcd_dat13 input boot_cfg2[5] lcd_dat14 input boot_cfg2[6] lcd_dat15 input boot_cfg2[7] lcd_dat16 input boot_cfg4[0] lcd_dat17 input boot_cfg4[1] lcd_dat18 input boot_cfg4[2]
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 66 nxp semiconductors boot mode configuration 5.2 boot devices interfaces allocation table 60 lists the interfaces that can be used by the boot process in accordance with the specific boot mode configuration. the table also desc ribes the interface?s specific mode s and iomuxc allocation, which are configured during boot when appropriate. lcd_dat19 input boot_cfg4[3] lcd_dat20 input boot_cfg4[4] lcd_dat21 input boot_cfg4[5] lcd_dat22 input boot_cfg4[6] lcd_dat23 input boot_cfg4[7] 1 pin value overrides fuse settings for bt_fuse_sel = ?0?. signal configuration as fuse override input at power up. these are special i/o lines that control the boot up configuration during product development. in production, the boot configuration can be controlled by fuses. table 60. interfaces allocation during boot interface ip instance allocated ball names during boot comment spi ecspi-1 ecspi1_miso, ec spi1_mosi, ecspi1_sclk, ecspi1_ss0, i2c1_scl , i2c1_sda, ecspi2_ss0 ? spi ecspi-2 ecspi2_miso, ec spi2_mosi, ecspi2_sclk, ecspi2_ss0, epdc_sd ce0, epdc_gdclk, epdc_gdoe ? spi ecspi-3 epdc_d9, epdc_d8, epdc_d11, epdc_d10, epdc_d12, epdc_d13, epdc_d14 ? spi ecspi-4 epdc_d1, epdc_d0, epdc_d3, epdc_d2, epdc_d2, epdc_d5, epdc_d6 ? sd/mmc usdhc-1 sd1_clk, sd1_cmd,sd1_dat0, sd1_dat1, sd1_dat2, sd1_dat3, sd1_dat4, sd1_dat5, sd1_dat6, sd1_dat7, gpio3_io30, gpio4_io7, ecspi2_mosi 1, 4, or 8 bit fastboot sd/mmc usdhc-2 sd2_clk, sd2_cmd, sd2_dat0, sd2_dat1, sd2_dat2, sd2_dat3, sd2_dat4, sd2_dat5, sd2_dat6, sd2_dat7, sd2_rst, ecspi1_mosi 1, 4, or 8 bit fastboot sd/mmc usdhc-3 sd3_clk, sd3_cmd, sd3_dat0, sd3_dat1, sd3_dat2, sd3_dat3, gpio3_io26, gpio3_io27, gpio3_io28, gpio3_io29, gpio4_io4, gpio4_io5 1, 4, or 8 bit fastboot usb usb_otg1_phy usb_otg1_dp usb_otg1_dn usb_otg1_vbus usb_otg1_chd_b ? table 59. fuses and associated pins used for boot (continued) ball name direction at reset efuse name
package information and contact assignments i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 67 6 package information and contact assignments this section includes the contact assignment information and mechanical package drawing. 6.1 14 x 14 mm package information 6.1.1 14 x 14 mm, 0.65 mm pitch, 24 x 24 ball matrix figure 39 shows the top, bottom, and side views of the 14 14 mm bga package.
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 68 nxp semiconductors package information and contact assignments figure 39. 14 x 14, 0.65 mm bga package top, bottom, and side views
package information and contact assignments i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 69 table 62 shows the 14 x 14 mm bga package details. 6.1.2 14 x 14 mm ground, power, sens e, not connected and reference contact assignments table 63 shows the device connection list for ground, power, sense, and reference contact signals. table 62. 14 x 14, 0.65 mm bga package details parameter symbol common dimensions minimum normal maximum total thickness a 1.03 ? 1.30 stand off a1 0.15 ? 0.25 substrate thickness a2 0.25 mold thickness a3 0.7 body size d 14 e14 ball diameter ? 0.3 ball opening ? 0.3 ball width b 0.25 ? 0.35 ball pitch e 0.65 ball count n 400 ? ? edge ball center to center d1 ? e1 ? body center to contact ball sd 0.65 se 0.65 package edge tolerance aaa 0.1 mold flatness bbb 0.2 coplanarity ddd 0.08 ball offset (package) eee 0.15 ball offset (ball) fff 0.08
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 70 nxp semiconductors package information and contact assignments table 64 displays an alpha-sorted list of the signal a ssignments including power rails. the table also includes out of reset pad state. table 63. 14 x 14 mm supplies contact assignment supply rail name ball (s) position(s) remark dram_vref k4 ? gnd a1, a7, a13, a20, b3, d4, d17, e5, e6, e9, e12, e15, e16, f5, f16, g1, g7, g8, g9, g10, g11, g12, g13, g14, g20, h3, h5, h7, h14, j5, j7, j14, j16, k7, k9, k10, k11, k12, k14, l5, l7, l9, l10, l11, l12, l14, m5, m7, m14, n3, n7, n14, p1, p5, p7, p8, p9, p10, p11, p12, p13, p1 4, p16, p20, r5, r16, t4, t6, t7, t15, v3, v12, y1, y4, y7, y11, y15, y20 ? gpanaio t16 analog pad ngnd_kel0 t14 ? nvcc_1v8 e7, e8, e13, e14, g16, h16, m16, n16, r7, r8 ? nvcc_3v3 f7, f8, f9, f10, f11, f12, f1 3, f14, f15, g15, h15, j15, k15, l15, m15, n15, p15, r9, r10, r11, r12, r13, r14, r15 ? nvcc_dram g5, g6, h6, j6, k6, l6, m6, n5, n6, p6 supply of the ddr interface nvcc_dram_2p5 f6, k5, r6 ? nvcc_pll v17 ? vdd_arm_in h11, h12, h13, j11, j12, j13, k13, l13 primary supply for the arm core vdd_high_cap u16, v16 secondary supply for the 2.5 v domain (internal regulator output?requires capa citor if internal regulator is used) vdd_high_in w17, y17 primary supply for the 2.5 v regulator vdd_snvs_cap u14 secondary supply for the snvs (internal regulator output?requires capacitor if internal regulator is used) vdd_snvs_in v14 primary supply for the snvs regulator vdd_soc_in h8, h9, h10, j8, j9, j10, k8, l8, m8, m9, m10, m11, m12, m13, n8, n9, n10, n11, n12, n13 primary supply for the soc vdd_usb_cap t13 secondary supply for the 3v domain (usbphy, mlpbphy, efuse), internal regulator output, requires capacitor if internal regulator is used. zqpad g3 ?
package information and contact assignments i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 71 table 64. 14 x 14 mm functional contact assignments ball name ball power group 1 ball type out of reset condition 2 during reset condition defaul t mode (reset mode) default function input / output value 3 aud_mclk f17 gpio gpio alt5 gpio1_gpio[6] not connected hi-z hi-z aud_rxc h17 gpio gpio alt5 gpio1_gpio[1] not connected hi-z hi-z aud_rxd h18 gpio gpio alt5 gpio1_gpio[2] not connected hi-z hi-z aud_rxfs f18 gpio gpio alt5 gpio1_gpio[0] not connected hi-z hi-z aud_txc g17 gpio gpio alt5 gpio1_gpio[3] not connected hi-z hi-z aud_txd g18 gpio gpio alt5 gpio1_gpio[5] not connected hi-z hi-z aud_txfs f19 gpio gpio alt5 gpio1_gpio[4] not connected hi-z hi-z boot_mode0 w11 reset gpio alt0 src.boot_mode[ 0] input pd (100k) pd (100k) boot_mode1 t11 reset gpio alt0 src.boot_mode[ 1] input pd (100k) pd (100k) clk1_n u15 anatop ? ? ? ? ? ? clk1_p v15 anatop ? ? ? ? ? ? dram_a0 p4 dram ddr alt0 dram_a[0] output 0 pu (100k) dram_a1 n4 dram ddr alt0 dram_a[1] output 0 pu (100k) dram_a2 m3 dram ddr alt0 dram_a[2] output 0 pu (100k) dram_a3 m4 dram ddr alt0 dram_a[3] output 0 pu (100k) dram_a4 l4 dram ddr alt0 dram_a[4] output 0 pu (100k) dram_a5 l1 dram ddr alt0 dram_a[5] output 0 pu (100k) dram_a6 l3 dram ddr alt0 dram_a[6] output 0 pu (100k) dram_a7 f4 dram ddr alt0 dram_a[7] output 0 pu (100k)
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 72 nxp semiconductors package information and contact assignments dram_a8 h4 dram ddr alt0 dram_a[8] output 0 pu (100k) dram_a9 g4 dram ddr alt0 dram_a[9] output 0 pu (100k) dram_cs0_b l2 dram ddr alt0 dram_cs0_b output 0 pu (100k) dram_cs1_b k2 dram ddr alt0 dram_cs1_b output 0 pu (100k) dram_d0 t2 dram ddr alt0 dram_d[0] input pu (100k) pu (100k) dram_d1 t1 dram ddr alt0 dram_d[1] input pu (100k) pu (100k) dram_d10 k1 dram ddr alt0 dram_d[10] input pu (100k) pu (100k) dram_d11 j1 dram ddr alt0 dram_d[11] input pu (100k) pu (100k) dram_d12 h2 dram ddr alt0 dram_d[12] input pu (100k) pu (100k) dram_d13 f2 dram ddr alt0 dram_d[13] input pu (100k) pu (100k) dram_d14 f1 dram ddr alt0 dram_d[14] input pu (100k) pu (100k) dram_d15 g2 dram ddr alt0 dram_d[15] input pu (100k) pu (100k) dram_d16 w3 dram ddr alt0 dram_d[16] input pu (100k) pu (100k) dram_d17 y3 dram ddr alt0 dram_d[17] input pu (100k) pu (100k) dram_d18 w2 dram ddr alt0 dram_d[18] input pu (100k) pu (100k) dram_d19 y2 dram ddr alt0 dram_d[19] input pu (100k) pu (100k) dram_d2 r2 dram ddr alt0 dram_d[2] input pu (100k) pu (100k) dram_d20 v2 dram ddr alt0 dram_d[20] input pu (100k) pu (100k) table 64. 14 x 14 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 during reset condition defaul t mode (reset mode) default function input / output value 3
package information and contact assignments i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 73 dram_d21 w1 dram ddr alt0 dram_d[21] input pu (100k) pu (100k) dram_d22 u1 dram ddr alt0 dram_d[22] input pu (100k) pu (100k) dram_d23 v1 dram ddr alt0 dram_d[23] input pu (100k) pu (100k) dram_d24 e2 dram ddr alt0 dram_d[24] input pu (100k) pu (100k) dram_d25 e1 dram ddr alt0 dram_d[25] input pu (100k) pu (100k) dram_d26 d1 dram ddr alt0 dram_d[26] input pu (100k) pu (100k) dram_d27 c2 dram ddr alt0 dram_d[27] input pu (100k) pu (100k) dram_d28 b1 dram ddr alt0 dram_d[28] input pu (100k) pu (100k) dram_d29 c1 dram ddr alt0 dram_d[29] input pu (100k) pu (100k) dram_d3 r1 dram ddr alt0 dram_d[3] input pu (100k) pu (100k) dram_d30 b2 dram ddr alt0 dram_d[30] input pu (100k) pu (100k) dram_d31 a2 dram ddr alt0 dram_d[31] input pu (100k) pu (100k) dram_d4 p2 dram ddr alt0 dram_d[4] input pu (100k) pu (100k) dram_d5 n2 dram ddr alt0 dram_d[5] input pu (100k) pu (100k) dram_d6 m2 dram ddr alt0 dram_d[6] input pu (100k) pu (100k) dram_d7 n1 dram ddr alt0 dram_d[7] input pu (100k) pu (100k) dram_d8 j2 dram ddr alt0 dram_d[8] input pu (100k) pu (100k) dram_d9 h1 dram ddr alt0 dram_d[9] input pu (100k) pu (100k) table 64. 14 x 14 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 during reset condition defaul t mode (reset mode) default function input / output value 3
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 74 nxp semiconductors package information and contact assignments dram_dqm0 p3 dram ddr alt0 dram_dqm[0] output 0 pu (100k) dram_dqm1 f3 dram ddr alt0 dram_dqm[1] output 0 pu (100k) dram_dqm2 t3 dram ddr alt0 dram_dqm[2] output 0 pu (100k) dram_dqm3 c3 dram ddr alt0 dram_dqm[3] output 0 pu (100k) dram_sdcke0 m1 dram ddr alt0 dram_sdcke[0] output 0 pd (100k) dram_sdcke1 k3 dram ddr alt0 dram_sdcke[1] output 0 pd (100k) dram_sdclk_0 j4 dram ddrcl k alt0 dram_sdclk[0] input hi-z pu (100k) dram_sdclk_0_b j3 dram ? ? ? ? ? ? dram_sdqs0 r3 dram ddrcl k alt0 dram_sdqs[0] input hi-z not connected dram_sdqs0_b r4 dram ? ? ? ? ? ? dram_sdqs1 e4 dram ddrcl k alt0 dram_sdqs[1] input hi-z not connected dram_sdqs1_b e3 dram ? ? ? ? ? ? dram_sdqs2 u2 dram ddrcl k alt0 dram_sdqs[2] input hi-z not connected dram_sdqs2_b u3 dram ? ? ? ? ? ? dram_sdqs3 d2 dram ddrcl k alt0 dram_sdqs[3] input hi-z not connected dram_sdqs3_b d3 dram ? ? ? ? ? ? ecspi1_miso l18 gpio gpio alt5 gpio4_gpio[10] not connected hi-z hi-z ecspi1_mosi m18 gpio gpio alt5 gpio4_gpio[9] not connected hi-z hi-z ecspi1_sclk m17 gpio gpio alt5 gpio4_gpio[8] not connected hi-z hi-z ecspi1_ss0 l17 gpio gpio alt 5 gpio4_gpio[11] not connected hi-z hi-z table 64. 14 x 14 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 during reset condition defaul t mode (reset mode) default function input / output value 3
package information and contact assignments i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 75 ecspi2_miso n18 gpio gpio alt5 gpio4_gpio[14] not connected hi-z hi-z ecspi2_mosi p18 gpio gpio alt5 gpio4_gpio[13] not connected hi-z hi-z ecspi2_sclk p17 gpio gpio alt5 gpio4_gpio[12] not connected hi-z hi-z ecspi2_ss0 n17 gpio gpio alt5 gpio4_gpio[15] not connected hi-z hi-z epdc_bdr0 b13 gpio gpio a lt5 gpio2_gpio[5] not connected hi-z hi-z epdc_bdr1 c13 gpio gpio a lt5 gpio2_gpio[6] not connected hi-z hi-z epdc_d0 c12 gpio gpio alt5 gpio1_gpio[7] not connected hi-z hi-z epdc_d1 b12 gpio gpio alt5 gpio1_gpio[8] not connected hi-z hi-z epdc_d10 d13 gpio gpio alt 5 gpio1_gpio[17] not connected hi-z hi-z epdc_d11 c11 gpio gpio alt 5 gpio1_gpio[18] not connected hi-z hi-z epdc_d12 c10 gpio gpio alt 5 gpio1_gpio[19] not connected hi-z hi-z epdc_d13 b9 gpio gpio alt5 gpio1_gpio[20] not connected hi-z hi-z epdc_d14 a9 gpio gpio alt5 gpio1_gpio[21] not connected hi-z hi-z epdc_d15 c9 gpio gpio alt5 gpio1_gpio[22] not connected hi-z hi-z epdc_d2 a12 gpio gpio alt5 gpio1_gpio[9] not connected hi-z hi-z epdc_d3 a11 gpio gpio alt 5 gpio1_gpio[10] not connected hi-z hi-z epdc_d4 b11 gpio gpio alt 5 gpio1_gpio[11] not connected hi-z hi-z epdc_d5 b10 gpio gpio alt 5 gpio1_gpio[12] not connected hi-z hi-z table 64. 14 x 14 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 during reset condition defaul t mode (reset mode) default function input / output value 3
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 76 nxp semiconductors package information and contact assignments epdc_d6 a10 gpio gpio alt 5 gpio1_gpio[13] not connected hi-z hi-z epdc_d7 e11 gpio gpio alt 5 gpio1_gpio[14] not connected hi-z hi-z epdc_d8 d11 gpio gpio alt 5 gpio1_gpio[15] not connected hi-z hi-z epdc_d9 d12 gpio gpio alt 5 gpio1_gpio[16] not connected hi-z hi-z epdc_gdclk c8 gpio gpio alt 5 gpio1_gpio[31] not connected hi-z hi-z epdc_gdoe a8 gpio gpio alt5 gpio2_gpio[0] not connected hi-z hi-z epdc_gdrl d10 gpio gpio alt5 gpio2_gpio[1] not connected hi-z hi-z epdc_gdsp a6 gpio gpio alt5 gpio2_gpio[2] not connected hi-z hi-z epdc_pwrcom b7 gpio gpio a lt5 gpio2_gpio[11] not connected hi-z hi-z epdc_pwrctrl0 c7 gpio gpio a lt5 gpio2_gpio[7] not connected hi-z hi-z epdc_pwrctrl1 d9 gpio gpio a lt5 gpio2_gpio[8] not connected hi-z hi-z epdc_pwrctrl2 b8 gpio gpio a lt5 gpio2_gpio[9] not connected hi-z hi-z epdc_pwrctrl3 e10 gpio gpio alt5 gpio2_gpio[10] not connected hi-z hi-z epdc_pwrint d8 gpio gpio a lt5 gpio2_gpio[12] not connected hi-z hi-z epdc_pwrstat c6 gpio gpio alt5 gpio2_gpio[13] not connected hi-z hi-z epdc_pwrwakeu p b5 gpio gpio alt5 gpio2_gpio[14] not connected hi-z hi-z epdc_sdce0 b6 gpio gpio alt 5 gpio1_gpio[27] not connected hi-z hi-z epdc_sdce1 d7 gpio gpio alt 5 gpio1_gpio[28] not connected hi-z hi-z table 64. 14 x 14 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 during reset condition defaul t mode (reset mode) default function input / output value 3
package information and contact assignments i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 77 epdc_sdce2 d6 gpio gpio alt 5 gpio1_gpio[29] not connected hi-z hi-z epdc_sdce3 d5 gpio gpio alt 5 gpio1_gpio[30] not connected hi-z hi-z epdc_sdclk a5 gpio gpio alt 5 gpio1_gpio[23] not connected hi-z hi-z epdc_sdle c5 gpio gpio alt5 gpio1_gpio[24] not connected hi-z hi-z epdc_sdoe c4 gpio gpio alt5 gpio1_gpio[25] not connected hi-z hi-z epdc_sdshr b4 gpio gpio alt5 gpio1_gpio[26] not connected hi-z hi-z epdc_vcom0 a4 gpio gpio alt5 gpio2_gpio[3] not connected hi-z hi-z epdc_vcom1 a3 gpio gpio alt5 gpio2_gpio[4] not connected hi-z hi-z gpio4_io16 u6 gpio gpio alt5 gpio4_gpio[16] not connected hi-z hi-z gpio4_io17 w4 gpio gpio alt5 gpio4_gpio[17] not connected hi-z hi-z gpio4_io18 y5 gpio gpio alt5 gpio4_gpio[18] not connected hi-z hi-z gpio4_io19 v4 gpio gpio alt5 gpio4_gpio[19] not connected hi-z hi-z gpio4_io20 u5 gpio gpio alt5 gpio4_gpio[20] not connected hi-z hi-z gpio4_io21 u4 gpio gpio alt5 gpio4_gpio[21] not connected hi-z hi-z gpio4_io22 w6 gpio gpio alt5 gpio4_gpio[22] not connected hi-z hi-z gpio4_io23 w5 gpio gpio alt5 gpio4_gpio[23] not connected hi-z hi-z gpio4_io24 y6 gpio gpio alt5 gpio4_gpio[24] not connected hi-z hi-z gpio4_io25 v5 gpio gpio alt5 gpio4_gpio[25] not connected hi-z hi-z table 64. 14 x 14 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 during reset condition defaul t mode (reset mode) default function input / output value 3
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 78 nxp semiconductors package information and contact assignments gpio4_io26 v6 gpio gpio alt5 gpio4_gpio[26] not connected hi-z hi-z i2c1_scl y9 gpio gpio alt5 gpio3_gpio[12] not connected hi-z hi-z i2c1_sda w9 gpio gpio alt5 gpio3_gpio[13] not connected hi-z hi-z i2c2_scl b14 gpio gpio alt 5 gpio3_gpio[14] not connected hi-z hi-z i2c2_sda a14 gpio gpio alt 5 gpio3_gpio[15] not connected hi-z hi-z jtag_mod t9 gpio gpio alt0 sjc.mod input pu (100k) pu (100k) jtag_tck v9 gpio gpio alt0 sjc.tck input pu (47k) pu (47k) jtag_tdi u8 gpio gpio alt0 sjc.tdi input pu (47k) pu (47k) jtag_tdo v10 gpio gpio alt0 sjc.tdo input 0 input keeper jtag_tms u9 gpio gpio alt0 sjc.tms input pu (47k) pu (47k) jtag_trstb u10 gpio gpio alt0 sjc.trstb input pu (47k) pu (47k) key_col0 d18 gpio gpio alt 5 gpio3_gpio[24] not connected hi-z hi-z key_col1 e18 gpio gpio alt 5 gpio3_gpio[26] not connected hi-z hi-z key_col2 d20 gpio gpio alt 5 gpio3_gpio[28] not connected hi-z hi-z key_col3 e19 gpio gpio alt 5 gpio3_gpio[30] not connected hi-z hi-z key_col4 c19 gpio gpio alt5 gpio4_gpio[0] not connected hi-z hi-z key_col5 d19 gpio gpio alt5 gpio4_gpio[2] not connected hi-z hi-z key_col6 c17 gpio gpio alt5 gpio4_gpio[4] not connected hi-z hi-z table 64. 14 x 14 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 during reset condition defaul t mode (reset mode) default function input / output value 3
package information and contact assignments i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 79 key_col7 a19 gpio gpio alt5 gpio4_gpio[6] not connected hi-z hi-z key_row0 f20 gpio gpio alt5 gpio3_gpio[25] not connected hi-z hi-z key_row1 e17 gpio gpio alt5 gpio3_gpio[27] not connected hi-z hi-z key_row2 e20 gpio gpio alt5 gpio3_gpio[29] not connected hi-z hi-z key_row3 c20 gpio gpio alt5 gpio3_gpio[31] not connected hi-z hi-z key_row4 b18 gpio gpio alt5 gpio4_gpio[1] not connected hi-z hi-z key_row5 c18 gpio gpio alt5 gpio4_gpio[3] not connected hi-z hi-z key_row6 b20 gpio gpio alt5 gpio4_gpio[5] not connected hi-z hi-z key_row7 b19 gpio gpio alt5 gpio4_gpio[7] not connected hi-z hi-z lcd_clk r18 gpio gpio alt5 gpio2_gpio[15] not connected hi-z hi-z lcd_dat0 u20 gpio gpio alt5 g pio2_gpio[20] input pd (100k) pd (100k) lcd_dat1 t20 gpio gpio alt5 g pio2_gpio[21] input pd (100k) pd (100k) lcd_dat10 m19 gpio gpio alt5 gpio2_gpio[30] input pd (100k) pd (100k) lcd_dat11 n20 gpio gpio alt5 gpio2_gpio[31] input pd (100k) pd (100k) lcd_dat12 m20 gpio gpio alt5 gpio3_gpio[0] input pd (100k) pd (100k) lcd_dat13 l20 gpio gpio alt5 gpio3_gpio[1] input pd (100k) pd (100k) lcd_dat14 l16 gpio gpio alt5 gpio3_gpio[2] input pd (100k) pd (100k) lcd_dat15 k20 gpio gpio alt5 gpio3_gpio[3] input pd (100k) pd (100k) table 64. 14 x 14 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 during reset condition defaul t mode (reset mode) default function input / output value 3
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 80 nxp semiconductors package information and contact assignments lcd_dat16 l19 gpio gpio alt5 gpio3_gpio[4] input pd (100k) pd (100k) lcd_dat17 k16 gpio gpio alt5 gpio3_gpio[5] input pd (100k) pd (100k) lcd_dat18 k19 gpio gpio alt5 gpio3_gpio[6] input pd (100k) pd (100k) lcd_dat19 j19 gpio gpio alt5 gpio3_gpio[7] input pd (100k) pd (100k) lcd_dat2 t19 gpio gpio alt5 g pio2_gpio[22] input pd (100k) pd (100k) lcd_dat20 k17 gpio gpio alt5 gpio3_gpio[8] input pd (100k) pd (100k) lcd_dat21 k18 gpio gpio alt5 gpio3_gpio[9] input pd (100k) pd (100k) lcd_dat22 j20 gpio gpio alt5 gpio3_gpio[10] input pd (100k) pd (100k) lcd_dat23 j17 gpio gpio alt5 gpio3_gpio[11] input pd (100k) pd (100k) lcd_dat3 t18 gpio gpio alt5 g pio2_gpio[23] input pd (100k) pd (100k) lcd_dat4 r20 gpio gpio alt5 g pio2_gpio[24] input pd (100k) pd (100k) lcd_dat5 t17 gpio gpio alt5 g pio2_gpio[25] input pd (100k) pd (100k) lcd_dat6 r17 gpio gpio alt5 g pio2_gpio[26] input pd (100k) pd (100k) lcd_dat7 r19 gpio gpio alt5 g pio2_gpio[27] input pd (100k) pd (100k) lcd_dat8 p19 gpio gpio alt5 g pio2_gpio[28] input pd (100k) pd (100k) lcd_dat9 n19 gpio gpio alt5 g pio2_gpio[29] input pd (100k) pd (100k) lcd_enable j18 gpio gpio alt5 gpio2_gpio[16] not connected hi-z hi-z lcd_hsync g19 gpio gpio alt5 gpio2_gpio[17] not connected hi-z hi-z table 64. 14 x 14 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 during reset condition defaul t mode (reset mode) default function input / output value 3
package information and contact assignments i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 81 lcd_reset h19 gpio gpio alt5 gpio2_gpio[19] not connected hi-z hi-z lcd_vsync h20 gpio gpio alt5 gpio2_gpio[18] not connected hi-z hi-z onoff u12 reset gpio alt0 src.reset_b input pu (100k) pu (100k) pmic_on_req y10 reset gpio alt0 snvs_lp_wrappe r.snvs_wakeup_ alarm output open drain with pu (100k) pu (100k) pmic_stby_req w10 reset gpio alt0 ccm.pmic_vstby_ req output 0 not connected por_b v11 reset gpio alt0 src.por_b input pu (100k) pu (100k) pwm1 t5 gpio gpio alt5 gpio3_gpio[23] not connected hi-z hi-z ref_clk_24m t8 gpio gpio alt5 gpio3_gpio[21] not connected hi-z hi-z ref_clk_32k t10 gpio gpio alt5 gpio3_gpio[22] not connected hi-z hi-z rtc_xtali y16 anatop ? ? ? ? ? ? rtc_xtalo w16 anatop ? ? ? ? ? ? sd1_clk d15 gpio gpio alt 5 gpio5_gpio[15] not connected hi-z hi-z sd1_cmd c15 gpio gpio alt5 gpio5_gpio[14] not connected hi-z hi-z sd1_dat0 a18 gpio gpio alt 5 gpio5_gpio[11] not connected hi-z hi-z sd1_dat1 c16 gpio gpio a lt5 gpio5_gpio[8] not connected hi-z hi-z sd1_dat2 b17 gpio gpio alt 5 gpio5_gpio[13] not connected hi-z hi-z sd1_dat3 b16 gpio gpio a lt5 gpio5_gpio[6] not connected hi-z hi-z sd1_dat4 d16 gpio gpio alt 5 gpio5_gpio[12] not connected hi-z hi-z table 64. 14 x 14 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 during reset condition defaul t mode (reset mode) default function input / output value 3
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 82 nxp semiconductors package information and contact assignments sd1_dat5 a17 gpio gpio a lt5 gpio5_gpio[9] not connected hi-z hi-z sd1_dat6 a16 gpio gpio a lt5 gpio5_gpio[7] not connected hi-z hi-z sd1_dat7 d14 gpio gpio alt 5 gpio5_gpio[10] not connected hi-z hi-z sd2_clk y19 gpio gpio alt 5 gpio5_gpio[5] not connected hi-z hi-z sd2_cmd w20 gpio gpio alt5 gpio5_gpio[4] not connected hi-z hi-z sd2_dat0 y18 gpio gpio a lt5 gpio5_gpio[1] not connected hi-z hi-z sd2_dat1 w18 gpio gpio alt 5 gpio4_gpio[30] not connected hi-z hi-z sd2_dat2 v18 gpio gpio a lt5 gpio5_gpio[3] not connected hi-z hi-z sd2_dat3 w19 gpio gpio alt 5 gpio4_gpio[28] not connected hi-z hi-z sd2_dat4 v20 gpio gpio a lt5 gpio5_gpio[2] not connected hi-z hi-z sd2_dat5 u17 gpio gpio alt 5 gpio4_gpio[31] not connected hi-z hi-z sd2_dat6 u18 gpio gpio alt 5 gpio4_gpio[29] not connected hi-z hi-z sd2_dat7 v19 gpio gpio a lt5 gpio5_gpio[0] not connected hi-z hi-z sd2_rst u19 gpio gpio alt5 gpio4_gpio[27] not connected hi-z hi-z sd3_clk u7 gpio gpio alt5 gpio5_gpio[18] not connected hi-z hi-z sd3_cmd w7 gpio gpio alt5 gpio5_gpio[21] not connected hi-z hi-z sd3_dat0 y8 gpio gpio alt5 gpio5_gpio[19] not connected hi-z hi-z sd3_dat1 w8 gpio gpio alt5 gpio5_gpio[20] not connected hi-z hi-z table 64. 14 x 14 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 during reset condition defaul t mode (reset mode) default function input / output value 3
package information and contact assignments i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 83 sd3_dat2 v7 gpio gpio alt5 gpio5_gpio[16] not connected hi-z hi-z sd3_dat3 v8 gpio gpio alt5 gpio5_gpio[17] not connected hi-z hi-z tamper t12 reset gpio alt0 snvs_lp_wrappe r.snvs_td1 input ? pd (100k) test_mode u11 reset gpio alt0 tcu.test_mode input ? pd (100k) uart1_rxd a15 gpio gpio alt5 gpio3_gpio[16] not connected hi-z hi-z uart1_txd b15 gpio gpio alt5 gpio3_gpio[17] not connected hi-z hi-z usb_otg1_chd_b w15 anatop ? ? ? ? ? ? usb_otg1_dn y14 anatop ? ? ? ? ? ? usb_otg1_dp w14 anatop ? ? ? ? ? ? usb_otg2_dn y12 anatop ? ? ? ? ? ? usb_otg2_dp w12 anatop ? ? ? ? ? ? wdog_b c14 gpio gpio alt 5 gpio3_gpio[18] not connected hi-z hi-z xtali v13 anatop ? ? ? ? ? ? xtalo u13 anatop ? ? ? ? ? ? zqpad g3 dram ? ? ? input hi-z not connected 1 all balls marked power group nvcc33_io or nvcc18_io ar e dual-voltage ios. the user supplies nvcc33_io and nvcc18_io. in the iomux for each ball, the user selects either 3.3 v or 1.8 v operation using the lve field in the pad control register for each ball. 2 the state immediately after reset and befor e rom firmware or software has executed. 3 variance of the pull-up and pull-down str engths are shown in the tables as follows: ? table 20, "dvgpio i/o dc parameters," on page 28 . ? table 21, "gpio i/o dc parameters," on page 29 ? table 22, "lpddr2/lpddr3 i/o dc electrical parameters," on page 30 table 64. 14 x 14 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 during reset condition defaul t mode (reset mode) default function input / output value 3
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 84 nxp semiconductors package information and contact assignments 6.1.3 14 x 14 mm, 0.65 mm pitch ball map table 65 shows the mapbga 14 x 14 mm, 0.65 mm pitch ball map. table 65. 14 x 14 mm, 0.65 mm pitch ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a gnd dram_d31 epdc_vcom1 epdc_vcom0 epdc_sdclk epdc_gdsp gnd epdc_gdoe epdc_d14 epdc_d6 epdc_d3 epdc-d2 gnd i2c2_sda uart1_rxd sd1_dat6 sd1_dat5 sd1_dat0 key_col7 gnd b dram_d28 dram_d30 gnd epdc_sdshr epdc_pwrwakeup epdc_sdce0 epdc_pwrcom epdc_pwrctrl2 epdc_d13 epdc_d5 epdc_d4 epdc_d1 epdc_bdr0 i2c2_scl uart1_txd sd1_dat3 sd1_dat2 key_row4 key_row7 key_row6 c dram_d29 dram_d27 dram_dqm3 epdc_sdoe epdc_sdle epdc_pwrstat epdc_pwrctrl0 epdc_gdclk epdc_d15 epdc_d12 epdc_d11 epdc_d0 epdc_bdr1 wdog_b sd1_cmd sd1_dat1 key_col6 key_row5 key_col4 key_row3 d dram_d26 dram_sdqs3 dram_sdqs3_b gnd epdc_sdce3 epdc_sdce2 epdc_sdce1 epdc_pwrint epdc_pwrctrl1 epdc_gdrl epdc_d8 epdc_d9 epdc_d10 sd1_dat7 sd1_clk sd1_dat4 gnd key_col0 key_col5 key_col2 e dram_d25 dram_d24 dram_sdqs1_b dram_sdqs1 gnd gnd nvcc_1v8 nvcc_1v8 gnd epdc_pwrctrl3 epdc_d7 gnd nvcc_1v8 nvcc_1v8 gnd gnd key_row1 key_col1 key_col3 key_row2 f dram_d14 dram_d13 dram_dqm1 dram_a7 gnd nvcc_dram_2p5 nvcc_3v3 nvcc_3v3 nvcc_3v3 nvcc_3v3 nvcc_3v3 nvcc_3v3 nvcc_3v3 nvcc_3v3 nvcc_3v3 gnd aud_mclk aud_rxfs aud_txfs key_row0
package information and contact assignments i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 85 g gnd dram_d15 zqpad dram_a9 nvcc_dram nvcc_dram gnd gnd gnd gnd gnd gnd gnd gnd nvcc_3v3 nvcc_1v8_2 aud_txc aud_txd lcd_hsync gnd h dram_d9 dram_d12 gnd dram_a8 gnd nvcc_dram gnd vdd_soc_in vdd_soc_in vdd_soc_in vdd_arm_in vdd_arm_in vdd_arm_in gnd nvcc_3v3 nvcc_1v8 aud_rxc aud_rxd lcd_reset lcd_vsync j dram_d11 dram_d8 dram_sdclk_0_b dram_sdclk_0 gnd nvcc_dram gnd vdd_soc_in vdd_soc_in vdd_soc_in vdd_arm_in vdd_arm_in vdd_arm_in gnd nvcc_3v3 gnd lcd_dat23 lcd_enable lcd_dat19 lcd_dat22 k dram_d10 dram_cs1_b dram_sdcke1 dram_vref nvcc_dram nvcc_dram_2p5 gnd vdd_soc_in gnd gnd gnd gnd vdd_arm_in gnd nvcc_3v3 lcd_dat17 lcd_dat20 lcd_dat21 lcd_dat18 lcd_dat15 l dram_a5 dram_cs0_b dram_a6 dram_a4 gnd nvcc_dram gnd vdd_soc_in gnd gnd gnd gnd vdd_arm_in gnd nvcc_3v3 lcd_dat14 ecspi1_ss0 ecspi1_miso lcd_dat16 lcd_dat13 m dram_sdcke0 dram_d6 dram_a2 dram_a3 gnd nvcc_dram gnd vdd_soc_in vdd_soc_in vdd_soc_in vdd_soc_in vdd_soc_in vdd_soc_in gnd nvcc_3v3 nvcc_1v8 ecspi1_sclk ecspi1_mosi lcd_dat10 lcd_dat12 n dram_d7 dram_d5 gnd dram_a1 nvcc_dram nvcc_dram gnd vdd_soc_in vdd_soc_in vdd_soc_in vdd_soc_in vdd_soc_in vdd_soc_in gnd nvcc_3v3 nvcc_1v8 ecspi2_ss0 ecspi2_miso lcd_dat9 lcd_dat11 p gnd dram_d4 dram_dqm0 dram_a0 gnd nvcc_dram gnd gnd gnd gnd gnd gnd gnd gnd nvcc_3v3 gnd ecspi2_sclk ecspi2_mosi lcd_dat8 gnd table 65. 14 x 14 mm, 0.65 mm pitch ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 86 nxp semiconductors package information and contact assignments r dram_d3 dram_d2 dram_sdqs0 dram_sdqs0_b gnd nvcc_dram_2p5 nvcc_1v8 nvcc_1v8 nvcc_3v3 nvcc_3v3 nvcc_3v3 nvcc_3v3 nvcc_3v3 nvcc_3v3 nvcc_3v3 gnd lcd_dat6 lcd_clk lcd_dat7 lcd_dat4 t dram_d1 dram_d0 dram_dqm2 gnd pwm1 gnd gnd ref_clk_24m jtag_mod ref_clk_32k boot_mode1 tamper vdd_usb_cap ngnd_kel0 gnd gpanaio lcd_dat5 lcd_dat3 lcd_dat2 lcd_dat1 u dram_d22 dram_sdqs2 dram_sdqs2_b gpio4_io21 gpio4_io20 gpio4_io16 sd3_clk jtag_tdi jtag_tms jtag_trstb test_mode onoff xtalo vdd_snvs_cap clk1_n vdd_high_cap sd2_dat5 sd2_dat6 sd2_rst lcd_dat0 v dram_d23 dram_d20 gnd gpio4_io19 gpio4_io25 gpio4_io226 sd3_dat2 sd3_dat3 jtag_tck jtag_tdo por_b gnd xtali vdd_snvs_in clk1_p vdd_high_cap nvcc_pll sd2_dat2 sd2_dat7 sd2_dat4 w dram_d21 dram_d18 dram_d16 gpio4_io17 gpio4_io23 gpio4_io22 sd3_cmd sd3_dat1 i2c1_sda pmc_stby_req boot_mode0 usb_otg2_dp usb_otg1_vbus usb_otg1_dp usb_otg1_chd_b rtc_xtalo vdd_high_in sd2_dat1 sd2_dat3 sd2_cmd y gnd dram_d19 dram_d17 gnd gpio4_io18 gpio4_io24 gnd sd3_dat0 i2c1_scl pmic_on_req gnd usb_otg2_dn usb_otg2_vbus usb_otg1_dn gnd rtc_xtali vdd_high_in sd2_dat0 sd2_clk gnd table 65. 14 x 14 mm, 0.65 mm pitch ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
revision history i.mx 6sll applications processors for industrial products, rev. 0.2, 11/2017 nxp semiconductors 87 7 revision history table 66 provides a history for this data sheet. table 66. i.mx 6sll data sheet document revision history rev. number date substantive change(s) rev. 0.2 11/2017 ? removed the hbm note in the table 7, "absolute maximum ratings and updated the esd hbm values ? added a note in the table 7, "absolute maximum ratings rev. 0.1 09/2017 ? added a note for hbm in the table 7, "absolute maximum ratings rev. 0 04/2017 ? initial version
document number: imx6sllcec rev. 0.2 11/2017 information in this document is provid ed solely to enable system and software implementers to use nxp products. there ar e no express or implied copyright licenses granted hereunder to design or fabricat e any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any produc t or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in nxp data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer? customer?s technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions. nxp, the nxp logo, freescale, the freescale logo, and the energy efficient solutions logo are trademarks of nxp b.v. all other product or service names are the property of their respective owners. arm and cortex are trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. all rights reserved. ? 2017 nxp b.v. how to reach us: home page: nxp.com web support: nxp.com/support

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