View LTC3440-15_9057915.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 for more information www.linear.com/ltc3440 description micropower synchronous buck-boost dc/dc converter features a pplications n single inductor n fixed frequency operation with battery voltages above, below or equal to the output n synchronous rectifcation: up to 96% effciency n 25a quiescent current in burst mode ? operation n up to 600ma continuous output current n no schottky diodes required (v out < 4.3v) n v out disconnected from v in during shutdown n 2.5v to 5.5v input and output range n programmable oscillator frequency from 300khz to 2mhz n synchronizable oscillator n burst mode enable control n <1a shutdown current n small thermally enhanced 10-pin msop and (3mm 3mm) dfn packages n palmtop computers n handheld instruments n mp3 players n digital cameras the lt c ? 3440 is a high effciency, fxed frequency, buck- boost dc/dc converter that operates from input voltages above, below or equal to the output voltage. the topology incorporated in the ic provides a continuous transfer function through all operating modes, making the prod - uct ideal for single lithium-ion, multicell alkaline or nimh applications where the output voltage is within the battery vo ltage range. the device includes two 0.19 n-channel mosfet switches and two 0.22 p-channel switches. switch - ing frequencies up to 2mhz are programmed with an ex ternal resistor and the oscillator can be synchronized to an external clock. quiescent current is only 25a in burst mode operation, maximizing battery life in portable applications. burst mode operation is user controlled and can b e enabled by driving the mode/sync pin high. if the mode/sync pin has either a clock or is driven low, then fxed frequency switching is enabled. other features include a 1a shutdown, soft-start con - trol, thermal shutdown and current limit. the ltc3440 is av ailable in the 10-pin thermally enhanced msop and (3mm 3mm) dfn packages. effciency vs v in sw1 v in shdn/ss mode/sync r t sw2 v out fb v c gnd 3 7 8 2 1 4 6 9 10 5 ltc3440 l1 10h r1 340k r2 200k r3 15k 3440 ta01 r t 60.4k c1: taiyo yuden jmk212bj106mg c2: taiyo yuden jmk325bj226mm l1: sumida cdrh6d38-100 *1 = burst mode operation 0 = fixed frequency c1 10f li-ion v in = 2.7v to 4.2v * + c5 1.5nf c2 22f v out 3.3v 600ma v in (v) 2.5 efficiency (%) 3.0 3.5 4.0 4.5 3440 ta02 5.0 100 98 96 94 92 90 88 86 84 82 80 5.5 v out = 3.3v i out = 100ma f osc = 1mhz t y pical a pplication li-ion to 3.3v at 600ma buck-boost converter l , lt, ltc, ltm, linear technology, burst mode and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. ltc3440 3440fc
2 for more information www.linear.com/ltc3440 a bsolute maxi m u m r atings (note 1) v in , v out voltage ....................................... C 0 .3v to 6v sw1, sw2 voltage ...................................... C 0.3v to 6v v c , r t , fb, shdn /ss, mode/sync voltage .................................. C 0.3v to 6v the denotes specifcations that apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = v out = 3.6v, r t = 60k, unless otherwise noted. operating temperature range (note 2).... C40c to 85c storage temperature range .................. C 65c to 125c lead temperature (soldering, 10 sec) ................... 3 00c electrical c h ara c teristics parameter conditions min typ max units input start-up voltage l 2.4 2.5 v input operating range l 2.5 5.5 v output voltage adjust range l 2.5 5.5 v feedback voltage l 1.196 1.22 1.244 v feedback input current v fb = 1.22v 1 50 na quiescent current, burst mode operation v c = 0v, mode/sync = 3v (note 3) 25 40 a quiescent current, shutdown shdn = 0v, not including switch leakage 0.1 1 a quiescent current, active v c = 0v, mode/sync = 0v (note 3) 600 1000 a nmos switch leakage switches b and c 0.1 5 a p in c on f iguration top view dd package 10-lead (3mm 3mm) plastic dfn exposed pad (pin 11) is gnd must be soldered to pcb 10 9 6 7 8 4 5 3 2 1 v c fb shdn/ss v in v out r t mode/sync sw1 sw2 gnd 11 t jmax = 125c, v ja = 43c/w, v jc = 3c/w 1 2 3 4 5 r t mode/sync sw1 sw2 gnd 10 9 8 7 6 v c fb shdn/ss v in v out top view ms package 10-lead plastic msop t jmax = 125c, v ja = 130c/w 1 layer board v ja = 100c/w 4 layer board v jc = 45c/w o r d er i n f or m ation lead free finish tape and reel part marking package description temperature range ltc3440edd#pbf ltc3440edd#trpbf lbkt 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc3440ems#pbf ltc3440ems#trpbf ltnp 10-lead plastic msop C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. consult ltc marketing for information on nonstandard lead based fnish parts. f o r more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ ltc3440 3440fc
3 for more information www.linear.com/ltc3440 parameter conditions min typ max units pmos switch leakage switches a and d 0.1 10 a nmos switch on resistance switches b and c 0.19 pmos switch on resistance switches a and d 0.22 input current limit l 1 a maximum duty cycle boost (% switch c on) buck (% switch a on) l l 55 100 75 % % m i nimum duty cycle l 0 % frequency accuracy l 0.8 1 1.2 mhz mode/sync threshold 0.4 2 v mode/sync input current v mode/sync = 5.5v 0.01 1 a error amp avol 90 db error amp source current 15 a error amp sink current 380 a shdn /ss threshold when ic is enabled when ea is at maximum boost duty cycle l 0.4 1 2.2 1. 5 v v shd n /ss input current v shdn = 5.5v 0.01 1 a the denotes specifcations that apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = v out = 3.6v, r t = 60k, unless otherwise noted. electrical c h aracteristics note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: the ltc3440e is guaranteed to meet performance specifcations from 0c to 70c. specifcations over the C 40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: current measurements are performed when the outputs are not switching. t y pical per f or m ance c h aracteristics li-ion to 3.3v effciency (f osc = 300khz) output current (ma) 30 efficiency (%) 90 100 20 80 50 70 60 40 0.1 10 100 1000 3440 g02 1 burst mode operation v in = 3.3v v in = 2.5v power loss (mw) v in = 4.2v 0.1 1 10 100 1000 f osc = 1mhz v in = 3.3v output current (ma) 30 efficiency (%) 90 100 20 80 50 70 60 40 0.1 10 100 1000 3440 g03 1 burst mode operation v in = 2.5v v in = 3.3v f osc = 2mhz v in = 4.2v li-ion to 3.3v effciency, power loss (f osc = 1mhz) li-ion to 3.3v effciency (f osc = 2mhz) output current (ma) 30 efficiency (%) 90 100 20 80 50 70 60 40 0.1 10 100 1000 3440 g01 1 burst mode operation v in = 2.5v v in = 3.3v f osc = 300khz v in = 4.2v ltc3440 3440fc
4 for more information www.linear.com/ltc3440 ty pical p er f or m ance ch aracteristics active quiescent current burst mode quiescent current error amp source current temperature (c) ?55 400 v in + v out current (a) 450 500 550 ?25 5 35 65 3440 g10 95 125 v in = v out = 3.6v switch pins in buck mode v out ripple during buck, buck/boost and boost modes switch pins in boost mode 250ns/div v in = 5v v out = 3.3v i out = 250ma sw2 2v/div sw1 2v/div 3440 g07 250ns/div v in = 2.5v v out = 3.3v i out = 250ma sw2 2v/div sw1 2v/div 3440 g08 1s/div l = 10h c out = 22f i out = 250ma f osc = 1mhz buck v in = 5v buck/boost v in = 3.78v boost v in = 2.5v v out 10mv/div ac coupled 3440 g09 switch pins during buck/boost switch pins on the edge of buck/boost and approaching boost switch pins on the edge of buck/boost and approaching buck 50ns/div v in = 3.78v v out = 3.3v i out = 250ma sw2 2v/div sw1 2v/div 3440 g04 50ns/div v in = 3.42v v out = 3.3v i out = 250ma sw2 2v/div sw1 2v/div 3440 g05 50ns/div v in = 4.15v v out = 3.3v i out = 250ma sw2 2v/div sw1 2v/div 3440 g06 temperature (c) ?55 10 v in + v out current (a) 20 30 40 ?25 5 35 65 3440 g11 95 125 v in = v out = 3.6v temperature (c) ?55 5 e/a source current (a) 10 15 20 ?25 5 35 65 3440 g12 95 125 v in = v out = 3.6v ltc3440 3440fc
5 for more information www.linear.com/ltc3440 ty pical p er f or m ance ch aracteristics output frequency nmos r ds(on) feedback voltage temperature (c) ?55 0.90 frequency (mhz) 0.95 1.00 1.05 1.10 ?25 5 35 65 3440 g13 95 125 v in = v out = 3.6v temperature (c) ?55 0.10 nmos r ds(on) () 0.15 0.20 0.25 0.30 ?25 5 35 65 3440 g14 95 125 v in = v out = 3.6v switches b and c temperature (c) ?55 1.196 feedback voltage (v) 1.216 1.236 ?25 5 35 65 3440 g15 95 125 v in = v out = 3v boost max duty cycle minimum start voltage current limit temperature (c) ?55 70 duty cycle (%) 75 80 85 90 ?25 5 35 65 3440 g19 95 125 v in = v out = 3.6v r t = 60k temperature (c) ?55 2.25 minimum start voltage (v) 2.30 2.35 2.40 ?25 5 35 65 3440 g20 95 125 temperature (c) ?55 1000 current limit (a) 1500 2000 2500 3000 ?25 5 35 65 3440 g21 95 125 v in = v out = 3.6v peak switch average input feedback voltage line regulation error amp sink current pmos r ds(on) temperature (c) ?55 60 line regulation (db) 70 80 90 ?25 5 35 65 3440 g16 95 125 v in = v out = 2.5v to 5.5v temperature (c) ?55 350 e/a sink current (a) 370 390 410 430 ?25 5 35 65 3440 g17 95 125 v in = v out = 3.6v temperature (c) ?55 0.10 pmos r ds(on) () 0.15 0.20 0.25 0.30 ?25 5 35 65 3440 g18 95 125 v in = v out = 3.6v switches a and d ltc3440 3440fc
6 for more information www.linear.com/ltc3440 p in functions r t (pin 1): timing resistor to program the oscillator frequency. the programming frequency range is 300khz to 2mhz. f r hz osc t = 61 0 10 ? mode/sync (pin 2): mode/sync = external clk : syn - chronization of the internal oscillator. a clock frequency o f t wice the desired switching frequency and with a pulse width between 100ns and 2s is applied. the oscillator free running frequency is set slower than the desired synchronized switching frequency to guarantee sync. the oscillator r t component value required is given by: r t = 8 ? 10 10 f sw where f sw = desired synchronized switching frequency. sw1 (pin 3): switch pin where the internal switches a and b are connected. connect inductor from sw1 to sw2. an optional schottky diode can be connected from sw1 to ground. minimize trace length to keep emi down. sw2 (pin 4): switch pin where the internal switches c and d are connected. for applications with output voltages over 4.3v, a schottky diode is required from sw2 to v out to ensure the sw pin does not exhibit excess voltage. gnd (pin 5): signal and power ground for the ic. v out (pin 6): output of the synchronous rectifer. a flter capacitor is placed from v out to gnd. v in (pin 7): input supply pin. internal v cc for the ic. a ceramic bypass capacitor as close to the v in pin and gnd (pin 5) is required. shdn /ss (pin 8): combined soft-start and shutdown. grounding this pin shuts down the ic. tie to >1.5v to enable the ic and >2.5v to ensure the error amp is not clamped from soft-start. an rc from the shutdown com - mand signal to this pin will provide a soft-start function by l imiting the rise time of the v c pin. fb (pin 9): feedback pin. connect resistor divider tap here. the output voltage can be adjusted from 2.5v to 5.5v. the feedback reference voltage is typically 1.22v. v c (pin 10): error amp output. a frequency compensa - tion network is connected from this pin to the fb pin to c o mpensate the loop. see the section compensating the feedback loop for guidelines. exposed pad (pin 11, dfn package only): ground. this pin must be soldered to the pcb and electrically connected to ground. ltc3440 3440fc
7 for more information www.linear.com/ltc3440 b lock diagra m ? + ? + ? + ? + ? + ? + 7 pwm logic and output phasing gate drivers and anticross conduction burst mode operation control 5s delay gnd uvlo 2.7a 2.4v r t sleep mode/sync 1 = burst mode operation 0 = fixed frequency r t osc sync supply current limit sw a sw1 sw2 v in 2.5v to 5.5v sw d i sense amp error amp 1.22v clamp reverse current limit sw b sw c ?0.4a 1 2 5 8 + 3 4 v out 6 fb 9 v c 10 shdn/ss shutdown r ss v in r2 c ss r1 3440 bd v out 2.5v to 5.5v pwm comparators ltc3440 3440fc
8 for more information www.linear.com/ltc3440 o peration the ltc3440 provides high effciency, low noise power for applications such as portable instrumentation. the ltc proprietary topology allows input voltages above, below or equal to the output voltage by properly phasing the output switches. the error amp output voltage on the v c pin determines the output duty cycle of the switches. since the v c pin is a fltered signal, it provides rejection of frequencies from well below the switching frequency. the low r ds(on) , low gate charge synchronous switches provide high frequency pulse width modulation control at high effciency. schottky diodes across the synchronous switch d and synchronous switch b are not required, but provide a lower drop during the break-before-make time (typically 15ns). the addition of the schottky diodes will improve peak effciency by typically 1% to 2% at 600khz. high effciency is achieved at light loads when burst mode operation is entered and when the ics quiescent current is a low 25a. l ow n oise f ixed f requency o pera tion oscillator th e frequency of operation is user programmable and is set through a resistor from the r t pin to ground where: f = 6e10 r t ? ? ? ? ? ? hz an internally trimmed timing capacitor resides inside the ic. the oscillator can be synchronized with an external clock applied to the mode/sync pin. a clock frequency of twice the desired switching frequency and with a pulse width between 100ns and 2s is applied. the oscillator r t component value required is given by: r t " 8 ? 10 10 f sw where f sw = desired synchronized switching frequency. for example to achieve a 1.2mhz synchronized switching frequency the applied clock frequency to the mode/sync pin is set to 2.4mhz and the timing resistor, r t , is set to 66.5k (closest 1% value). error amp the error amplifer is a voltage mode amplifer. the loop compensation components are confgured around the amplifer to provide loop compensation for the converter. the shdn/ss pin will clamp the error amp output, v c , to provide a soft-start function. supply current limit the current limit amplifer will shut pmos switch a off once the current exceeds 2.7a typical. the current ampli - fer delay to output is typically 50ns. reverse current limit t h e reverse current limit amplifer monitors the inductor current from the output through switch d. once a nega - tive inductor current exceeds C 400ma typical, the ic will s h ut off switch d. output switch control figure 1 shows a simplifed diagram of how the four internal switches are connected to the inductor, v in , v out and gnd. figure 2 shows the regions of operation for the ltc3440 as a function of the internal control voltage, v ci . the v ci voltage is a level shifted voltage from the output of the error amp (v c pin) (see figure 5). the output switches are properly phased so the transfer between operation modes is continuous, fltered and transparent to the user. when v in approaches v out the buck/boost region is reached where the conduction time of the four switch region is typically 150ns. referring to figures 1 and 2, the various regions of operation will now be described. figure 1. simplifed diagram of output switches 3 sw1 4 sw2 pmos a nmos b 7 v in pmos d nmos c 3440 f01 6 v out v out ltc3440 3440fc
9 for more information www.linear.com/ltc3440 buck region (v in > v out ) switch d is always on and switch c is always off during this mode. when the internal control voltage, v ci , is above voltage v1, output a begins to switch. during the off time of switch a, synchronous switch b turns on for the remainder of the time. switches a and b will alternate similar to a typical synchronous buck regulator. as the control volt - age increases, the duty cycle of switch a increases until t h e maximum duty cycle of the converter in buck mode reaches d max _ buck , given by: d max _ buck = 100 C d4 sw % where d4 sw = duty cycle % of the four switch range. d 4 sw = (150ns ? f) ? 100 % where f = operating frequency, hz. beyond this point the four switch, or buck/boost region is reached. buck/boost or four switch (v in ~ v out ) when the internal control voltage, v ci , is above voltage v2, switch pair ad remain on for duty cycle d max_buck , and the switch pair ac begins to phase in. as switch pair ac phases in, switch pair bd phases out accordingly. when the v ci voltage reaches the edge of the buck/boost range, at voltage v3, the ac switch pair completely phase out the bd pair, and the boost phase begins at duty cycle d4 sw . figure 2. switch control vs internal control voltage, v ci the input voltage, v in , where the four switch region begins is given by: v in = v out 1? (150ns s f) v the point at which the four switch region ends is given by: v in = v out (1 C d) = v out (1 C 150ns ? f) v boost region (v in < v out ) switch a is always on and switch b is always off dur - ing this mode. when the internal control voltage, v ci , is above voltage v3, switch pair cd will alternately switch to provide a boosted output voltage. this operation is typical to a synchronous boost regulator. the maximum duty cycle of the converter is limited to 75% typical and is reached when v ci is above v4. burst mode operation burst mode operation is when the ic delivers energy to the output until it is regulated and then goes into a sleep mode where the outputs are off and the ic is consuming only 25a. in this mode the output ripple has a variable frequency component that depends upon load current. during the period where the device is delivering energy to the output, the peak current will be equal to 400ma typical and the inductor current will terminate at zero current for each cycle. in this mode the maximum average output current is given by: i out(max)burst 0.1 s v in v out + v in a burst mode operation is user controlled, by driving the mode/sync pin high to enable and low to disable. the peak effciency during burst mode operation is less than the peak effciency during fxed frequency because the part enters full-time 4-switch mode (when servicing the output) with discontinuous inductor current as illus - trated in figures 3 and 4. during burst mode operation, th e control loop is nonlinear and cannot utilize the control voltage from the error amp to determine the control mode, 75% d max boost d min boost d max buck duty cycle 0% v4 (2.05v) v3 (1.65v) boost region buck region buck/boost region v2 (1.55v) v1 (0.9v) 3440 f02 a on, b off pwm cd switches d on, c off pwm ab switches four switch pwm internal control voltage, v ci o peration ltc3440 3440fc
10 for more information www.linear.com/ltc3440 therefore full-time 4-switch mode is required to maintain the buck/boost function. the effciency below 1ma becomes dominated primarily by the quiescent current and n o t the peak effciency. the equation is given by: efficiency burst ( bm) ? i load 25 a + i load where ( bm) is typically 79% during burst mode opera - tion for an esr of the inductor of 50m. for 200m of i n ductor esr, the peak effciency ( bm) drops to 75%. burst mode operation to fixed frequency transient response when transitioning from burst mode operation to fxed frequency, the system exhibits a transient since the modes of operation have changed. for most systems this transient is acceptable, but the application may have stringent input current and/or output voltage requirements that dictate a broad-band voltage loop to minimize the transient. lowering the dc gain of the loop will facilitate the task (10m fb to v c ) at the expense of dc load regulation. type 3 compensation is also recommended to broad band the loop and roll off past the two pole response of the lc of the converter (see closing the feedback loop). 7 v in a 3 sw1 5 gnd 4 sw2 l + ? 6 v out d c 400ma i inductor 0ma 3440 f03 t1 b di dt v in l 7 v in a 3 sw1 5 gnd 4 sw2 l ? + 6 v out d c 400ma i inductor 0ma 3440 f04 t2 b di dt v out l ? figure 3. inductor charge cycle during burst mode operation figure 4. inductor discharge cycle during burst mode operation o peration ltc3440 3440fc
11 for more information www.linear.com/ltc3440 o peration s oft -s t art the soft-start function is combined with shutdown. when the shdn /ss pin is brought above typically 1v, the ic is enabled but the ea duty cycle is clamped from component selection figure 5. soft-start circuitry ? + 9 10 v in error amp 1.22v 15a fb r1 r2 c p1 v c v out 8 shdn/ss c ss 1v enable signal r ss soft-start clamp to pwm comparators chip enable 3440 f05 ? + v ci inductor selection the high frequency operation of the ltc3440 allows the use of small surface mount inductors. the inductor cur - rent ripple is typically set to 20% to 40% of the maximum in ductor current. for a given ripple the inductance terms are given as follows: l vv v fi ripple v h l vv v fi ripple v h in min out in min out max out out in max out out max in max > ( ) > ( ) () () () () () () ? ? ?? ? , ?C ?? ? where f = operating frequency, mhz the v c pin. a detailed diagram of this function is shown in figure 5. the components r ss and c ss provide a slow ramping voltage on the shdn /ss pin to provide a soft-start function. figure 6. recommended component placement. traces carrying high current are direct. trace area at fb and v c pins are kept low. lead length to battery should be kept short 3440 f06 gnd c2 d2 ltc3440 multiple vias l1 r t v c fb shdn/ss v in v out mode/sync sw1 gnd sw2 d1 v in r1 r2 v out c1 1 2 3 4 5 10 9 8 7 6 applications in f or m ation ltc3440 3440fc
12 for more information www.linear.com/ltc3440 applications in f or m ation the output capacitance is usually many times larger in order to handle the transient response of the converter. for a rule of thumb, the ratio of the operating frequency to the unity-gain bandwidth of the converter is the amount the output capacitance will have to increase from the above calculations in order to maintain the desired transient response. the other component of ripple is due to the esr (equiva - lent series resistance) of the output capacitor. low esr c a pacitors should be used to minimize output voltage ripple. for surface mount applications, taiyo yuden ceramic capacitors, avx tps series tantalum capacitors or sanyo poscap are recommended. input capacitor selection since the v in pin is the supply voltage for the ic it is recommended to place at least a 4.7f, low esr bypass capacitor. table 2. capacitor vendor information supplier phone fax web site avx (803) 448-9411 (803) 448-1943 www.avxcorp.com sanyo (619) 661-6322 (619) 661-1055 www.sanyovideo.com taiyo yuden (408) 573-4150 (408) 573-4159 www.t-yuden.com optional schottky diodes to achieve a 1%-2% effciency improvement above 50mw, schottky diodes can be added across synchronous switches b (sw1 to gnd) and d (sw2 to v out ). the schottky diodes will provide a lower voltage drop during the break-before-make time (typically 15ns) of the nmos to pmos transition. general purpose diodes such as a 1n914 are not recommended due to the slow recovery times and will compromise effciency. if desired a large schottky diode, such as an mbrm120t3, can be used from sw2 to v out . a low capacitance schottky diode is recommended from gnd to sw1 such as a phillips pmeg2010ea or e qu ivalent. ripple = allowable inductor current ripple (e.g., 0.2 = 20%) v in(min) = minimum input voltage, v v in(max) = maximum input voltage, v v out = output voltage, v i out(max) = maximum output load current for high effciency, choose an inductor with a high frequen - cy core material, such as ferrite, to reduce core loses. the i n ductor should have low esr (equivalent series resistance) to reduce the i 2 r losses, and must be able to handle the peak inductor current without saturating. molded chokes or chip inductors usually do not have enough core to sup - port the peak inductor currents in the 1a to 2a region. to mi nimize radiated noise, use a toroid, pot core or shielded bobbin inductor. see table 1 for suggested components and table 2 for a list of component suppliers. table 1. inductor vendor information supplier phone fax web site coilcraft (847) 639-6400 (847) 639-1469 www.coilcraft.com coiltronics (561) 241-7876 (561) 241-9339 www.coiltronics.com murata usa: (814) 237-1431 (800) 831-9172 u s a: (814) 238-0490 w w w.murata.com sumida usa: (847) 956-0666 japan: 81(3) 3607-5111 (847) 956-0702 81(3) 3607-5144 w w w.japanlink.com/ sumida output capacitor selection the bulk value of the capacitor is set to reduce the ripple due to charge into the capacitor each cycle. the steady state ripple due to charge is given by: %_ ?C ? ?? % %_ ?C ? ?? ? % () () () () () ripple boost iv v cv f ripple buck iv v cv vf out max out in min out out out max in max out out in max out = () = () 100 100 2 where c out = output flter capacitor, f ltc3440 3440fc
13 for more information www.linear.com/ltc3440 applications in f or m ation output voltage > 4.3v a schottky diode from sw to v out is required for output voltages over 4.3v. the diode must be located as close to the pins as possible in order to reduce the peak voltage on sw2 due to the parasitic lead and trace inductance. input voltage > 4.5v for applications with input voltages above 4.5v which could exhibit an overload or short-circuit condition, a 2/1nf series snubber is required between the sw1 pin and gnd. a schottky diode such as the phillips pmeg2010ea or equivalent from sw1 to v in should also be added as close to the pins as possible. for the higher input voltages v in bypassing becomes more critical, therefore, a ceramic bypass capacitor as close to the v in and gnd pins as possible is also required. operating frequency selection there are several considerations in selecting the oper - ating frequency of the converter. the frst is, what are t h e sensitive frequency bands that cannot tolerate any spectral noise? for example, in products incorporating rf communications, the 455khz if frequency is sensitive to any noise, therefore switching above 600khz is desired. some communications have sensitivity to 1.1mhz and in that case a 2mhz converter frequency may be employed. other considerations are the physical size of the converter and effciency. as the operating frequency goes up, the inductor and flter capacitors go down in value and size. the trade off is in effciency since the switching losses due to gate charge are going up proportional with frequency. additional quiescent current due to the output switches gate charge is given by: buc k: 500e C12 ? v in ? f boos t: 250e C12 ? (v in + v out ) ? f buc k/boost: f ? (750e C12 ? v in + 250e C12 ? v out ) where f = switching frequency closing the feedback loop the ltc3440 incorporates voltage mode pwm control. the control to output gain varies with operation region (buck, boost, buck-boost), but is usually no greater than 15. the output flter exhibits a double pole response is given by: f filter _ pole = 1 2 s l s c out hz (in buck mode) f filter_pole = v in 2 ? v out ? ? l ? c out hz (in boost mode) where l is in henries and c out is the output flter capaci - tor in farads. t h e output flter zero is given by: f filter _ zero = 1 2 s r esr s c out hz where r esr is the capacitor equivalent series resistance. a troublesome feature in boost mode is the right-half plane zero (rhp), and is given by: f rhpz = v in 2 2 s i out s l s v out hz the loop gain is typically rolled off before the rhp zero frequency. a simple type i compensation network can be incorporated to stabilize the loop but at a cost of reduced bandwidth and slower transient response. to ensure proper phase margin, the loop requires to be crossed over a decade before the lc double pole. the unity-gain frequency of the error amplifer with the type i compensation is given by: f ug = 1 2 s r1 s cp1 hz most applications demand an improved transient response to allow a smaller output flter capacitor. to achieve a higher bandwidth, type iii compensation is required. two zeros are required to compensate for the double-pole response. ltc3440 3440fc
14 for more information www.linear.com/ltc3440 short-circuit improvements the ltc3440 is current limited to 2.7a peak to protect the ic from damage. at input voltages above 4.5v a current limit condition may produce undesirable voltages to the ic due to the series inductance of the package, as well figure 8. error amplifer with type iii compensation 1.22v r1 r2 3440 f08 fb 9 v c c p1 c z1 r z v out 10 c p2 ? + error amp figure 7. error amplifer with type i compensation 1.22v r1 r2 3440 f07 fb 9 v c c p1 v out 10 ? + error amp f pole1 1 2 ? ? 32e 3 ? r1 ? c p1 hz which is extremely close to dc f zero1 = 1 2 ? ? r z ? c p1 hz f zero2 = 1 2 ? ? r1 ? c z 1 hz f pole2 = 1 2 ? ? r z ? c p 2 hz as the traces and external components. following the recommendations for output voltage >4.3v and input voltage >4.5v will improve this condition. additional short-circuit protection can be accomplished with some external circuitry. in an overload or short-circuit condition the ltc3440 volt - age loop opens and the error amp control voltage on the v c pin slams to the upper clamp level. this condition forces boost mode operation in order to attempt to provide more output voltage and the ic hits a peak switch current limit of 2.7a. when switch current limit is reached switches b and d turn on for the remainder of the cycle to reverse the volts ttfdpoetpouifjoevdupsmuipvhiuijtqsfwfoutdvssfou run away, this condition produces four switch operation producing a current foldback characteristic and the aver - age input current drops. the ic is trimmed to guarantee gr eater than 1a average input current to meet the maximum load demand, but in a short-circuit or overload condition the foldback characteristic will occur producing higher peak switch currents. to minimize this affect during this condition the following circuits can be utilized. restart circuit for a sustained short-circuit the circuit in figure 9 will force a soft-start condition. the only design constraint is that r2/c2 time constant must be longer than the soft-start components r1/c1 to ensure start-up. figure 9. soft-start reset circuitry for a sustained short-circuit c2 10nf c1 4.7nf r2 1m r1 1m v out v in soft-start so/ss m2 nmos vn2222 m1 nmos vn2222 d1 1n4148 3440 f09 applications in f or m ation ltc3440 3440fc
15 for more information www.linear.com/ltc3440 figure 10. simple input current control utilizing the voltage loop 3-cell to 3.3v at 600ma converter sw1 v in shdn/ss mode/sync r t sw2 v out fb v c gnd 3 7 8 2 1 4 6 9 10 5 ltc3440 l1 4.7h d1 r3 15k r5 10k r1 340k r2 200k 3440 ta03a r t 45.3k f osc = 1.5mhz c1: taiyo yuden jmk212bj106mg c2: taiyo yuden jmk325bj226mm d1, d2: central semiconductor cmdsh2-3 l1: sumida cdr43-4r7m *1 = burst mode operation 0 = fixed frequency c1 10f 3 cells v in = 2.7v to 4.5v * c4 150pf c3 33pf d2 c5 10pf c2 22f v out 3.3v 600ma + output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3440 ta03b 0 1 burst mode operation v in = 2.7v v in = 3.3v f osc = 1.5mhz v in = 4.5v 3-cell to 3.3v effciency input_voltage fb_pin vin_pin q1 2n3906 r1 0.5 c1 10f v1 simple average input current control a simple average current limit circuit is shown in figure 10. once the input current of the ic is above ap - p roximately 1a, q1 will start sourcing current into the fb p i n and lower the output voltage to maintain the average input current. since the voltage loop is utilized to perform average current limit, the voltage control loop is main - tained and the v c voltage does not slam. the averaging function of current comes from the fact that voltage loop compensation is also used with this circuit. applications in f or m ation t y pical applications ltc3440 3440fc
16 for more information www.linear.com/ltc3440 t y pical applications low profle (<1.1mm) li-ion to 3.3v at 200ma converter sw1 v in shdn/ss mode/sync r t sw2 v out fb v c gnd 3 7 8 2 1 4 6 9 10 5 ltc3440 l1 4.7h r1 340k r2 200k r3 15k 3440 ta04a r t 30.1k c1: taiyo yuden jmk212bj475mg c2: taiyo yuden jmk212bj475mg l1: coilcraft lpo1704-472m *1 = burst mode operation 0 = fixed frequency f osc = 2mhz c1 4.7f li-ion v in = 2.5v to 4.2v * + c4 1.5nf c2 4.7f v out 3.3v 200ma output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3440 ta04b 0 1 burst mode operation v in = 2.5v v in = 3.3v v in = 4.2v effciency 3-cell to 5v boost converter with output disconnect sw1 v in shdn/ss mode/sync r t sw2 v out fb v c gnd 3 7 8 2 1 4 6 9 10 5 ltc3440 l1 10h r1 619k r2 200k 3440 ta06a r t 60.4k c1: taiyo yuden jmk212bj106mg c2: taiyo yuden jmk325bj226mm d1: on semiconductor mbrm120t3 l1: sumida cdrh4d28-100 *1 = burst mode operation 0 = fixed frequency ** locate components as close to ic as possible c1 10f c3 0.1f 3 cells r4 1m v in = 2.7v to 4.5v * sd c4 1.5nf 15k f osc = 1mhz c2** 22f v out 5v 300ma + d1** output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3440 ta06b 0 1 burst mode operation v in = 2.7v f osc = 1mhz v in = 3.6v v in = 4.5v 3-cell to 5v boost effciency ltc3440 3440fc
17 for more information www.linear.com/ltc3440 t y pical applications sw1 v in shdn/ss mode/sync r t sw2 v out fb v c gnd 3 7 8 2 1 4 6 9 10 5 ltc3440 l1 3.3h r1 340k r5 10k r2 200k r3 15k d1** 3440 ta07a r t 30.1k c1, c2: taiyo yuden jmk212bj106mm d1: on semiconductor mbrm120t3 l1: sumida cdrh4d28-3r3 *1 = burst mode operation 0 = fixed frequency ** locate components as close to ic as possible c1 10f f osc = 2mhz li-ion v in = 2.5v to 4.2v * + c4 150pf c5 10pf c2** 10f v out 0.4v to 5v c3 33pf v out = 3.3v C 1.7v ? (v dac ? 1.22v) r6 200k dac wcdma power amp power supply with dynamic voltage control effciency of the wcdma power amp power supply input voltage (v) 2.5 efficiency (%) 92 96 100 4.5 3440 ta07b 88 84 90 94 98 86 82 80 3 3.5 4 5 v out = 3.4v i out = 100ma i out = 250ma i out = 600ma sw1 v in shdn/ss mode/sync r t sw2 v out fb v c gnd 3 7 8 2 1 4 6 9 10 5 ltc3440 l1 10h r5 24k 3440 ta08 r t 60.4k r s 0.1 r4 1k c1: taiyo yuden jmk212bj106mg c2: taiyo yuden jmk325bj226mm l1: sumida cdrh-4d28-100 *1 = burst mode operation 0 = fixed frequency c1 10f v in 2.5v to 5.5v usb/pcmcia power 500ma max * v out 3.6v 2a (pulsed) c5 10nf r6 130k r1 392k r2 200k ? + 1/2 lt1490a 2n3906 ? + 1/2 lt1490a 1n914 c6 to c9 470f 4 1.22 ? r4 r5 ? r s i currentlimit = gsm modem powered from usb or pcmcia with 500ma input current limit ltc3440 3440fc
18 for more information www.linear.com/ltc3440 dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc pin 1 notch r = 0.20 or 0.35 45 chamfer msop (ms) 0213 rev f seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max detail ?a? 0.53 0.152 (.021 .006) 0.254 (.010) 0 ? 6 typ detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 0.1016 0.0508 (.004 .002) ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661 rev f) p ackage description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. ltc3440 3440fc
19 for more information www.linear.com/ltc3440 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision histor y rev date description page number c 8/14 modifed flter pole equation in closing the feedback loop section 13 (revision history begins at rev c) ltc3440 3440fc
20 for more information www.linear.com/ltc3440 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2001 lt 0814 rev c ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3440 r elate d p arts ty pical a pplication part number description comments lt1613 550ma(i sw ), 1.4mhz, high effciency step-up dc/dc converter 90% effciency, v in : 0.9v to 10v, v out(min) = 34v, i q = 3ma, i sd = <1a, thinsot? package lt1618 1.5a(i sw ), 1.25mhz, high effciency step-up dc/ dc converter 90% effciency, v in : 1.6v to 18v, v out(min) = 35v, i q = 1.8ma, i sd = <1a, ms10 package ltc1877 600ma(i out ), 550khz, synchronous step-down dc/dc converter 95% effciency, v in : 2.7v to 10v, v out(min) = 0.8v, i q = 10a, i sd = <1a, ms8 package ltc1878 600ma(i out ), 550khz, synchronous step-down dc/dc converter 95% effciency, v in : 2.7v to 6v, v out(min) = 0.8v, i q = 10a, i sd = <1a, ms8 package ltc1879 1.2a(i out ), 550khz, synchronous step-down dc/ dc converter 95% effciency, v in : 2.7v to 10v, v out(min) = 0.8v, i q = 15a, i sd = <1a, tssop16 package lt1961 1.5a(i sw ), 1.25mhz, high effciency step-up dc/ dc converter 90% effciency, v in : 3v to 25v, v out(min) = 35v, i q = 0.9ma, i sd = 6a, ms8e package ltc3400/ltc3400b 600ma(i sw ), 1.2mhz, synchronous step-up dc/ dc converter 92% effciency, v in : 0.85v to 5v, v out(min) = 5v, i q = 19a/300a, i sd = <1a, thinsot package ltc3401 1a(i sw ), 3mhz, synchronous step-up dc/dc converter 9 7 % effciency, v in : 0.5v to 5v, v out(min) = 6v, i q = 38a, i sd = <1a, ms10 package ltc3402 2a(i sw ), 3mhz, synchronous step-up dc/dc converter 9 7 % effciency, v in : 0.5v to 5v, v out(min) = 6v, i q = 38a, i sd = <1a, ms10 package ltc3405/ltc3405a 300ma(i out ), 1.5mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.7v to 6v, v out(min) = 0.8v, i q = 20a, i sd = <1a, thinsot package ltc3406/ltc3406b 600ma(i out ), 1.5mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 20a, i sd = <1a, thinsot package ltc3411 1.25a(i out ), 4mhz, synchronous step-down dc/ dc converter 95% effciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd = <1a, ms10 package ltc3412 2.5a(i out ), 4mhz, synchronous step-down dc/ dc converter 95% effciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd = <1a, tssop16e package ltc3441/ltc3443 1.2a(i out ), 1mhz/0.6mhz, micropower synchronous buck-boost dc/dc converter 95% effciency, v in : 2.4v to 5.5v, v out(min) : 2.4v to 5.25v, i q = 25a, i sd = <1a, dfn package effciency 3440 ta05 output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.1 10 100 1000 1.0 v in = 4.2v v in = 3.3v burst mode operation li-ion to 3.3v at 600ma buck-boost converter sw1 v in shdn/ss mode/sync r t sw2 v out fb v c gnd 3 7 8 2 1 4 6 9 10 5 ltc3440 l1 10h r1 340k r2 200k r3 15k 3440 ta01 r t 60.4k c1: taiyo yuden jmk212bj106mg c2: taiyo yuden jmk325bj226mm l1: sumida cdrh6d38-100 *1 = burst mode operation 0 = fixed frequency c1 10f li-ion v in = 2.7v to 4.2v * + c5 1.5nf c2 22f v out 3.3v 600ma ltc3440 3440fc

▲Up To Search▲

Price & Availability of LTC3440-15

	To Download LTC3440-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .