View LSM6DS33_9053255.PDF datasheet online --- IC-ON-LINE

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this is information on a product in full production. october 2015 docid027423 rev 4 1/77 LSM6DS33 inemo inertial module: always-on 3d accelerometer and 3d gyroscope datasheet - production data features ? power consumption: 0.9 ma in combo normal mode and 1.25 ma in combo high-performance mode up to 1.6 khz. ? ?always-on? experience with low power consumption for both accelerometer and gyroscope ? smart fifo up to 8 kbyte based on features set ? compliant with android k and l ? 2/4/8/16 g full scale ? 125/245/500/1000/2000 dps full scale ? analog supply voltage: 1.71 v to 3.6 v ? independent ios supply (1.62 v) ? compact footprint, 3 mm x 3 mm x 0.86 mm ? spi/i 2 c serial interface with main processor data synchronization feature ? embedded temperature sensor ? ecopack ? , rohs and ?green? compliant applications ? pedometer, step detector and step counter ? significant motion and tilt functions ? indoor navigation ? tap and double-tap detection ? iot and connected devices ? intelligent power saving for handheld devices ? vibration monitoring and compensation ? free-fall detection ? 6d orientation detection description the LSM6DS33 is a system-in-package featuring a 3d digital accelerometer and a 3d digital gyroscope performing at 1.25 ma (up to 1.6 khz odr) in high- performance mode and enabling always-on low-power features for an optimal motion experience for the consumer. the LSM6DS33 supports main os requirements, offering real, virtual and batch sensors with 8 kbyte for dynamic data batching. st?s family of mems sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. the various sensing elements are manufactured using specialized micromachining processes, while the ic interfaces are developed using cmos technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element. the LSM6DS33 has a full-scale acceleration range of 2/4/8/16 g and an angular rate range of 125/245/500/1000/2000 dps. high robustness to mechanical shock makes the LSM6DS33 the preferred choice of system designers for the creation and manufacturing of reliable products. the LSM6DS33 is available in a plastic land grid array (lga) package. lga-16l (3 x 3 x 0.86 mm) typ. table 1. device summary part number temp. range [c] package packing LSM6DS33 -40 to +85 lga-16l (3 x 3 x 0.86 mm) tray LSM6DS33tr -40 to +85 tape & reel www.st.com
contents LSM6DS33 2/77 docid027423 rev 4 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 embedded low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 tilt detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4.2 i 2 c - inter-ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6.2 zero-g and zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 accelerometer power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4.3 continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4.4 continuous-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.5 bypass-to-continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.6 fifo reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.7 filter block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
docid027423 rev 4 3/77 LSM6DS33 contents 77 6.1 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.1 i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 LSM6DS33 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2 pin compatibility with lsm6ds0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1 func_cfg_access (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2 fifo_ctrl1 (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.3 fifo_ctrl2 (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.4 fifo_ctrl3 (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.5 fifo_ctrl4 (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.6 fifo_ctrl5 (0ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.7 orient_cfg_g (0bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.8 int1_ctrl (0dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.9 int2_ctrl (0eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.10 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.11 ctrl1_xl (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.12 ctrl2_g (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.13 ctrl3_c (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.14 ctrl4_c (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.15 ctrl5_c (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.16 ctrl6_c (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.17 ctrl7_g (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.18 ctrl8_xl (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.19 ctrl9_xl (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.20 ctrl10_c (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
contents LSM6DS33 4/77 docid027423 rev 4 9.21 wake_up_src (1bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.22 tap_src (1ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.23 d6d_src (1dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.24 status_reg (1eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.25 out_temp_l (20h), out_temp(21h) . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.26 outx_l_g (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.27 outx_h_g (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.28 outy_l_g (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.29 outy_h_g (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.30 outz_l_g (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.31 outz_h_g (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.32 outx_l_xl (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.33 outx_h_xl (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.34 outy_l_xl (2ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.35 outy_h_xl (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.36 outz_l_xl (2ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.37 outz_h_xl (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.38 fifo_status1 (3ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.39 fifo_status2 (3bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.40 fifo_status3 (3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.41 fifo_status4 (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.42 fifo_data_out_l (3eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.43 fifo_data_out_h (3fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.44 timestamp0_reg (40h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.45 timestamp1_reg (41h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.46 timestamp2_reg (42h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.47 step_timestamp_l (49h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.48 step_timestamp_h (4ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.49 step_counter_l (4bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.50 step_counter_h (4ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.51 func_src (53h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.52 tap_cfg (58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.53 tap_ths_6d (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
docid027423 rev 4 5/77 LSM6DS33 contents 77 9.54 int_dur2 (5ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.55 wake_up_ths (5bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.56 wake_up_dur (5ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.57 free_fall (5dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.58 md1_cfg (5eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.59 md2_cfg (5fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10 embedded functions register mapping . . . . . . . . . . . . . . . . . . . . . . . . . 69 11 embedded functions registers description . . . . . . . . . . . . . . . . . . . . . 70 11.1 pedo_ths_reg (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.2 sm_ths (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.3 pedo_deb_reg (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.4 step_count_delta (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 13 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.1 lga-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.2 lga-16 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
list of tables LSM6DS33 6/77 docid027423 rev 4 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 table 6. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. i 2 c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10. i 2 c terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 30 table 15. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 30 table 16. registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 17. func_cfg_access register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 18. func_cfg_access register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 19. fifo_ctrl1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 20. fifo_ctrl1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 21. fifo_ctrl2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 22. fifo_ctrl2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 23. fifo_ctrl3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 24. fifo_ctrl3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 25. gyro fifo decimation setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 26. accelerometer fifo decimation setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 27. fifo_ctrl4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 28. fifo_ctrl4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 29. third fifo data set decimation setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 table 30. fifo_ctrl5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 31. fifo_ctrl5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 32. fifo odr selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 33. fifo mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 34. orient_cfg_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 35. orient_cfg_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 36. settings for orientation of axes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 37. int1_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 38. int1_ctrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 39. int2_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 40. int2_ctrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 41. who_am_i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 42. ctrl1_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 43. ctrl1_xl register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 44. accelerometer odr register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 table 45. bw and odr (high-performance mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 46. ctrl2_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 47. ctrl2_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 48. gyroscope odr configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
docid027423 rev 4 7/77 LSM6DS33 list of tables 77 table 49. ctrl3_c register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 50. ctrl3_c register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 51. ctrl4_c register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 52. ctrl4_c register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 53. ctrl5_c register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 54. ctrl5_c register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 55. output registers rounding pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 56. angular rate sensor self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 57. linear acceleration sensor self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 58. ctrl6_c register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 59. ctrl6_c register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 60. ctrl7_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 61. ctrl7_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 62. gyroscope high-pass filter mode configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 63. ctrl8_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 64. ctrl8_xl register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 65. accelerometer slope and high-pass filter selection and cutoff frequency . . . . . . . . . . . . . . 53 table 66. ctrl9_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 67. ctrl9_xl register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 68. ctrl10_c register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 69. ctrl10_c register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 70. wake_up_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 71. wake_up_src register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 72. tap_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 73. tap_src register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 74. d6d_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 75. d6d_src register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 76. status_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 77. status_reg register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 78. out_temp_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 79. out_temp_h register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 80. out_temp register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 81. outx_l_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 82. outx_l_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 83. outx_h_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 84. outx_h_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 85. outy_l_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 86. outy_l_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 87. outy_h_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 88. outy_h_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 89. outz_l_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 90. outz_l_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 91. outz_h_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 92. outz_h_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 93. outx_l_xl register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 94. outx_l_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 95. outx_h_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 96. outx_h_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 97. outy_l_xl register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 98. outy_l_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 99. outy_h_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 100. outy_h_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
list of tables LSM6DS33 8/77 docid027423 rev 4 table 101. outz_l_xl register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 102. outz_l_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 103. outz_h_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 104. outz_h_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 105. fifo_status1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 106. fifo_status1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 107. fifo_status2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 108. fifo_status2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 109. fifo_status3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 110. fifo_status3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 111. fifo_status4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 112. fifo_status4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 113. fifo_data_out_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 114. fifo_data_out_l register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 115. fifo_data_out_h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 116. fifo_data_out_h register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 117. timestamp0_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 118. timestamp0_reg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 119. timestamp1_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 120. timestamp1_reg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 121. timestamp2_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 122. timestamp2_reg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 123. step_timestamp_l register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 table 124. step_timestamp_l register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 125. step_timestamp_h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 126. step_timestamp_h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 127. step_counter_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 128. step_counter_l register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 129. step_counter_h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 table 130. step_counter_h register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 131. func_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 132. func_src register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 133. tap_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 134. tap_cfg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 135. tap_ths_6d register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 136. tap_ths_6d register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 137. threshold for d4d/d6d function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 138. int_dur2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 139. int_dur2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 140. wake_up_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 141. wake_up_ths register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 142. wake_up_dur register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 143. wake_up_dur register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 144. free_fall register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 145. free_fall register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 146. threshold for free-fall function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 147. md1_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 148. md1_cfg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 149. md2_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 150. md2_cfg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 151. registers address map - embedded functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 152. pedo_ths_reg register default values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
docid027423 rev 4 9/77 LSM6DS33 list of tables 77 table 153. pedo_ths_reg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 154. sm_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 155. sm_ths register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 156. pedo_deb_reg register default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 157. pedo_deb_reg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 158. step_count_delta register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 159. step_count_delta register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 160. reel dimensions for carrier tape of lga-16 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 161. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
list of figures LSM6DS33 10/77 docid027423 rev 4 list of figures figure 1. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 3. i 2 c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4. accelerometer chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 5. accelerometer composite filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 6. gyroscope chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 7. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 8. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 9. multiple byte spi read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 10. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11. multiple byte spi write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 12. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 13. LSM6DS33 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 14. schematic 1 (pin 15 connected to gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 15. schematic 2 (pin 15 connected to vdd, vdd_io = vdd). . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 16. lga 3x3x0.86 16l package outline and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 17. carrier tape information for lga-16 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 18. lga-16 package orientation in carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 19. reel information for carrier tape of lga-16 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
docid027423 rev 4 11/77 LSM6DS33 overview 77 1 overview the LSM6DS33 is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis digital gyroscope. the integrated power-efficient modes are able to reduce the power consumption down to 1.25 ma in high-performance mode, combining always-on low-power features with superior sensing precision for an optimal motion experience for the consumer thanks to ultra-low noise performance for both the gyroscope and accelerometer. the LSM6DS33 delivers best-in-class motion sensing that can detect orientation and gestures in order to empower application developers and consumers with features and capabilities that are more sophisticated than simply orienting their devices to portrait and landscape mode. the event-detection interrupts enable efficient and reliable motion tracking and contextual awareness, implementing hardware recognition of free-fall events, 6d orientation, tap and double-tap sensing, activity or inactivity, and wakeup events. the LSM6DS33 supports main os requirements, offering real, virtual and batch mode sensors. in addition, the LSM6DS33 can efficiently run the sensor-related features specified in android, saving power and enabling faster reaction time. in particular, the LSM6DS33 has been designed to implement hardware features such as significant motion, tilt, pedometer functions, and time stamping. up to 8 kbyte of fifo with dynamic allocation of significant data (i.e. sensors, temperature, step counter and time stamp) allows overall power saving of the system. like the entire portfolio of mems sensor modules, the LSM6DS33 leverages the robust and mature in-house manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. the various sensing elements are manufactured using specialized micromachining processes, while the ic interfaces are developed using cmos technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element. the LSM6DS33 is available in a small plastic land grid array (lga) package of 3 x 3 x 0.86 mm to address ultra-compact solutions.
embedded low-power features LSM6DS33 12/77 docid027423 rev 4 2 embedded low-power features the LSM6DS33 has been designed to be fully compliant with android, featuring the following on-chip functions: ? 8 kbyte data buffering ? 100% efficiency with flexible configurations and partitioning ? possibility to store time stamp ? event-detection interrupts (fully configurable): ? free-fall ? wakeup ? 6d orientation ? tap and double-tap sensing ? activity / inactivity recognition ? specific ip blocks with negligible power consumption and high-performance: ? pedometer functions: step detector and step counters ? tilt (android compliant, refer to section 2.1: tilt detection for additional info ? significant motion (android compliant) 2.1 tilt detection the tilt function helps to detect activity change and has been implemented in hardware using only the accelerometer to achieve both the targets of ultra-low power consumption and robustness during the short duration of dynamic accelerations. it is based on a trigger of an event each time the device's tilt changes by an angle greater than 35 degrees from the start position. the tilt function can be used with different scenarios, for example: a) trigger when phone is in a front pants pocket and the user goes from sitting to standing or standing to sitting; b) doesn?t trigger when phone is in a front pants pocket and the user is walking, running or going upstairs.
docid027423 rev 4 13/77 LSM6DS33 pin description 77 3 pin description figure 1. pin connections in the LSM6DS33 an i 2 c slave interface or spi (3- and 4-wire) serial interface is available. 9'',2 %27720 9,(: 6&/ 6'$ 6'2 &6 5(6 ,17 ,17 9'' 5(6 1& *1' *1' 5(6 5(6 5(6 7239,(: ',5(&7,212)7+( '(7(&7$%/( $1*8/$55$7(6 ; = ; < 7239,(: ',5(&7,212)7+( '(7(&7$%/( $&&(/(5$7,216 < ; = ? ? ?
pin description LSM6DS33 14/77 docid027423 rev 4 table 2. pin description pin# name function 1 vddio (1) 1. recommended 100 nf filter capacitor. power supply for i/o pins 2 scl i 2 c serial clock (scl) spi serial port clock (spc) 3 sda i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 4 sdo/sa0 spi 4-wire interface serial data output (sdo) i 2 c least significant bit of the device address (sa0) 5cs i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 6 int2 programmable interrupt 7 int1 programmable interrupt 8 res reserved, connect to gnd 9 res reserved, connect to gnd 10 res reserved, connect to gnd 11 res reserved, connect to gnd 12 gnd 0 v supply 13 gnd 0 v supply 14 nc leave unconnected 15 res reserved, connect to gnd 16 vdd (2) 2. recommended 100 nf capacitor. power supply
docid027423 rev 4 15/77 LSM6DS33 module specifications 77 4 module specifications 4.1 mechanical characteristics @ vdd = 1.8 v, t = 25 c unless otherwise noted. table 3. mechanical characteristics symbol parameter test conditions min. typ. (1) max. unit la_fs linear acceleration measurement range 2 g 4 8 16 g_fs angular rate measurement range 125 dps 245 500 1000 2000 la_so linear acceleration sensitivity fs = 2 0.061 m g /lsb fs = 4 0.122 fs = 8 0.244 fs = 16 0.488 g_so angular rate sensitivity fs = 125 4.375 mdps/lsb fs = 245 8.75 fs = 500 17.50 fs = 1000 35 fs = 2000 70 la_sodr linear acceleration sensitivity change vs. temperature (2) from -40 to +85 delta from t=25 1 % g_sodr angular rate sensitivity change vs. temperature (2) from -40 to +85 delta from t=25 1.5 % la_tyoff linear acceleration typical zero- g level offset accuracy (3) 40 m g g_tyoff angular rate typical zero-rate level (3) 10 dps la_offdr linear acceleration zero- g level change vs. temperature (2) 0.5 m g/ c g_offdr angular rate typical zero-rate level change vs. temperature (2) 0.05 dps/c rn rate noise density 7 mdps/ ? hz an acceleration noise density fs= 2 g odr = 104 hz 90 g / ? hz
module specifications LSM6DS33 16/77 docid027423 rev 4 la_odr linear acceleration output data rate 13 26 52 104 208 416 833 1666 3332 6664 hz g_odr angular rate output data rate 13 26 52 104 208 416 833 1666 top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. measurements are performed in a uniform temperature setup. 3. values after soldering . table 3. mechanical characteristics (continued) symbol parameter test conditions min. typ. (1) max. unit
docid027423 rev 4 17/77 LSM6DS33 module specifications 77 4.2 electrical characteristics @ vdd = 1.8 v, t = 25 c unless otherwise noted. table 4. electrical characteristics for details related to the LSM6DS33 operating modes, refer to 5.2: gyroscope power modes and 5.3: accelerometer power modes . symbol parameter test conditions min. typ. (1) 1. typical specifications are not guaranteed. max. unit vdd supply voltage 1.71 1.8 3.6 v vdd_io power supply for i/o 1.62 vdd+0.1 v iddhp gyroscope and accelerometer in high-performance mode up to odr = 1.6 khz 1.25 ma iddnm gyroscope and accelerometer in normal mode odr = 208 hz 0.9 ma iddlp gyroscope and accelerometer in low-power mode odr = 13 hz 0.42 ma la_iddhp accelerometer current consumption in high-performance mode up to odr = 1.6 khz 240 a la_iddnm accelerometer current consumption in normal mode odr = 104 hz 70 a la_iddlm accelerometer current consumption in low-power mode odr = 13 hz 24 a iddpd gyroscope and accelerometer in power down 6 a top operating temperature range -40 +85 c
module specifications LSM6DS33 18/77 docid027423 rev 4 4.3 temperature sensor characteristics @ vdd = 1.8 v, t = 25 c unless otherwise noted. table 5. temperature sensor characteristics symbol parameter test condition min. typ. (1) 1. typical specifications are not guaranteed. max. unit todr temperature refresh rate 52 hz toff temperature offset (2) 2. the output of the temperature sensor is 0 lsb (typ.) at 25 c. -15 +15 c tsen temperature sensitivity 16 lsb/c tst temperature stabilization time (3) 3. time from power on bit to valid data based on characterization data. 500 s t_adc_res temperature adc resolution 12 bit top operating temperature range -40 +85 c
docid027423 rev 4 19/77 LSM6DS33 module specifications 77 4.4 communication interface characteristics 4.4.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 2. spi slave timing diagram note: measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output ports. table 6. spi slave timing values symbol parameter value (1) unit min max t c(spc) spi clock cycle 100 ns f c(spc) spi clock frequency 10 mhz t su(cs) cs setup time 5 ns t h(cs) cs hold time 20 t su(si) sdi input setup time 5 t h(si) sdi input hold time 15 t v(so) sdo valid output time 50 t h(so) sdo output hold time 5 t dis(so) sdo output disable time 50 1. values are guaranteed at 10 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results, not tested in production
module specifications LSM6DS33 20/77 docid027423 rev 4 4.4.2 i 2 c - inter-ic control interface subject to general operating conditions for vdd and top. figure 3. i 2 c slave timing diagram note: measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports. table 7. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min max min max f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3.45 0 0.9 s t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production. 6' $ 6&/ w vx63 w z6&// w vx6'$ w vx65 w k67 w z6&/+ w k6'$ w z6365 67$57 5(3($ 7(' 67$ 57 6723 67$ 57
docid027423 rev 4 21/77 LSM6DS33 module specifications 77 4.5 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v. table 8. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v t stg storage temperature range -40 to +125 c sg acceleration g for 0.1 ms 10,000 g esd electrostatic discharge protection (hbm) 2 kv vin input voltage on any control pin (including cs, scl/spc, sda/sdi/sdo, sdo/sa0) 0.3 to vdd_io +0.3 v this device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. this device is sensitive to electrostatic discharge (esd), improper handling can cause permanent damage to the part.
module specifications LSM6DS33 22/77 docid027423 rev 4 4.6 terminology 4.6.1 sensitivity linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. because the sensor can measure dc accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and over time. the sensitivity tolerance describes the range of sensitivities of a large number of sensors. an angular rate gyroscope is device that produces a positive-going digital output for counterclockwise rotation around the axis considered. sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. this value changes very little over temperature and time. 4.6.2 zero- g and zero-rate level linear acceleration zero- g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady state on a horizontal surface will measure 0 g on both the x-axis and y-axis, whereas the z-axis will measure 1 g . ideally, the output is in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as 2?s complement number). a deviation from the ideal value in this case is called zero- g offset. offset is to some extent a result of stress to mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?linear acceleration zero- g level change vs. temperature? in table 3 . the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a group of sensors. zero-rate level describes the actual output signal if there is no angular rate present. the zero-rate level of precise mems sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. this value changes very little over temperature and time.
docid027423 rev 4 23/77 LSM6DS33 functionality 77 5 functionality 5.1 operating modes the LSM6DS33 has three operating modes available: ? only accelerometer active and gyroscope in power-down ? only gyroscope active and accelerometer in power-down ? both accelerometer and gyroscope sensors active with independent odr the accelerometer is activated from power down by writing odr_xl[3:0] in ctrl1_xl (10h) while the gyroscope is activated from power-down by writing odr_g[3:0] in ctrl2_g (11h) . for combo mode the odrs are totally independent. 5.2 gyroscope power modes in the LSM6DS33, the gyroscope can be configured in four different operating modes: power-down, low-power, normal mode and high-performance mode. the operating mode selected depends on the value of the g_hm_mode bit in ctrl7_g (16h) . if g_hm_mode is set to ?0?, high-performance mode is valid for all odrs (from 13 hz up to 1.6 khz). to enable the low-power and normal mode, the g_hm_mode bit has to be set to ?1?. low- power mode is available for lower odr (13, 26, 52 hz) while normal mode is available for odrs equal to 104 and 208 hz. 5.3 accelerometer power modes in the LSM6DS33, the accelerometer can be configured in four different operating modes: power-down, low-power, normal mode and high-performance mode. the operating mode selected depends on the value of the xl_hm_mode bit in ctrl6_c (15h) . if xl_hm_mode is set to ?0?, high-performance mode is valid for all odrs (from 13 hz up to 6.66 khz). to enable the low-power and normal mode, the xl_hm_mode bit has to be set to ?1?. low- power mode is available for lower odrs (13, 26, 52 hz) while normal mode is available for odrs equal to 104 and 208 hz. 5.4 fifo the presence of a fifo allows consistent power saving for the system since the host processor does not need continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the fifo. LSM6DS33 embeds 8 kbytes data fifo to store the following data: ? gyroscope ? accelerometer ? step counter and time stamp ? temperature
functionality LSM6DS33 24/77 docid027423 rev 4 writing data in the fifo can be configured to be triggered by the: - accelerometer/gyroscope data-ready signal; in which case the odr must be lower than or equal to both the accelerometer and gyroscope odrs; - step detection signal. in addition, each data can be stored at a decimated data rate compared to fifo odr and it is configurable by the user, setting the registers fifo_ctrl3 (08h) and fifo_ctrl4 (09h) . the available decimation factors are 2, 3, 4, 8, 16, 32. programmable fifo threshold can be set in fifo_ctrl1 (06h) and fifo_ctrl2 (07h) using the fth [11:0] bits. to monitor the fifo status, dedicated registers ( fifo_status1 (3ah) , fifo_status2 (3bh) , fifo_status3 (3ch) , fifo_status4 (3dh) ) can be read to detect fifo overrun events, fifo full status, fifo empty status, fifo threshold status and the number of unread samples stored in the fifo. to generate dedicated interrupts on the int1 and int2 pads of these status events, the configuration can be set in int1_ctrl (0dh) and int2_ctrl (0eh) . fifo buffer can be configured according to five different modes: ? bypass mode ? fifo mode ? continuous mode ? continuous-to-fifo mode ? bypass-to-continuous mode each mode is selected by the fifo_mode_[2:0] in fifo_ctrl5 (0ah) register. to guarantee the correct acquisition of data during the switching into and out of fifo mode, the first sample acquired must be discarded. 5.4.1 bypass mode in bypass mode ( fifo_ctrl5 (0ah) (fifo_mode_[2:0] = 000), the fifo is not operational and it remains empty. bypass mode is also used to reset the fifo when in fifo mode. 5.4.2 fifo mode in fifo mode ( fifo_ctrl5 (0ah) (fifo_mode_[2:0] = 001) data from the output channels are stored in the fifo until it is full. to reset fifo content, bypass mode should be selected by writing fifo_ctrl5 (0ah) (fifo_mode_[2:0]) to '000' after this reset command, it is possible to restart fifo mode by writing fifo_ctrl5 (0ah) (fifo_mode_[2:0]) to '001'. fifo buffer memorizes up to 4096 samples of 16 bits each but the depth of the fifo can be resized by setting the fth [11:0] bits in fifo_ctrl1 (06h) and fifo_ctrl2 (07h) . if the stop_on_fth bit in ctrl4_c (13h) is set to '1', fifo depth is limited up to fth [11:0] bits in fifo_ctrl1 (06h) and fifo_ctrl2 (07h) . 5.4.3 continuous mode continuous mode ( fifo_ctrl5 (0ah) (fifo_mode_[2:0] = 110) provides a continuous fifo update: as new data arrives, the older data is discarded.
docid027423 rev 4 25/77 LSM6DS33 functionality 77 a fifo threshold flag fifo_status2 (3bh) (fth) is asserted when the number of unread samples in fifo is greater than or equal to fifo_ctrl1 (06h) and fifo_ctrl2 (07h) (fth [11:0]). it is possible to route fifo_status2 (3bh) (fth) to the int1 pin by writing in register int1_ctrl (0dh) (int1_fth) = ?1? or to the int2 pin by writing in register int2_ctrl (0eh) (int2_fth) = ?1?. a full-flag interrupt can be enabled, int1_ctrl (0dh) (int_ full_flag) = '1', in order to indicate fifo saturation and eventually read its content all at once. if an overrun occurs, at least one of the oldest samples in fifo has been overwritten and the over_run flag in fifo_status2 (3bh) is asserted. in order to empty the fifo before it is full, it is also possible to pull from fifo the number of unread samples available in fifo_status1 (3ah) and fifo_status2 (3bh) (diff_fifo[11:0]). 5.4.4 continuous-to-fifo mode in continuous-to-fifo mode ( fifo_ctrl5 (0ah) (fifo_mode_[2:0] = 011), fifo behavior changes according to the trigger event detected in one of the following interrupt registers func_src (53h) , tap_src (1ch) , wake_up_src (1bh) and d6d_src (1dh) . when the selected trigger bit is equal to '1', fifo operates in fifo mode. when the selected trigger bit is equal to '0', fifo operates in continuous mode. 5.4.5 bypass-to-continuous mode in bypass-to-continuous mode ( fifo_ctrl5 (0ah) (fifo_mode_[2:0] = '100'), data measurement storage inside fifo operates in continuous mode when selected triggers in one of the following interrupt registers func_src (53h) , tap_src (1ch) , wake_up_src (1bh) and d6d_src (1dh) are equal to '1', otherwise fifo content is reset (bypass mode). 5.4.6 fifo reading procedure the data stored in fifo are accessible from dedicated registers ( fifo_data_out_l (3eh) and fifo_data_out_h (3fh) ) and each fifo sample is composed of 16 bits. all fifo status registers ( fifo_status1 (3ah) , fifo_status2 (3bh) , fifo_status3 (3ch) , fifo_status4 (3dh) ) can be read at the start of a reading operation, minimizing the intervention of the application processor. saving data in the fifo buffer is organized in four fifo data sets consisting of 6 bytes each: the 1 st fifo data set is reserved for gyroscope data; the 2 nd fifo data set is reserved for accelerometer data;
functionality LSM6DS33 26/77 docid027423 rev 4 5.4.7 filter block diagrams figure 4. accelerometer chain figure 5. accelerometer composite filter $'& %:b;/>@ 'ljlwdo /3)lowhu $qdorj $qwldoldvlqj /3)lowhu 2'5b;/>@ &rpsrvlwh )lowhu /3) 6/23( ),/7(5 'ljlwdo /3)lowhu 'ljlwdo +3)lowhu 6/23(b)'6 25 )81&b(1 +3&)b;/>@ /3)b;/b(1 +3b6/23(b;/b(1 ;/ 2xwsxw 5hj ),)2 :dnhxs '' 6/23(b)'6 /2:b3$66b21b' )uhhidoo $qgurlg ixqfwlrqv $fwlylw\ ,qdfwlylw\ 6'7ds 6/23(b)'6 25 )81&b(1 /3) /3)b;/b(1 +3b6/23(b;/b(1 /3)b;/b(1 +3b6/23(b;/b(1
docid027423 rev 4 27/77 LSM6DS33 functionality 77 figure 6. gyroscope chain $'& 'ljlwdo +3)lowhu +3b*b(1 /3)lowhu $qdorj $qwldoldvlqj /3)lowhu 2'5b*>@
digital interfaces LSM6DS33 28/77 docid027423 rev 4 6 digital interfaces the registers embedded inside the LSM6DS33 may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pins. to select/exploit the i 2 c interface, the cs line must be tied high (i.e connected to vdd_io). 6.1 i 2 c serial interface the LSM6DS33 i 2 c is a bus slave. the i 2 c is employed to write the data to the registers, whose content can also be read back. the relevant i 2 c terminology is provided in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both the lines must be connected to vdd_io through external pull-up resistors. when the bus is free, both the lines are high. the i 2 c interface is implemeted with fast mode (400 khz) i 2 c standards as well as with the standard mode. in order to disable the i 2 c block, (i2c_disable) = 1 must be written in ctrl4_c (13h) . table 9. serial interface pin description pin name pin description cs spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) scl/spc i 2 c serial clock (scl) spi serial port clock (spc) sda/sdi/sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo/sa0 spi serial data output (sdo) i 2 c less significant bit of the device address table 10. i 2 c terminology term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
docid027423 rev 4 29/77 LSM6DS33 digital interfaces 77 6.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the LSM6DS33 is 110101xb. the sdo/sa0 pin can be used to modify the less significant bit of the device address. if the sdo/sa0 pin is connected to the supply voltage, lsb is ?1? (address 1101011b); else if the sdo/sa0 pin is connected to ground, the lsb value is ?0? (address 1101010b). this solution permits to connect and address two different inertial modules to the same i 2 c bus. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the LSM6DS33 behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been returned, an 8-bit sub-address (sub) is transmitted. the increment of the address is configured by the ctrl3_c (12h) (if_inc). the slave address is completed with a read/write bit. if the bit is ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write) the master will transmit to the slave with direction unchanged. table 11 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 11. sad+read/write patterns command sad[6:1] sad[0] = sa0 r/w sad+r/w read 110101 0 1 11010101 (d5h) write 110101 0 0 11010100 (d4h) read 110101 1 1 11010111 (d7h) write 110101 1 0 11010110 (d6h) table 12. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak table 13. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak
digital interfaces LSM6DS33 30/77 docid027423 rev 4 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line, scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. 6.2 spi bus interface the LSM6DS33 spi is a bus slave. the spi allows writing and reading the registers of the device. the serial interface communicates to the application using 4 wires: cs , spc , sdi and sdo . figure 7. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are, respectively, the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . table 14. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 15. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data dat a data &6 63& 6', 6'2 5: $' $' $' $' $' $' ', ', ', ', ', ', ', ', '2 '2 '2 '2 '2 '2 '2 '2 $'
docid027423 rev 4 31/77 LSM6DS33 digital interfaces 77 both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : r w bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in latter case, the chip will drive sdo at the start of bit 8. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands further blocks of 8 clock periods will be added. when the ctrl3_c (12h) (if_inc) bit is ?0?, the address used to read/write data remains the same for every block. when the ctrl3_c (12h) (if_inc) bit is ?1?, the address used to read/write data is increased at every block. the function and the behavior of sdi and sdo remain unchanged. 6.2.1 spi read figure 8. spi read protocol the spi read command is performed with 16 clock pulses. a multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : read bit. the value is 1. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). bit 16-... : data do(...-8). further data in multiple byte reads. &6 63& 6', 6'2 5: '2 '2 '2 '2 '2 '2 '2 '2 $' $' $' $' $' $' $'
digital interfaces LSM6DS33 32/77 docid027423 rev 4 figure 9. multiple byte spi read protocol (2-byte example) 6.2.2 spi write figure 10. spi write protocol the spi write command is performed with 16 clock pulses. a multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1 -7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writes. figure 11. multiple byte spi write protocol (2-byte example) &6 63& 6', 6'2 5: '2 '2 '2 '2 '2 '2 '2 '2 $' $' $' $' $' $' '2 '2 '2 '2 '2 '2 '2 '2 $' &6 63& 6', 5: ', ', ', ', ', ', ', ', $' $' $' $' $' $' $' &6 63& 6', 5: $' $' $' $' $' $' ', ', ', ', ', ', ', ', ',',',',',',', ', $'
docid027423 rev 4 33/77 LSM6DS33 digital interfaces 77 6.2.3 spi read in 3-wire mode a 3-wire mode is entered by setting the ctrl3_c (12h) (sim) bit equal to ?1? (spi serial interface mode selection). figure 12. spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). a multiple read command is also available in 3-wire mode. &6 63& 6',2 5: '2 '2 '2 '2 '2 '2 '2 '2 $' $' $' $' $' $' $'
application hints LSM6DS33 34/77 docid027423 rev 4 7 application hints 7.1 LSM6DS33 electrical connections figure 13. LSM6DS33 electrical connections the device core is supplied through the vdd line. power supply decoupling capacitors (c1, c2 = 100 nf ceramic) should be placed as near as possible to the supply pin of the device (common design practice). the functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the spi/i 2 c interface. the functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the spi/i 2 c interface. 723 9,(: 9'',2 6&/ 6'2 &6 ,17 ,17 1& 5(6 9'' *1' *1' 5(6 5(6 5(6 *1' q) & 6'$ 9ggb,2 *1' q) & 5(6 *1' *1' 9'' 9ggb,2 5sx 5sx n2kp 6&/ 6'$ 3xooxswrehdgghg &frqiljxudwlrq ,
docid027423 rev 4 35/77 LSM6DS33 application hints 77 7.2 pin compatibility with lsm6ds0 figure 14. schematic 1 (pin 15 connected to gnd) ?) q) & & *1' *1' 9'' 9'' &ds 5(6 *1' q)9 & 5(6 5(6 5(6 *1' *1' 5(6 *1' ,17 5(6 5 &6 6'26$2 6'$6',6'2 6&/63& 9ggb,2 & q) 9ggb,2 *1' 7239,(: 9ggb,2 5sx 5sx n2kp 6&/ 6'$ 3xooxswrehdgghg &frqiljxudwlrq , &pxvwjxdudqwhhq)ydoxhxqghu 9eldvfrqglwlrq & & 5 /60'6 q)9 ?) 'rqrwprxqw /60'6 1rw qhfhvvdu\ 1rw qhfhvvdu\ 2kp
application hints LSM6DS33 36/77 docid027423 rev 4 figure 15. schematic 2 (pin 15 connected to vdd, vdd_io = vdd) ?) q) & & *1' *1' 9'' 9'' &ds 5(6 *1' q)9 & 5(6 5(6 5(6 *1' *1' 5(6 *1' ,17 5(6 5 &6 6'26$ 6'$6',6'2 6&/63& 9ggb,2 & q) 9'' *1' 7239,(: ,17 &pxvwjxdudqwhhq)ydoxhxqghu 9eldvfrqglwlrq & & 5 /60'6 q)9 ?) 'rqrwprxqw /60'6 1rw qhfhvvdu\ 1rw qhfhvvdu\ 2kp 9'' 5sx 5sx n2kp 6&/ 6'$ 3xooxswrehdgghg &frqiljxudwlrq ,
docid027423 rev 4 37/77 LSM6DS33 register mapping 77 8 register mapping the table given below provides a list of the 8/16 bit registers embedded in the device and the corresponding addresses. table 16. registers address map name type register address default comment hex binary reserved r/w 00 00000000 00000000 reserved func_cfg_access r/w 01 00000001 00000000 embedded functions configuration register reserved r/w 02-05 - reserved fifo_ctrl1 r/w 06 00000110 00000000 fifo configuration registers fifo_ctrl2 r/w 07 00000111 00000000 fifo_ctrl3 r/w 08 00001000 00000000 fifo_ctrl4 r/w 09 00001001 00000000 fifo_ctrl5 r/w 0a 00001010 00000000 orient_cfg_g r/w 0b 00001011 00000000 reserved r/w 0c 00001100 - reserved int1_ctrl r/w 0d 00001101 00000000 int1 pin control int2_ctrl r/w 0e 00001110 00000000 int2 pin control who_am_i r 0f 00001111 01101001 who i am id ctrl1_xl r/w 10 00010000 00000000 accelerometer and gyroscope control registers ctrl2_g r/w 11 00010001 00000000 ctrl3_c r/w 12 00010010 00000100 ctrl4_c r/w 13 00010011 00000000 ctrl5_c r/w 14 00010100 00000000 ctrl6_c r/w 15 00010101 00000000 ctrl7_g r/w 16 00010110 00000000 ctrl8_xl r/w 17 0001 0111 00000000 ctrl9_xl r/w 18 00011000 00111000 ctrl10_c r/w 19 00011001 00111000 reserved 1a 00011010 - reserved wake_up_src r 1b 00011011 output interrupts registers tap_src r 1c 00011100 output d6d_src r 1d 00011101 output
register mapping LSM6DS33 38/77 docid027423 rev 4 status_reg r 1e 00011110 output status data register reserved r 1f 0001 1111 - reserved out_temp_l r 20 00100000 output temperature output data register out_temp_h r 21 00100001 output outx_l_g r 22 00100010 output gyroscope output register outx_h_g r 23 00100011 output outy_l_g r 24 00100100 output outy_h_g r 25 00100101 output outz_l_g r 26 00100110 output outz_h_g r 27 00100111 output outx_l_xl r 28 00101000 output accelerometer output register outx_h_xl r 29 00101001 output outy_l_xl r 2a 00101010 output outy_h_xl r 2b 00101011 output outz_l_xl r 2c 00101100 output outz_h_xl r 2d 00101101 output reserved 2e-39 - reserved fifo_status1 r 3a 00111010 output fifo status registers fifo_status2 r 3b 00111011 output fifo_status3 r 3c 00111100 output fifo_status4 r 3d 00111101 output fifo_data_out_l r 3e 00111110 output fifo data output registers fifo_data_out_h r 3f 001 11111 output timestamp0_reg r 40 01000000 output timestamp output registers timestamp1_reg r 41 01000001 output timestamp2_reg r/w 42 01000010 output reserved 43-48 - reserved step_timestamp_l r 49 0100 1001 output step counter timestamp registers step_timestamp_h r 4a 0100 1010 output step_counter_l r 4b 01001011 output step counter output registers step_counter_h r 4c 01001100 output reserved 4d-52 - reserved table 16. registers address map (continued) name type register address default comment hex binary
docid027423 rev 4 39/77 LSM6DS33 register mapping 77 registers marked as reserved must not be changed. writing to those registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up. func_src r 53 01010011 output interrupt register reserved 54-57 - reserved tap_cfg r/w 58 01011000 00000000 interrupt registers tap_ths_6d r/w 59 01011001 00000000 int_dur2 r/w 5a 01011010 00000000 wake_up_ths r/w 5b 01011011 00000000 wake_up_dur r/w 5c 01011100 00000000 free_fall r/w 5d 01011101 00000000 md1_cfg r/w 5e 01011110 00000000 md2_cfg r/w 5f 0101 1111 00000000 reserved 60-6b - reserved table 16. registers address map (continued) name type register address default comment hex binary
register description LSM6DS33 40/77 docid027423 rev 4 9 register description the device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. the register addresses, made up of 7 bits, are used to identify them and to write the data through the serial interface. 9.1 func_cfg_access (01h) enable embedded functions register (r/w). table 18. func_cfg_access register description 9.2 fifo_ctrl1 (06h) fifo control register (r/w). table 20. fifo_ctrl1 register description 9.3 fifo_ctrl2 (07h) fifo control register (r/w). table 17. func_cfg_access register func_cfg_en 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) func_cfg_en enable access to the embedded functions configuration registers (1) from address 02h to 32h. default value: 0. (0: disable access to embedded functions configuration registers; 1: enable access to embedded functions configuration registers) 1. the embedded functions configuration registers details are available in 10: embedded functions register mapping and 11: embedded functions registers description . table 19. fifo_ctrl1 register fth_7 fth_6 fth_5 fth_4 fth_3 fth_2 fth_1 fth_0 fth_[7:0] fifo threshold level setting (1) . default value: 0000 0000. watermark flag rises when the number of bytes written to fifo after the next write is greater than or equal to the threshold level. minimum resolution for the fifo is 1 lsb = 2 bytes (1 word) in fifo 1. for a complete watermark threshold configuration, consider fth_[11:8] in fifo_ctrl2 (07h) . table 21. fifo_ctrl2 register timer_pedo _fifo_en timer_pedo _fifo_drdy 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) fth_11 fth10 fth_9 fth_8
docid027423 rev 4 41/77 LSM6DS33 register description 77 table 22. fifo_ctrl2 register description 9.4 fifo_ctrl3 (08h) fifo control register (r/w). table 24. fifo_ctrl3 register description timer_pedo _fifo_en enable pedometer step counter and time stamp. default: 0 (0: disable step counter and time stamp data; 1: enable step counter and time stamp data.) timer_pedo _fifo_drdy fifo write mode. default: 0 (0: enable write in fifo based on xl/gyro data-ready; 1: enable write in fifo at every step detected by step counter.) fth_[11:8] fifo threshold level setting (1) . default value: 0000 watermark flag rises when the number of bytes written to fifo after the next write is greater than or equal to the threshold level. minimum resolution for the fifo is 1lsb = 2 bytes (1 word) in fifo 1. for a complete watermark threshold configuration, consider fth_[11:8] in fifo_ctrl1 (06h) table 23. fifo_ctrl3 register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) dec_fifo _gyro2 dec_fifo _gyro1 dec_fifo _gyro0 dec_fifo _xl2 dec_fifo _xl1 dec_fifo _xl0 dec_fifo_gyro [2:0] gyro fifo (first data set) decimation setting. default: 000 for the configuration setting, refer to table 25 . dec_fifo_xl [2:0] accelerometer fifo (second data set) decimation setting. default: 000 for the configuration setting, refer to table 26 . table 25. gyro fifo decimation setting dec_fifo_gyro [2:0] configuration 000 gyro sensor not in fifo 001 no decimation 010 decimation with factor 2 011 decimation with factor 3 100 decimation with factor 4 101 decimation with factor 8 110 decimation with factor 16 111 decimation with factor 32
register description LSM6DS33 42/77 docid027423 rev 4 9.5 fifo_ctrl4 (09h) fifo control register (r/w). table 28. fifo_ctrl4 register description table 26. accelerometer fifo decimation setting dec_fifo_xl [2:0] configuration 000 accelerometer sensor not in fifo 001 no decimation 010 decimation with factor 2 011 decimation with factor 3 100 decimation with factor 4 101 decimation with factor 8 110 decimation with factor 16 111 decimation with factor 32 table 27. fifo_ctrl4 register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. only_high _data timer_pedo _dec_fifo2 timer_pedo _dec_fifo1 timer_pedo _dec_fifo1 0 (1) 0 (1) 0 (1) only_high_data 8-bit data storage in fifo. default: 0 (0: disable msbyte only memorization in fifo for xl and gyro; 1: enable msbyte only memorization in fifo for xl and gyro in fifo) timer_pedo_dec_ fifo[2:0] third fifo data set decimation setting. default: 000 for the configuration setting, refer to table 29 . these bits are used when the bit timer_pedo_fifo_en is set to ?1? in fifo_ctrl2 (07h) table 29. third fifo data set decimation setting timer_pedo_dec_fifo[2:0] configuration 000 third fifo data set not in fifo 001 no decimation 010 decimation with factor 2 011 decimation with factor 3 100 decimation with factor 4 101 decimation with factor 8 110 decimation with factor 16 111 decimation with factor 32
docid027423 rev 4 43/77 LSM6DS33 register description 77 9.6 fifo_ctrl5 (0ah) fifo control register (r/w). table 31. fifo_ctrl5 register description table 30. fifo_ctrl5 register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. odr_ fifo_3 odr_ fifo_2 odr_ fifo_1 odr_ fifo_0 fifo_ mode_2 fifo_ mode_1 fifo_ mode_0 odr_fifo_[3:0] fifo odr selection, setting fifo_mode also. default: 0000 for the configuration setting, refer to table 32 fifo_mode_[2:0] fifo mode selection bits, setting odr_fifo also. default value: 000 for the configuration setting refer to table 33 table 32. fifo odr selection odr_fifo_[3:0] configuration (1) 1. if the device is working at an odr slower than the one selected, fifo odr is limited to that odr value. moreover, these bits are effective if the timer_pedo_fifo_drdy bit of fifo_ctrl2 (07h) is set to 0. 0000 fifo disabled 0001 fifo odr is set to 13 hz 0010 fifo odr is set to 26 hz 0011 fifo odr is set to 52 hz 0100 fifo odr is set to 104 hz 0101 fifo odr is set to 208 hz 0110 fifo odr is set to 416 hz 0111 fifo odr is set to 833 hz 1000 fifo odr is set to 1.66 khz 1001 fifo odr is set to 3.33 khz 1010 fifo odr is set to 6.66 khz table 33. fifo mode selection fifo_mode_[2:0] configuration mode 000 bypass mode. fifo disabled. 001 fifo mode. stops collecting data when fifo is full. 010 reserved 011 continuous mode until trigger is deasserted, then fifo mode. 100 bypass mode until trigger is deasserted, then continuous mode. 101 reserved 110 continuous mode. if the fifo is full, the new sample overwrites the older one. 111 reserved
register description LSM6DS33 44/77 docid027423 rev 4 9.7 orient_cfg_g (0bh) angular rate sensor sign and orientation register (r/w). table 34. orient_cfg_g register table 35. orient_cfg_g register description 9.8 int1_ctrl (0dh) int1 pad control register (r/w). each bit in this register enables a signal to be carried through int1. the pad?s output will supply the or combination of the selected signals. table 37. int1_ctrl register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) signx_g signy_g signz_g orient_2 orient_1 orient_0 signx_g pitch axis (x) angular rate sign. default value: 0 (0: positive sign; 1: negative sign) signy_g roll axis (y) angular rate sign. default value: 0 (0: positive sign; 1: negative sign) signz_g yaw axis (z) angular rate sign. default value: 0 (0: positive sign; 1: negative sign) orient [2:0] directional user-orientation selection. default value: 000 for the configuration setting, refer to table 36 . table 36. settings for orientation of axes orient [2:0] 000 001 010 011 100 101 pitch x x y y z z roll y z x z x y yaw z y z x y x int1_ step_ detector int1_sign _mot int1_full _flag int1_ fifo_ovr int1_ fth int1_ boot int1_ drdy_g int1_ drdy_xl
docid027423 rev 4 45/77 LSM6DS33 register description 77 table 38. int1_ctrl register description 9.9 int2_ctrl (0eh) int2 pad control register (r/w). each bit in this register enables a signal to be carried through int2. the pad?s output will supply the or combination of the selected signals. table 39. int2_ctrl register table 40. int2_ctrl register description int1_ step_ detector pedometer step recognition interrupt enable on int1 pad. default value: 0 (0: disabled; 1: enabled) int1_sign_mot significant motion interrupt enable on int1 pad. default value: 0 (0: disabled; 1: enabled) int1_full_flag fifo full flag interrupt enable on int1 pad. default value: 0 (0: disabled; 1: enabled) int1_fifo_ovr fifo overrun interrupt on int1 pad. default value: 0 (0: disabled; 1: enabled) int1_fth fifo threshold interrupt on int1 pad. default value: 0 (0: disabled; 1: enabled) int1_ boot boot status available on int1 pad. default value: 0 (0: disabled; 1: enabled) int1_drdy_g gyroscope data ready on int1 pad. default value: 0 (0: disabled; 1: enabled) int1_drdy_xl accelerometer data ready on int1 pad. default value: 0 (0: disabled; 1: enabled) int2_step _delta int2_step_ count_ov int2_ full_flag int2_ fifo_ovr int2_ fth int2_ drdy _temp int2_ drdy_g int2_ drdy_xl int2_step_delta pedometer step recognition interrupt on delta time (1) enable on int2 pad. default value: 0 (0: disabled; 1: enabled) 1. delta time value is defined in register step_count_delta (15h). int2_step_count _ov step counter overflow interrupt enable on int2 pad. default value: 0 (0: disabled; 1: enabled) int2_ full_flag fifo full flag interrupt enable on int2 pad. default value: 0 (0: disabled; 1: enabled) int2_fifo_ovr fifo overrun interrupt on int2 pad. default value: 0 (0: disabled; 1: enabled) int2_fth fifo threshold interrupt on int2 pad. default value: 0 (0: disabled; 1: enabled) int2_drdy_temp temperature data ready in int2 pad. default value: 0 (0: disabled; 1: enabled) int2_drdy_g gyroscope data ready on int2 pad. default value: 0 (0: disabled; 1: enabled) int2_drdy_xl accelerometer data ready on int2 pad. default value: 0 (0: disabled; 1: enabled)
register description LSM6DS33 46/77 docid027423 rev 4 9.10 who_am_i (0fh) who_am_i register (r). this register is a read-only register. its value is fixed at 69h. 9.11 ctrl1_xl (10h) linear acceleration sensor control register 1 (r/w). table 42. ctrl1_xl register table 43. ctrl1_xl register description table 41. who_am_i register 01101001 odr_xl3 odr_xl2 odr_xl1 odr_xl0 fs_xl1 fs_xl0 bw_xl1 bw_xl0 odr_xl [3:0] output data rate and power mode selection . default value: 0000 (see table 44 ). fs_xl [1:0] accelerometer full-scale selection. default value: 00. (00: 2 g ; 01: 16 g ; 10: 4 g ; 11: 8 g ) bw_xl [1:0] anti-aliasing filter bandwidth selection. default value: 00 (00: 400 hz; 01: 200 hz; 10: 100 hz; 11: 50 hz) table 44. accelerometer odr register setting odr_ xl3 odr_ xl2 odr_ xl1 odr_ xl0 odr selection [hz] when xl_hm_mode = 1 odr selection [hz] when xl_hm_mode = 0 0 0 0 0 power-down power-down 0 0 0 1 13 hz (low power) 13 hz (high performance) 0 0 1 0 26 hz (low power) 26 hz (high performance) 0 0 1 1 52 hz (low power) 52 hz (high performance) 0 1 0 0 104 hz (normal mode) 104 hz (high performance) 0 1 0 1 208 hz (normal mode) 208 hz (high performance) 0 1 1 0 416 hz (high performance) 416 hz (high performance) 0 1 1 1 833 hz (high performance) 833 hz (high performance) 1 0 0 0 1.66 khz (high performance) 1.66 khz (high performance) 1 0 0 1 3.33 khz (high performance) 3.33 khz (high performance) 1 0 1 0 6.66 khz (high performance) 6.66 khz (high performance)
docid027423 rev 4 47/77 LSM6DS33 register description 77 table 45. bw and odr (high-performance mode) odr (1) 1. filter not used when accelerometer is in normal and low-power modes. analog filter bw (xl_hm_mode = 0) xl_bw_scal_odr = 0 xl_bw_scal_odr = 1 6.66 - 3.33 khz filter not used bandwidth is determined by setting bw_xl[1:0] in ctrl1_xl (10h) 1.66 khz 400 hz 833 hz 400 hz 416 hz 200 hz 208 hz 100 hz 104 - 13 hz 50 hz
register description LSM6DS33 48/77 docid027423 rev 4 9.12 ctrl2_g (11h) angular rate sensor control register 2 (r/w). table 46. ctrl2_g register table 47. ctrl2_g register description odr_g3 odr_g2 odr_g1 odr_g0 fs_g1 fs_g0 fs_125 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. odr_g [3:0] gyroscope output data rate selection . default value: 0000 (refer to table 46 ) fs_g [1:0] gyroscope full-scale selection. default value: 00 (00: 245 dps; 01: 500 dps; 10: 1000 dps; 11: 2000 dps) fs_125 gyroscope full-scale at 125 dps. default value: 0 (0: disabled; 1: enabled) table 48. gyroscope odr configuration setting odr_g3 odr_g2 odr_g1 odr_g0 odr [hz] when g_hm_mode = 1 odr [hz] when g_hm_mode = 0 0 0 0 0 power down power down 0 0 0 1 13 hz (low power) 13 hz (high performance) 0 0 1 0 26 hz (low power) 26 hz (high performance) 0 0 1 1 52 hz (low power) 52 hz (high performance) 0 1 0 0 104 hz (normal mode) 104 hz (high performance) 0 1 0 1 208 hz (normal mode) 208 hz (high performance) 0 1 1 0 416 hz (high performance) 416 hz (high performance) 0 1 1 1 833 hz (high performance) 833 hz (high performance) 1 0 0 0 1.66 khz (high performance) 1.66 khz (high performance)
docid027423 rev 4 49/77 LSM6DS33 register description 77 9.13 ctrl3_c (12h) control register 3 (r/w). table 49. ctrl3_c register boot bdu h_lactive pp_od sim if_inc ble sw_reset table 50. ctrl3_c register description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content (1) ) 1. boot request is executed as soon as internal oscillator is turned on. it is possible to set bit while in power- down mode, in this case it will be served at the next normal mode or sleep mode. bdu block data update. default value: 0 (0: continuous update; 1: output registers not updated until msb and lsb have been read) h_lactive interrupt activation level. default value: 0 (0: interrupt output pads active high; 1: interrupt output pads active low) pp_od push-pull/open-drain selection on int1 and int2 pads. default value: 0 (0: push-pull mode; 1: open-drain mode) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface). if_inc register address automatically incremented during a multiple byte access with a serial interface (i 2 c or spi). default value: 1 (0: disabled; 1: enabled) ble big/little endian data selection. default value 0 (0: data lsb @ lower address; 1: data msb @ lower address) sw_reset software reset. default value: 0 (0: normal mode; 1: reset device) this bit is cleared by hardware after next flash boot.
register description LSM6DS33 50/77 docid027423 rev 4 9.14 ctrl4_c (13h) control register 4 (r/w). 9.15 ctrl5_c (14h) control register 5 (r/w). table 53. ctrl5_c register table 51. ctrl4_c register xl_bw_ scal_odr sleep_g int2_on_ int1 fifo_ temp_en drdy_ mask i2c_disable 0 stop_on _fth table 52. ctrl4_c register description xl_bw_ scal_odr accelerometer bandwidth selection. default value: 0 (0 (1) : bandwidth determined by odr selection, refer to table 45 ; 1 (2) : bandwidth determined by setting bw_xl[1:0] in ctrl1_xl (10h) register.) 1. filter used in high-performance mode only with odr less than 3.33 khz. 2. filter used in high-performance mode only. sleep_g gyroscope sleep mode enable. default value: 0 (0: disabled; 1: enabled) int2_on_int1 all interrupt signals available on int1 pad enable. default value: 0 (0: interrupt signals divided between int1 and int2 pads; 1: all interrupt signals in logic or on int1 pad) fifo_temp_en enable temperature data as 4 th fifo data set (3) . default: 0 (0: disable temperature data as 4 th fifo data set; 1: enable temperature data as 4 th fifo data set) 3. this bit is effective if the timer_pedo_fifo_en bit of fifo_ctrl2 register is set to 0. drdy_mask configuration 1 (4) data available enable bit. default value: 0 (0: da timer disabled; 1: da timer enabled) 4. in configuration 1, switching to combo mode, data are collected in fifo only when both accelerometer and gyroscope are set. switching to accelerometer only, data are collected in fifo after filter setting. i2c_disable disable i 2 c interface. default value: 0 (0: both i 2 c and spi enabled; 1: i 2 c disabled, spi only) stop_on_fth enable fifo threshold level use. default value: 0. (0: fifo depth is not limited; 1: fifo depth is limited to threshold level) rounding2 rounding1 rounding0 0 (1) 1. this bit must be set to ?0? for the correct operation of the device st1_g st0_g st1_xl st0_xl table 54. ctrl5_c register description rounding[2:0] circular burst-mode (rounding) read from output registers. default: 000 (000: no rounding; others: refer to table 55 ) st_g [1:0] angular rate sensor self-test enable. default value: 00 (00: self-test disabled; other: refer to table 56 ) st_xl [1:0] linear acceleration sensor self-test enable. default value: 00 (00: self-test disabled; other: refer to table 57 )
docid027423 rev 4 51/77 LSM6DS33 register description 77 9.16 ctrl6_c (15h) angular rate sensor control register 6 (r/w). table 55. output registers rounding pattern rounding[2:0] rounding pattern 000 no rounding 001 accelerometer only 010 gyroscope only 011 gyroscope + accelerometer table 56. angular rate sensor self-test mode selection st1_g st0_g self-test mode 0 0 normal mode 0 1 positive sign self-test 1 0 not allowed 1 1 negative sign self-test table 57. linear acceleration sensor self-test mode selection st1_xl st0_xl self-test mode 0 0 normal mode 0 1 positive sign self-test 1 0 negative sign self-test 1 1 not allowed table 58. ctrl6_c register trig_en lvlen lvl2_en xl_hm_mode 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) 0 (1) 0 (1) table 59. ctrl6_c register description trig_en gyroscope data edge-sensitive trigger enable. default value: 0 (0: external trigger disabled; 1: external trigger enabled) lvlen gyroscope data level-sensitive trigger enable. default value: 0 (0: level-sensitive trigger disabled; 1: level sensitive trigger enabled) lvl2_en gyroscope level-sensitive latched enable. default value: 0 (0: level-sensitive latched disabled; 1: level sensitive latched enabled) xl_hm_mode high-performance operating mode disable for accelerometer (1) . default value: 0 (0: high-performance operating mode enabled; 1: high-performance operating mode disabled) 1. normal and low-power mode depends on the odr setting, for details refer to table 44 .
register description LSM6DS33 52/77 docid027423 rev 4 9.17 ctrl7_g (16h) angular rate sensor control register 7 (r/w). 9.18 ctrl8_xl (17h) linear acceleration sensor control register 8 (r/w). table 60. ctrl7_g register g_hm_mode hp_g_ en hpcf_g1 hpcf_g0 hp_g_r st rounding_ status 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) table 61. ctrl7_g register description g_hm_mode high-performance operating mode disable for gyroscope (1) . default: 0 (0: high-performance operating mode enabled; 1: high-performance operating mode disabled) 1. normal and low-power mode depends on the odr setting, for details refer to table 48 . hp_g_en gyroscope high-pass filter enable. default value: 0 (0: hpf disabled; 1: hpf enabled) hp_g_rst gyro digital hp filter reset. default: 0 (0: gyro digital hp filter reset off; 1: gyro digital hp filter reset on) rounding_ status source register rounding function enable on status_reg (1eh) , func_src (53h) and wake_up_src (1bh) registers. default value: 0 (0: disabled; 1: enabled) hpcf_g[1:0] gyroscope high-pass filter cutoff frequency selection. default value: 00. refer to table 62 . table 62. gyroscope high-pass filter mode configuration hpcf_g1 hpcf_g0 high-pass filter cutoff frequency 0 0 0.0081 hz 0 1 0.0324 hz 1 0 2.07 hz 1 1 16.32 hz table 63. ctrl8_xl register lpf2_xl_ en hpcf_ xl1 hpcf_ xl0 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) hp_slope_x l_en 0 (1) low_pass _on_6d
docid027423 rev 4 53/77 LSM6DS33 register description 77 9.19 ctrl9_xl (18h) linear acceleration sensor control register 9 (r/w). table 64. ctrl8_xl register description lpf2_xl_en accelerometer low-pass filter lpf2 selection. refer to figure 5 . hpcf_xl[1:0] accelerometer slope filter and high-pass filter configuration and cutoff setting. refer to table 65 . hp_slope_xl_en accelerometer slope filter / high-pass filter selection. refer to figure 5 . low_pass_on_6d low-pass filter on 6d function selection. refer to figure 5 . table 65. accelerometer slope and high-pass filter selection and cutoff frequency hpcf_xl[1:0] applied filter hp filter cutoff frequency [hz] 00 slope odr_xl/50 01 high-pass odr_xl/100 10 high-pass odr_xl/9 11 high-pass odr_xl/400 table 66. ctrl9_xl register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) zen_xl yen_xl xen_xl 0 (1) 0 (1) 0 (1) table 67. ctrl9_xl register description zen_xl accelerometer z-axis output enable. default value: 1 (0: z-axis output disabled; 1: z-axis output enabled) yen_xl accelerometer y-axis output enable. default value: 1 (0: y-axis output disabled; 1: y-axis output enabled) xen_xl accelerometer x-axis output enable. default value: 1 (0: x-axis output disabled; 1: x-axis output enabled)
register description LSM6DS33 54/77 docid027423 rev 4 9.20 ctrl10_c (19h) control register 10 (r/w). 9.21 wake_up_src (1bh) wake up interrupt source register (r). table 68. ctrl10_c register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) zen_g yen_g xen_g func_en pedo_rst _step sign_ motion_en table 69. ctrl10_c register description zen_g gyroscope yaw axis (z) output enable. default value: 1 (0: z-axis output disabled; 1: z-axis output enabled) yen_g gyroscope roll axis (y) output enable. default value: 1 (0: y-axis output disabled; 1: y axis output enabled) xen_g gyroscope pitch axis (x) output enable. default value: 1 (0: x-axis output disabled; 1: x-axis output enabled) func_en enable embedded functionalities (pedometer, tilt, significant motion) and accelerometer hp and lpf2 filters (refer to figure 5 ). default value: 0 (0: disable functionalities of embedded functions and accelerometer filters; 1: enable functionalities of embedded functions and accelerometer filters) pedo_rst_ step reset pedometer step counter. default value: 0 (0: disabled; 1: enabled) sign_motion _en enable significant motion function. default value: 0 (0: disabled; 1: enabled) table 70. wake_up_src register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) ff_ia sleep_ state_ia wu_ia x_wu y_wu z_wu table 71. wake_up_src register description ff_ia free-fall event detection status. default: 0 (0: free-fall event not detected; 1: free-fall event detected) sleep_ state_ia sleep event status. default value: 0 (0: sleep event not detected; 1: sleep event detected) wu_ia wakeup event detection status. default value: 0 (0: wakeup event not detected; 1: wakeup event detected.) x_wu wakeup event detection status on x-axis. default value: 0 (0: wakeup event on x-axis not detected; 1: wakeup event on x-axis detected) y_wu wakeup event detection status on y-axis. default value: 0 (0: wakeup event on y-axis not detected; 1: wakeup event on y-axis detected) z_wu wakeup event detection status on z-axis. default value: 0 (0: wakeup event on z-axis not detected; 1: wakeup event on z-axis detected)
docid027423 rev 4 55/77 LSM6DS33 register description 77 9.22 tap_src (1ch) tap source register (r). 9.23 d6d_src (1dh) portrait, landscape, face-up and face-down source register (r) table 72. tap_src register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. tap_ia single_ tap double_ tap tap_sign x_tap y_tap z_tap table 73. tap_src register description tap_ia tap event detection status. default: 0 (0: tap event not detected; 1: tap event detected) single_tap single-tap event status. default value: 0 (0: single tap event not detected; 1: single tap event detected) double_tap double-tap event detection status. default value: 0 (0: double-tap event not detected; 1: double-tap event detected.) tap_sign sign of acceleration detected by tap event. default: 0 (0: positive sign of acceleration detected by tap event; 1: negative sign of acceleration detected by tap event) x_tap tap event detection status on x-axis. default value: 0 (0: tap event on x-axis not detected; 1: tap event on x-axis detected) y_tap tap event detection status on y-axis. default value: 0 (0: tap event on y-axis not detected; 1: tap event on y-axis detected) z_tap tap event detection status on z-axis. default value: 0 (0: tap event on z-axis not detected; 1: tap event on z-axis detected) table 74. d6d_src register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. d6d_ia zh zl yh yl xh xl table 75. d6d_src register description d6d_ ia interrupt active for change position portrait, landscape, face-up, face-down. default value: 0 (0: change position not detected; 1: change position detected) zh z-axis high event (over threshold). default value: 0 (0: event not detected; 1: event (over threshold) detected) zl z-axis low event (under threshold). default value: 0 (0: event not detected; 1: event (under threshold) detected) yh y-axis high event (over threshold). default value: 0 (0: event not detected; 1: event (over-threshold) detected) yl y-axis low event (under threshold). default value: 0 (0: event not detected; 1: event (under threshold) detected) x_h x-axis high event (over threshold). default value: 0 (0: event not detected; 1: event (over threshold) detected) x_l x-axis low event (under threshold). default value: 0 (0: event not detected; 1: event (under threshold) detected)
register description LSM6DS33 56/77 docid027423 rev 4 9.24 status_reg (1eh) 9.25 out_temp_l (20h), out_temp(21h) temperature data output register (r). l and h registers together express a 16-bit word in two?s complement (r). 9.26 outx_l_g (22h) angular rate sensor pitch axis (x) angular rate output register (r). the value is expressed as a 16-bit word in two?s complement. (r) table 76. status_reg register - - - - ev_boot tda gda xlda table 77. status_reg register description ev_boot boot running flag signal. default value: 0 (0: no boot running; 1: boot running) tda temperature new data available. default: 0 (0: no set of data is available at temperature sensor output; 1: a new set of data is available at temperature sensor output) gda gyroscope new data available. default value: 0 (0: no set of data available at gyroscope output; 1: a new set of data is available at gyroscope output) xlda accelerometer new data available. default value: 0 (0: no set of data available at accelerometer output; 1: a new set of data is available at accelerometer output) table 78. out_temp_l register temp7 temp6 temp5 temp4 temp3 temp2 temp1 temp0 table 79. out_temp_h register temp15 temp14 temp13 temp12 temp11 temp10 temp9 temp8 table 80. out_temp register description temp[15:0] temperature sensor output data the value is expressed as two?s complement sign extended on the msb. table 81. outx_l_g register d7 d6 d5 d4 d3 d2 d1 d0 table 82. outx_l_g register description d[7:0] pitch axis (x) angular rate value (lsbyte)
docid027423 rev 4 57/77 LSM6DS33 register description 77 9.27 outx_h_g (23h) angular rate sensor pitch axis (x) angular rate output register (r). the value is expressed as a 16-bit word in two?s complement. (r) 9.28 outy_l_g (24h) angular rate sensor roll axis (y) angular rate output register (r). the value is expressed as a 16-bit word in two?s complement. (r). 9.29 outy_h_g (25h) angular rate sensor roll axis (y) angular rate output register (r). the value is expressed as a 16-bit word in two?s complement. (r). 9.30 outz_l_g (26h) angular rate sensor yaw axis (z) angular rate output register (r). the value is expressed as a 16-bit word in two?s complement. (r). table 83. outx_h_g register d15 d14 d13 d12 d11 d10 d9 d8 table 84. outx_h_g register description d[15:8] pitch axis (x) angular rate value (msbyte) table 85. outy_l_g register d7 d6 d5 d4 d3 d2 d1 d0 table 86. outy_l_g register description d[7:0] roll axis (y) angular rate value (lsbyte) table 87. outy_h_g register d15 d14 d13 d12 d11 d10 d9 d8 table 88. outy_h_g register description d[15:8] roll axis (y) angular rate value (msbyte) table 89. outz_l_g register d7 d6 d5 d4 d3 d2 d1 d0 table 90. outz_l_g register description d[7:0] yaw axis (z) angular rate value (lsbyte)
register description LSM6DS33 58/77 docid027423 rev 4 9.31 outz_h_g (27h) angular rate sensor yaw axis (z) angular rate output register (r). the value is expressed as a 16-bit word in two?s complement. 9.32 outx_l_xl (28h) linear acceleration sensor x-axis output register (r). the value is expressed as a 16-bit word in two?s complement. 9.33 outx_h_xl (29h) linear acceleration sensor x-axis output register (r). the value is expressed as a 16-bit word in two?s complement. 9.34 outy_l_xl (2ah) linear acceleration sensor y-axis output register (r). the value is expressed as a 16-bit word in two?s complement. table 91. outz_h_g register d15 d14 d13 d12 d11 d10 d9 d8 table 92. outz_h_g register description d[15:8] yaw axis (z) angular rate value (msbyte) table 93. outx_l_xl register d7 d6 d5 d4 d3 d2 d1 d0 table 94. outx_l_xl register description d[7:0] x-axis linear acceleration value (lsbyte) table 95. outx_h_xl register d15 d14 d13 d12 d11 d10 d9 d8 table 96. outx_h_xl register description d[15:8] x-axis linear acceleration value (msbyte) table 97. outy_l_xl register d7 d6 d5 d4 d3 d2 d1 d0 table 98. outy_l_xl register description d[7:0] y-axis linear acceleration value (lsbyte)
docid027423 rev 4 59/77 LSM6DS33 register description 77 9.35 outy_h_xl (2bh) linear acceleration sensor y-axis output register (r). the value is expressed as a 16-bit word in two?s complement. 9.36 outz_l_xl (2ch) linear acceleration sensor z-axis output register (r). the value is expressed as a 16-bit word in two?s complement. 9.37 outz_h_xl (2dh) linear acceleration sensor z-axis output register (r). the value is expressed as a 16-bit word in two?s complement. 9.38 fifo_status1 (3ah) fifo status control register (r). for a proper reading of the register, it is recommended to set the bdu bit in ctrl3_c (12h) to 1. table 105. fifo_status1 register table 106. fifo_status1 register description table 99. outy_h_g register d15 d14 d13 d12 d11 d10 d9 d8 table 100. outy_h_g register description d[15:8] y-axis linear acceleration value (msbyte) table 101. outz_l_xl register d7 d6 d5 d4 d3 d2 d1 d0 table 102. outz_l_xl register description d[7:0] z-axis linear acceleration value (lsbyte) table 103. outz_h_xl register d15 d14 d13 d12 d11 d10 d9 d8 table 104. outz_h_xl register description d[15:8] z-axis linear acceleration value (msbyte) diff_ fifo_7 diff_ fifo_6 diff_ fifo_5 diff_ fifo_4 diff_ fifo_3 diff_ fifo_2 diff_ fifo_1 diff_ fifo_0 diff_fifo_[7:0] number of unread words (16-bit axes) stored in fifo (1) . 1. for a complete number of unread samples, consider diff_fifo [11:8] in fifo_status2 (3bh)
register description LSM6DS33 60/77 docid027423 rev 4 9.39 fifo_status2 (3bh) fifo status control register (r). for a proper reading of the register, it is recommended to set the bdu bit in ctrl3_c (12h) to 1. table 107. fifo_status2 register table 108. fifo_status2 register description 9.40 fifo_status3 (3ch) fifo status control register (r). for a proper reading of the register, it is recommended to set the bdu bit in ctrl3_c (12h) to 1. table 109. fifo_status3 register table 110. fifo_status3 register description fth fifo_ over_run fifo_ full fifo_ empty diff_ fifo_11 diff_ fifo_10 diff_ fifo_9 diff_ fifo_8 fth fifo watermark status. default value: 0 (0: fifo filling is lower than watermark level (1) ; 1: fifo filling is equal to or higher than the watermark level) 1. fifo watermark level is set in fth_[11:0] in fifo_ctrl1 (06h) and fifo_ctrl2 (07h) fifo_over_run fifo overrun status. default value: 0 (0: fifo is not completely filled; 1: fifo is completely filled) fifo_full fifo full status. default value: 0 (0: fifo is not full; 1: fifo will be full at the next odr) fifo_empty fifo empty bit. default value: 0 (0: fifo contains data; 1: fifo is empty) diff_fifo_[7:0] number of unread words (16-bit axes) stored in fifo (2) . 2. for a complete number of unread samples, consider diff_fifo [11:8] in fifo_status1 (3ah) fifo_ pattern _7 fifo_ pattern _6 fifo_ pattern _5 fifo_ pattern _4 fifo_ pattern _3 fifo_ pattern _2 fifo_ pattern _1 fifo_ pattern _0 fifo_ pattern_[7:0] word of recursive pattern read at the next reading.
docid027423 rev 4 61/77 LSM6DS33 register description 77 9.41 fifo_status4 (3dh) fifo status control register (r). for a proper reading of the register, it is recommended to set the bdu bit in ctrl3_c (12h) to 1. table 111. fifo_status4 register table 112. fifo_status4 register description 9.42 fifo_data_out_l (3eh) fifo data output register (r). for a proper reading of the register, it is recommended to set the bdu bit in ctrl3_c (12h) to 1. 9.43 fifo_data_out_h (3fh) fifo data output register (r). for a proper reading of the register, it is recommended to set the bdu bit in ctrl3_c (12h) to 1. 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) fifo_ pattern_9 fifo_ pattern_8 fifo_ pattern_[9:8] word of recursive pattern read at the next reading. table 113. fifo_data_out_l register data_ out_ fifo_l_7 data_ out_ fifo_l_6 data_ out_ fifo_l_5 data_ out_ fifo_l_4 data_ out_ fifo_l_3 data_ out_ fifo_l_2 data_ out_ fifo_l_1 data_ out_ fifo_l_0 table 114. fifo_data_out_l register description data_out_fifo_l_[7:0] fifo data output (first byte) table 115. fifo_data_out_h register data_ out_ fifo_h_7 data_ out_ fifo_h_6 data_ out_ fifo_h_5 data_ out_ fifo_h_4 data_ out_ fifo_h_3 data_ out_ fifo_h_2 data_ out_ fifo_h_1 data_ out_ fifo_h_0 table 116. fifo_data_out_h register description data_out_fifo_h_[7:0] fifo data output (second byte)
register description LSM6DS33 62/77 docid027423 rev 4 9.44 timestamp0_reg (40h) time stamp first byte data output register (r). the value is expressed as a 24-bit word and the bit resolution is defined by setting the value in wake_up_dur (5ch) . 9.45 timestamp1_reg (41h) time stamp second byte data output register (r). the value is expressed as a 24-bit word and the bit resolution is defined by setting value in wake_up_dur (5ch) . 9.46 timestamp2_reg (42h) time stamp third byte data output register (r/w). the value is expressed as a 24-bit word and the bit resolution is defined by setting the value in wake_up_dur (5ch) . to reset the timer, the aah value has to be stored in this register. 9.47 step_timestamp_l (49h) step counter timestamp information register (r). when a step is detected, the value of timestamp_reg1 register is copied in step_timestamp_l. table 117. timestamp0_reg register timesta mp0_7 timesta mp0_6 timesta mp0_5 timesta mp0_4 timesta mp0_3 timesta mp0_2 timesta mp0_1 timesta mp0_0 table 118. timestamp0_reg register description timestamp0_[7:0] timestamp first byte data output table 119. timestamp1_reg register timesta mp1_7 timesta mp1_6 timesta mp1_5 timesta mp1_4 timesta mp1_3 timesta mp1_2 timesta mp1_1 timesta mp1_0 table 120. timestamp1_reg register description timestamp1_[7:0] timestamp second byte data output table 121. timestamp2_reg register timesta mp2_7 timesta mp2_6 timesta mp2_5 timesta mp2_4 timesta mp2_3 timesta mp2_2 timesta mp2_1 timesta mp2_0 table 122. timestamp2_reg register description timestamp2_[7:0] timestamp third byte data output table 123. step_timestamp_l register step_ timesta mp_l_7 step_ timesta mp_l_6 step_ timesta mp_l_5 step_ timesta mp_l_4 step_ timesta mp_l_3 step_ timesta mp_l_2 step_ timesta mp_l_1 step_ timesta mp_l_0 table 124. step_timestamp_l register description step_timestamp_l[7:0] timestamp of last step detected.
docid027423 rev 4 63/77 LSM6DS33 register description 77 9.48 step_timestamp_h (4ah) step counter timestamp information register (r). when a step is detected, the value of timestamp_reg2 register is copied in step_timestamp_h. 9.49 step_counter_l (4bh) step counter output register (r). 9.50 step_counter_h (4ch) step counter output register (r). 9.51 func_src (53h) significant motion, tilt, step detector interrupt source register (r). table 125. step_timestamp_h register step_ timesta mp_h_7 step_ timesta mp_h_6 step_ timesta mp_h_5 step_ timesta mp_h_4 step_ timesta mp_h_3 step_ timesta mp_h_2 step_ timesta mp_h_1 step_ timesta mp_h_0 table 126. step_timestamp_h register description step_timestamp_h[7:0] timestamp of last step detected. table 127. step_counter_l register step_co unter_l _7 step_co unter_l _6 step_co unter_l _5 step_co unter_l _4 step_co unter_l _3 step_co unter_l _2 step_co unter_l _1 step_co unter_l _0 table 128. step_counter_l register description step_counter_l_[7:0] step counter output (lsbyte) table 129. step_counter_h register step_co unter_h _7 step_co unter_h _6 step_co unter_h _5 step_co unter_h _4 step_co unter_h _3 step_co unter_h _2 step_co unter_h _1 step_co unter_h _0 table 130. step_counter_h register description step_counter_h_[7:0] step counter output (msbyte) table 131. func_src register step_count_ delta_ia sign_ motion_ia tilt_ia step_ detected step_ overflow 00 0
register description LSM6DS33 64/77 docid027423 rev 4 9.52 tap_cfg (58h) time stamp, pedometer, tilt, filtering, and tap recognition functions configuration register (r/w). table 132. func_src register description step_count _delta_ia pedometer step recognition on delta time status. default value: 0 (0: no step recognized during delta time; 1: at least one step recognized during delta time) sign_ motion_ia significant motion event detection status. default value: 0 (0: significant motion event not detected; 1: significant motion event detected) tilt_ia tilt event detection status. default value: 0 (0: tilt event not detected; 1: tilt event detected) step_ detected step detector event detection status. default value: 0 (0: step detector event not detected; 1: step detector event detected) step_ overflow step counter overflow status. default value: 0 (0: step counter value < 2 16 ; 1: step counter value reached 2 16 ) table 133. tap_cfg register timer_ en pedo_en tilt_en slope _fds tap_x_en tap_y_en tap_z_en lir table 134. tap_cfg register description timer_en time stamp count enable, output data are collected in timestamp0_reg (40h) , timestamp1_reg (41h) , timestamp2_reg (42h) register. default: 0 (0: time stamp count disabled; 1: time stamp count enabled) pedo_en pedometer algorithm enable. default value: 0 (0: pedometer algorithm disabled; 1: pedometer algorithm enabled) tilt_en tilt calculation enable. default value: 0 (0: tilt calculation disabled; 1: tilt calculation enabled.) slope_fds enable accelerometer hp and lpf2 filters (refer to figure 5 ). default value: 0 (0: disable; 1: enable) tap_x_en enable x direction in tap recognition. default value: 0 (0: x direction disabled; 1:x direction enabled) tap_y_en enable y direction in tap recognition. default value: 0 (0: y direction disabled; 1:y direction enabled) tap_z_en enable z direction in tap recognition. default value: 0 (0: z direction disabled; 1:z direction enabled) lir latched interrupt. default value: 0 (0: interrupt request not latched; 1: interrupt request latched)
docid027423 rev 4 65/77 LSM6DS33 register description 77 9.53 tap_ths_6d (59h) portrait/landscape position and tap function threshold register (r/w). 9.54 int_dur2 (5ah) tap recognition function setting register (r/w). table 135. tap_ths_6d register d4d_en sixd_ths 1 sixd_ths 0 tap_ths 4 tap_ths 3 tap_ths 2 tap_ths 1 tap_ths 0 table 136. tap_ths_6d register description d4d_en 4d orientation detection enable (z-axis position detection is disabled). default value: 0 (0: disabled; 1: enabled) sixd_ths[1:0] threshold for d6d function. default value: 00 for details, refer to table 137 . tap_ths[4:0] threshold for tap recognition. default value: 00000 table 137. threshold for d4d/d6d function sixd_ths[1:0] threshold value 00 80 degrees 01 70 degrees 10 60 degrees 11 50 degrees table 138. int_dur2 register dur3 dur2 dur1 dur0 quiet1 quiet0 shock1 shock0 table 139. int_dur2 register description dur[3:0] duration of maximum time gap for double tap recognition. default: 0000 when double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. the default value of these bits is 0000b which corresponds to 16*odr_xl time. if dur[3:0] bits are set to a different value, 1lsb corresponds to 32*odr_xl time. quiet[1:0] expected quiet time after a tap detection. default value: 00 quiet time is the time after the first detected tap in which there must not be any overthreshold event. the default value of these bits is 00b which corresponds to 2*odr_ time. if quiet[1:0] bits are set to a different value, 1lsb corresponds to 4*odr_time. shock[1:0] maximum duration of overthreshold event. default value: 00 maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. the default value of these bits is 00b which corresponds to 4*odr_ time. if shock[1:0] bits are set to a different value, 1lsb corresponds to 8*odr_time.
register description LSM6DS33 66/77 docid027423 rev 4 9.55 wake_up_ths (5bh) single and double-tap function threshold register (r/w). 9.56 wake_up_dur (5ch) free-fall, wakeup, time stamp and sleep mode functions duration setting register (r/w). table 140. wake_up_ths register single_ double _tap inactivity wk_ths5 wk_ths4 wk_ths3 wk_ths2 wk_ths1 wk_ths0 table 141. wake_up_ths register description single_double_tap single/double-tap event enable. default: 0 (0: only single-tap event enabled; 1: both single and double-tap events enabled) inactivity inactivity event enable. default value: 0 (0: sleep disabled; 1: sleep enabled) wk_ths[5:0] threshold for wakeup. default value: 000000 table 142. wake_up_dur register ff_dur5 wake_ dur1 wake_ dur0 timer_ hr sleep_ dur3 sleep_ dur2 sleep_ dur1 sleep_ dur0 table 143. wake_up_dur register description ff_dur5 free fall duration event. default: 0 for the complete configuration of the free-fall duration, refer to ff_dur[4:0] in free_fall (5dh) configuration. wake_dur[1:0] wake up duration event. default: 00 1lsb = 1 odr_time timer_hr time stamp register resolution setting (1) . default value: 0 (0: 1lsb = 6.4 ms; 1: 1lsb = 25 s) 1. configuration of this bit affects timestamp0_reg (40h) , timestamp1_reg (41h) , timestamp2_reg (42h) , step_timestamp_l (49h) , step_timestamp_h (4ah) , and step_count_delta (15h) registers. sleep_dur[3:0] duration to go in sleep mode. default value: 0000 1 lsb = 512 odr
docid027423 rev 4 67/77 LSM6DS33 register description 77 9.57 free_fall (5dh) free-fall function duration setting register (r/w). 9.58 md1_cfg (5eh) functions routing on int1 register (r/w). table 144. free_fall register ff_dur4 ff_dur3 ff_dur2 ff_dur1 ff_dur0 ff_ths2 ff_ths1 ff_ths0 table 145. free_fall register description ff_dur[4:0] free-fall duration event. default: 0 for the complete configuration of the free fall duration, refer to ff_dur5 in wake_up_dur (5ch) configuration ff_ths[2:0] free fall threshold setting. default: 000 for details refer to table 146 . table 146. threshold for free-fall function ff_ths[2:0] threshold value 000 156 m g 001 219 m g 010 250 m g 011 312 m g 100 344 m g 101 406 m g 110 469 m g 111 500 m g table 147. md1_cfg register int1_ inact_ state int1_ single_ tap int1_wu int1_ff int1_ double_ tap int1_6d int1_tilt int1_ timer table 148. md1_cfg register description int1_inact_ state routing on int1 of inactivity mode. default: 0 (0: routing on int1 of inactivity disabled; 1: routing on int1 of inactivity enabled) int1_single_ tap single-tap recognition routing on int1. default: 0 (0: routing of single-tap event on int1 disabled; 1: routing of single-tap event on int1 enabled) int1_wu routing of wakeup event on int1. default value: 0 (0: routing of wakeup event on int1 disabled; 1: routing of wakeup event on int1 enabled)
register description LSM6DS33 68/77 docid027423 rev 4 9.59 md2_cfg (5fh) functions routing on int2 register (r/w). int1_ff routing of free-fall event on int1. default value: 0 (0: routing of free-fall event on int1 disabled; 1: routing of free-fall event on int1 enabled) int1_double _tap routing of tap event on int1. default value: 0 (0: routing of double-tap event on int1 disabled; 1: routing of double-tap event on int1 enabled) int1_6d routing of 6d event on int1. default value: 0 (0: routing of 6d event on int1 disabled; 1: routing of 6d event on int1 enabled) int1_tilt routing of tilt event on int1. default value: 0 (0: routing of tilt event on int1 disabled; 1: routing of tilt event on int1 enabled) int1_timer routing of end counter event of timer on int1. default value: 0 (0: routing of end counter event of timer on int1 disabled; 1: routing of end counter event of timer event on int1 enabled) table 148. md1_cfg register description (continued) table 149. md2_cfg register int2_ inact_ state int2_ single_ tap int2_wu int2_ff int2_ double_ tap int2_6d int2_tilt 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. table 150. md2_cfg register description int2_inact_ state routing on int2 of inactivity mode. default: 0 (0: routing on int2 of inactivity disabled; 1: routing on int2 of inactivity enabled) int2_single_ tap single-tap recognition routing on int2. default: 0 (0: routing of single-tap event on int2 disabled; 1: routing of single-tap event on int2 enabled) int2_wu routing of wakeup event on int2. default value: 0 (0: routing of wakeup event on int2 disabled; 1: routing of wake-up event on int2 enabled) int2_ff routing of free-fall event on int2. default value: 0 (0: routing of free-fall event on int2 disabled; 1: routing of free-fall event on int2 enabled) int2_double _tap routing of tap event on int2. default value: 0 (0: routing of double-tap event on int2 disabled; 1: routing of double-tap event on int2 enabled) int2_6d routing of 6d event on int2. default value: 0 (0: routing of 6d event on int2 disabled; 1: routing of 6d event on int2 enabled) int2_tilt routing of tilt event on int2. default value: 0 (0: routing of tilt event on int2 disabled; 1: routing of tilt event on int2 enabled)
docid027423 rev 4 69/77 LSM6DS33 embedded functions register mapping 77 10 embedded functions register mapping the table given below provides a list of the registers for the embedded functions avaialble in the device and the corresponding addresses. embedded functions registers are accessible when func_cfg_en is set to ?1? in func_cfg_access (01h) . registers marked as reserved must not be changed. writing to those registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up. table 151. registers address map - embedded functions name type register address default comment hex binary reserved - 02-0e reserved pedo_ths_reg r/w 0f 00001111 00000000 reserved - 10-12 reserved sm_ths r/w 13 00010011 00000110 pedo_deb_reg r/w 14 00010100 00000000 step_count_delta r/w 15 0001 0101 00000000 reserved - 24-32 reserved
embedded functions registers description LSM6DS33 70/77 docid027423 rev 4 11 embedded functions registers description 11.1 pedo_ths_reg (0fh) table 152. pedo_ths_reg register default values table 153. pedo_ths_reg register description procedure to modify the pedometer minimum threshold: ? write reg func_cfg_access (01h) = 80h (enables access to the embedded functions registers) ? set min threshold in bits [4:0] of reg 0fh (1lsb = 16 m g @ fs = 2 g ) ? write reg func_cfg_access (01h) = 00h (disables access to the embedded functions registers) note: all modifications of the content of the embedded functions registers have to be performed with the device in power-down mode. 11.2 sm_ths (13h) significant motion configuration register (r/w). pedo_4g - - ths_ min4 ths_ min3 ths_ min2 ths_ min1 ths_ min0 pedo_ 4g this bit sets the internal full scale used in pedometer functions. using this bit, saturation is avoided (e.g. fast walk). 0: internal full scale = 2 g . 1: internal full scale 4 g (device full_scale @ctrl1_xl must be 4 g , otherwise internal full scale is 2 g ) ths_ min[4:0] configurable minimum threshold. 1lsb = 16 m g @pedo_4g=0, 1lsb = 32 m g @pedo_4g=1 table 154. sm_ths register sm_ths_ 7 sm_ths_ 6 sm_ths_ 5 sm_ths_ 4 sm_ths_ 3 sm_ths_ 2 sm_ths_ 1 sm_ths_ 0 table 155. sm_ths register description sm_ths[7:0] significant motion threshold. default value: 00000110
docid027423 rev 4 71/77 LSM6DS33 embedded functions registers description 77 11.3 pedo_deb_reg (14h) the procedure to modify the pedometer debounce time is the following: ? write reg func_cfg_access (01h) = 80h (enables access to the embedded functions) ? set debounce time in bits [3:7] of reg 14h (1lsb = 80 ms.this value must be > 0) ? write reg func_cfg_access (01h) = 00h (disables access to the embedded functions registers) note: all modifications of the content of the embedded functions registers have to be performed with the device in power-down mode. 11.4 step_count_delta (15h) time period register for step detection on delta time (r/w). table 156. pedo_deb_reg register default values deb_ time4 deb_ time3 deb_ time2 deb_ time1 deb_ time0 deb_ step2 deb_ step1 deb_ step0 00000110 table 157. pedo_deb_reg register description deb_ time[4:0] if this time between steps is greater than deb_time*80ms, the debouncer is reactivated deb_ step[2:0] minimum number of steps to increment step counter (debouncer) table 158. step_count_delta register sc_ delta_7 sc_ delta_6 sc_ delta_5 sc_ delta_4 sc_ delta_3 sc_ delta_2 sc_ delta_1 sc_ delta_0 table 159. step_count_delta register description sc_delta[7:0] time period value (1) (1lsb = 1.6384 s) 1. this value is effective if the timer_en bit of the tap_cfg register is set to 1 and the timer_hr bit of the wake_up_dur register is set to 0.
soldering information LSM6DS33 72/77 docid027423 rev 4 12 soldering information the lga package is compliant with the ecopack ? , rohs and "green" standard. it is qualified for soldering heat resistance according to jedec j-std-020. leave "pin 1 indicator" unconnected during soldering. land pattern and soldering recommendations are available at www .st.com/mems .
docid027423 rev 4 73/77 LSM6DS33 package information 77 13 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. 13.1 lga-16 package information figure 16. lga 3x3x0.86 16l package outline and dimensions 'lphqvlrqvduhlqploolphwhuxqohvvrwkhuzlvhvshflilhg *hqhudo7rohudqfhlvppxqohvvrwkhuzlvhvshflilhg 287(5',0(16,216 ,7(0 ',0(16,21>pp@ 72/(5$1&(>pp@ ? @ / > k w j q h / ? @ : > k w g l : ; $ 0 @ + > w k j l h +
package information LSM6DS33 74/77 docid027423 rev 4 13.2 lga-16 packing information figure 17. carrier tape information for lga-16 package figure 18. lga-16 package orientation in carrier tape
docid027423 rev 4 75/77 LSM6DS33 package information 77 figure 19. reel information for carrier tape of lga-16 package table 160. reel dimensions for carrier tape of lga-16 package reel dimensions (mm) a (max) 330 b (min) 1.5 c 13 0.25 d (min) 20.2 n (min) 60 g 12.4 +2/-0 t (max) 18.4
revision history LSM6DS33 76/77 docid027423 rev 4 14 revision history table 161. document revision history date revision changes 18-feb-2015 1 initial release 17-jul-2015 2 updated registers in section 9: register description 27-jul-2015 3 first public release 09-oct-2015 4 updated package representation on page 1 added pedo_ths_reg (0fh) and pedo_deb_reg (14h) added section 13.2: lga-16 packing information
docid027423 rev 4 77/77 LSM6DS33 77 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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