this is information on a product in full production. december 2013 docid025277 rev 1 1/8 USBULC6-2F4 2-line, ultralow capacitance protection in 0.3 mm pitch datasheet - production data features ? ultralow capacitance diode (1.5 pf max) ? 0.3 mm pitch ? two data lines (d+ and d-) protected against esd ? breakdown voltage v br = 6.0 v min. ? flip chip, 300 m pitch, lead-free ? very low leakage current ? very small pcb area ? rohs compliant benefits ? minimized impact on rise and fall times for maximum data integrity ? low pcb space occupation ? higher reliability offered by monolithic integration complies with the following standards ? iec 61000-4-2 level 4: ? 15 kv (air discharge) ? 8 kv (contact discharge) description the USBULC6-2F4 is a monolithic, application specific discrete device dedicated to esd protection of high speed interfaces. its ultralow line capacitance secures a high level of signal integrity without compromising the protection of downstream sensitive chips against the most stringently characterized esd strikes. figure 1. pin layout (bump side) figure 2. device configuration flip chip USBULC6-2F4 (4 bumps) b 1 2 a a2 a1 b2 b1 note: b1 and b2 bumps must be grounded on the pcb together www.st.com
characteristics USBULC6-2F4 2/8 docid025277 rev 1 1 characteristics figure 3. electrical char acteristics - definitions table 1. absolute maximum ratings (t amb = 25 c) symbol parameter value unit v pp iec 61000-4-2, level 4, contact discharge 8kv p pp peak pulse power dissipation (8/20 s) 60 w t j maximum junction temperature 125 c t op operating temperature range -30 to + 85 c t stg storage temperature range -55 to +150 c table 2. electrical char acteristics - values (t amb = 25 c) symbol test conditions min. typ. max. unit v br i r = 1 ma 6 - v i rm v rm = 3 v per line - - 100 na c line v line = 0 v, v osc = 30 mv, f = 1 mhz - - 1.5 pf r d dynamic resistance, pulse duration 100 ns i/o to gnd - 0.73 - ? gnd to i/o - 0.72 - c = line capacitance line symbol parameter v = breakdown voltage i = leakage current @ v v = stand-off voltage v = clamping voltage i = peak pulse current br rm rm rm cl pp v i v cl v br v rm i f v f i rm i pp i = forward current f v = forward voltage f
docid025277 rev 1 3/8 USBULC6-2F4 characteristics 8 figure 4. eye diagram, board only (according to usb 2.0 high speed specification) figure 5. eye diagram, board with USBULC6-2F4 (according to usb 2.0 high speed specification) figure 6. esd response to iec 61000-4-2 (+8 kv contact discharge) (1) figure 7. esd response to iec 61000-4-2 (-8 kv contact discharge) (1) 1. test board connected with a 50 ohm cable and 20 db + 20 db attenuator to an oscilloscope on 50 ohm input. esd generator return path connected to pcb ground plane. 20 v/div v : esd peak voltage v :clamping voltage @ 30 ns v :clamping voltage @ 60 ns pp cl cl v :clamping voltage @ 100 ns cl 1 2 3 4 20 ns/div 118.7 v 16.6 v 9.2 v 1 4 3 23.6 v 2 10 v/div 20 ns/div v : esd peak voltage v :clamping voltage @ 30 ns v :clamping voltage @ 60 ns pp cl cl v :clamping voltage @ 100 ns cl 2 3 4 -5.2 v -1.5 v 4 3 1 -8.7 v 2 1 -80.8 v figure 8. junction capacitance versus frequency (typical values) figure 9. analog crosstalk versus frequency (typical values) c (pf) f (mhz) 1 10 100 1000 1.5 1.0 0.5 0.0 a1 / a2 a1 and a2 / gnd t = 25 c v = 30 mv j osc db 100k 1m 10m 100m 1g 10g - 100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 f (hz) i1-02
characteristics USBULC6-2F4 4/8 docid025277 rev 1 figure 10. insertion losses versus frequency figure 11. tlp measurement s21 (db) f (hz) 10 30 100 300 1 g 10 g 3 g -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 i01 i01 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 5 10 15 20 25 30 35 40 45 50 i/o to gnd gnd to i/o v cl (v) i pp (a) figure 12. peak pulse power versus initial junction temperature (m aximum values, pulse 8/20 s) figure 13. peak pulse power versus exponential pulse duration (maximum values) 0 10 20 30 40 50 60 70 80 90 100 0 25 50 75 100 125 150 8/20s p pp (w) t j (c) 1 10 100 1000 10 100 1000 t j initial = 25 c p pp (w) tp(s) figure 14. clamping voltage versus peak pulse current (typical values) figure 15. leakage current versus junction temperature (typical values) 0.1 1 10 6789101112131415161718 8/20s t j = 25 c v cl (v) i pp (a) 0.1 1 10 100 25 35 45 55 65 75 85 95 105 115 125 v r =v rm = 3 v io/gnd t j (c) i r (na)
docid025277 rev 1 5/8 USBULC6-2F4 package information 8 2 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 16. package dimensions figure 17. footprint recommendations figure 18. marking 172 m 172 m 645 m 30 m 645 m 30 m 300 m 30 m 175 m 20 m 120m 300 m 30 605 m 55 copper pad diameter: 220 m recommended 260 m maximum solder stencil opening: 220 m recommended solder mask opening: 300 m minimum z e dot, xx = marking
package information USBULC6-2F4 6/8 docid025277 rev 1 figure 19. tape and reel specifications note: more information is available in the stmicroelectronics application notes: an4208: ?flip chip: package description and recommendations for use? an1751: ?emi filters: recomme ndations and measurements? user direction of unreeling all dimensions in mm 4.0 0.1 2.0 0.05 8.0 0.3 4.0 0.1 1.75 0.1 3.5 - 0.05 ? 1.55 0.05 0.69 0.05 0.20 0.05 0.73 0.05 0.73 0.05 dot identifying pin a1 location e e e z z z
docid025277 rev 1 7/8 USBULC6-2F4 ordering information 8 3 ordering information figure 20. ordering information scheme 4 revision history table 3. ordering information order code marking package weight base qty delivery mode USBULC6-2F4 ez flip chip 0.516 mg 5000 tape and reel (7?) usb ulc 6 - 2 f4 usb protection ultra low capacitance breakdown voltage number of lines package 6 = 6 v min 2 = 2 lines f = flip chip = l 4 ead-free, pitch = 300 m table 4. document revision history date revision changes 20-dec-2013 1 initial release.
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