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fn7840 rev.2.00 sep 8, 2017 ISL97691 2.4v led driver with independen t analog and pwm dimming control s of 2 backlights for 3d application datasheet fn7840 rev.2.00 page 1 of 19 sep 8, 2017 the ISL97691 is intersil?s highly integrated 4 channel led driver for single cell li-ion battery operated mobile displays requiring analog dimming, and for 3d mobile display applications. it drives four 40ma channels of leds up to 26v from an input supply 2.4v to 5.5v. the ISL97691 will also drive 60ma channels up to 21v at 30% du ty for high peak current 3d modes. the ISL97691 provides 4 channels of current with 2 independent analog dimming controls and 2 independent pwm dimming controls. channels 1 and 2 form one channel group and channels 3 and 4 form the other channel group. each channel group?s analog dimming is controlled through 1-wire communication with 6-bi t resolution and each channel group?s pwm dimming is controlled by a separate pwm input. this unique setup allows 2d or 3d application where independent and dynamic channel control of led peak current and pwm dimming duty cycle are possible. the ISL97691 employs adaptive boost architec ture that allo ws ultra low dimming duty cycle as low as 0.005% at 100hz dimming frequency. the driver features dynamic headroom control that monitors the highest led forward voltage string and uses its feedback signal for the minimu m output regulation. the ISL97691 incorporates extensive protection functions including string open and short ci rcuit detections, ovp, and otp. the switching frequency can be adjusted from 400khz to 1.5mhz. the device is offered in a 16 ld tqfn 3x3mm package and can operate in ambient temperature from -40c to +85c. features ? 2.4v minimum input voltage, no need for higher voltage supplies ?4 x 60ma (note 1 ) and 4 x 40ma (note 2 ) led current ? 2 groups of independent analog and pwm current controls - 1-wire interfaces for 6-bit analog dimming - pwm inputs for pwm dimming - 0.005% minimum pwm dimming duty cycle at 100hz ? low 0.8ma quiescent current ? 2.5% current matching ? adjustable switching freque ncy from 400khz to 1.5mhz ?fault protection - ovp, otp, channel open/short circuit protections notes: 1. not exceeding 30% of the frame rate (1/t frame ), with v in > 2.7v and t a < +55c. 2. v in > 2.7v applications ? tablet, notebook pc, and smart phone displays led backlighting ? mobile displays for 2d or 3d led backlighting related literature ? for a full list of related documents, visit our website - ISL97691 product page i figure 1. typical application circuit fig ure 2. ultra low pwm dimming linearity fsw agnd ovp vin 1-wire_1 iset comp d1 ch1 ch2 ch3 ch4 pgnd lx v in = 2.7v~5.5v v out = 24.5v, 4 x 60ma* l1 10h 12k 15nf 10 1f 4.7f 4.7f 470k 23.7k 143k 17.8k 100pf 2.2nf ISL97691 4.7f 1-wire_2 *not exceeding 30% pwm duty pwm2 pwm_1 ? ? ? ? ? ? 0.0001 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 input dimming duty cycle (%) iled (ma) f pwm : 200hz f pwm : 100hz
ISL97691 fn7840 rev.2.00 page 2 of 19 sep 8, 2017 block diagram ref gen vin gm amp ch1 ch4 pwm/ pfm logic fet drivers ovp reg osc & ramp comp imax highest vf string detect temp sensor iset + - o/p short ref_ ovp ref_ vsc internal bias open ckt, short ckt detection dynamic headroom control ovp fsw pwmi_1 pwm dimming controller up to 26v lx v in = 2.4v~5.5v pwmi_2 10h ISL97691 ch2 ch3 pgnd 2x4.7f ilimit s = 0 dc1 pwm1 + - 1 + - 2 pwm2 + - 3 + - 4 8-bit dac 6-bit dac dc2 6-bit dac 1-wire i/f 1-wire_1 1-wire_2 comp part number (notes 3 , 4 , 5 ) part marking temp range (c) package (rohs compliant) pkg. dwg. # ISL97691irtz 7691 -40 to +85 16 ld tqfn l16.3x3d ISL97691irtz-evalz evaluation board notes: 3. add ?-t? suffix for 6k unit or ?-tk? suffix for 1k unit tape and reel. refer to tb347 for details on reel specifications. 4. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets ; molding compounds/die attach materials and 100% matte tin plate - e3 termination finish, which is rohs compliant and co mpatible with both snpb and pb -free soldering operations. inters il pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 5. for moisture sensitivity level (msl), see the product information page for ISL97691 . for more information on msl see tb363 .
ISL97691 fn7840 rev.2.00 page 3 of 19 sep 8, 2017 pin configuration ISL97691 (16 ld 3mmx3mm tqfn ) top view pin description pin number pin name i/o description 1 agnd s analog ground for precision circuits. 2 comp i external compensation. fit a series rc comprising 12k and 15nf from comp to gnd. 3 iset i channel current setting. the led channel current is adjusted from 15ma to 60ma with resistor r set from iset pin to gnd. 4 1-wire_1 i 1-wire interface 1 for controlling channels 1 and 2 with 6-bit analog dimming. 5 1-wire_2 i 1-wire interface 2 for controlling channels 3 and 4 with 6-bit analog dimming. 6 pwmi_1 i pwm input 1 for controlling channels 1 an d 2 pwm dimming. during the pwm off period, the 1-wire_1 data will remain at the previous programmed level. 7 pwmi_2 i pwm input 2 for controlling channels 3 an d 4 pwm dimming. during the pwm off period, the 1-wire_2 data will remain at the previous programmed level. 8 vin i input supply voltage. 9 lx o input to boost switch. 10 pgnd s power ground (lx, c in , and c out power return). 11 fsw i switching frequency adjustment. the boost switch ing frequency is adjusted from 400khz to 1.5mhz with resistor r fsw from fsw pin to gnd. 12 ovp i overvoltage protection input. 13 ch1 i channel 1 current sink and channel moni toring. tie pin to gnd if channel unused. 14 ch2 i channel 2 current sink and channel moni toring. tie pin to gnd if channel unused. 15 ch3 i channel 3 current sink and channel moni toring. tie pin to gnd if channel unused. 16 ch4 i channel 4 current sink and channel moni toring. tie pin to gnd if channel unused. epad x no electrical connection but should be used to connect pgnd and agnd. for example, uses top plane as pgnd and bottom plane as agnd with vias on epad to allow he at dissipation and minimum noise coupling from pgnd to agnd operation. 1 3 4 15 agnd comp iset 1-wire_1 ch4 ch3 ch2 ch1 16 14 13 2 12 10 9 11 6 578 ovp fsw pgnd lx 1-wire_2 pwmi_2 en/pwmi_2 vin thermal pad
ISL97691 fn7840 rev.2.00 page 4 of 19 sep 8, 2017 table of contents absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pwm boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 autoshutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 dimming controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 analog dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pwm dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 current matching and current accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 dynamic headroom control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 operation with input voltage greater than 5.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 input capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 overvoltage protection (ovp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 boost output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 schottky diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 unused led channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 high current applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 pcb layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pcb layout with tqfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 general power pad design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 fault protection and monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 short circuit protection (scp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 open circuit protection (ocp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 over-temperature protection (otp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ISL97691 fn7840 rev.2.00 page 5 of 19 sep 8, 2017 absolute maximum rating s thermal information vin, fsw, iset, comp, ovp . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.5v pwmi_1, pwmi_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.5v 1-wire_1, 1-wire_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.5v ch1 to ch4, lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v pgnd, agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v above voltage ratings are all with respect to agnd pin esd ratings human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . .2.5kv machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 200v charged device model (jesd22-c101e) . . . . . . . . . . . . . . . . . . . . . . . 2kv latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 16 ld tqfn (notes 6 , 7 ) . . . . . . . . . . . . . . . 51 4.6 thermal characterization (typical) psi jt (c/w) 16 ld tqfn (note 8 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.11 maximum continuous junction temperature . . . . . . . . . . . . . . . . .+125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tb379 . 7. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 8. psi jt is the psi junction-to-top thermal characterization parameter. if the package top temperature can be measured with this rating then the die junction temperature can be estimated more accurately than the ? jc and ? jc thermal resistance ratings. electrical specifications all specifications below are characterized at t a = -40c to +85c; v in = 3.3v, pwmi_1 = 3.3v, r iset = 26.7k , unless otherwise noted. boldface limits apply across the operating temperature range, -40c to +85c. parameter description condition min (note 9 )typ max (note 9 )unit general v in backlight supply voltage t a = +25c 2.4 5.5 v i vin v in active current, all strings 100% duty, i led = 40ma all channels 100% duty 2.5 ma all channels 0% duty 0.8 ma i autoshutdown v in shutdown current, both 1-wire interface inputs inactive pwmi_1 and pwmi_2 low longer than t pwmtimeout 1a v out output voltage v in ? 2.7v, i led = 40ma 26 v t wake wakeup time from sleep boost and channels operating 1.5 2.2 ms v uvlo undervoltage lockout threshold 2 2.15 2.35 v v uvlo_hys undervoltage lockout hysteresis 150 mv boost switching regulator ss soft-start 100% led duty cycle 7 ms swilimit boost fet current limit 2.5 2.8 3.2 a r ds(on) internal boost switch on-resistance t a = +25c 212 m eff_peak peak efficiency v in = 5.5v, v out = 21v, t a = +25c, r fsw = 144k ?? i ch1-ch4 = 20ma, l = 10h with dcr ?? 150m 90 % v in = 2.4v, v out = 21v, t a = +25c, r fsw = 144k ?? i ch1-ch4 = 20ma, l = 10h with dcr ?? 150m 74 % d max boost maximum duty cycle fsw = 400khz 93.5 % fsw = 1.5mhz 93 %
ISL97691 fn7840 rev.2.00 page 6 of 19 sep 8, 2017 d min boost minimum duty cycle fsw = 400khz 11 % fsw = 1.5mhz 15 % f sw boost switching frequency r fsw = 216k 360 400 440 khz r fsw = 72.1k 1.2 mhz r fsw = 57.7k 1.35 1.5 1.65 mhz ilx_leakage lx leakage current lx = 26v 10 a reference i match channel-to-channel dc current matching i led = 20ma -2.5 +2.5 % i acc current accuracy i led = 20ma -3 +3 % fault detection v sc channel short circuit threshold 6.75 8 9.25 v v temp over-temperature threshold 150 c v ovplo overvoltage limit on ovp pin 1.18 1.22 1.245 v ovp fault ovp short detection fault level 70 mv channel current sinks v headroom dominant channel current sink headroom at ch pin i led = 20ma, t a = +25c 300 (note 11 ) mv v headroom_range dominant channel current sink headroom range at chx pin i led = 20ma, t a = +25c 65 mv i led(max) maximum led current per channel 2.7v ? v in ? 5.5v, v out = 21v, 30% of t frame , t a ?? +70c 60 ma maximum total led current for all strings limited to 120ma 2.7v ? v in ? 5.5v, v out = 21v, 30% of t frame , t a ? +70c 60 ma maximum total led current for all strings limited to 110ma 2.7v ? v in ? 5.5v, v out = 24.5v, 31.25% of t frame , t a ? +70c 60 ma 1-wire interface t logic1 timing range for logic 1 device in normal operation 15 45 s t logic1_wake timing range for logic 1 for first bit transmission during shutdown device in autoshutdown 25 45 s t logic0 timing range for logic 0 device in normal operation 90 120 s t logic0_wake timing range for logic 0 for first bit transmission during shutdown device in autoshutdown 100 120 s t load timing range for load device in normal operation 218 s t hi valid 1-wire_1 or 1-wire_2 high time device in normal operation 3 s pwm generator v il pwm input low voltage 0.5 v v ih pwm input high voltage 1.5 v electrical specifications all specifications below are characterized at t a = -40c to +85c; v in = 3.3v, pwmi_1 = 3.3v, r iset = 26.7k , unless otherwise noted. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter description condition min (note 9 )typ max (note 9 )unit
ISL97691 fn7840 rev.2.00 page 7 of 19 sep 8, 2017 f pwmi pwmi input frequency range (1/t pwm ) 100 30,000 hz t pwmtimeout low duration on both pwmi_1 and pwmi_2 for driver to enter auto low-power shutdown 120 ms pwm acc pwm dimming output resolution 80 ns t pwm_on_min pwm dimming minimum on-time 350 ns t l channels 1 and 2 on time in 1 frame t frame = 4.17ms, i led = 60ma 30%*t frame 35%*t frame ms t frame = 16.67ms, i led = 60ma 30%*t frame 35%*t frame ms t r channels 3 and 4 on time in 1 frame t frame = 4.17ms, i led = 60ma 30%*t frame 35%*t frame ms t frame = 16.67ms, i led = 60ma 30%*t frame 35%*t frame ms notes: 9. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 10. at maximum v in of 5.5v, minimum v out is 6v. minimum v out can be lower at lower v in . 11. varies within the range specified by v headroom_range . electrical specifications all specifications below are characterized at t a = -40c to +85c; v in = 3.3v, pwmi_1 = 3.3v, r iset = 26.7k , unless otherwise noted. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter description condition min (note 9 )typ max (note 9 )unit
ISL97691 fn7840 rev.2.00 page 8 of 19 sep 8, 2017 typical performance curves figure 3. efficiency vs v in (i ch = 20ma, f dim = 200hz, v out = 21v, leds = 4p7s) figure 4. efficiency vs pwm dimming (v in = 3.7v, i ch = 20ma, f dim = 200hz, v out = 21v, leds = 4p7s) figure 5. pwm dimming linearity (v in = 3.7v, f dim = 200hz, v out = 21v, leds = 4p7s) figure 6. channel matching accuracy (v in = 3.7v, i ch = 20ma, v out = 21v, leds = 4p7s) figure 7. start-up (100% direct pwm dimming, v in = 3.7v, i ch = 20ma, f dim = 200hz, leds = 4p7s) figure 8. start-up (50% direct pwm dimming, v in = 3.7v, i ch = 20ma, f dim = 200hz, leds = 4p7s) 76 78 80 82 84 86 88 90 92 2.8 3.3 3.8 4.3 4.8 input voltage (v) 4p5s 4p7s efficiency (%) 50 55 60 65 70 75 80 85 90 0 20406080100 pwm dimming (%) 4p5s 4p7s efficiency (%) 0 2 4 6 8 10 12 14 16 18 20 0 20406080100 pwm dimming (%) led current (ma) -2.00 -1.50 -1.00 -0.50 0.00 0.50 1.00 1.50 2.00 012345 channel no matching accuracy (%) v_lx v_ch v_out i_l v_lx v_ch v_out i_l
ISL97691 fn7840 rev.2.00 page 9 of 19 sep 8, 2017 figure 9. 100% dire ct pwm dimming (v in = 3.7v, i ch = 20ma, f dim = 200hz, leds = 4p7s) figure 10. 50% direct pwm dimming (v in = 3.7v , i ch = 20ma, f dim = 200hz, leds = 4p7s) figure 11. boost switching and channel voltage ripple (v in = 3.7v , i ch = 20ma, f dim = 200hz, leds = 4p7s, 22h, f sw = 600khz) figure 12. minimum dimming duty cycle (pwm dimming input 0.003%, f dim = 100hz) figure 13. boost fet current limit figure 14. led dc current control with 1-wire interface typical performance curves (continued) v_lx v_ch v_out i_l v_lx v_ch v_out i_l v_lx v_ch v_out i_l pwm input i_ch binary: 100000 (32) binary: 111111 (64) 100% iled 50% iled 0% iled ( led turned off) binary: 000000 (0)
ISL97691 fn7840 rev.2.00 page 10 of 19 sep 8, 2017 figure 15. 3d application timing diagram w )5$0( &k /('v &k /('v 3:0 'lpplqj w / w 5 , /(' , /(' 3:0 'lpplqj w 3:0b21 w 3:0 w 3:0b21 w 3:0 i 3:0 w 3:0 figure 16. 2d application timing diagram w 3:0b21 w )5$0( w / , /(' 3:0 'lpplqj 3:0 'lpplqj w 5 , /(' w 3:0 w 3:0b21 w 3:0 &k /('v &k /('v w )5$0( w / , /(' 3:0 'lpplqj 3:0 'lpplqj w 5 , /(' &k /('v &k /('v w '(/$< i 3: 0 w 3: 0 figure 17. 1-wire interface ?1? ?0? ?0? ?1? ?0? ?1? ?load? 25s (15~45s) 0 200s 400s 600s 800s 1ms 1.2ms 1.4ms 1.6ms 1.8ms time 100s (90~120s) 250s (218s min)
ISL97691 fn7840 rev.2.00 page 11 of 19 sep 8, 2017 theory of operation pwm boost converter the current mode pwm boost converter produces the minimal voltage needed to enable the led stack with the highest forward voltage drop to run at the programmed current. the ISL97691 employs current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. this architecture achieves the fast transient response which is essential for portable product backlight applications where the backlight must not flicker when the power source is changed from a drained battery to an ac/dc adapter. the number of leds that can be driven by the ISL97691 depends on the type of led chosen in the application. the maximum output is 26v at 40ma from 2.7v input, or 21v at 60ma from 2.7v input with 30% dimming duty. autoshutdown the ISL97691 simplifies the implementation of low power shutdown by detecting that both pwm inputs 1-wire_1 and 1-wire_2 have been low for 120ms (typical). when this timeout is detected on both 1-wire_1 and 1-wire_2, the boost converter and led string drivers are turned off while retaining the value of the two internal 6-bit 1-wire re gisters which store the analog dimming values. the 1-wire interfaces may be written during shutdown mode subject to the following constraints: ? any interface (1-wire_1 or 1-wire_2) to be written during shutdown should idle hi gh between transmissions ? the first bit of every 6-bit 1-wi re transmission must be sent with a tighter timing toleranc e than normal (25s minimum for logic 1, 100s minimum for logic 0). the extra 10s allows the ISL97691 to wakeup and measure the transmission. it is recommended that applications requiring 1-wire transmissions during shutdown simply apply the constraints described above to all transmissions. dimming controls the ISL97691 provides two groups, channels 1 and 2 as one group and channels 3 and 4 as the other group, with independent analog and pwm dimming. the maximum led current is set globally for all channels by r set in the range 15ma to 60ma per equation 1 : where: r set is resistor from iset pin to gnd ( ? i ledmax is the peak current set by resistor r set (a) for example, if the maximum required led current (i ledmax ) is 60ma, then the r set value needed is: choose nearest standard resistor: 17.8k ?? 0.1% analog dimming the channel peak current for the two groups may be reduced from the maximum led current set by r set by analog dimming through two 6-bit dacs. the dacs are updated with simple negative pulse duration and pulse counting 1-wire interfaces. channels 1 and 2 are set through the 1-wire_1 pin, and channels 3 and 4 are set through the 1-wire_2 pin. the two 1-wire interfaces are independent of the two pwm inputs pwmi_1 and pwmi_2, and any combination of these 4 inputs may be active at the same time. the 1-wire interface provides 6-bit (64-level) analog dimming resolution. the interface uses a normally high connection for use with open-drain driving schemes and intersil?s 1-wire interface. when held low for between 15s and 45s, the interface reads a logic 1. when held low for between 90s and 120s the interface reads a logic 0. when held low for greater that 215s, the interface loads the last 6 bi ts into the brightness control register and updates the peak current. the required minimum high time is 3s. the 1-wire programming is summarized as follows: ? logic 0 = negative pulse >90s and <120s ? logic 1 = negative pulse >15s and <45s ? load = negative pulse >215s figure 18 shows an example of transmitting and loading the value b?100101?. the serial interface defaults to b?111111? (63) on power-up. the maximum led current i ledmax set by resistor r set for each of the two channel groups 1 and 2 is digitally adjusted by each channel?s brightness control register per equation 3 : where: n is the integer value 1 to 63 in the channel groups? brightness control register i ledmax is the peak current set by resistor r set (a) i ledmax 1066 r set --------------- = (eq. 1) r set 1066 0.06 ? 17.8k ? == (eq. 2) + - + - pwm signal ref + - 1-wire data 6-bit dac figure 18. i led i ledmax n 63 ------ ? = (eq. 3)
ISL97691 fn7840 rev.2.00 page 12 of 19 sep 8, 2017 pwm dimming the ISL97691 employs direct pwm dimming such that the output pwm dimming follows directly with the input pwm signal without modifying the input frequency. pwm dimming for channels 1 and 2 are set by the pwmi_1 pin, and channels 3 and 4 are set by the pwmi_2 pin. these two pwm inputs are independent of the two 1-wire interfaces 1-wire_1 and 1-wire_2, and any combination of these 4 inputs may be active at the same time. the average led current of each channel can be calculated as equation 4 : where: i led is the current set by 1-wire_n interface (a) pwm is the duty of the signal at the pwmi_n pin during the pwm off-time, the two 1-wire data will remain at the previous programmed levels. current matching and current accuracy each channel of the led current is regulated by a current sink circuit. the led peak current is set by the external r set resistor according to equation 1 . the current sink mosfets in each led driver channel output are designed to operate within a range of about 300mv to optimize power loss versus accuracy requirements. the sources of errors of the channel-to-channel current matching come from intern al amplifier offsets, internal layout and reference accuracy. these parameters are optimized for current matching and absolute current accuracy. absolute accuracy is also determined by the external resistor r set , so a 0.1% tolerance resistor is recommended. dynamic headroom control the ISL97691 features a proprietary dynamic headroom control circuit that detects the highest forward voltage string or effectively the lowest voltage on any of the channel pins. when this lowest channel voltage is lower than the short circuit threshold, v sc , such voltage will be used to help set the output voltage of the boost regulator. the boost regulates the output to the correct level such that the lowest channel pin is at the target headroom voltage. since all led stacks are connected to the same output voltage, the other channel pins will have a higher voltage, but the regulated current sink circuit on each channel will ensure that each channel has the same current. soft-start once the ISL97691 is powered up, the boost regulator will begin to switch and the current in the inductor will ramp-up. the current in the boost power switch is monitored and the switching is terminated in any cycle where the current exceeds the current limit. the ISL97691 includes a soft-start feature where this current limit starts at a low value (350ma). this is stepped up to the final 2.8a current limit in 7 further steps of 350ma. these steps will happen over typically 7ms, and will be extended at low led pwm frequencies if the led duty cycle is low. this allows the output capacitor to be charged to the required value at a low current limit and prevents high input current for systems that have only a low to medium output current requirement. note that there will be also an initial in-rush current to c out when v in is applied. this is determined by the ramp rate of v in and the values of c out and l. power-off sequence operation with input voltage greater than 5.5v the ISL97691 boost regulator can operate from an input voltage higher than 5.5v, and up to 23v, as long as an additional supply voltage between 2.4v and 5.5v is available for the vin pin. please refer to figure 21 for a typical application schematic adopting this solution. i led ave ?? i led pwm ? = (eq. 4) figure 19. vin vo 1_wire_n pwmi ichn soft-start (7ms) feedback regulation established uvlo (rising) figure 20. vin vo 1_wire_n pwmi_n chn v uvlo - 150mv boost converter turned off t off after reaching (v uvlo - 150mv) depends on application
ISL97691 fn7840 rev.2.00 page 13 of 19 sep 8, 2017 component selection the design of the boost converte r is simplified by an internal compensation scheme allowing ea sy design without complicated calculations. please select your component values using the recommendations below. input capacitor it is recommended that a 4.7f to 10f x5r/x7r or equivalent ceramic input capacitor is used. overvoltage protection (ovp) the integrated ovp circuit monitors the boost output voltage, v out , and keeps the voltage at a safe le vel. the ovp threshold is set as shown in equation 5 : where: v ovp is the maximum boost output voltage, v out (v) r 1 is the resistor from ovp pin to the boost output ( ) r 2 is the resistor from ovp pin to gnd ( ) the total r 1 plus r 2 series resistance should be high to minimize power loss through the resistor network. for example, choosing r 1 =470k and r 2 = 23.7k per the ? typical application circuit ? on page 1 , sets v ovp (typ) to 25.41v (equation 6 ). the ovp threshold, r 1 , and r 2 tolerances should also be taken into account (equations 7 and 8 ). calculating v ovp using the ovp threshold range (1.18v to 1.24v) and 0.1% resistor tolerances gives an actual v ovp range of 24.53v to 25.88v for the 25.4v example above (equations 9 and 10 ). it is recommended that parallel capacitors are placed across the ovp resistors such that r 1 /r 2 = c 2 /c 1 . using a c 1 value of at least 30pf is recommended. these capacitors reduce the ac impedance of the ovp node, which reduces noise susceptibility when using high value resistors. fsw fpwm agnd ovp vin sda/pwmi iset comp scl d1 ch1 ch2 ch3 ch4 pgnd lx v batt : 2.4v~21.8v v out : 24.5v, 6 x 20ma ch5 ch6 l1 10h 12k 15nf 4.7f 4.7f 470k 23.7k 143k 291k 53k 100pf 2.2nf ISL97691 4.7f en 2.4v~5.5v ? ? ? ? ? ? figure 21. led driver operation with input voltage up to 26v v ovp typ ?? 1.22v r1 r2 + r2 ---------------------- ? = (eq. 5) v ovp typ ?? 1.22v 470 23.7 + 23.7 --------------------------- - ? 25.41v == (eq. 6) v ovp min ?? 1.18v r1min r2max + r2max --------------------------------------------- - ? = (eq. 7) v ovp max ?? 1.24v r1max r2min + r2min --------------------------------------------- - ? = (eq. 8) v ovp min ?? 1.18v 470 0.999 ? ?? 23.7 1.001 ? ?? + 23.7 1.001 ? ?? --------------------------------------------------------------- ---------------- - ? 24.53v == (eq. 9) v ovp max ?? 1.24v 470 1.001 ? ?? 23.7 0.999 ? ?? + 23.7 0.999 ? ?? --------------------------------------------------------------- ---------------- - ? 25.88v == (eq. 10)
ISL97691 fn7840 rev.2.00 page 14 of 19 sep 8, 2017 boost output voltage range the working range of the boost output voltage, v out is from 40% to 100% of the maximum output voltage, v ovp , set by resistors r 1 and r 2 as described in the previous section. the target applications should be co nsidered carefully to ensure that v ovp is not set unnecessarily high. for example, using r 1 = 470k and r 2 = 23.7k per the typical application circuit on page 2 sets v ovp to between 24.53v to 25.88v when tolerancing is considered. the minimum voltage, v ovp (min) = 24.53v, sets the maximum number of leds per channel because this the worst case minimum voltage that the boost co nverter is guaranteed to supply. the maximum voltage, v ovp (max) = 25.88v, sets the minimum number of leds per channel beca use it sets the lowest voltage that the boost converter is guaranteed to reach: 40% x 25.88v = 10.35v. using leds with a v f tolerance of 3v to 4v, this v ovp example is suitable for strings of 4 to 6 leds. if fewer than 4 leds per channel are specified, v ovp must be reduced. switching frequency the boost switching frequency is adjusted by resistor r fsw (equation 11 ): where: f sw is the desirable boost switching frequency (hz) r fsw is resistor from fsw pin to gnd ( ) inductor choose the inductance according to table 1 : the inductor saturation current rating should be at least the figure provided by equation 12 : where: i l is the minimum inductor sa turation current rating (a) v out is the maximum output voltage set by ovp (v) i led is the sum of the channel currents (a) vin is the minimum input voltage (v) if the calculation produces a curre nt rating higher than the 3.15a maximum boost switch current limit, then a 3a inductor current rating is adequate. for example, for a system using 4 led channels with 30ma per channel and a maximum output voltage (ovp) of 24.53v with an input supply of 2.7v minimum: output capacitor it is recommended that a 2.2f to 3.3f x5r/x7r or equivalent ceramic output capacitor is used. schottky diode the schottky diode should be rated for at least the same forward current as the inductor, and for reverse voltage to at least the maximum output voltage, ovp. compensation the ISL97691?s boost regulator uses a current mode control architecture with a standardised external compensation network connected to the comp pin. the component values shown in the typical application circuit, figure 1 , on page 1 should be used. the network comprises a series rc of 12k and 15nf also from comp to gnd. applications unused led channels connect unused led channels to gnd. high current applications each channel of the ISL97691 supports 40ma continuous sink current. for applications that need higher current, multiple channels can be paralleled (table 2 ). the example below shows ch1 and ch2 paralleled. table 1. inductor selection boost frequency inductance 400khz to 700khz 10h to 15h 700khz to 1mhz 6.8h to 10h 1mhz to 1.5mhz 4.7h to 8.2h 1.5mhz 3.3h to 4.7h f sw 8.65 10 ? 10 ?? r fsw ------------------------------- - = (eq. 11) i l 1.35 v out i led ? ? v in ---------------------------------------------------- - = (eq. 12) table 2. paralleling channels for higher current total channels channel current channel connections 4 40ma per channel ch1, ch2, ch3, ch4 2 80ma per channel {ch1 & ch2}, {ch3 & ch4} 1 160ma {ch1 & ch2 & ch3 & ch4} note: pwmi_1 and pwmi_2 must driven together for total channels 1. i l 1.35 24.53 4 0.03 ? ?? ? ? 2.7 --------------------------------------------------------------- - - 1.47a == (eq. 13) ch1 ch2 figure 22.
ISL97691 fn7840 rev.2.00 page 15 of 19 sep 8, 2017 pcb layout considerations pcb layout with tqfn package great care is needed in designing a pc board for stable ISL97691 operation. as shown in the ? typical application circuit ? on page 1 , the separation of pgnd and agnd is essential, keeping the agnd referenced only local to the chip. this minimizes switching noise injection to th e feedback sensing and analog areas, as well as eliminating dc e rrors form high current flow in resistive pc board traces. pgnd and agnd should be on the top and bottom layers respectively in the two layer pcb. a star ground connection should be formed by connecting the led ground return and agnd pins to the thermal pad with vias (figure 23 ). the ground connection shou ld be into this ground net, on the top plane. the bottom plane then forms a quiet analog ground area that both shields components on the top plane, as well as providing easy access to all sensitive components. for example, the grou nd side of the iset resistor can be dropped to the bottom plane, providing a very low impedance path back to the agnd pin, which does not have any circulating high currents to inte rfere with it. the bottom plane can also be used as a thermal ground, so the agnd area should be sized sufficiently large to dissipate the required power. for multi-layer boards, the agnd plane can be the second layer. this provides easy access to the agnd net, but allows a larger thermal ground and main ground supply to come up through the thermal vias from a lower plane. figure 24 shows the example of the pcb layout of ISL97691. this type of layout is particularly im portant for this type of product, resulting in high current flow in the main loop?s traces. careful attention should be focused in the following layout details: 1. boost input capacitors (cin), output capacitors (cout), inductor and schottky diode shou ld be placed together in a nice tight layout. keeping the gr ounds of the input, and output connected with low impedance and wide metal is very important to keep these nodes closely coupled. 2. if possible, try to maintain central ground node on the board and use the input capacitors to avoid excessive input ripple for high output current supplies. th e filtering capacitors should be placed close to the vin pin. 3. for optimum load regulation and true vout sensing, the ovp resistors should be connected in dependently to the top of the output capacitors and away from the higher dv/dt traces. the ovp connection then needs to be as short as possible to the pin. the agnd connection of the lower ovp components is critical for good regulation. 4. the comp network and the rest of the analog components (on iset, fsw, etc.) should be referenced to agnd. 5. the heat of the chip is main ly dissipated through the exposed thermal pad so maximizing the copper area around is a good idea. a solid ground is always helpful for the thermal and emi performance. 6. the inductor and input and output capacitors should be mounted as tight as possible, to reduce the audible noise and inductive ringing. general power pad de sign considerations figure 23 shows an example of how to use vias to remove heat from the ic. we recommend you fill the thermal pad area with vias. a typical via array would be to fill the thermal pad foot print with vias spaced such that the ce ntre to centre spacing is three times the radius of the via. keep the vias small, but not so small that their inside diameter prevents solder wicking through the holes during reflow. figure 23. via pattern of ISL97691 tqfn
ISL97691 fn7840 rev.2.00 page 16 of 19 sep 8, 2017 fault protection and monitoring the ISL97691 features extensive protection functions to handle failure conditions automatically. refer to figure 15 and table 3 for details of the fault protections. the led failure mode is either op en or short circuit. an open circuit failure of an led only results in the loss of one channel of leds without affecting other chan nels. similarly, a short circuit condition on a channel that result s in that channel being turned off does not affect other channels. due to the lag in boost response to any load change at its output, certain transient events (such as led current steps or significant step changes in led duty cycle) can transiently look like led fault modes. the ISL97691 uses feedback from the leds to determine when it is in a stable operating region and prevents apparent faults during these tran sient events from allowing any of the led stacks to fault out. see table 3 for more details. short circuit protection (scp) the short circuit detection circuit monitors the voltage on each channel and disables faulty channels which are above the short circuit protection threshold, nomi nally 8v (the action taken is described in table 3 ). open circuit protection (ocp) when one of the leds becomes op en circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. the ISL97691 monitors the current in each channel such that any string which reaches the intended output current is considered ?good?. should the cu rrent subsequently fall below the target, the channel will be considered an ?open circuit?. furthermore, should the boost output of the ISL97691 reach the v ovp limit, all channels which are not ?good? will immediately be considered as ?open circuit?. detection of an ?open circuit? ch annel will result in a time-out before disabling of the affected channel. undervoltage lockout if the input voltage falls below the v uvlo level of ~2.15v, the ISL97691 will stop switching and be reset. operation will restart only if the v in is back in the normal operating range. over-temperature protection (otp) the ISL97691 has an over-temperature protection threshold set to +150c. if this threshold is reached, the boost stops switching and the channel output current sinks are switched off. the ISL97691 can be restarted by toggling v in to below the v uvlo level of ~2.15v, then back up to the normal input voltage level. figure 24. example of pcb layout
ISL97691 fn7840 rev.2.00 page 17 of 19 sep 8, 2017 figure 25. simplified fault protections qx chx dc1 pwm/oc1/sc1 ref fet driver lx imax ilimit ovp vin t2 otp thrm shdn q1 vsc ch1 vout dc2 pwm/ocx/scx temp sensor logic t1 otp thrm shdn o/p short fault detect logic pwm generator fault flag table 3. protections table case failure mode detection mode failed channel action good channels action v out regulated by 1 ch1 short circuit over-temperature protection (otp) not triggered, ch1 < 8v ch1 on and burns power ch2 through ch4 normal highest led string v f of ch2 - ch4 2 ch1 short circuit otp triggered boost conv erter and channels are shut down until v in is cycled - 3 ch1 short circuit otp not triggered, ch1 > 8v ch1 disabled after 190ms time-out ch2 through ch4 normal highest led string v f of ch2 - ch4 4 ch1 open circuit with infinite resistance otp not triggered, ch1 < 8v v out will ramp to ovp. ch1 will time-out after 190ms and switch off. v out will then reduce to normal level ch2 through ch4 normal highest led string v f of ch2 - ch4 5output led stack voltage too high v out = v ovp any channel that is below the target current will time-out after 190ms while v out is regulated at v ovp , and v out will then return to the normal regulation voltage required for other channels highest led string v f of ch1 - ch4
fn7840 rev.2.00 page 18 of 19 sep 8, 2017 ISL97691 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2012-2017. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. for the most updated datasheet, application notes, related documentation, and related parts, see the respective product information page found at www.intersil.com . for a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary . you can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please visi t our website to make sure you have the latest revision. date revision change september 8, 2017 fn7840.2 applied new header/footer. added related literature on page 1. updated ordering information notes. added v headroom_range spec to electrical specifications table. added corresponding note 11. in the current matching and current accuracy section - updated 2nd sentence in paragraph 2 for clarification. updated about intersil section. november 26, 2012 fn7840.1 updated features on page 1. removed en from pwm_2 pin in typical application circ uit on page 1 and from the pwmi_2 in block diagram on page 2. added ?operation with input voltage greater than 5.5v? on page 12. added figure ?led driver operation with input voltage up to 26v? on page 13. in ?absolute maximum ratings? on page 5, changed hbm from 2kv to 2.5kv. changed cdm from 1kv to 2kv. june 13, 2012 fn7840.0 initial release.
ISL97691 fn7840 rev.2.00 page 19 of 19 sep 8, 2017 package outline drawing l16.3x3d 16 lead thin quad flat no-lead plastic package rev 0, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.25mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.15 index area pin 1 a 3.00 b 3.00 pin #1 b 0.10 m a c 4 6 6 0.05 1 12 4 9 13 16 8 5 1.60 sq 16x 0.23 16x 0.400.10 4x 1.50 12x 0.50 (16x 0.60) ( 1.60) (2.80 typ) (16x 0.23) (12x 0.50) c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 0.75 0.05 0.08 0.10 c c c index area see detail x jedec reference drawing: mo-220 weed. 7. for the most recent package outline drawing, see l16,3x3d .

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