View SN74SSTU32864_9039998.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 1 post office box 655303 ? dallas, texas 75265 member of the texas instruments widebus+ ? family pinout optimizes ddr-ii dimm pcb layout configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer chip-select inputs gate the data outputs from changing state and minimizes system power consumption output edge-control circuitry minimizes switching noise in an unterminated line supports sstl_18 data inputs differential clock (clk and clk ) inputs supports lvcmos switching levels on the control and reset inputs reset input disables differential input receivers, resets all registers, and forces all outputs low latch-up performance exceeds 100 ma per jesd 78, class ii esd protection exceeds jesd 22 ? 5000-v human-body model (a114-a) ? 200-v machine model (a115-a) ? 1000-v charged-device model (c101) description/ordering information this 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-v to 1.9-v v cc operation. in the 1:1 pinout configuration, only one device per dimm is required to drive nine sdram loads. in the 1:2 pinout configuration, two devices per dimm are required to drive 18 sdram loads. all inputs are sstl_18, except the lvcmos reset (reset ) and lvcmos control (cn) inputs. all outputs are edge-controlled circuits optimized for unterminated dimm loads and meet sstl_18 specifications. the SN74SSTU32864 operates from a differential clock (clk and clk ). data are registered at the crossing of clk going high and clk going low. the c0 input controls the pinout configuration of the 1:2 pinout from register-a configuration (when low) to register-b configuration (when high). the c1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). c0 and c1 should not be switched during normal operation. they should be hard-wired to a valid low or high level to configure the register in the desired mode. in the 25-bit 1:1 pinout configuration, the a6, d6, and h6 terminals are driven low and should not be used. the device supports low-power standby operation. when reset is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (v ref ) inputs are allowed. in addition, when reset is low, all registers are reset and all outputs are forced low. the lvcmos reset and cn inputs always must be held at a valid logic high or low level. the two v ref pins (a3 and t3), are connected together internally by approximately 150 ? . however, it is necessary to connect only one of the two v ref pins to the external v ref power supply. an unused v ref pin should be terminated with a v ref coupling capacitor. ordering information t a package ? orderable part number top-side marking 0 c to 70 c lfbga ? gke tape and reel SN74SSTU32864gker su864 ? package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. copyright ? 2003, texas instruments incorporated widebus+ is a trademark of texas instruments. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 2 post office box 655303 ? dallas, texas 75265 description/ordering information (continued) the device also supports low-power active operation by monitoring both system chip select (dcs and csr ) inputs and will gate the qn outputs from changing states when both dcs and csr inputs are high. if either dcs or csr input is low, the qn outputs function normally. the reset input has priority over the dcs and csr control and forces the output low. if the dcs control functionality is not desired, the csr input can be hard-wired to ground, in which case, the setup-time requirement for dcs is the same as for the other d data inputs. to ensure defined outputs from the register before a stable clock has been supplied, reset must be held in the low state during power up. terminal assignments for 1:1 register (c0 = 0, c1 = 0) 12345 6 a d1 (dcke) nc v ref v cc q1 (qcke) dnu b d2 d15 gnd gnd q2 q15 c d3 d16 v cc v cc q3 q16 d d4 (dodt) nc gnd gnd q4 (qodt) dnu e d5 d17 v cc v cc q5 q17 f d6 d18 gnd gnd q6 q18 g nc reset v cc v cc c1 c0 h clk d7 (dcs ) gnd gnd q7 (qcs ) dnu j clk csr v cc v cc nc nc k d8 d19 gnd gnd q8 q19 l d9 d20 v cc v cc q9 q20 m d10 d21 gnd gnd q10 q21 n d11 d22 v cc v cc q11 q22 p d12 d23 gnd gnd q12 q23 r d13 d24 v cc v cc q13 q24 t d14 d25 v ref v cc q14 q25 each pin name in parentheses indicates the ddr-ii dimm signal name. nc ? no internal connection dnu ? do not use gke package (top view) j h g f e d c b a 2 134 6 5 p n m l k t r
SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 3 post office box 655303 ? dallas, texas 75265 logic diagram for 1:1 register configuration (positive logic) d clk r to 21 other channels (d3, d5, d6, d8 ? d25) g2 a5 reset q1 (qcke) j1 clk h1 clk a3, t3 v ref a1 d1 (dcke) d clk r d5 q4 (qodt) d1 d4 (dodt) d clk r h5 q7 (qcs ) h2 d7 (dcs ) j2 csr b1 d2 d clk r b5 q2 one of 22 channels ce
SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 4 post office box 655303 ? dallas, texas 75265 terminal assignments for 1:2 register a (c0 = 0, c1 = 1) 123456 a d1 (dcke) nc v ref v cc q1a (qckea) q1b (qckeb) b d2 dnu gnd gnd q2a q2b c d3 dnu v cc v cc q3a q3b d d4 (dodt) nc gnd gnd q4a (qodta) q4b (qodtb) e d5 dnu v cc v cc q5a q5b f d6 dnu gnd gnd q6a q6b g nc reset v cc v cc c1 c0 h clk d7 (dcs ) gnd gnd q7a (qcsa ) q7b (qcsb ) j clk csr v cc v cc nc nc k d8 dnu gnd gnd q8a q8b l d9 dnu v cc v cc q9a q9b m d10 dnu gnd gnd q10a q10b n d11 dnu v cc v cc q11a q11b p d12 dnu gnd gnd q12a q12b r d13 dnu v cc v cc q13a q13b t d14 dnu v ref v cc q14a q14b each pin name in parentheses indicates the ddr-ii dimm signal name. nc ? no internal connection dnu ? do not use gke package (top view) j h g f e d c b a 2 134 6 5 p n m l k t r
SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 5 post office box 655303 ? dallas, texas 75265 logic diagram 1:2 register-a configuration (positive logic) d clk r to 10 other channels (d3, d5, d6, d8 ? d14) g2 a5 reset q1a (qckea) j1 clk h1 clk a3, t3 v ref a1 d1 (dcke) a6 q1b (qckeb) d clk r d5 q4a (qodta) d1 d4 (dodt) d6 q4b (qodtb) d clk r h5 q7a (qcsa ) h2 d7 (dcs ) h6 q7b (qcsb ) j2 csr b1 d2 clk r b5 q2a b6 q2b one of eleven channels ce d
SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 6 post office box 655303 ? dallas, texas 75265 terminal assignments for 1:2 register b (c0 = 1, c1 = 1) 123456 a d1 nc v ref v cc q1a q1b b d2 dnu gnd gnd q2a q2b c d3 dnu v cc v cc q3a q3b d d4 nc gnd gnd q4a q4b e d5 dnu v cc v cc q5a q5b f d6 dnu gnd gnd q6a q6b g nc reset v cc v cc c1 c0 h clk d7 (dcs ) gnd gnd q7a (qcsa ) q7b (qcsb ) j clk csr v cc v cc nc nc k d8 dnu gnd gnd q8a q8b l d9 dnu v cc v cc q9a q9b m d10 dnu gnd gnd q10a q10b n d11 (dodt) dnu v cc v cc q11a (qodta) q11b (qodtb) p d12 dnu gnd gnd q12a q12b r d13 dnu v cc v cc q13a q13b t d14 (dcke) dnu v ref v cc q14a (qckea) q14b (qckeb) each pin name in parentheses indicates the ddr-ii dimm signal name. nc ? no internal connection dnu ? do not use gke package (top view) j h g f e d c b a 2 134 6 5 p n m l k t r
SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 7 post office box 655303 ? dallas, texas 75265 logic diagram 1:2 register-b configuration (positive logic) d clk r to 10 other channels (d2 ? d6, d8 ? d10, d12 ? d13) g2 t5 reset q14a (qckea) j1 clk h1 clk a3, t3 v ref t1 d14 (dcke) t6 q14b (qckeb) d clk r n5 q11a (qodta) n1 d11 (dodt) n6 q11b (qodtb) d clk r h5 q7a (qcsa ) h2 d7 (dcs ) h6 q7b (qcsb ) j2 csr a1 d1 d clk r a5 q1a a6 q1b one of eleven channels ce
SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 8 post office box 655303 ? dallas, texas 75265 terminal functions terminal name description electrical characteristics gnd ground ground input v cc power-supply voltage 1.8 v nominal v ref input reference voltage 0.9 v nominal clk positive master clock input differential input clk negative master clock input differential input c0, c1 configuration control inputs ? register a, register b, 1:1, 1:2 select lvcmos inputs reset asynchronous reset input ? resets registers and disables v ref data and clock differential-input receivers lvcmos input d1 ? d25 data inputs ? clocked in on the crossing of the rising edge of clk and the falling edge of clk sstl_18 inputs csr , dcs chip select inputs ? disables d1-d25 ? outputs switching when both inputs are high sstl_18 inputs dodt the outputs of this register bit will not be suspended by the dcs and csr control. sstl_18 input dcke the outputs of this register bit will not be suspended by the dcs and csr control. sstl_18 input q1 ? q25 ? data outputs that are suspended by the dcs and csr control 1.8 v cmos outputs qcs data output that will not be suspended by the dcs and csr control 1.8 v cmos output qodt data output that will not be suspended by the dcs and csr control 1.8 v cmos output qcke data output that will not be suspended by the dcs and csr control 1.8 v cmos output nc no internal connection dnu do not use ? inputs are in standby-equivalent mode, and outputs are driven low. ? data inputs = d2, d3, d5, d6, d8 ? d25 when c0 = 0 and c1 = 0 data inputs = d2, d3 d5, d6, d8 ? d14 when c0 = 0 and c1 = 1 data inputs = d1 ? d6, d8 ? d10, d12, d13 when c0 = 1 and c1 = 1. ? data outputs = q2, q3, q5, q6, q8 ? q25 when c0 = 0 and c1 = 0 data outputs = q2, q3 q5, q6, q8 ? q14 when c0 = 0 and c1 = 1 data outputs = q1 ? q6, q8 ? q10, q12, q13 when c0 = 1 and c1 = 1.
SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 9 post office box 655303 ? dallas, texas 75265 function tables inputs output reset dcs csr clk clk dn qn h l x l l h lx hh h xl ll h xl hh h hh xq 0 h x x l or h l or h x q 0 l x or floating x or floating x or floating x or floating x or floating l inputs outputs reset clk clk dcke, dcs , dodt qcke, qcs , qodt h h h h ll h l or h l or h x q 0 l x or floating x or floating x or floating l absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, v cc ? 0.5 v to 2.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see notes 1 and 2) ? 0.5 v to 2.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o (see notes 1 and 2) ? 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through each v cc or gnd 100 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 3) 36 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observe d. 2. this value is limited to 2.5 v maximum. 3. the package thermal impedance is calculated in accordance with jesd 51-7.
SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 10 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 4) min nom max unit v cc supply voltage 1.7 1.9 v v ref reference voltage 0.49 v cc 0.5 v cc 0.51 v cc v v i input voltage 0 v cc v v ih ac high-level input voltage data inputs, csr v ref +250 mv v v il ac low-level input voltage data inputs, csr v ref ? 250 mv v v ih dc high-level input voltage data inputs, csr v ref +125 mv v v il dc low-level input voltage data inputs, csr v ref ? 125 mv v v ih high-level input voltage reset , cn 0.65 v cc v v il low-level input voltage reset , cn 0.35 v cc v v icr common-mode input voltage range clk, clk 0.675 1.125 v v i(pp) peak-to-peak input voltage clk, clk 600 mv i oh high-level output current ? 8 ma i ol low-level output current 8 ma t a operating free-air temperature 0 70 c note 4: the reset and cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. the differential inputs must not be floating unless reset is low. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004.
SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 11 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ ? max unit v oh i oh = ? 100 a 1.7 v to 1.9 v v cc ? 0.2 v v oh i oh = ? 6 ma 1.7 v 1.2 v v ol i ol = 100 a 1.7 v to 1.9 v 0.2 v v ol i ol = 6 ma 1.7 v 0.5 v i i all inputs ? v i = v cc or gnd 1.9 v 5 a i cc static standby reset = gnd i o =0 19v 100 a i cc static operating reset = v cc , v i = v ih(ac) or v il(ac) i o = 0 1 . 9 v 40 ma dynamic operating ? clock only reset = v cc , v i = v ih(ac) or v il(ac) , clk and clk switching 50% duty cycle 28 a/ mhz i ccd dynamic operating ? per each data input, 1:1 configuration reset = v cc , v i = v ih(ac) or v il(ac) , clk and clk switchin g 50% dut y c y cle , i o = 0 1.8 v 18 a/ clock dynamic operating ? per each data input, 1:2 configuration c a d c s c g 50% du y cyc e, one data input switching at one-half clock frequency, 50% duty cycle 36 mhz/ d input chip-select-enabled low-power active mode ? clock only reset = v cc , v i = v ih(ac) or v il(ac) , clk and clk switching 50% duty cycle 27 a/ mhz i ccdlp chip-select-enabled low-power active mode ? 1:1 configuration reset = v cc , v i = v ih(ac) or v il(ac) , clk and clk switchin g 50% dut y c y cle , i o = 0 1.8 v 2 a/ clock chip-select-enabled low-power active mode ? 1:2 configuration c a d c s c g 50% du y cyc e, one data input switching at one-half clock frequency, 50% duty cycle 2 mhz/ d input data inputs, csr v i = v ref 250 mv 2.5 3 3.5 c i clk, clk v icr = 0.9 v, v i(pp) = 600 mv 1.8 v 2 3 pf reset v i = v cc or gnd 2.5 ? all typical values are at v cc = 1.8 v, t a = 25 c. ? each v ref pin (a3 or t3) should be tested independently, with the other (untested) pin open. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see figure 1 and note 5) min max unit f clock clock frequency 500 mhz t w pulse duration, clk, clk high or low 1 ns t act differential inputs active time (see note 6) 10 ns t inact differential inputs inactive time (see note 7) 15 ns dcs before clk , clk , csr high; csr before clk , clk , dcs high 0.7 t su setup time dcs before clk , clk , csr low 0.5 ns dodt, dcke, and data before clk , clk 0.5 t h hold time dcs , dodt, dcke, and data after clk , clk 0.5 ns notes: 5. all input slew rates are 1 v/ns 20%. 6. v ref must be held at a valid input level and data inputs must be held low for a minimum time of t act max, after reset is taken high. 7. v ref , data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of t inact max, after reset is taken low.
SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 12 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see figure 1) parameter from (input) to (output) v cc = 1.8 v 0.1 v unit (input) (output) min max f max 500 mhz t pdm ? clk and clk q 1.4 2.5 ns t pdmss ? clk and clk q 2.7 ns t rphl ? reset q 3 ns ? includes 350-ps test-load transmission-line delay output slew rates over recommended operating free-air temperature range (unless otherwise noted) (see figure 2) parameter from to v cc = 1.8 v 0.1 v unit min max dv/dt_r 20% 80% 1.9 4.9 v/ns dv/dt_f 80% 20% 1.9 4.9 v/ns dv/dt_ ? 20% or 80% 80% or 20% 1 v/ns difference between dv/dt_r (rising edge rate) and dv/dt_f (falling edge rate)
SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 13 post office box 655303 ? dallas, texas 75265 parameter measurement information v cc /2 voltage and current waveforms inputs active and inactive times notes: a. c l includes probe and jig capacitance. b. i cc tested with clock and data inputs held at v cc or gnd, and i o = 0 ma. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , input slew rate = 1 v/ns 20% (unless otherwise noted). d. the outputs are measured one at a time with one transition per measurement. e. v ref = v cc /2 f. v ih = v ref + 250 mv (ac voltage levels) for differential inputs. v ih = v cc for lvcmos input. g. v il = v ref ? 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. h. v i(pp) = 600 mv i. t plh and t phl are the same as t pd . 0 v v cc t h t su voltage waveforms setup and hold times timing inputs v icr v ref input v il v ih v ref v i(pp) t phl v oh v ol output v tt v tt t plh t phl v ih v il v ol v oh lvcmos reset input output voltage waveforms propagation delay times v tt v cc /2 v i(pp ) v icr timing inputs v icr voltage waveforms propagation delay times v cc /2 v ref input v ref t w voltage waveforms pulse duration v ih v il lvcmos reset input t act t inact 10% 90% i cc (operating) i cc (standby) i cc (see note b) clock inputs load circuit r l = 1 k ? v cc z o = 50 ?, t d = 350 ps z o = 50 ?, t d = 350 ps c l = 30 pf (see note a) output test point dut r l = 100 ? clk out clk z o = 50 ?, t d = 350 ps test point test point r l = 1 k ? figure 1. load circuit and voltage waveforms
SN74SSTU32864 25-bit configurable registered buffer with sstl_18 inputs and outputs sces434 ? march 2003 14 post office box 655303 ? dallas, texas 75265 parameter measurement information notes: a. c l includes probe and jig capacitance. b. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , input slew rate = 1 v/ns 20% (unless otherwise specified). v oh v ol output 20% voltage waveforms high-to-low slew-rate measurement load circuit high-to-low slew-rate measurement v cc c l = 5 pf (see note a) test point dut out r l = 50 ? 80% dt_f dv_f v oh v ol output 20% voltage waveforms low-to-high slew-rate measurement 80% dt_r dv_r load circuit low-to-high slew-rate measurement c l = 5 pf (see note a) test point dut out r l = 50 ? figure 2. output slew-rate measurement information
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) SN74SSTU32864gker active lfbga gke 96 1000 tbd / level-3-220c-168 hr SN74SSTU32864zker active lfbga zke 96 1000 green (rohs & no sb/br) / level-3-250c-1week (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 30-mar-2005 addendum-page 1

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

▲Up To Search▲

Price & Availability of SN74SSTU32864

	To Download SN74SSTU32864 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .