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| S79FL256S/s79fl512s 256 mbit (32 mb)/ 512 mbit (64 mb), 3 v, dual-quad spi flash cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00518 rev. *d revised november 09, 2017 features ? density ? 256 mbit (32 mbytes) ? 512 mbit (64 mbytes) ? serial peripheral interface (spi) ? spi clock polarity and phase modes 0 and 3 ? double data rate (ddr) option ? extended addressing: 24- or 32-bit address options ? read commands ? dual-quad spi quad read: 104 mhz clock rate (104 mb/ s) ? dual-quad spi quad ddr read: 80 mhz clock rate (160 mb/s) ? normal, fast, quad, quad ddr ? autoboot - power up or reset and execute a normal or quad read command automat ically at a preselected address ? common flash interface (cfi) data for configuration information. ? programming (3 mbytes/s) ? 512-byte or 1024-byte page programming buffer options ? quad-input page programming (qpp) for slow clock systems ? automatic ecc - internal hardware error correction code generation with single bit error correction ? erase (1 mbyte/s) ? hybrid sector size option ? physi cal set of thirty two 8-kbyte sectors at top or bottom of address space with all remaining sectors of 128 kbytes ? uniform sector option ? alwa ys erase 512-kbyte blocks for software compatibility with hi gher density and future devices. ? cycling endurance ? 100,000 program-erase cycles on any sector, minimum ? data retention ? 20 year data retention, minimum ? security features ? separate one time program (otp) array of 2048 bytes ? block protection: ? status register bits to control protection against program or erase of a contiguous range of sectors. ? hardware and software control options ? advanced sector protection (asp) ? individual sector protection controlled by boot code or password ? cypress ? 65 nm mirrorbit ? technology with eclipse ? architecture ? core supply voltage: 2.7v to 3.6v ? temperature range: ? industrial (-40c to +85c) ? industrial plus (-40c to +105c) ? automotive, aec-q100 grade 3 (-40c to +85c) ? automotive, aec-q100 grade 2 (-40c to +105c) ? packages (all pb-free) ? 16-lead soic (300 mil) ? software features ? program suspend and resume ? erase suspend and resume ? status register provides status of embedded erase or programming operation ? common flash interface (cfi) compliant ? allows host system to identify the flash device and determine its capabilities ? user-configurable configuration register ? hardware features ? hardware reset input (reset#) - resets device to standby state
document number: 002-00518 rev. *d page 2 of 111 S79FL256S/s79fl512s performance summary maximum read rates sdr dual-quad spi command clock rate (mhz) mbytes/s read 50 12.5 fast read 133 33 quad read 104 104 maximum read ra tes ddr dual-quad spi command clock rate (mhz) mbytes/s ddr quad read 80 160 typical program and erase rates dual-quad spi operation kbytes/s page programming (512-byte page buffer) 2000 page programming (1024-byte page buffer) 3000 8-kbyte physical sector erase (hybrid sector option) 60 128-kbyte physical sector erase (hybrid sector option) 1000 512-kbyte logical sector erase 1000 typical current consumption, dual-quad spi operation current (ma) serial read 50 mhz 32 (max) serial fast read 133 mhz 66 (max) quad read 104 mhz 122 (max) program 200 (max) erase 200 (max) standby 0.14 (typ) document number: 002-00518 rev. *d page 3 of 111 S79FL256S/s79fl512s contents 1. overview ....................................................................... 4 1.1 general description ....................................................... 4 1.2 glossary......................................................................... 4 1.3 other resources............................................................ 5 hardware interface 2. signal descriptions ..................................................... 6 2.1 input/output summary................................................... 6 2.2 multiple input / output (dua l-quad spi) ....... ........... ...... 7 2.3 reset# ........... .............. .............. .............. .............. ...... 7 2.4 multiple input / output (dual- quad) .............. ........... ...... 7 2.5 serial clock (sck) ......................................................... 7 2.6 chip select (cs#) .......................................................... 8 2.7 input output io0 - io7 ................................................... 8 2.8 core voltage supply (v cc ) ............................................ 8 2.9 versatile i/o power supply (v io ) ................................... 8 2.10 supply and signal ground (v ss ) ................................... 8 2.11 not connected (nc) ...................................................... 8 2.12 reserved for future use (rfu )..................................... 8 2.13 do not use (dnu) ................. ........... ............ ........... ...... 8 2.14 block diagrams.............................................................. 9 3. signal protocols ......................................................... 10 3.1 spi clock modes ......................................................... 10 3.2 command protocol ...................................................... 11 3.3 interface states............................................................ 15 3.4 configuration register effects on the interface ........... 18 3.5 data protection ............................................................ 18 4. electrical specifications ............................................ 19 4.1 absolute maximum ratings ...... ................................... 19 4.2 operating ranges........................................................ 19 4.3 power-up and power-down ..... ................................... 20 4.4 dc characteristics ....................................................... 22 5. timing specifications ................................................ 23 5.1 key to switching waveforms . ...................................... 23 5.2 ac test conditions ...................................................... 23 5.3 reset............................................................................ 24 5.4 sdr ac characteristics............................................... 27 5.5 ddr ac characteristics .............................................. 29 6. physical interface ...................................................... 31 6.1 dual-quad soic 16-lead pa ckage.............. ............... 31 6.2 soic 16 physical diagram .......................................... 32 software interface 7. address space maps .................................................. 33 7.1 overview....................................................................... 33 7.2 flash memory array...................................................... 33 7.3 id-cfi address space .................................................. 35 7.4 otp address space ..................................................... 35 7.5 registers....................................................................... 37 8. data protection ........................................................... 46 8.1 secure silicon region (otp). .......... ........... ........... ....... 46 8.2 write enable command.......... ............... .............. ......... 46 8.3 block protection ............................................................ 47 8.4 advanced sector protection ......................................... 48 9. commands .................................................................. 52 9.1 command set summary............................................... 53 9.2 identification commands .............................................. 59 9.3 register access commands......................................... 61 9.4 read memory array commands ............. .............. ....... 70 9.5 program flash array commands ................................. 77 9.6 erase flash array commands...................................... 81 9.7 one time program array commands .......................... 85 9.8 advanced sector protection commands ...................... 86 9.9 reset commands ......................................................... 92 9.10 embedded algorithm performa nce tables ................... 93 10. data integrity ............................................................... 94 10.1 erase endurance .......................................................... 94 10.2 data retention ................... ........................................... 94 11. software interface reference .................................... 95 11.1 command summary ..................................................... 95 11.2 device id and common flash interface (id-cfi) address map................................................... 97 11.3 initial delivery state ........... ......................................... 107 ordering information 12. ordering information S79FL256S/s79fl512s ........ 108 13. revision history ........................................................ 110 document history page ............. .......................................110 sales, solutions, and legal information .........................111 worldwide sales and design supp ort ............ ..............111 products .......................................................................111 psoc? solutions .........................................................111 cypress developer community .. ..................................111 technical support ................... .....................................111 document number: 002-00518 rev. *d page 4 of 111 S79FL256S/s79fl512s 1. overview 1.1 general description the cypress S79FL256S/s79fl512s devices are fl ash non-volatile memory products using: ? mirrorbit technology - that stores two data bits in each memory array transistor ? eclipse architecture - that dramatically improves program and erase performance ? 65 nm process lithography the S79FL256S/s79fl512s devices connect two quad i/o spi devices with a single cs# resulting in an eight bit i/o data path. this byte i/o interface is called dual-quad i/o. these devices connect to a host system via a serial peripheral interface (spi). trad itional spi single bit serial input and out put (io1 and io5) is supported as well as four-bit (quad i/o or qio) serial commands. this mu ltiple width interface is called spi multi- i/o or mio. in addition, these two devices add support for double da ta rate (ddr) read commands for qio that transfers address and read data on both edges of the clock. the eclipse architecture features a page pr ogramming buffer that allows up to 256 words (512 bytes) or 512 words (1024 bytes) to be programmed in one operation, resulting in significantly faster effective programming (up to 2 mb/s or 3 mb/s respectively) a nd erase (up to 1 mb/s) than prior generat ion spi program or erase algorithms. executing code directly from flash memory is often called execute-in-place or xip. by using the s79fl-s devices at the higher c lock rates supported, with qio or ddr-qio comma nds, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, nor flash memories while reducing signal count dramatically. the s79fl-s products offer high density coupled with the fast est read and write performance re quired by a variety of embedded applications. they are ideal for c ode shadowing, xip, and data storage. 1.2 glossary command all information transferred between the host system and memory during one period while cs# is low. this includes the instruction (sometimes calle d an operation code or opcode) and any required address, mode bits, la tency cycles, or data. ddp (dual die package) two die stacked within the same package to increas e the memory capacity of a single package. often also referred to as a multi-chip package (mcp). ddr (double data rate) when input and output are latched on every edge of sck. ecc ecc unit = 16 byte aligned and length data groups in the main flash array and otp array, each of which has its own hidden ecc syndrome to enable error correction on each group. flash the name for a type of electrical erase progra mmable read only memory (eeprom) that erases large blocks of memory bits in parallel, making the erase operatio n much faster than early eeprom. high a signal voltage level v ih or a logic level representing a binary one (1). instruction the 8 bit code indicating the function to be performed by a command (sometimes called an operation code or opcode). the instruction is alwa ys the first 8 bits transferred from host system to the memory in any command. low a signal voltage level ? v il or a logic level representing a binary zero (0). lsb (least significant bit) generally the right most bit, with the lowest order of magnitude value, within a group of bits of a register or data value. msb (most significant bit) generally the left most bit, with the highest order of magnitude value, within a group of bits of a register or data value. non-volatile no power is needed to maintain data stored in the memory. document number: 002-00518 rev. *d page 5 of 111 S79FL256S/s79fl512s 1.3 other resources 1.3.1 cypress flash memory roadmap www.cypress.com/product-roadmaps /cypress-flash-memory-roadmap 1.3.2 links to software www.cypress.com/software-and-d rivers-cypress-flash-memory 1.3.3 links to application notes www.cypress.com/appnotes 1.3.4 specification bulletins specification bulletins provide informatio n on temporary differences in feature desc ription or parametric variance since the publication of the last full data sheet. contact your local sale s office for details. obtain the latest list of company locatio ns and contact information at www.cypress.com/contact-us . opn (ordering part number) the alphanumeric string specifying the memory devi ce type, density, package, factory non-volatile configuration, etc. used to select the desired device. page 512 or 1024 bytes aligned and length group of data. pcb printed circuit board. register bit references are in the format: register_name[bit_number] or register_name[bit_range_msb: bit_range_lsb]. sdr (single data rate) when input is latched on the rising edge and output on the falling edge of sck. sector erase unit size; depending on device model and sector location, this may be 8 kbytes, 128 kbytes or 512 kbytes. write an operation that changes data within volatile or non-volatile registers bits or non-volatile flash memory. when changing non-volatile data, an erase and reprogramming of any unchanged non- volatile data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in the same way that vo latile data is modified ? as a single operation. the non-volatile data appears to the host system to be updated by the si ngle write command, wi thout the need for separate commands for erase and repr ogram of adjacent, but unaffected data. document number: 002-00518 rev. *d page 6 of 111 S79FL256S/s79fl512s hardware interface serial peripheral interface with multip le input / output (spi-mio) dual-quad many memory devices connect to their host system with separate pa rallel control, address, and data signals that require a large number of signal connections and larger package size. the large number of connections increase power consumption due to so many signals switching and the la rger package increases cost. the s25fl-s dual-quad spi devices reduce the number of signals for connection to the host system by serially transferring all control, address, and data information over 10 signals. this r educes the cost of the memory package, reduces signal switching power, and either reduces the host connection count or fr ees host connectors for use in providing other features. the s25fl-s dual-quad spi devices use the industry standard sing le bit serial peripheral interface (spi) using two quad spi devices in each package (quad spi-1 and quad spi-2). this interf ace is called dual-quad and enables support of byte wide (8 bit ) serial transfers. there is one packa ge option available for S79FL256S/s79fl512s: ? 16-pin soic package for documentation simplicity, all ac timings and waveforms and dc specification are defined using single cs# (chip select) and sck (serial clock) signals. for S79FL256S/s79fl512s, the cs# si gnals and the sck signals for quad spi-1 and quad spi-2 are internally tied together in the package. 2. signal descriptions 2.1 input/output summary table 1. dual-quad input/output descriptions signal name type description reset# input hardware reset: low = device resets and retu rns to standby state, ready to receive a command. the signal has an internal pull-up resistor and may be left unconnected in the host system if not used. sck input serial clock cs# input chip select io0 i/o i/o 0 for quad spi-1 io1 i/o i/o 1 for quad spi-1 io2 i/o i/o 2 for quad spi-1 io3 i/o i/o 3 for quad spi-1 io4 i/o i/o 0 for quad spi-2 io5 i/o i/o 1 for quad spi-2 io6 i/o i/o 2 for quad spi-2 io7 i/o i/o 3 for quad spi-2 vcc supply core power supply vss supply ground nc unused not connected. no device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a pr inted circuit board (pcb). however, any signal connected to a nc pin must not have voltage levels higher than the vcc absolute maximum (supply voltage). rfu reserved reserved for future use. no device internal signal is currently connected to the package connector but there is potential future use for the connector for a signal. it is recommended to not use rfu connectors for pcb routing channels so that the pcb may take advantage of future enhanced feat ures in compatible footprint devices. document number: 002-00518 rev. *d page 7 of 111 S79FL256S/s79fl512s 2.2 multiple input / output (dual-quad spi) quad input / output (i/o) commands send in structions to the memory only on the io0 (quad spi-1) and io4 (quad spi-2) signals. address is sent from the host to the memory as four bit (nibbl e) on io0, io1, io2, io3 (quad spi-1)and repeated on io4, io5, io 6, io7 (quad spi-2). data is s ent and returned to the host as bytes on io0 - io7. 2.3 reset# the reset# input provides a hardware method of resetting the device to standby state, ready for receiving a command. when reset# is driven to logic low (v il ) for at least a period of t rp , the device: ? terminates any operation in progress, ? tristates all outputs, ? resets the volatile bits in the configuration register, ? resets the volatile bits in the status registers, ? resets the bank address register to zero, ? loads the program buffer with all ones, ? reloads all internal configuration information necessary to bring the device to standby mode, ? and resets the internal control unit to standby state. reset# causes the same initialization process as is performed when power comes up and requires t pu time. reset# may be asserted low at an y time. to ensure data in tegrity any operation that was interru pted by a hardware reset should be reinitiated once the device is ready to accept a command sequence. when reset# is first asserted low, the device draws i cc1 (50 mhz value) during t pu . if reset# continues to be held at v ss the device draws cmos standby current (i sb ). reset# has an internal pull- up resistor and may be left unconnected in the hos t system if not used. the reset# input is not available on all packages options. when not available the reset# input of th e device is tied to the ina ctive state, inside the package. 2.4 multiple input / output (dual-quad) quad input / output (i/o) commands send in structions to the memory only on the io0 (quad spi-1) and io4 (quad spi-2) signals. address is sent from the host to the memory as four bit (nibbl e) on io0, io1, io2, io3 (quad spi-1)and repeated on io4, io5, io 6, io7 (quad spi-2). data is s ent and returned to the host as bytes on io0 - io7. 2.5 serial clock (sck) this input signal provides the synchronization reference for the spi interface. instructions, add resses, or data input are latc hed on the rising edge of the sck signal. data output changes after th e falling edge of sck, in sdr commands, and after every edge in ddr commands. dnu reserved do not use. a device internal signal may be connected to the package connector. the connection may be used by cypress for test or other purposes and is not intended for connection to any host system signal. any d nu signal related function will be inactive when the signal is at vil. the signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to vss. do not use these connections for pcb signal routing cha nnels. do not connect any ho st system signal to this connection. table 1. dual-quad input/output descriptions (continued) signal name type description document number: 002-00518 rev. *d page 8 of 111 S79FL256S/s79fl512s 2.6 chip select (cs#) the chip select signal indicates when a command for the device is in process and the other sig nals are relevant for the memory device. when the cs# signal is at the logic high state, the dev ice is not selected and all input signals are ignored and all ou tput signals are high impedance. unless an internal program, erase or write registers (wrr) embedded operation is in progress, the device will be in the standby power mode. driving the cs# input to logic low state enables the de vice, placing it in the active power mode. after power-up, a falling edge on cs# is required prior to the start of any command. 2.7 input output io0 - io7 these signals are input and outputs for receiving instructions, addr esses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sck, in sdr commands, and on every edge of sck , in ddr commands). 2.8 core voltage supply (v cc ) v cc is the voltage source for all device internal logic. it is th e single voltage used for all device internal functions including read, program, and erase. the voltage may vary from 2.7v to 3.6v. 2.9 versatile i/o power supply (v io ) v io functionality is not supported on the standard configuration of the S79FL256S/s79fl512s devices. 2.10 supply and signal ground (v ss ) v ss is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers. 2.11 not connected (nc) no device internal signal is connected to the package connector no r is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a printed circuit board (pcb). ho wever, any signal connected to an nc must not have voltage levels higher than v cc . 2.12 reserved for future use (rfu) no device internal signal is currently connected to the package connector but is ther e potential future use of the connector. i t is recommended to not use rfu connectors for pcb routing channe ls so that the pcb may take advantage of future enhanced features in compatib le footprint devices. 2.13 do not use (dnu) a device internal signal may be connected to the package connecto r. the connection may be used by cypress for test or other purposes and is not intended for connection to any host system signal. any dnu signal related function will be inactive when th e signal is at v il . the signal has an internal pull-down resistor and may be left unconnected in t he host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to these connections. document number: 002-00518 rev. *d page 9 of 111 S79FL256S/s79fl512s 2.14 block diagrams figure 1. spi host and s79fl2 56s / s79fl512s dual-quad spi devices in the 16-pin soic package note: 1. the chip select (cs#) and clock (sck) signals for quad spi-1 and quad spi-2 are internally tied together in the 16-pin soic p ackage. quad spi -1 quad spi -2 io0 ? io3 io4 ? io7 io0 ? io3 io4 ? io7 sck cs# reset# sck cs# reset# spi host S79FL256S / s79fl512s dual-quad device document number: 002-00518 rev. *d page 10 of 111 S79FL256S/s79fl512s 3. signal protocols 3.1 spi clock modes 3.1.1 single data rate (sdr) the s25fl-s devices can be driven by an embedded microcontroller (b us master) in either of the two following clocking modes. ? mode 0 with clock polarity (cpol) = 0 and, clock phase (cpha) = 0 ? mode 3 with cpol = 1 and, cpha = 1 for these two modes, input data into the device is always latched in on the rising edge of the sck signal and the output data i s always available from the falling edge of the sck clock signal. the difference between the two modes is t he clock polarity when the bus master is in standby mode and not transferring any data . ? sck will stay at logic low st ate with cpol = 0, cpha = 0 ? sck will stay at logic high state with cpol = 1, cpha = 1 figure 2. dual-quad spi sdr modes supported timing diagrams throughout the remainder of the document are g enerally shown as both mode 0 and 3 by showing sck as both high and low at the fall of cs#. in some cases a timing diagram ma y show only mode 0 with sck low at the fall of cs#. in such a case, mode 3 timing simply means clock is high at the fall of cs# so no sck rising edge set up or hold time to the falling edge of cs# is needed for mode 3. sck cycles are measured (counted) from one falling edge of sc k to the next falling edge of sck. in mode 0 the beginning of the first sck cycle in a command is measured from the falling edge of cs# to the first falling edge of sck because sck is already l ow at the beginning of a command. 3.1.2 double data rate (ddr) mode 0 and mode 3 are also supported for ddr commands. in ddr co mmands, the instruction bits ar e always latched on the rising edge of clock, the same as in sdr commands. however, the addre ss and input data that follow the instruction are latched on both the rising and falling edges of sck. the first address bit is latched on the first rising edge of sck following the falling edg e at the end of the last instruction bit. the first bit of output data is driven on the falling edge at the end of the last access latency ( dummy) cycle. sck cycles are measured (counted) in the same way as in sdr co mmands, from one falling edge of sck to the next falling edge of sck. in mode 0 the beginning of the first sck cycle in a command is measur ed from the falling edge of cs# to the fi rst falling edge of sck because sck is already low at the beginning of a command. cpol=0_cpha=0_sclk cpol=1_cpha=1_sclk cs# io0 io1 io4 io5 msb msb msb msb document number: 002-00518 rev. *d page 11 of 111 S79FL256S/s79fl512s figure 3. dual-quad spi ddr modes supported 3.2 command protocol all communication between the host system and s25fl-s memo ry devices is in the form of units called commands. all commands begin with an instruction that selects the type of information transfer or device operation to be performed. comma nds may also have an address, instruction modifier, latency period, da ta transfer to the memory, or data transfer from the memory. all instruction, address, and data information is transferred serially between the host system and memory device. quad input / output (i/o) commands provide an address sent from the host as four bit (nibble) groups on io0, io1, io2, io3 and repeated on io4, io 5, io6, io7, then followed by dummy cycles. data is return ed to the host as byte on io0 - io7. this is refer enced as 2-8-8 for quad i/o command protocols. commands are structured as follows: ? each command begins with cs# going low and ends with cs# returning high. the memory device is selected by the host driving the chip select (cs#) signal low throughout a command. ? the serial clock (sck) marks the transfer of each bit or group of bits between the host and memory. ? each command begins with an 8-bit (byte) instruction. the instru ction is always presented only as a single bit serial sequence on the serial input (si) signal with one bit transferred to the memo ry device on each sck rising edge. the instruction selects the type of information transfer or device operation to be performed. ? the instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in the device. the instruction determines the address space used . the address may be either a 24-bit or a 32-bit byte boundary, address. the address transfers occur on sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? quad i/o read instructions send an instruct ion modifier called continuous read mode bits, following the address, to indicate whether the next command will be of the same type with an implied, rather than an expl icit, instruction. these mode bits initia te or end the continuous read mode. in continuou s read mode, the next command thus does not provide an instruction byte, only a new address and mode bits. this reduces the time needed to send ea ch command when the same command type is repeated in a sequence of commands. the mode bit transfers occur on sc k rising edge, in sdr commands, or on every sck edge, in ddr commands. cpol=0_cpha=0_sclk cpol=1_cpha=1_sclk cs# transfer_phase io0 io1 io2 io3 io4 io5 io6 io7 inst. 7 inst. 0 a28 a24 a0 m4 m0 dl p . dl p . d0 d1 a29 a25 a1 m5 m1 dl p . dl p . d0 d1 a30 a26 a2 m6 m2 dl p . dl p . d0 d1 a31 a27 a3 m7 m3 dl p . dl p . d0 d1 inst. 7 inst. 0 a28 a24 a0 m4 m0 dl p . dl p . d0 d1 a29 a25 a1 m5 m1 dl p . dl p . d0 d1 a30 a26 a2 m6 m2 dl p . dl p . d0 d1 a31 a27 a3 m7 m3 dl p . dl p . d0 d1 dummy / dlp address mode instruction document number: 002-00518 rev. *d page 12 of 111 S79FL256S/s79fl512s ? the width of all transfers following the inst ruction are determined by the instruction sent. following transfers may continue t o be single bit serial on only the si or serial output (so) signals, they may be done in 4-bit groups per (quad) transfer on the io0 -io3 signals. within the quad groups the least significant bit is on io0. more significant bits are placed in significance order on each higher numbered io signal. single bits or parallel bit groups are transferred in most to least significant bit order. ? some instructions send an instruction modifier called mode bits, fo llowing the address, to indicate that the next command will be of the same type with an implied, rather than an explicit, inst ruction. the next command thus doe s not provide an instruction b yte, only a new address and mode bits. this reduces the time needed to send each command when the same command type is repeated in a sequence of commands. the mode bit transfers occur on sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? the address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host. ? write data bit transfers occur on sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? sck continues to toggle during any read a ccess latency period. th e latency may be zero to severa l sck cycles (also referred to as dummy cycles). at the end of the read latency cycles, the fi rst read data bits are driven from the outputs on sck falling ed ge at the end of the last read latency cycle. the first read data bits are considered transferred to the host on the following sck ri sing edge. each following transfer occurs on the next sck rising e dge, in sdr commands, or on every sck edge, in ddr commands. ? if the command returns read data to the host, the device conti nues sending data transfers until th e host takes the cs# signal h igh. the cs# signal can be driven high after any transfer in the read data sequence. this will terminate the command. ? at the end of a command that does not retu rn data, the host drives the cs# input high. the cs# signal must go high after the eighth bit, of a stand alone instruction or, of the last write data byte that is transferred. that is, the cs# signal must be d riven high when the number of clock cycles after cs# sign al was driven low is an exact multiple of eight cycles. if the cs# signal does no t go high exactly at the eight sck cycle boundar y of the instruction or wr ite data, the command is rejected and not executed. ? all instruction, address, and mode bits ar e shifted into the device with the most signi ficant bits (msb) first. the data bits a re shifted in and out of the device msb first. all data is transferred in byte units with the lowest address byte sent first. foll owing bytes of data are sent in lowest to highest by te address order i.e. the byte address increments. ? all attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. the embedded operation will continue to execute without any affect. a very limited set of commands are accepted during an embedded operation. these are discussed in the individual command descriptions. ? depending on the command, the time for execution varies. a co mmand to read status information fr om an executing command is available to determine when the command completes execution and whether the command was successful. 3.2.1 command sequence examples figure 4. dual-quad stan d alone instruction command note: 1. instruction needs to be the same for both io0 (quad spi-1) and io4 (quad spi-2). cs# sck io0 io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction document number: 002-00518 rev. *d page 13 of 111 S79FL256S/s79fl512s figure 5. dual-quad single bit wide input command note: 1. instruction needs to be the same for both io0 (quad spi-1) and io4 (quad spi-2). figure 6. dual-quad single bit wide i/o command without latency note: 1. instruction needs to be the same for both io0 (quad spi-1) and io4 (quad spi-2). figure 7. dual-quad single bit wide i/o command with latency note: 1. instruction needs to be the same for both io0 (quad spi-1) and io4 (quad spi-2). cs# sclk io0 io4 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data cs# sclk io0 io1 io2-io3 io4 io5 io6-io7 phase 7 6 5 4 3 2 1 0 31 1 0 3 2 1 0 3 2 1 0 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 7 6 5 4 instruction address data 1 data 2 cs# sclk io0 io1 io2-io3 io4 io5 io6-io7 phase 7 6 5 4 3 2 1 0 31 1 0 3 2 1 0 3 2 1 0 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 7 6 5 4 instruction address dummy cycles data 1 data 2 document number: 002-00518 rev. *d page 14 of 111 S79FL256S/s79fl512s figure 8. dual-quad, quad output read command note: 1. a = msb of address = 23 for 3-byte address, or 31 for 4-byte address. figure 9. dual-quad, quad i/o command notes: 1. instruction, address and mode bits needs to be the same for both io0-io3 (quad spi-1) and io4-io7 (quad spi-2). 2. the gray bits are optional, the host does not have to drive bits during that cycle. figure 10. dual-quad ddr quad i/o read command notes: 1. instruction, address and mode bits needs to be the same for both io0-io3 (quad spi-1) and io4-io7 (quad spi-2). 2. the gray bits are optional, the host does not have to drive bits during that cycle. additional sequence diagrams, specific to each command, are provided in section 9., commands on page 52 . cs# sck io0 io1 io2 io3 io4 io5 io6 io7 phase 7 6 5 4 3 2 1 0 a 1 0 0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 7 6 5 4 3 2 1 0 a 1 0 4 4 4 4 4 5 5 5 5 5 6 6 6 6 6 7 7 7 7 7 instruction address dummy d1 d2 d3 d4 d5 cs# sclk io0 io1 io2 io3 io4 io5 io6 io7 phase 7 6 5 4 3 2 1 0 28 4 0 4 0 0 0 0 0 29 5 1 5 1 1 1 1 1 30 6 2 6 2 2 2 2 2 31 7 3 7 3 3 3 3 3 7 6 5 4 3 2 1 0 28 4 0 4 0 4 4 4 4 29 5 1 5 1 5 5 5 5 30 6 2 6 2 6 6 6 6 31 7 3 7 3 7 7 7 7 instruction address mode dummy d1 d2 d3 d4 cs# sclk io0 io1 io2 io3 io4 io5 io6 io7 phase 7 6 5 4 3 2 1 0 28 24 20 16 12 8 4 0 4 0 7 6 5 4 3 2 1 0 0 0 0 0 29 25 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 1 1 1 1 30 26 22 18 14 10 6 2 6 2 7 6 5 4 3 2 1 0 2 2 2 2 31 27 23 19 15 11 7 3 7 3 7 6 5 4 3 2 1 0 3 3 3 3 7 6 5 4 3 2 1 0 28 24 20 16 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 4 4 4 29 25 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 5 5 5 30 26 22 18 14 2 6 2 6 2 7 6 5 4 3 2 1 0 6 6 6 6 31 27 23 19 15 3 7 3 7 3 7 6 5 4 3 2 1 0 7 7 7 7 instruction address mode dummy dlp d1 d2 d3 d4 document number: 002-00518 rev. *d page 15 of 111 S79FL256S/s79fl512s 3.3 interface states this section describes the input and output signal levels as related to the spi interface behavior. legend: z = no driver - floating signal hl = host driving v il hh = host driving v ih hv = either hl or hh x = hl or hh or z ht = toggling between hl and hh ml = memory driving v il mh = memory driving v ih mv = either ml or mh 3.3.1 power-off when the core supply voltage is at or below the v cc (low) voltage, the device is consider ed to be powered off. the device does not react to external signals, and is prevented from performing any program or erase operation. 3.3.2 low power hardwa re data protection when v cc is less than v cc (cut-off) the memory device will ignore commands to ensure that program and erase operations can not start when the core supply volta ge is out of the operating range. table 2. dual-quad interface states summary interface state vdd sck cs# reset# io0 - io7 power-off document number: 002-00518 rev. *d page 17 of 111 S79FL256S/s79fl512s 3.3.9 dual-quad single output cycle ? memory to host transfer several commands transfer information back to the host on the serial outputs (io1 and io5) signals. the host keeps reset# high, cs# low. the memory ignores the serial input (io0 and io4) signals. the memory drives io1 and io5 with data. the next interface state continues to be dual output cycl e until the host returns cs# to high ending the command. 3.3.10 qpp or qor address input cycle the quad page program and quad output read commands send addr ess to the memory only on io0 and io4. the other io signals are ignored because the device must be in quad mode for th ese commands thus the hold and write protect features are not active. the host keeps reset# hi gh, cs# low, and drives io0. for qpp the next interface state following the delivery of address is the quad input cycle. for qor the next interface state following ad dress is a quad latency cycle if there are latency cycles needed or quad output cycle if no latency is required. 3.3.11 quad input cycle ? host to memory transfer the quad i/o read command transfers four address or mode bits to the memory in each cycle. the quad page program command transfers four data bits to the memory in each cycle. the host keeps reset# high, cs# low, and drives the io signals. for quad i/o read the next interface state fo llowing the delivery of address and mode bits is a quad latency cycle if there are latency cycles needed or quad output cycle if no latency is requi red. for quad page program the host returns cs# high following the delivery of data to be programmed an d the interface returns to standby state. 3.3.12 quad latency (dummy) cycle read commands may have zero to several late ncy cycles during which read data is read fr om the main flash memory array before transfer to the host. the number of latency cycles are determi ned by the latency code in the configuration register (cr[7:6]). during the latency cycles, the host keeps reset# high, cs# low. the host may drive the io signals during these cycles or the host may leave the io floating. the memory does not use any data driven on io duri ng the latency cycles. the hos t must stop driving the io signals on the falling edge at the end of the last latency cycle. it is recommended that the host stop driving them during all latency cycles so that there is sufficien t time for the host drivers to tu rn off before the memory begins to drive at the end of the la tency cycles. this prevents driver conflict between host and memory when the signal direction changes. the memory does not drive the io signals during the latency cycles. the next interface state following the la st latency cycle is a quad output cycle. 3.3.13 quad output cycle ? memory to host transfer the quad output read and quad i/o read return data to the host eight bits in each cycle. the host keeps reset# high, and cs# low. the memory drives data on io0-io3 signals during the quad output cycles. the next interface state continues to be quad output c ycle until the host returns cs# to high ending the command. 3.3.14 ddr quad input cycle ? host to memory transfer the ddr quad i/o read command sends address, and mode bits to t he memory on all the io signals. eight bits are transferred on the rising edge of sck and four bits on the falling edge in each cycle. the host keeps reset# high, and cs# low. the next interface state following the delivery of address and mode bits is a ddr latency cycle. document number: 002-00518 rev. *d page 18 of 111 S79FL256S/s79fl512s 3.3.15 ddr latency cycle ddr read commands may have one to several latency cycles during which read data is read from the main flash memory array before transfer to the host. the number of latency cycles are determined by the latency code in the configuration register (cr1[7:6]). during th e latency cycles, the host keeps reset # high and cs# low. the host may not drive the io signals during the se cycles. so that there is sufficient time for the host drivers to turn off before the memory begins to drive. this prevents driv er conflict between host and memory when the signal direction changes. the memory has an option to drive all the io signals with a data learning pattern (dlp) during the last 4 latency cycles. the dl p option should not be enabled when there are fewer than five latency cycles so that there is at least one cycle of high imped ance for turn around of the io signals before the memory begins driving the dlp. when there are more than 4 cycles of latenc y the memory does not drive the io signals until the last four cycl es of latency. the next interface state following the last latency cycle is a ddr quad output cycle, depending on the instruction. 3.3.16 ddr quad output cycle ? memory to host transfer the ddr quad i/o read command returns bits to the host on all th e io signals. eight bits are transferred on the rising edge of sck and four bits on the falling edge in each cycle. the host keeps reset# high, and cs# low. the next interface state continues to be ddr quad output cycle until the host returns cs# to high ending the command. 3.4 configuration register effects on the interface the configuration register bits 7 and 6 (cr1[7:6]) select the la tency code for all read commands . the latency code selects the number of mode bit and latency cycl es for each type of instruction. the configuration register bit-1 (cr1[1]) selects whether quad mode is enabled and allow quad page program, quad output read, and quad i/o read commands. quad mode must also be selected to allow read ddr quad i/o commands. this quad bit is set to 1 by default for dual-quad spi. 3.5 data protection some basic protection against unintended changes to stored data are provided and controlled purel y by the hardware design. thes e are described below. other software managed protecti on methods are discussed in the software section ( page 33 ) of this document. 3.5.1 power-up when the core supply voltage is at or below the v cc (low) voltage, the device is consider ed to be powered off. the device does not react to external signals, and is prevented from performing any program or erase operation. program and erase operations contin ue to be prevented during the power-on reset (por) because no comma nd is accepted until the exit from por to the interface standby state. 3.5.2 low power when v cc is less than v cc (cut-off) the memory device will ignore commands to ensure that program and erase operations can not start when the core supply volta ge is out of the operating range. 3.5.3 clock pulse count the device verifies that all program, eras e, and write registers (wrr) commands consis t of a clock pulse co unt that is a multip le of eight before executing them. a comm and not having a multiple of 8 clock pulse count is ignored and no error status is set for t he command. document number: 002-00518 rev. *d page 19 of 111 S79FL256S/s79fl512s 4. electrical specifications 4.1 absolute maximum ratings notes: 1. see input signal overshoot on page 20 for allowed maximums during signal transition. 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 3. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other condi tions above those indicated in the operational sect ions of this data sheet is not implied. ex posure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 4.2 operating ranges operating ranges define those limit s between which the functionalit y of the device is guaranteed. 4.2.1 temperature ranges note: 1. automotive operating and performance parameters will be determine d by device characterization and may vary from standard indu strial temperature range devices as currently shown in this specification. table 3. absolute maximum ratings storage temperature plastic packages ?65c to +150c ambient temperature with power applied ?65c to +125c v cc ?0.5v to +4.0v input voltage with respect to ground (v ss ) (note 1) ?0.5v to +(v cc + 0.5v) output short circuit current (note 2) 100 ma table 4. recommended operating ranges parameter symbol conditions spec unit min max ambient temperature t a industrial (i) devices -40 +85 c automotive (a) - in cabin -40 +105 document number: 002-00518 rev. *d page 20 of 111 S79FL256S/s79fl512s 4.2.2 input sign al overshoot during dc conditions, input or i/o signals should remain equal to or between v ss and v cc . during voltage transitions, inputs or i/os may overshoot v ss to ?2.0v or overshoot to v cc +2.0v, for periods up to 20 ns. figure 11. maximum negative overshoot waveform figure 12. maximum positive overshoot waveform 4.3 power-up and power-down the device must not be selected at power-up or power- down (that is, cs# must follo w the voltage applied on v cc ) until v cc reaches the correct value as follows: ? v cc (min) at power-up, and then for a further delay of t pu ? v ss at power-down a simple pull-up resistor (generally of the order of 100 k ? ) on chip select (cs#) can usually be used to insure safe and proper power-up and power-down. the device ignores all instructions until a time delay of t pu has elapsed after the moment that v cc rises above the minimum v cc threshold. see figure 13 . however, correct operation of th e device is not guaranteed if v cc returns below v cc (min) during t pu . no command should be sent to the device until the end of t pu . after power-up (t pu ), the device is in standby mode (not deep power down mode), draws cmos standby current (i sb ), and the wel bit is reset. during power-down or voltage drops below v cc (cut-off), the voltage must drop below v cc (low) for a period of t pd for the part to initialize correctly on power-up. see figure 14 . if during a voltage drop the v cc stays above v cc (cut-off) the part will stay initialized and will work correctly when v cc is again above v cc (min). in the event power-on reset (por) did not complete correctly after power up, the assertion of the reset# signal or receiving a software reset command (reset) will restart the por process. normal precautions must be taken for supply rail decoupling to stabilize the v cc supply at the device. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the pa ckage supply connection (this ca pacitor is generally of the order of 0.1 f). v il - 2.0v 20 ns 20 ns 20 ns v ih v cc + 2.0v 20 ns 20 ns 20 ns document number: 002-00518 rev. *d page 21 of 111 S79FL256S/s79fl512s figure 13. power-up figure 14. power-down and voltage drop table 5. power-up / power-down voltage and timing symbol parameter min max unit v cc (min) v cc (minimum operation voltage) 2.7 v v cc (cut-off) v cc (cut 0ff where re-initialization is needed) 2.4 v v cc (low) v cc (low voltage for initialization to occur) v cc (low voltage for initialization to occur at embedded) 1.0 2.3 v t pu v cc (min) to read operation 300 s t pd v cc (low) time 1.0 s (max) (min) v cc t pu full device access time v cc v cc t pd (max) (min) v cc t pu device access allowed time v cc v cc no device access allowed (cut-off) v cc (low) v cc document number: 002-00518 rev. *d page 22 of 111 S79FL256S/s79fl512s 4.4 dc characteristics applicable within operating -40c to +85c range. notes: 1. typical values are at t ai = 25 c and v cc = 3v. 2. outputs switching current is not included. 3. industrial temperature range / automotive in-cabin temperature range. 4.4.1 active power and standby power modes the device is enabled and in the active power mode when chip se lect (cs#) is low. when cs# is high, the device is disabled, but may still be in an active power mode until all program, erase, and write operations have complete d. the device then goes into t he standby power mode, and powe r consumption drops to i sb . table 6. dc characteristics symbol parameter test conditions min typ (1) max unit vil input low voltage -0.5 0.2xvcc v vih input high voltage 0.7xvcc vcc+0.4 v vol output low voltage iol = 1.6 ma, vcc=vcc min 0.15 x vcc v voh output high voltage ioh = ?0.1 ma 0.85 x vcc v ili input leakage current vcc=vcc max, vin=vih or vil 4 a ilo output leakage current vcc=vcc max, vin=vih or vil 4 a icc1 active power supply current (read) serial sdr@50 mhz serial sdr@133 mhz quad sdr@ 80 mhz quad sdr@104 mhz quad ddr@ 80 mhz outputs unconnected during read data return (2) 32 66/70 (3) 100 122 180 ma icc2 active power supply current (page program) cs#=vcc 200 ma icc3 active power supply current (wrr) cs#=vcc 200 ma icc4 active power supply current (se) cs#=vcc 200 ma icc5 active power supply current (be) cs#=vcc 200 ma isb (industrial) standby current reset#, cs#=vc c; si, sck = vcc or vss, industrial temp 140 200 a isb (automotive) standby current reset#, cs#=vc c; si, sck = vcc or vss, automotive te m p 140 600 a document number: 002-00518 rev. *d page 23 of 111 S79FL256S/s79fl512s 5. timing specifications 5.1 key to switching waveforms figure 15. waveform element meanings figure 16. input, output, and timing reference levels 5.2 ac test conditions figure 17. test setup input symbol output valid at logic high or low high impedance any change permitted logic high logic low changing, state unknown valid at logic high or low high impedance logic high logic low v cc + 0.4v 0.7 x v cc 0.2 x v cc - 0.5v timing reference level 0.5 x v cc 0.85 x v cc 0.15 x v cc input levels output levels device under te s t c l document number: 002-00518 rev. *d page 24 of 111 S79FL256S/s79fl512s notes: 1. output high-z is defined as the point where data is no longer driven. 2. input slew rate: 1.5 v/ns. 3. ac characteristics tables assume clock and da ta signals have the same slew rate (slope). 4. ddr operation. 5.2.1 capacitance characteristics note: 1. for more information on capacitance, please consult the ibis models. 5.3 reset 5.3.1 power-on (cold) reset the device executes a power-on reset (por) process until a time delay of t pu has elapsed after the moment that v cc rises above the minimum v cc threshold. see figure 13 on page 21 , table 5 on page 21 , and table 9 on page 26 . the device must not be selected (cs# to go high with v cc ) during power-up (t pu ), i.e. no commands may be sent to the device until the end of t pu . reset# is ignored during por. if reset # is low during por and remains lo w through and beyo nd the end of t pu , cs# must remain high until t rh after reset# returns high. reset# must return high for greater than t rs before returning low to initiate a hardware reset. figure 18. reset low at the end of por table 7. ac measurement conditions symbol parameter min max unit c l load capacitance 30 15 (4) pf input rise and fall times 2.4 ns input pulse voltage 0.2 x v cc to 0.8 v cc v input timing ref voltage 0.5 v cc v output timing ref voltage 0.5 v cc v table 8. capacitance parameter test conditions min max unit c in input capacitance (applies to sck, cs#, reset#) 1 mhz 14 pf c out output capacitance (applies to all i/o) 1 mhz 20 pf vcc reset# cs# if reset# is low at tpu end cs# must be high at tpu end tpu trh document number: 002-00518 rev. *d page 25 of 111 S79FL256S/s79fl512s figure 19. reset high at the end of por figure 20. por followed by hardware reset 5.3.2 hardware (warm) reset when the reset # input transitions from v ih to v il the device will reset register states in the same manner as power-on reset but, does not go through the full reset process that is performed during po r. the hardware reset process requires a period of t rph to complete. if the por process did not complete correctly for any reason during power-up (t pu ), reset# going low will initiate the full por process instead of the hardware reset process and will require t pu to complete the por process. the reset# input provides a hardware method of re setting the flash memory device to standby state. ? reset# must be high for t rs following t pu or t rph , before going low again to initiate a hardware reset. ? when reset# is driven low for at least a minimum period of time (t rp ), the device terminates any opera tion in progress, tri-states all outputs, and ignores all read/write commands for the duration of t rph . the device resets the interface to standby state. ? if cs# is low at the time reset# is asserted, cs# must return high during t rph before it can be asserted low again after t rh . figure 21. hardware reset vcc reset# cs# if reset# is high at tpu end cs# may stay high or go low at tpu end tpu tpu vcc reset# cs# trs tpu tpu reset# cs# any prior reset trs trp trh trh trph trph document number: 002-00518 rev. *d page 26 of 111 S79FL256S/s79fl512s notes: 1. reset# low is optional and ignored during power-up (t pu ). if reset# is asserted during the end of t pu , the device will remain in the reset state and t rh will determine when cs# may go low. 2. sum of t rp and t rh must be equal to or greater than t rph. table 9. hardware reset parameters parameter description limit time unit t rs reset setup - prior reset end and reset# high before reset# low min 50 ns t rph reset pulse hold - reset# low to cs# low min 35 s t rp reset# pulse width min 200 ns t rh reset hold - reset# high before cs# low min 50 ns document number: 002-00518 rev. *d page 27 of 111 S79FL256S/s79fl512s 5.4 sdr ac characteristics notes: 1. only applicable as a constraint for wrr instruction when srwd is set to a 1. 2. full v cc range (2.7 - 3.6v) and cl = 30 pf. 3. regulated v cc range (3.0 - 3.6v) and cl = 30 pf. 4. regulated v cc range (3.0 - 3.6v) and cl = 15 pf. 5. 10% duty cycle is supported for frequencies ? 50 mhz. 6. maximum value only applies during program/erase suspend/resume commands. table 10. ac characteristics (v cc 2.7v to 3.6v) symbol parameter min typ max unit f sck, r sck clock frequency for read and 4read instructions dc 50 mhz f sck, c sck clock frequency for single commands as shown in table 38 on page 55 (4) dc 133 mhz f sck, c sck clock frequency for the following dual and quad commands: qor, 4qor, qior, 4qior dc 104 mhz f sck, qpp sck clock frequency for the qpp, 4qpp commands dc 80 mhz p sck sck clock period 1/ f sck ? t wh , t ch clock high time (5) 45% p sck ns t wl , t cl clock low time (5) 45% p sck ns t crt , t clch clock rise time (slew rate) 0.1 v/ns t cft , t chcl clock fall time (slew rate) 0.1 v/ns t cs cs# high time (read instructions) cs# high time (program/erase) 10 50 ns t css cs# active setup time (relative to sck) 3 ns t csh cs# active hold time (relative to sck) 3 3000 (6) ns t su data in setup time 1.5 ns t hd data in hold time 2 ns t v clock low to output valid 8.0 (2) 7.65 (3) 6.5 (4) ns t ho output hold time 2 ns t dis output disable time 0 8 ns t wps wp# setup time 20 (1) ns t wph wp# hold time 100 (1) ns t hlch hold# active setup time (relative to sck) 3 ns t chhh hold# active hold time (relative to sck) 3 ns t hhch hold# non active setup time (relative to sck) 3 ns t chhl hold# non active hold time (relative to sck) 3 ns t hz hold# enable to output invalid 8 ns t lz hold# disable to output valid 8 ns document number: 002-00518 rev. *d page 28 of 111 S79FL256S/s79fl512s 5.4.1 clock timing figure 22. clock timing 5.4.2 input / output timing figure 23. spi sdr dual-quad timing v il max v ih min tch tcrt tcft tcl v cc / 2 p sck cs# sck io msb in lsb in msb out . lsb out tcsh tcss tcss tsu thd tlz tho tcs tdis tv document number: 002-00518 rev. *d page 29 of 111 S79FL256S/s79fl512s 5.5 ddr ac characteristics notes: 1. regulated v cc range (3.0 - 3.6v) and cl =15 pf. 2. maximum value only applies during program/erase suspend/resume commands. 5.5.1 ddr input timing figure 24. spi ddr input timing table 11. ac characteristics ddr operation symbol parameter 80 mhz unit min typ max f sck, r sck clock frequency for ddr read instruction dc 80 mhz p sck, r sck clock period for d dr read instruction 12.5 ? ns t wh , t ch clock high time 45% p sck ns t wl , t cl clock low time 45% p sck ns t cs cs# high time (read instructions) 10 ns t css cs# active setup time (relative to sck) 3 ns t csh cs# active hold time (rela tive to sck) 3 ns t su io in setup time 1.5 3000 (2) ns t hd io in hold time 1.5 ns t v clock low to output valid 1.5 6.5 (1) ns t ho output hold time 1.5 ns t dis output disable time 8 ns t lz clock to output low impedance 0 8 ns t o_skew first output to last output data valid time 600 ps cs# sck io msb in lsb in tcss tcss tcsh tcsh tcs tsu tsu thd thd document number: 002-00518 rev. *d page 30 of 111 S79FL256S/s79fl512s 5.5.2 ddr output timing figure 25. spi ddr output timing figure 26. spi ddr data valid window notes: 1. t clh is the shorter duration of t cl or t ch . 2. t o_skew is the maximum difference (delta) between the minimum and maximum t v (output valid) across all io signals. 3. t ott is the maximum output transition time from one va lid data value to the next valid data value on each io. 4. t ott is dependent on system level considerations including: a. memory device output impedance (drive strength). b. system level parasitics on the ios (primarily bus capacitance). c. host memory controller input v ih and v il levels at which 0 to 1 and 1 to 0 transitions are recognized. d. as an example, assuming that the above c onsiderations result a memory output slew rate of 2v/ns and a 3v transition (from 1 t o 0 or 0 to 1) is required by the host, the t ott would be: t ott = 3v/(2v/ns) = 1.5 ns e. t ott is not a specification tested by cypres s, it is system dependent and must be de rived by the system designer based on the above considerations. 5. the minimum data valid window (t dv ) can be calculated as follows: a. as an example, assuming: i. 80 mhz clock frequency = 12.5 ns clock period ii. ddr operations are specified to have a duty cycle of 45% or higher iii. t clh = 0.45*psck = 0.45x12.5 ns = 5.625 ns iv. t o_skew = 600 ps v. t ott = 1.5 ns b. t dv = t clh - t o_skew - t ott c. t dv = 5.625 ns - 600 ps - 1.5 ns = 3.525 ns cs# sck si io msb lsb tcs tho tv tv tdis tlz io0 io1 io2 io_valid io3 tdv slow d1 slow d2 fast d1 fast d2 tv to_skew tv sck d1 valid tott tch tcl tdv d2 valid p sck document number: 002-00518 rev. *d page 31 of 111 S79FL256S/s79fl512s 6. physical interface 6.1 dual-quad soic 16-lead package figure 27. 16-pin soic package (300 mil) 1 2 3 4 16 15 14 13 io3 vcc reset# io7 nc io4 io0 sck 5 6 7 8 12 11 10 9 io2 vss nc io6 io5 nc cs# io1 document number: 002-00518 rev. *d page 32 of 111 S79FL256S/s79fl512s 6.2 soic 16 physical diagram figure 28. soic 16-lead, 300-mil body width (ss3016) 6.2.1 special handling instru ctions for fbga packages flash memory devices in bga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date 0.33 c 0.25 m d ca-b 0.20 c a-b 0.10 c 0.10 c 0.10 c d 2x 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. 1. all dimensions are in millimeters. notes: d and e1 dimensions are determined at datum h. flash, but inclusive of any mismatch between the top and bottom of exclusive of mold flash, tie bar burrs, gate burrs and interlead 4. the package top may be smaller than the package bottom. dimensions 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified 7. the dimensions apply to the flat section of the lead between 0.10 to maximum material condition. the dambar cannot be located on the 8. dimension "b" does not include dambar protrusion. allowable dambar lower radius of the lead foot. identifier must be located within the index area indicated. 9. this chamfer feature is optional. if it is not present, then a pin 1 10. lead coplanarity shall be within 0.10 mm as measured from the h 0 d l2 n e a1 b c e e1 a 0.75 10.30 bsc 1.27 bsc 0.30 10.30 bsc 0.33 0 0.25 16 0.20 7.50 bsc 0.10 0.31 8 0.51 2.65 2.35 a2 2.05 2.55 b1 0.27 0.48 0.30 0.20 c1 l1 0.40 l 1.27 1.40 ref 0.25 bsc 0 5 15 0 0 1 2 - dimensions symbol min. nom. max. - - - - - - - - - - - - mold flash, protrusions or gate burrs shall not exceed 0.15 mm per d and e1 are determined at the outmost extremes of the plastic body 0.25 mm from the lead tip. protrusion shall be 0.10 mm total in excess of the "b" dimension at the plastic body. package length. seating plane. so3016 kota besy 24-oct-16 24-oct-16 *a 002-15547 package outline, 16 lead soic 12 to fit 10.30x7.50x2.65 mm so3016/sl3016/ss3016 sl3016 ss3016 document number: 002-00518 rev. *d page 33 of 111 S79FL256S/s79fl512s software interface this section discusses the features and behaviors most relevant to host system software that interacts with the S79FL256S/ s79fl512s memory devices. 7. address space maps 7.1 overview 7.1.1 extended address the s25fl-s devices support 32-bit addresses to enable higher de nsity devices than allowed by previous generation (legacy) spi devices that supported only 24-bit addresses. a 24-bit byte resolution address can access only 16 mbytes (128 mbits) of maximum density. a 32-bit byte resolution address allows direct addre ssing of up to a 4 gbytes (32 gbits) of address space. legacy commands continue to support 24-bit addresses for backwa rd software compatibility. extended 32-bit addresses are enabled in three ways: ? bank address register ? a software (command) loadable internal register that supplies the high or der bits of address when legac y 24-bit addresses are in use. ? extended address mode ? a bank address regi ster bit that changes all legacy command s to expect 32 bits of address supplied from the host system. ? new commands ? that perform both legacy and new functions, which expect 32-bit address. the default condition at power-up and after reset, is the bank address register loaded with zero s and the extended address mode set for 24-bit addresses. this enables legacy software compatible access to the fi rst 128 mbits of a device. 7.1.2 multiple address spaces many commands operate on the main flash memory array. some commands operate on address spaces separate from the main flash array. each separate address space uses the full 32-bit address but may only define a smal l portion of the available addr ess space. 7.2 flash memory array the main flash array is divided into erase units called sector s. the sectors are organized as uniform 512-kbyte sectors. table 12. s79fl512s sector and memory address map, bottom 8-kbyte sectors sector size (kbyte) sector count sector range address range (byte address) notes 832 sa00 00000000h-00000fffh sector starting address ? sector ending address : : sa31 0001f000h-0001ffffh 128 510 sa32 00020000h-0002ffffh : : sa541 01ff0000h-01ffffffh document number: 002-00518 rev. *d page 34 of 111 S79FL256S/s79fl512s table 13. s79fl512s sector and memory address map, top 8-kbyte sectors sector size (kbyte) sector count sector range address range (byte address) notes 128 510 sa00 0000000h-000ffffh sector starting address ? sector ending address :: sa509 01fd0000h-01fdffffh 832 sa510 01fe0000h-01fe0fffh :: sa541 01fff000h-01ffffffh table 14. s79fl512s sector and memory address map, uniform 512-kbyte sectors sector size (kbyte) sector count sector range address range (8-bit) notes 512 128 sa00 0000000h-003ffffh sector starting address ? sector ending address : : sa127 1fc0000h-1ffffffh table 15. S79FL256S sector and memory address map, bottom 8-kbyte sectors sector size (kbyte) sector count sector range address range (byte address) notes 832 sa00 00000000h-00000fffh sector starting address ? sector ending address : : sa31 0001f000h-0001ffffh 128 254 sa32 00020000h-0002ffffh : : sa285 00ff0000h-00ffffffh table 16. S79FL256S sector and memory address map, top 8-kbyte sectors sector size (kbyte) sector count sector range address range (byte address) notes 128 254 sa00 0000000h-000ffffh sector starting address ? sector ending address : : sa253 00fd0000h-00fdffffh 8 32 sa254 00fe0000h-00fe0fffh : : sa285 00fff000h-00ffffffh document number: 002-00518 rev. *d page 35 of 111 S79FL256S/s79fl512s note : these are condensed tables that use a couple of sectors as references. there are address ranges that are not explicitly liste d. 7.3 id-cfi address space the rdidj command (9fh) reads information from a separate fl ash memory address space for device identification (id) and common flash interface (cfi) information. see device id and common flash interface (id-cfi) address map on page 97 for the tables defining the contents of t he id-cfi address space. the id-cfi address spac e is programmed by cypress and read-only for the host system. 7.4 otp address space each S79FL256S/s79fl512s memory device has a 2048-byte one time program (otp) address spac e that is separate from the main flash array. the otp area is divided into 64, individually lockable, 32-byte aligned and length regions. in each 32-byte region starting at address zero: ? the 16 lowest address bytes are programmed by cypress with a 128 -bit random number. only cypress is able to program these bytes. ? the next 4 higher address bytes (otp lock bytes) are used to provide one bit per otp region to permanently protect each region from programming. the bytes are erased when shipped from cypr ess. after an otp region is programmed, it can be locked to prevent further programming, by programming the related protection bit in the otp lock bytes. ? the next higher 12 bytes of the lowest address region are reserv ed for future use (rfu). the bits in these rfu bytes may be programmed by the host system but it must be understood that a fu ture device may use those bits fo r protection of a larger otp space. the bytes are erased when shipped from cypress. the remaining regions are erased when shipped from cypress, a nd are available for programming of additional permanent data. refer to figure 29 for a pictorial representation of the otp memory space. the otp memory space is intende d for increased system security. otp values, su ch as the random number programmed by cypress, can be used to ?mate? a flash component with t he system cpu/asic to prev ent device substitution. the configuration register freeze (cr1[0]) bit protects the entire otp memory space fr om programming when set to 1. this allows trusted boot code to control programming of otp regions then set the freeze bit to prevent further otp memory space programming during the remainder of normal power-on system operation. during the programming of each otp region, bits 0-3 are programm ed on quad spi-1 via io0-io3, and bits 4-7 are programmed on quad spi-2 via io4-io7. table 17. S79FL256S sector and memory address map, uniform 512-kbyte sectors sector size (kbyte) sector count sector range address range (byte address) notes 512 64 sa00 0000000h-003ffffh sector starting address ? sector ending address : : sa63 0fc0000h-0ffffffh document number: 002-00518 rev. *d page 36 of 111 S79FL256S/s79fl512s figure 29. otp address space ? quad spi-1 and spi-2 note: 1. it is recommended that the lock bytes for quad spi-1 and quad spi-2 be programmed with identical data. 32-byte otp region 30 . . . reserve d lock byte s lock bits 31 to 0 ... when programmed to ? 0? each lock bit protects its related 32 byte region from any further programming contents of region 0 { byte 0 byte 10 byte 1 f 32-byte otp region 31 32-byte otp region 29 32-byte otp region 3 32-byte otp region 2 32-byte otp region 1 32-byte otp region 0 16-byte random number 32-byte otp region 30 . . . reserve d lock byte s byte 0 byte 10 byte 1 f 32-byte otp region 31 32-byte otp region 29 32-byte otp region 3 32-byte otp region 2 32-byte otp region 1 32-byte otp region 0 16-byte random number lock bits 31 to 0 ... when programmed to ? 0? each lock bit protects its related 32 byte region from any further programming contents of region 0 { quad spi-1 quad spi-2 table 18. otp address map for quad spi-1 and quad spi-2 region byte address range (hex) contents initial delivery state (hex) region 0 000 least significant byte of cypress programmed random number cypress programmed random number ... ... 00f most significant byte of cypress programmed random number 010 to 013 region locking bits byte 10 [bit 0] locks region 0 from programming when = 0 ... byte 13 [bit 7] locks region 31 from programming when = 0 all bytes = ff (1) 014 to 01f reserved for future use (rfu) all bytes = ff region 1 020 to 03f available for user programming all bytes = ff region 2 040 to 05f available for user programming all bytes = ff ... ... available for user programming all bytes = ff region 31 7e0 to 7ff available for user programming all bytes = ff document number: 002-00518 rev. *d page 37 of 111 S79FL256S/s79fl512s 7.5 registers registers are small groups of memory cells us ed to configure how the s25fl-s dual-quad spi memory devices o perate or to report the status of device operations. the regi sters are accessed by specific commands. the commands (and hexadecimal instruction codes) used for each register are noted in each register description. each S79FL256S/s79fl512s dual-quad spi device has a register of each type, one for each individual die. these include the status register-1, status register-2, configuration register, au toboot register, bank address register, ecc status register, as p register, password register, ppb lock regist er, ppb access register, dyb access regist er, and ddr data l earning registers. each register must be accessed by a command given in paralle l to io0-io3 (quad spi-1) and fo r io4-io7 (quad spi-2). reading and writing to each of these registers mu st also be done in parallel for io0-io3 (quad spi-1) and for io4-io7 (quad spi-2). the individual register bits may be volatile, non-volatile, or o ne time programmable (otp). the type for each bit is noted in e ach register description. the default state shown for each bit refers to the state after power-on reset, hardware reset, or softwar e reset if the bit is volatile. if the bit is non-volat ile or otp, the default state is the valu e of the bit when the device is shipped fr om cypress. non-volatile bits have the same cycling (erase and program) endurance as the main flash array. 7.5.1 status register-1 (sr1) related commands: read status register (rdsr1 05h), write registers (wrr 01h) , write enable (wren 06h), write disable (wrdi 04h), clear status register (clsr 30h). the status register contains both status and control bits: status register write disable (srwd) sr1[7] : places the device in the hardware protec ted mode when this bit is set to 1 and the wp# input is driven low. in this mode, the srwd, bp2, bp1, and bp0 bits of the status register become read-only bits and the write registers (wrr) command is no longer accepted for execut ion. if wp# is high the srwd bit and bp bits may be changed by the wrr command. if srwd is 0, wp# has no effect and the sr wd bit and bp bits may be changed by the wrr command. the srwd bit has the same non-volatile endurance as the main flash array. table 19. status register-1 (sr1) bits field name function type default state description 7 srwd status register write disable non-volatile 0 1 = locks state of srwd, bp, and configuration register bits when wp# is low by ignoring wrr command 0 = no protection, even when wp# is low 6 p_err programming error occurred volatile, read only 0 1 = error occurred. 0 = no error 5 e_err erase error occurred volatile, read only 0 1 = error occurred 0 = no error 4 bp2 block protection volatile if cr1[3]=1, non-volatile if cr1[3]=0 1 if cr1[3]=1, 0 when shipped from cypress protects selected range of sectors (block) from program or erase 3 bp1 2 bp0 1 wel write enable latch volatile 0 1 = device accept s write registers (wrr), program or erase commands 0 = device ignore s write registers (wrr), program or erase commands this bit is not affected by wrr, only wren and wrdi commands affect this bit 0 wip write in progress volatile, read only 0 1 = device busy, a write registers (wrr), program, erase or other operation is in progress 0 = ready device is in standby mode and can accept commands document number: 002-00518 rev. *d page 38 of 111 S79FL256S/s79fl512s program error (p_err) sr1[6] : the program error bit is used as a program o peration success or failure indication. when the program error bit is set to a 1 it indicates that there was an error in the last program operation. this bit will also be set w hen the user attempts to program within a protected main memory sector or lo cked otp region. when the program error bit is set to a 1 this b it can be reset to 0 with the clear status regi ster (clsr) command. this is a read-only bit and is not affected by the wrr command . erase error (e_err) sr1[5] : the erase error bit is used as an erase operation su ccess or failure indication. when the erase error bit is set to a 1 it indicates that there was an error in the last erase operation. this bit will also be set when the user att empts to erase an individual protected main memory sector. the bulk erase comma nd will not set e_err if a protec ted sector is found during the command execution. when the erase error bit is set to a 1 this bit can be reset to 0 with the clear status register (clsr) command. this is a read-only bit and is not affected by the wrr command. block protection (bp2, bp1, bp0) sr1[4:2] : these bits define the main flash array area to be software-protected against program and erase commands. the bp bits are either volatile or non-vola tile, depending on the state of the bp non-volatile bit (bpnv) i n the configuration register. when one or more of the bp bits is set to 1, the relevant memory area is protected against program and erase. the bulk erase (be) command can be executed only when the bp bits are cleared to 0?s. see block protection on page 47 for a description of how the bp bit values select the memory array area protected. the bp bi ts have the same non-volatile endurance as the main flash array. write enable latch (wel) sr1[1] : the wel bit must be set to 1 to enable progra m, write, or erase operations as a means to provide protection against inadvertent changes to memory or register values. the writ e enable (wren) command execution sets the write enable latch to a 1 to allow any program, erase, or write commands to execute afte rwards. the write disable (wrdi) command can be used to set the write enable latch to a 0 to prevent all program, eras e, and write commands from execution. the wel bit is cleared to 0 at the end of any successful program, write, or erase operation. fo llowing a failed operation the wel b it may remain set and should be cleared with a wrdi command following a clsr command. after a power down/power up sequence, hardware reset, or software reset, the write enable latch is set to a 0 the wrr command does not affect this bit. write in progress (wip) sr1[0] : indicates whether the device is performing a program, write, erase operation, or any other operation, during which a new operation command will be ignored. when the bit is set to a 1 the device is busy performing an operation. while wip is 1, only read stat us (rdsr1 or rdsr2), erase suspend (er sp), program suspend (p gsp), clear status register (clsr), and software reset (reset) commands may be accepted. ersp and pgsp will only be a ccepted if memory array erase or program operations are in progress. the status r egister e_err and p_err bits are updated while wip = 1. when p_err or e_err bits are set to one, the wip bit will remain set to one indicating the device remains busy and unable to receive new operation commands. a clear status register (clsr) command mu st be received to return the device to standby mode. when the wip bit is cleared to 0 no operation is in progress. this is a read-only bit. 7.5.2 configuration register-1 (cr1) related commands: read configuration regi ster (rdcr 35h), write registers (wrr 01h). t he configuration register bits can be changed using the wrr command with si xteen input cycles. the configuration register co ntrols certain interface and data protection functions. table 20. configuration register (cr1) bits field name function type default state description 7 lc1 latency code non-volatile 0 selects number of init ial read latency cycles see latency code tables 6 lc0 0 5 tbprot configures start of block protection otp 0 1 = bp starts at bottom (low address) 0 = bp starts at top (high address) 4 rfu rfu rfu 0 reserved for future use 3 bpnv configures bp2-0 in status register otp 0 1 = volatile 0 = non-volatile 2 tbparm configures parameter sectors location otp 0 1 = 8-kb physical sectors at top, (high address) 0 = 8-kb physical sector s at bottom (low address) rfu in uniform sector devices document number: 002-00518 rev. *d page 39 of 111 S79FL256S/s79fl512s latency code (lc) cr1[7:6]: the latency code selects the number of mode and dummy cycles between the end of address and the start of read data outp ut for all read commands. some read commands send mode bits following the address to indi cate that the next command will be of the same type with an implied, rather than an explicit, instruction. the next command thus does not provide an instruction byte, only a new address a nd mode bits. this reduces the time needed to send each comma nd when the same command type is repeated in a sequence of commands. dummy cycles provide additional latency that is needed to complete the initial read access of the flash array before data can b e returned to the host system. so me read commands require addit ional latency cycles as the sck frequency is increased. the following latency code tables provide different la tency settings that are configured by cypress. where mode or latency (dummy) cycles are shown in the tables as a dash, that read command is not supported at the frequency shown. read is supported only up to 50 mhz but the same late ncy value is assigned in each latency code and the command may be used when the device is operated at ? 50 mhz with any latency code setting. simila rly, only the fast read command is supported up to 133 mhz but the same 10b latency code is used for fast read up to 133 mhz and for the other dual and quad read commands up to 104 mhz. it is not necessary to change the latency co de from a higher to a lower frequency when operating at lower frequencies where a particular command is s upported. the latency code values for a higher frequency can be used for accesses at lower frequencies. the enhanced high performance settings provide latency options the same or faster than additional alternate source spi memories . read ddr data learning pattern (dlp) bits may be placed within the dummy cycles immediately bef ore the start of read data, if there are 5 or more dummy cycles. see read memory array commands on page 70 for more information on the dlp. 1 quad puts the device into quad i/o operation non-volatile 1 1 = quad for the s79fl-s dual-quad spi device, the default state is set for quad and should not be changed. 0 freeze lock current state of bp2-0 bits in status register, tbprot in configuration register, and otp regions volatile 0 1 = block protection and otp locked 0 = block protection and otp un-locked table 20. configuration register (cr1) (continued) bits field name function type default state description table 21. latency codes for sdr enhanced high performance freq. (mhz) lc read fast read read quad out quad i/o read (03h, 13h) (0bh, 0ch) (6bh, 6ch) (ebh, ech) mode dummy mode dummy mode dummy mode dummy 501100000021 8000- - 080824 9001- - 080824 10410- - 080825 13310--08---- document number: 002-00518 rev. *d page 40 of 111 S79FL256S/s79fl512s note: 1. when using ddr i/o commands with the data learning pattern (dlp) enabled, a latency code that provides 5 or more dummy cycles should be selected to allow 1 cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle dlp. so it is recommended to use lc 00 for ddr quad io read, if the data learning pattern (dlp) for ddr is used. top or bottom protection (tbprot) cr1[5]: this bit defines the operation of the blo ck protection bits bp2, bp1, and bp0 in the status register. as described in the status register section, the bp2-0 bits allow t he user to optionally protect a portion of the array, ranging from 1/64, 1/4, 1/2, etc., up to t he entire array. when tbprot is set to a 0 the block protection is defined to start f rom the top (maximum address) of the array. when tbpr ot is set to a 1 the block protection is defined to start from the bottom (zero address) of the array. the tbprot bit is otp and set to a 0 when shipped from cypress. if t bprot is programmed to 1, an attempt to change it back to 0 will fail and set the program error bit (p_err in sr1[6]). the desired state of tbpr ot must be selected during the init ial configuration of the device during system manufa cture; before t he first program or erase operation on the main flash array. tbprot must not be programmed after programming or erasing is done in the main flash array. cr1[4]: reserved for future use block protection non-volatile (bpnv) cr1[3] : the bpnv bit defines whether or not the bp2-0 bits in the status register are volatile or non-volatile. the bpnv bit is otp and cleared to a0 wit h the bp bits cleared to 000 when shipped from cypress. when bpnv is set to a 0 the bp2-0 bits in the status register are non-volat ile. when bpnv is set to a 1 the bp2-0 bits in the status register are volatile and will be reset to binary 111 after por, hard ware reset, or command reset. if bpnv is programmed to 1, an attempt to change it back to 0 will fail and set the program error bit (p_err in sr1[6]). tbparm cr1[2] : tbparm defines the logical location of the parameter block. t he parameter block consists of thirty-two 8-kb small sectors (sms), which replace two 128-kb sectors. when tbparm is set to a 1 the parameter block is in the top of the memor y array address space. when tbparm is set to a 0 the parameter block is at the bottom of the array. tbparm is otp and set to a 0 when it ships from cypress. if tbparm is programmed to 1, an a ttempt to change it back to 0 will fail and set the program error bit (p_err in sr1[6]). quad data width (quad) cr1[1] : when set to 1, this bit switches the data width of the device to 4-bit quad mode. the commands for serial read still function normally. the quad bit in the s25fl-s devices is factory set to 1 and should not be changed. freeze protection (freeze) cr1[0] : the freeze bit, when set to 1, locks the current state of the bp2-0 bits in status register, the tbprot and tbparm bits in the configuration register, and the otp address space. this preven ts writing, programming, or erasing these areas. as long as the freeze bit remains cleared to logic 0 the other bits of t he configuration register, includi ng freeze, are writable, and the otp address space is programmable. once the freeze bit has been written to a logic 1 it can only be cleared to a logic 0 by a power-off to power-on cycle or a ha rdware reset. software reset will not affect the state of the f reeze bit. the freeze bit is volatile and the def ault state of freeze after power-on is 0. the freeze bit can be set in parallel with updating other values in cr1 by a single wrr command. table 22. latency codes for ddr enhanced high performance freq. (mhz) lc ddr quad i/o read (edh, eeh) mode dummy 50 11 1 3 80 00 1 6 document number: 002-00518 rev. *d page 41 of 111 S79FL256S/s79fl512s 7.5.3 status register-2 (sr2) related commands: read status register-2 (rdsr2 07h). erase suspend (es) sr2[1] : the erase suspend bit is used to determine when the device is in erase suspend mode. this is a status bit that cannot be wri tten. when erase suspend bit is set to 1, the devi ce is in erase suspend mode. when erase suspend bit is cleared to 0, the device is not in erase suspend mode. refe r to erase suspend and resume commands (75h) (7ah) for details about the erase suspend/resume commands. program suspend (ps) sr2[0]: the program suspend bit is used to determine when the device is in program suspend mode. this is a status bit that cannot be writte n. when program suspend bit is set to 1, the device is in program suspend mode. when the program suspend bit is cleared to 0, the device is not in program suspend mode. refer to program suspend (pgsp 85h) and resume (pgrs 8ah) on page 80 for details. 7.5.4 autoboot register related commands: autoboot read (abrd 14h) and autoboot write (abwr 15h). the autoboot register provides a means to au tomatically read boot code as part of the power on reset, hardwa re reset, or softwa re reset process. 7.5.5 bank address register related commands: bank register access (brac b9h), write register (wrr 01h), bank regi ster read (brrd 16h) and bank register write (brwr 17h). the bank address register supplies additional high order bits of the main flash array byte boundary address for legacy commands that supply only the low order 24 bits of address. the bank address is used as the hi gh bits of address (above a23) for all 3-b yte address commands when extadd=0. the bank address is not us ed when extadd = 1 and traditional 3-byte address commands are instead required to provide all four bytes of address. table 23. status register-2 (sr2) bits field name function type default state description 7 rfu reserved 0 reserved for future use 6 rfu reserved 0 reserved for future use 5 rfu reserved 0 reserved for future use 4 rfu reserved 0 reserved for future use 3 rfu reserved 0 reserved for future use 2 rfu reserved 0 reserved for future use 1 es erase suspend volatile, read only 0 1 = in erase suspend mode 0 = not in erase suspend mode 0 ps program suspend volatile, read only 0 1 = in program suspend mode 0 = not in program suspend mode table 24. autoboot register bits field name function type default state description 31 to 9 absa autoboot start address non-volatile 000000h 512 byte boundary address for the start of boot code access 8 to 1 absd autoboot start delay non-volatile 00h number of initial delay cycles between cs# going low and the first bit of boot code being transferred 0 abe autoboot enable non-volatile 0 1 = autoboot is enabled 0 = autoboot is not enabled document number: 002-00518 rev. *d page 42 of 111 S79FL256S/s79fl512s extended address (extadd) bar[7]: extadd controls the address field size for le gacy spi commands. by default (power up reset, hardware reset, a nd software reset), it is cleared to 0 for 3 bytes (2 4 bits) of address. when set to 1, the legacy comm ands will require 4 bytes (32 bits) for the address field. this is a volatile bit. 7.5.6 ecc status register (eccsr) related commands: ecc read (eccrd 18h). eccsr does not have user programmable non- volatile bits. all defined bits are volatile read only status. the default state of these bits are set by hardware. see section 9.5.1.1, automatic ecc on page 77 . the status of ecc in each ecc unit is provided by the 8-bit ecc status register (eccsr). th e ecc register read command is written followed by an ecc unit address. the contents of the st atus register then indicates, for the selected ecc unit, whether there is an error in the ecc unit eight bit error correction code, the e cc unit of 16 bytes of data, or that ecc is disabled for that ecc unit. eccsr[2] = 1 indicates an error was corrected in the ecc. eccsr[ 1] = 1 indicates an error was corrected in the ecc unit data. eccsr[0] = 1 indicates the ecc is disabled. the default state of ?0? for all these bits indicates no failures and ecc is enable d. eccsr[7:3] are reserved. these have undefined high or low values that can change fr om one ecc status read to another. these bits should be treated as ?don?t care? an d ignored by any software reading status. table 25. bank address register (bar) bits field name function type default state description 7 extadd extended address enable volatile 0b 1 = 4-byte (32-bits) addressing required from command. 0 = 3-byte (24-bits) addressing from command + bank address 6 to 2 rfu reserved volatile 00000b reserved for future use 1 ba25 bank address volatile 0 a25 for 1 gb device 0 rfu bank address volatile 0 rfu for lower density device table 26. ecc status register (eccsr) bits field name function type default state description 7 to 3 rfu reserved 0 reserved for future use 2 eecc error in ecc volatile, read only 0 1 = single bit error found in the ecc unit eight bit error correction code 0 = no error. 1 eeccd error in ecc unit data volatile, read only 0 1 = single bit error co rrected in ecc unit data. 0 = no error. 0 eccdi ecc disabled volatile, read only 0 1 = ecc is disabled in the selected ecc unit. 0 = ecc is enabled in the selected ecc unit. document number: 002-00518 rev. *d page 43 of 111 S79FL256S/s79fl512s 7.5.7 asp register (aspr) related commands: asp r ead (asprd 2bh) and asp program (aspp 2fh). the asp register is a 16-bit otp memory lo cation used to permanen tly configure the behavior of ad vanced sector protection (asp) features. note: 1. default value depends on ordering part number, see initial delivery state on page 107 . reserved for future use (rfu) aspr[15:3, 0] . password protection mode lock bit (pwdmlb) aspr[2]: when programmed to 0, the password protection mode is permanently selected. persistent protection mode lock bit (pst mlb) aspr[1]: when programmed to 0, the persistent protection mode is permanently selected. pwdmlb and pstmlb are mutually exclusive, only one may be programmed to zero. 7.5.8 password register (pass) related commands: password read (passrd e7h) and password program (passp e8h). table 27. asp register (aspr) bits field name function type default state description 15 to 9 rfu reserved otp 1 reserved for future use 8 rfu reserved otp (note 1) reserved for future use 7 rfu reserved otp (note 1) reserved for future use 6 rfu reserved otp 1 reserved for future use 5 rfu reserved otp (note 1) reserved for future use 4 rfu reserved otp (note 1) reserved for future use 3 rfu reserved otp (note 1) reserved for future use 2 pwdmlb password protection mode lock bit otp 1 0 = password protection mode permanently enabled. 1 = password protection mode not permanently enabled. 1 pstmlb persistent protection mode lock bit otp 1 0 = persistent protection mode permanently enabled. 1 = persistent protection mode not permanently enabled. 0 rfu reserved otp 1 reserved for future use table 28. password register (pass) bits field name function type default state description 63 to 0 pwd hidden password otp ffffffff- ffffffffh non-volatile otp storage of 64-bit password. the password is no longer readable after the password protection mode is selected by programming asp register bit 2 to zero. document number: 002-00518 rev. *d page 44 of 111 S79FL256S/s79fl512s 7.5.9 ppb lock register (ppbl) related commands: ppb lock read (plbrd a7h, plbwr a6h) 7.5.10 ppb access re gister (ppbar) related commands: ppb read (ppbrd e2h) 7.5.11 dyb access re gister (dybar) related commands: dyb read (dybrd e0h) and dyb program (dybp e1h). table 29. ppb lock register (ppbl) bits field name function type default state description 7 to 1 rfu reserved volatile 00h reserved for future use 0 ppblock protect ppb array volatile persistent protection mode = 1 password protection mode = 0 0 = ppb array protected until next power cycle or hardware reset 1 = ppb array may be programmed or erased. table 30. ppb access register (ppbar) bits field name function type default state description 7 to 0 ppb read or program per sector ppb non-volatile ffh 00h = ppb for the sector addressed by the ppbrd or ppbp command is programmed to 0, protecting that sector from program or erase operations. ffh = ppb for the sector addressed by the ppbrd or ppbp command is erased to 1, not protecting that sector from program or erase operations. table 31. dyb access register (dybar) bits field name function type default state description 7 to 0 dyb read or write per sector dyb volatile ffh 00h = dyb for the sector addressed by the dybrd or dybp command is cleared to 0, protecting that sector from program or erase operations. ffh = dyb for the sector addressed by the dybrd or dybp command is set to 1, not protecting that sector from program or erase operations. document number: 002-00518 rev. *d page 45 of 111 S79FL256S/s79fl512s 7.5.12 spi ddr data learning registers related commands: program nvdlr (pnvdl r 43h), write vdlr (wvdlr 4ah), data learning pattern read (dlprd 41h). the data learning pattern (dlp) resides in an 8-bit non-volatile da ta learning register (nvdlr) as well as an 8-bit volatile da ta learning register (vdlr). when shipped from cypress, the nvdlr value is 00h. once programmed, the nvdlr cannot be reprogrammed or erased; a copy of the data pattern in the nvdlr wil l also be written to the vdlr. the vdlr can be written to at any time, but on reset or power cycles the data pattern will revert back to what is in the nvdl r. during the learning phase des cribed in the spi ddr modes, the dlp will come from the vdlr. each io will output the same dlp value for every clock edge. for example, if the dlp is 34h (or binary 00110100) then during th e first clock edge all io?s will output 0; subsequently, the 2nd clock edge all i/o?s will output 0, the 3rd will output 1, etc. when the vdlr value is 00h, no preamb le data pattern is presented durin g the dummy phase in the ddr commands. table 32. non-volatile data learning register (nvdlr) bits field name function type default state description 7 to 0 nvdlp non-volatile data learning pattern otp 00h otp value that may be transferred to the host during ddr read command latency (dummy) cycles to provide a training pattern to help the host more accurately center the data capture point in the received data bits. table 33. volatile data learning register (nvdlr) bits field name function type default state description 7 to 0 vdlp volatile data learning pattern volatile takes the value of nvdlr during por or reset volatile copy of the nvdlp used to enable and deliver the data learning pattern (dlp) to t he outputs. the vdlp may be changed by the host during system operation. document number: 002-00518 rev. *d page 46 of 111 S79FL256S/s79fl512s 8. data protection 8.1 secure silicon region (otp) the device has a 2048-byte one time program (otp) address space th at is separate from the main flash array. the otp area is divided into 32, individually lockable, 64-byte aligned and length regions. the otp memory space is intended for increased system securi ty. otp values can ?mate? a flash component with the system cpu/ asic to prevent device substitution. see otp address space on page 35 , one time program array commands on page 85 , and otp read (otpr 4bh) on page 85 . 8.1.1 reading otp memory space the otp read command uses the same protocol as fast read. otp read operations outside the valid 2-kb otp address range will yield indeterminate data. 8.1.2 programming otp memory space the protocol of the otp programming command is the same as page program. the otp program command can be issued multiple times to any given otp address, but this address space can never be erased. automatic ecc is programmed on the first programming operation to each 16-byte region. programming within a 16-byte region more than once disables the ecc. it is recommended to program each 16-byte portion of each 32-byte region once so that ecc remains enabled to provide the best data integrity. the valid address range for otp program is depicted in figure 29, otp address space ? quad spi-1 and spi-2 on page 36 . otp program operations outside the valid otp address range will be ig nored and the wel in sr1 will remain high (set to 1). otp program operations while freeze = 1 will fail with p_err in sr1 set to 1. 8.1.3 cypress programmed random number cypress standard practice is to program the low order 16 bytes of the otp memory space (locations 0x0 to 0xf) with a 128-bit random number using the linear congruential random number meth od. the seed value for the algorithm is a random number concatenated with the day and time of tester insertion. 8.1.4 lock bytes the lsb of each lock byte protects the lowest address region related to the byte, the msb protects the highest address region related to the byte. the next higher address byte similarly prot ects the next higher 8 regions. the lsb bit of the lowest addre ss lock byte protects the higher address 16 bytes of the lowest address region. in other word s, the lsb of location 0x10 protects all t he lock bytes and rfu bytes in the lowest address region from further programming. see section 7.4, otp address space on page 35 . 8.2 write enable command the write enable (wren) command must be written prior to an y command that modifies non-volatile data. the wren command sets the write enable latch (wel) bit. the wel bit is cleared to 0 (disables writes) during power-u p, hardware reset, or after the device completes t he following commands: ?reset ? page program (pp) ? sector erase (se) ? bulk erase (be) ? write disable (wrdi) ? write registers (wrr) ? quad-input page programming (qpp) ? otp byte programming (otpp) document number: 002-00518 rev. *d page 47 of 111 S79FL256S/s79fl512s 8.3 block protection the block protect bits (status register bits bp2, bp1, bp0) in combination with the configurati on register tbprot bit can be us ed to protect an address range of the main flash array from program and erase operations. the size of the range is determined by t he value of the bp bits and the upper or lower starting point of the range is selected by the tbprot bit of the configuration regi ster. when block protection is enabled (i.e., any bp2-0 are set to 1), advanced sector protection (asp) can still be used to protect sectors not protected by the block protecti on scheme. in the case that both asp and bl ock protection are used on the same secto r the logical or of asp and block protection related to the sector is used. recommendation: asp an d block protection should not b e used concurrently. use one or the other, but not both. 8.3.1 freeze bit bit0 of the configuration register is the freeze bit. the freeze bit locks the bp2-0 bits in status register-1 and the tbprot b it in the configuration register to their value at the time the fr eeze bit is set to 1. once the freeze bit has been written to a logic 1 it cannot be cleared to a logic 0 until a power-on-reset is exec uted. as long as the freeze bit is cleared to logic 0 the statu s register bp bits and the tbprot bit of the configuration register are writ able. the freeze bit also protects the entire otp memory space from programming when set to 1. any attempt to change the bp bits with the wrr command while freeze = 1 is ignored and no error status is set. table 34. upper array start of protection (tbprot = 0) status register content protected fraction of memory array protected memo ry (kbytes) bp2 bp1 bp0 S79FL256S 256 mb s79fl512s 512 mb 000none00 0 0 1 upper 64th 512 1024 0 1 0 upper 32nd 1024 2048 0 1 1 upper 16th 2048 4096 1 0 0 upper 8th 4096 8192 1 0 1 upper 4th 8192 16384 1 1 0 upper half 16384 32768 1 1 1 all sectors 32768 65536 table 35. lower array start of protection (tbprot = 1) status register content protected fraction of memory array protected memo ry (kbytes) bp2 bp1 bp0 S79FL256S 256 mb s79fl512s 512 mb 000none00 0 0 1 lower 64th 512 1024 0 1 0 lower 32nd 1024 2048 0 1 1 lower 16th 2048 4096 1 0 0 lower 8th 4096 8192 1 0 1 lower 4th 8192 16384 1 1 0 lower half 16384 32768 1 1 1 all sectors 32768 65536 document number: 002-00518 rev. *d page 48 of 111 S79FL256S/s79fl512s 8.4 advanced sector protection advanced sector protection (asp) is the name used for a set of independent hardware and softwar e methods used to disable or enable programming or erase operations, individually, in any or all sectors. an overview of these methods is shown in figure 30 . block protection and asp protection settings for each sector are logically or?d to def ine the protection for each sector, i.e. if either mechanism is protecting a sector the sector cannot be programmed or erased. refer to block protection on page 47 for full details of the bp2-0 bits. figure 30. advanced sector protection overview every main flash array sector has a non-vo latile (ppb) and a vo latile (dyb) protection bit asso ciated with it. wh en either bit is 0, the sector is protected from pr ogram and erase operations. the ppb bits are protected from program and erase when the ppb lo ck bit is 0. there are two meth ods for managing the state of the ppb lock bit, persistent prot ection and password protection. the persistent protection method sets the ppb lock bit to 1 durin g por, or hardware reset so that the ppb bits are unprotected by a device reset. there is a command to clear the ppb lock bit to 0 to protect the ppb. there is no comman d in the persistent protection method to set the ppb lock bit to 1, therefore the ppb lock bit will rema in at 0 until the next power-off or hardwar e reset. the persistent protection method allows boot code the option of changing sector prot ection by programming or erasing the ppb, then protecting the ppb from furt her change for the remainder of normal system operation by clea ring the ppb lock bit to 0. thi s is sometimes called boot-code controlled sector protection. the password method clears the ppb lock bit to 0 during por, or hardwa re reset to protect the ppb. a 64-bit password may be permanently programmed and hidden for the password method. a comm and can be used to provide a password for comparison with the hidden password. if the passw ord matches, the ppb lock bit is set to 1 to u nprotect the ppb. a command can be used to clear the ppb lock bit to 0. this method requires use of a password to control ppb protection. the selection of the ppb lock bit management method is made by programming otp bits in the asp register so as to permanently select the method used. asp register one time programmable password method ( aspr[2]=0) persistent method ( aspr[1]=0) 64 - bit password (one time protect) pbb lock bit ?0? = ppbs locked sector 0 memory array sector n - 2 sector 1 sector 2 sector n - 1 sector n 1.) n = highest address sector ppb 0 persistent protection bit (ppb) ppb n - 2 ppb 1 ppb 2 ppb n - 1 ppb n dyb 0 dynamic protection bit (dyb) dyb n - 2 dyb 1 dyb 2 dyb n - 1 dyb n 2.) 3.) dyb are volatile bits ?1? =ppbs unlocked 64 - (one time protect) a sector is protected if its ppb =?0? or its dyb = ?0? - 1 - - - ppb are programmed individually but erased as a group 4.) ppb lock bit is volatile and defaults to ?1? (persistent mode), or ?0? (password mode) upon reset 5.) ppb lock = ?0? locks all ppbs to their current state 6.) password method requires a password to set ppb lock to ?1? to enable program or erase of ppb bits 7.) persistent method only allows ppb lock to be cleared to ?0? to prevent program or erase of ppb bits. power off or hardware reset required to set ppb lock to ?1? document number: 002-00518 rev. *d page 49 of 111 S79FL256S/s79fl512s 8.4.1 asp register the asp register is used to permanently configure the behavior of advanced se ctor protection (asp) features. see table 27, asp register (aspr) on page 43 . as shipped from the factory, all devices default asp to the persistent protection mo de, with all sectors u nprotected, when powe r is applied. the device programmer or host system must then choose which sector protection method to use. programming either of the, one-time programmable, protecti on mode lock bits, locks the part pe rmanently in the selected mode: ? aspr[2:1] = 11 = no asp mode selected, pers istent protection mode is the default. ? aspr[2:1] = 10 = persistent prot ection mode permanently selected. ? aspr[2:1] = 01 = password protection mode permanently selected. ? aspr[2:1] = 00 = illegal condition, attempting to program both bits to zero results in a programming failure. asp register programming rules: ? if the password mode is chosen, the password must be progra mmed prior to setting the protection mode lock bits. ? once the protection mode is selected, the protection mode lock bits are permanently protected from programming and no further changes to the asp register is allowed. the programming time of the asp register is the same as the ty pical page programming time. the system can determine the status of the asp register programming operation by re ading the wip bit in the status register. see status register-1 (sr1) on page 37 for information on wip. after selecting a sector protecti on method, each sector can operate in each of the following states: ? dynamically locked ? a sector is protect ed and can be changed by a simple command. ? persistently locked ? a sector is protec ted and cannot be changed if its ppb bit is 0. ? unlocked ? the sector is unprotected and can be changed by a simple command. 8.4.2 persistent protection bits the persistent protection bits (ppb) are located in a se parate nonvolatile flash array. one of the ppb bits is related to each sector. when a ppb is 0, its related se ctor is protected from program and erase operat ions. the ppb are programm ed individually but mus t be erased as a group, similar to the way individual words may be pr ogrammed in the main array but an entire sector must be eras ed at the same time. the ppb have the same program and erase e ndurance as the main flash memory array. preprogramming and verification prior to erasure are handled by the device. programming a ppb bit requ ires the typical page programming time. erasing all the ppbs requires typical sector erase time. duri ng ppb bit programming and ppb bit erasing, status is available by re ading the status register. read ing of a ppb bit requires the initial access time of the device. persistent protection notes: ? each ppb is individually programmed to 0 and all are erased to 1 in parallel. ? if the ppb lock bit is 0, the ppb program or ppb erase command doe s not execute and fa ils without programmi ng or erasing the ppb. ? the state of the ppb for a given sector can be verified by usi ng the ppb read command. document number: 002-00518 rev. *d page 50 of 111 S79FL256S/s79fl512s 8.4.3 dynamic protection bits dynamic protection bits are volatile and unique for each sector and can be individually modified. dyb only control the protecti on for sectors that have their ppb set to 1. by issuing the dyb write command, a dyb is cleared to 0 or set to 1, thus placing each se ctor in the protected or unprotected state res pectively. this feature allows software to easily protect sectors against inadvertent changes, yet does not prevent the easy removal of protection when changes are needed. the dybs can be set or cleared as often as needed as they are volatile bits. 8.4.4 ppb lock bit (ppbl[0]) the ppb lock bit is a volatile bit for protecting all ppb bits. when cleared to 0, it locks all ppbs and when set to 1, it allo ws the ppbs to be changed. the plbwr command is used to clear the ppb lock bit to 0. the ppb lock bit must be clear ed to 0 only after all the ppbs are configured to the desired settings. in persistent protection mode, the ppb lock is set to 1 during por or a ha rdware reset. when cleared to 0, no software command sequence can set the ppb lock bit to 1, only another hardware reset or power-up can set the ppb lock bit. in the password protection mode, the ppb lock bit is cleare d to 0 during por or a hardware reset. the ppb lock bit can only be set to 1 by the password unlock command. 8.4.5 sector protection states summary each sector can be in one of the following protection states: ? unlocked ? the sector is unprotected and protection can be cha nged by a simple command. the protection state defaults to unprotected after a power cycle, so ftware reset, or hardware reset. ? dynamically locked ? a sector is protect ed and protection can be changed by a simple command. the protection state is not saved across a power cycle or reset. ? persistently locked ? a sector is protecte d and protection can only be changed if the ppb lock bit is set to 1. the protection state is non-volatile and saved across a power cycle or reset. changing the protection state requires programming and or erase of the ppb bits table 36. sector protection states protection bit values sector state ppb lock ppb dyb 1 1 1 unprotected ? ppb and dyb are changeable 1 1 0 protected ? ppb and dyb are changeable 1 0 1 protected ? ppb and dyb are changeable 1 0 0 protected ? ppb and dyb are changeable 0 1 1 unprotected ? ppb not changeable, dyb is changeable 0 1 0 protected ? ppb not changeable, dyb is changeable 0 0 1 protected ? ppb not changeable, dyb is changeable 0 0 0 protected ? ppb not changeable, dyb is changeable document number: 002-00518 rev. *d page 51 of 111 S79FL256S/s79fl512s 8.4.6 persistent protection mode the persistent protection method sets the ppb lock bit to 1 during por or hardware reset so that the ppb bits are unprotected b y a device hardware reset. softwa re reset does not affect the ppb lock bit. the plbwr command can clear the ppb lock bit to 0 to protect the ppb. there is no command to set the ppb lock bit therefore the ppb lock bit will remain at 0 until the next power-o ff or hardware reset. 8.4.7 password protection mode password protection mode allows an even higher level of security t han the persistent sector protec tion mode, by requiring a 64- bit password for unlocking the ppb lock bit. in addition to this password requirement, after power up and hardware reset, the ppb l ock bit is cleared to 0 to ensure protection at power-up. successf ul execution of the password un lock command by entering the entir e password clears the ppb lock bit, al lowing for sector ppb modifications. password protection notes: ? once the password is programmed and verified, the password mode (aspr[2]=0) must be set in order to prevent reading the password. ? the password program command is only capable of programming ?0?s. programming a 1 after a cell is programmed as a 0 results in the cell left as a 0 with no programming error set. ? the password is all 1?s when shipped from cypress. it is located in its own memory space and is accessible through the use of t he password program and password read commands. ? all 64-bit password combinations are valid as a password. ? the password mode, once programmed, prevents reading the 64 -bit password and further pass word programming. all further program and read commands to the password region are disabled and these commands are ignored. there is no means to verify what the password is after the password mode lock bit is selected. password verification is only allowed before selecting the password protection mode. ? the protection mode lock bits are not erasable. ? the exact password must be entered in order for the unlocking function to occur. if the password unlock command provided password does not match the hidden internal password, the unl ock operation fails in the same manner as a programming operation on a protected sector. the p_err bit is set to one and t he wip bit remains set. in this case it is a failure to chang e the state of the ppb lock bit because it is stil l protected by the lack of a valid password. ? the password unlock command cannot be accepted any faster than once every 100 s 20 s. this makes it take an unreasonably long time (58 million years) for a hacker to run th rough all the 64-bit combinations in an attempt to correctly ma tch a password. the read status register-1 co mmand may be used to read the wip bit to determine when the device has completed the password unlock command or is ready to accept a new pa ssword command. when a valid password is provided the password unlock command does not insert the 100 s de lay before returning the wip bit to zero. ? if the password is lost after se lecting the password mo de, there is no way to set the ppb lock bit. ? ecc status may only be read from sectors that are readable. in read protection mode the addresses are forced to the boot sector address. ecc status is shown in that se ctor while read protection mode is active. document number: 002-00518 rev. *d page 52 of 111 S79FL256S/s79fl512s 9. commands all communication between the host system and the s25fl-s dual-quad spi memory devices is in the form of units called commands. all commands begin with an instruction that selects the type of information transfer or device operation to be performed. comma nds may also have an address, instruction modifier, latency period, da ta transfer to the memory, or data transfer from the memory. all instruction, address, and data information is transferred serially between the host system and memory device. all instructions are transferred from host to memory as a single bit serial sequence on the si signal. single bit wide commands may provide an address or data sent only on the si signal. data may be sent back to the host serially on so signal. quad output commands provide an address sent to the memory only on the io0 and io4 signal. data will be returned to the host as a sequence of 8-bit (byte) groups on io0 - io7. quad input/output (i/o) commands provide an address sent from the host as four-bit (nibble) groups on quad spi-1 io0 - io3 and quad spi-2 io4 - io7. data is returned to the host similarly as 8-bit (byte) groups on io0 - io7. commands are structured as follows: ? each command begins with an eight bit (byte) instruction. ? the instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in the device. the address may be either a 24-bit or 32-bit byte boundary address. ? the s25fl-s serial peripheral interface with multiple io provides the option for each transfer of address and data information to be done one, or four bits in parallel. this enables a trade of f between the number of signal connections (io bus width) and the speed of information transfer. if the host system can support a f our-bit wide io bus the memory performance can be increased by using the instructions t hat provide parallel four-bit (quad) transfers. ? the width of all transfers following the instruct ion are determined by the instruction sent. ? all single bits or parallel bit groups are transfe rred in most to least significant bit order. ? some instructions send instruction modifier (mode) bits followin g the address to indicate that the next command will be of the same type with an implied, rather than an explicit, instruction. the next command thus does not provide an instruction byte, on ly a new address and mode bits. this reduces the time needed to send each command when the same command type is repeated in a sequence of commands. ? the address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host. ? read latency may be zero to several sck cycl es (also referred to as dummy cycles). ? all instruction, address, mode, and data information is transferre d in byte granularity. addresses are shifted into the device with the most significant byte first. all data is transferred with the lowest address by te sent first. following bytes of data are s ent in lowest to highest byte address order i.e. the byte address increments. ? all attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. the embedded operation will continue to execute without any affect. a very limited set of commands are accepted during an embedded operation. these are discussed in the individual command descriptions. while a program, erase, or write operation is in progress, it is recommended to check that the write-in progre ss (wip) bit is 0 before issuing most commands to the device, t o ensure the new command can be accepted. ? depending on the command, the time for execution varies. a co mmand to read status information fr om an executing command is available to determine when the command completes execution and whether the command was successful. ? although host software in some cases is used to directly cont rol the spi interface signals, the hardware interfaces of the host system and the memory device gener ally handle the details of signal relationships and ti ming. for this reas on, signal relations hips and timing are not covered in detail within this software interf ace focused section of the document. instead, the focus is on t he logical sequence of bits transferred in each command rather than the signal timing and relationships. following are some genera l signal relationship descriptions to keep in mind. for additional information on the bit level format and signal timing relation ships of commands, see command protocol on page 11 . document number: 002-00518 rev. *d page 53 of 111 S79FL256S/s79fl512s ? the host always controls the chip select (cs#), serial clo ck (sck), and serial input (io0 and io4) for single-bit wide transfers. the memory drives the io0-io7 signals during transfers. ? all commands begin with the host selecting the memory by driving cs# low before th e first rising edge of sck. cs# is kept low throughout a command and when cs# is returned high the command ends. generally, cs# remains low for eight bit transfer multiples to transfer byte granular ity information. some commands will not be accepted if cs# is returned high not at an 8-bit boundary. 9.1 command set summary the S79FL256S/s79fl512s dual-quad spi devices each contain tw o quad spi devices (quad spi-1 and quad spi-2)) stacked in a dual die package (ddp). both devices are selected to dec ode each command instruction and address when the cs# signal, shared by both devices, goes low. quad spi-1 device responds to commands, address, data in and data out on io0-io3. quad spi- 2 device responds to commands, address, data in and data out on io 4-io7. all commands are executed by both devices in parallel. both quad spi devices must be co nfigured, by writing to the various status and c onfiguration registers in parallel, to define t he same overall sector map and behavior of both devices, selected by each cs# for the ddp. 9.1.1 extended addressing to accommodate addressing above 128 mb, there are three options: 1. new instructions are provided with 4-byte add ress, used to access up to 32 gb of memory. instruction name description code (hex) 4fast_read read fast (4-byte address) 0c 4read read (4-byte address) 13 4qor read quad out (4-byte address) 6c 4qior quad i/o read (4-byte address) ec 4ddrqior ddr quad i/o read (4-byte address) ee 4pp page program (4-byte address) 12 4qpp quad page program (4-byte address) 34 4p4e parameter 8-kb erase (4-byte address) 21 4se erase 512 kb (4-byte address) dc document number: 002-00518 rev. *d page 54 of 111 S79FL256S/s79fl512s 2. for backward compatibility to the 3-byte address instructions , the standard instructions can be used in conjunction with the extadd bit in the bank address register (bar[7]). by default bar[7] is cleared to 0 (following power up and hardware reset), to enable 3-byte (24-bit) addressing. when set to 1, the legacy commands are changed to require 4 bytes (32 bits) for the address field. the following instructions can be used in conjunction with extadd bit to switch from 3 bytes to 4 bytes of address field. 3. for backward compatibility to the 3-byte addressing, the st andard instructions can be used in conjunction with the bank address register: a. the bank address register is used to switch between 128-mbit (16-mbyte) banks of memory, the standard 3-byte address selects an address within the bank selected by the bank address register. i. the host system writes the bank address r egister to access beyond the first 128 mbits of memory. ii. this applies to read, er ase, and program commands. b. the bank register provides the high order (4th) byte of address, which is used to addr ess the available memory at addresses greater than 16 mbytes. c. bank register bits are volatile. i. on power up, the default is bank0 (the lowest address 16 mbytes). d. for read, the device will continuously trans fer out data until the end of the array. i. there is no bank to bank delay. ii. the bank address register is not updated. iii. the bank address register value is used only for the initial address of an access. instruction name description code (hex) read read (3-byte address) 03 fast_read read fast (3-byte address) 0b qor read quad out (3-byte address) 6b qior quad i/o read (3-byte address) eb ddrqior ddr quad i/o read (3-byte address) ed pp page program (3-byte address) 02 qpp quad page program (3-byte address) 32 p4e parameter 8-kb erase (3-byte address) 20 se erase 128 / 512 kb (3-byte address) d8 table 37. bank address map bank address register bits bank memory array address range (hex) bit 1 bit 0 0 0 0 00000000 00ffffff 0 1 1 01000000 01ffffff 1 0 2 02000000 02ffffff 1 1 3 03000000 03ffffff document number: 002-00518 rev. *d page 55 of 111 S79FL256S/s79fl512s table 38. S79FL256S/s79fl512s command set (sorted by function) function command name command description instruction value (hex) maximum frequency (mhz) read device identification read_id (rems) read electronic manufacturer signature 90 133 rdid read id (jedec manufacturer id and jedec cfi) 9f 133 res read electronic signature ab 50 register access rdsr1 read status register-1 05 133 rdsr2 read status register-2 07 133 rdcr read configuration register-1 35 133 wrr write register (status-1, configuration-1) 01 133 wrdi write disable 04 133 wren write enable 06 133 clsr clear status register-1 - erase/prog. fail reset 30 133 eccrd ecc read (4-byte address) 18 133 abrd autoboot register read 14 133 (quad=0) 104 (quad=1) abwr autoboot register write 15 133 brrd bank register read 16 133 brwr bank register write 17 133 brac bank register access (legacy command formerly used for deep power down) b9 133 dlprd data learning pattern read 41 133 pnvdlr program nv data learning register 43 133 wvdlr write volatile data learning register 4a 133 read flash array read read (3- or 4-byte address) 03 50 4read read (4-byte address) 13 50 fast_read fast read (3- or 4-byte address) 0b 133 4fast_read fast read (4-byte address) 0c 133 qor read quad out (3- or 4-byte address) 6b 104 4qor read quad out (4-byte address) 6c 104 qior quad i/o read (3- or 4-byte address) eb 104 4qior quad i/o read (4-byte address) ec 104 ddrqior ddr quad i/o read (3- or 4-byte address) ed 66 4ddrqior ddr quad i/o read (4-byte address) ee 66 program flash array pp page program (3- or 4-byte address) 02 133 4pp page program (4-byte address) 12 133 qpp quad page program (3- or 4-byte address) 32 80 qpp quad page program - alternate instruction (3- or 4-byte address) 38 80 4qpp quad page program (4-byte address) 34 80 pgsp program suspend 85 133 pgrs program resume 8a 133 document number: 002-00518 rev. *d page 56 of 111 S79FL256S/s79fl512s 9.1.2 read device identification there are multiple commands to read information about the device manufacturer, device type, and device features. spi memories from different vendors have used different commands and forma ts for reading information about the memories. the S79FL256S/ s79fl512s devices support the three most common device information commands. erase flash array p4e parameter 8-kb, sector erase (3- or 4-byte address) 20 133 4p4e parameter 8-kb, sector erase (4-byte address) 21 133 be bulk erase 60 133 be bulk erase (alternate command) c7 133 se erase 128 kb or 512 kb (3- or 4-byte address) d8 133 4se erase 128 kb or 512 kb (4-byte address) dc 133 ersp erase suspend 75 133 errs erase resume 7a 133 one time program array otpp otp program 42 133 otpr otp read 4b 133 advanced sector protection dybrd dyb read e0 133 dybwr dyb write e1 133 ppbrd ppb read e2 133 ppbp ppb program e3 133 ppbe ppb erase e4 133 asprd asp read 2b 133 aspp asp program 2f 133 plbrd ppb lock bit read a7 133 plbwr ppb lock bit write a6 133 passrd password read e7 133 passp password program e8 133 passu password unlock e9 133 reset reset software reset f0 133 mbr mode bit reset ff 133 reserved for future use mpm reserved for multi-i/o-high perf mode (mpm) a3 133 rfu reserved-18 reserved 18 rfu reserved-e5 reserved e5 rfu reserved-e6 reserved e6 table 38. S79FL256S/s79fl512s command set (sorted by function) (continued) function command name command description instruction value (hex) maximum frequency (mhz) document number: 002-00518 rev. *d page 57 of 111 S79FL256S/s79fl512s 9.1.3 register read or write there are multiple registers for reporting embedded operation st atus or controlling device c onfiguration options. there are commands for reading or writing these registers. registers contai n both volatile and non-volatile bits. non-volatile bits in re gisters are automatically erased and programmed as a single (write) operation. 9.1.3.1 monitoring operation status the host system can determine when a write, pr ogram, erase, suspend or ot her embedded o peration is complete by monitoring the write in progress (wip) bit in the status re gister. the read from status register-1 command provides the state of the wip bit. the program error (p_err) and erase error (e_err) bits in the status register indicate whether the most recent program or erase command has not completed successfully. when p_err or e_err bits are set to one, the wip bit will remain set to one indicating the device remains busy. under this condition, only the clsr, wrdi, rdsr1, rdsr2, and software reset commands are valid commands. a clear status register (clsr) followed by a write disable (wrdi) command must be sent to return the device to standby state. clsr clears the wip, p_err, and e_err bits. wrdi clears the wel bit. al ternatively, hardware reset, or software reset (reset) may be used to retu rn the device to standby state. 9.1.3.2 configuration there are commands to read, write, and prot ect registers that control interface path width, interface timing, interface address length, and some aspects of data protection. 9.1.4 read flash array data may be read from the memory starting at any byte boundary. data bytes are sequ entially read from incrementally higher byte addresses until the host ends the data transfer by driving cs# i nput high. if the byte address reaches the maximum address of t he memory array, the read will continue at address zero of the array. there are several different read commands to specify different access latency and data path widths. double data rate (ddr) commands also define the address and data bit relationship to both sck edges: ? the read command provides a single address bit per sck rising edge on the io0 and io4 signal with read data returning a single bit per sck falling edge on the io1 and io5 signal. this command has zero latency between the address and the returning data but is limited to a maximum sck rate of 50 mhz. ? other read commands have a latency period between the address and returning data but can operat e at higher sck frequencies. the latency depends on the configuration register latency code. ? the fast read command provides a single address bit per sck rising edge on the io0 and io4 signal with read data returning a single bit per sck falling edge on the io1 and io5 signal and may operate up to 133 mhz. ? quad output read commands provide address a single bit per sc k rising edge on the io0 and io4 signal with read data returning four bits of data per sck falling edge on the io0- io7 signals. ? quad i/o read commands provide address four bits per sck rising edge with read data returning four bits of data per sck falling edge on the io0-io7 signals. ? quad double data rate read command provides address four bits per every sck edge with read data returning four bits of data per every sck edge on the io0-io7 signals. double data rate (ddr) operation is only supported for core and i/o voltages of 3 to 3.6v. document number: 002-00518 rev. *d page 58 of 111 S79FL256S/s79fl512s 9.1.5 program flash array programming data requires two commands: write enable (wren) , and page program (pp or qpp). the page program command accepts from 1 byte up to 512 or 1024 consecutive bytes of data (page) to be programmed in one operation. programming means that bits can either be left at 1, or programmed from 1 to 0. changing bits from 0 to 1 requires an erase operation. 9.1.6 erase flash array the sector erase (se) and bulk erase (be) commands set all the bits in a sector or the entire memory array to 1. a bit needs to be first erased to 1 before programming can change it to a 0. while bi ts can be individually programmed from a 1 to 0, erasing bit s from 0 to 1 must be done on a sector-wide (se) or array-wide (be) level. 9.1.7 otp, block protection, an d advanced sector protection there are commands to read and program a separate one time pr ogrammable (otp) array for permanent data such as a serial number. there are commands to control a contiguous group (block) of flash memory array sectors th at are protected from program and erase operations. there are commands to control which individual flash memory a rray sectors are protected from program and erase operations. 9.1.8 reset there is a command to reset to the default conditions present af ter power on to the device. there is a command to reset (exit f rom) the enhanced performance read modes. 9.1.9 reserved some instructions are reserved for future use. in this ge neration of the S79FL256S/s79fl512s, some of these command instructions may be unused and not affect device operation, so me may have undefined results. some commands are reserved to ensure that a legacy or alternate source device command is allowed without affect. this allows legacy software to issue some commands that are not relevant for the current generation S79FL256S/s79fl512s devices with the assurance these commands do not cause some unexpected action. some commands are reserved for use in special versions of the fl -s not addressed by this document or for a future generation. this allows new host memory controller designs to plan the fl exibility to issue these command instructions. the command format is defined if known at the time this document revision is published. document number: 002-00518 rev. *d page 59 of 111 S79FL256S/s79fl512s 9.2 identification commands 9.2.1 read identification ? re ms (read_id or rems 90h) the read_id command identifies the device manufacturer id and the device id. the command is also referred to as read electronic manufacturer and device signature (rems). read-id (rems) is only supported for backward compatibility and should not be used for new software designs. new software designs should instead make use of the rdid command. the command is initiated by shifting on si the instruction code ?90h? followed by a 24 -bit address of 00000h. following this, t he manufacturer id and the device id are shifted out on so star ting at the falling edge of sck afte r address. the manufacturer id and the device id are always shifted out with the msb first. if t he 24-bit address is set to 000001h, then the device id is read ou t first followed by the manufacturer id. the manufacturer id and de vice id output data toggles between address 000000h and 000001h until terminated by a low to high transition on cs# input. the maximum clock frequency for the read_id command is 133 mhz. for the dual-quad spi device the read ident ification (rems) instruction and data read is only done on quad spi-1 using io0 and io1. figure 31. read_id (90h) command sequence table 39. read_id values device manufacturer id (hex) device id (hex) S79FL256S 01 19 s79fl512s 01 20 cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction manufacture id device id document number: 002-00518 rev. *d page 60 of 111 S79FL256S/s79fl512s 9.2.2 read identifi cation (rdid 9fh) the read identification (rdid) co mmand provides read access to manufacturer iden tification, device ident ification, and common flash interface (cfi) information. the manufacturer identification is assigned by jedec. the cfi structure is defined by jedec standard. the device identification and cfi values are assigned by cypress. the jedec common flash interface (cfi) specification defines a de vice information structure, which allows a vendor-specified software flash management program (driver) to be used for entire fa milies of flash devices. software support can then be device - independent, jedec manufacturer id independent , forward and backward-compatible for the specified flash device families. system vendors can standardize t heir flash drivers for long-term software compatib ility by using the cfi values to configure a family driver from the cfi information of the device in use. any rdid command issued while a program, erase, or write cycle is in progress is ignored and has no effect on execution of the program, erase, or write cycle that is in progress. the rdid instruction is shifted on si. after the last bit of the rdid instruction is sh ifted into the device, a byte of manufac turer identification, two bytes of dev ice identification, extended device identification, and cfi information will be shifted sequent ially out on so. as a whole this information is referred to as id-cfi. see id-cfi address space on page 35 for the detail description of the id- cfi contents. continued shifting of output bey ond the end of the defined id-cfi address spac e will provide undefined data. the rdid command sequence is terminated by driving cs# to the logic high state anytime during data output. for the S79FL256S/s79fl512s dual-quad spi devices, the read id entification (rdid) instruction and data read is only done on quad spi-1 using io0 and io1. the maximum clock frequency for the rdid command is 133 mhz. figure 32. read identification (rdid 9fh) command sequence 9.2.3 read electronic si gnature (res) (abh) the res command is used to read a single byte electronic signat ure from so. res is only supported for backward compatibility and should not be used for new software designs. new softwa re designs should instead make use of the rdid command. the res instruction is shifted in followed by three dummy bytes onto si. after the last bit of the three dummy bytes are shifte d into the device, a byte of electronic signature will be shifted out of so. each bit is shifted out by the falling edge of sck. the m aximum clock frequency for the res command is 50 mhz. the electronic signature can be read repeatedly by applying multiples of eight clock cycles. the res command sequence is terminated by driving cs# to the logic high state anytime during data output. for the s25fl-s dual-quad spi devices, the read electronic signature (res) instruction and data read is only done on quad spi- 1 using io0 and io1. figure 33. read electronic signature (res abh) command sequence cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data n cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction (abh) dummy device id document number: 002-00518 rev. *d page 61 of 111 S79FL256S/s79fl512s 9.3 register access commands 9.3.1 read status regi ster-1 (rdsr1 05h) the read status register-1 (rdsr1) command allows the status register-1 contents of quad spi-1 to be read from io1 and quad spi-2 to be read from io5. the status regi ster-1 contents may be read at any time, ev en while a program, er ase, or write operat ion is in progress. it is possible to read the status register-1 c ontinuously by providing multiple s of eight clock cycles. the sta tus is updated for each eight cycle read. the maximum clo ck frequency for the rdsr1 (05h) command is 133 mhz. figure 34. dual-quad read status register-1 (rdsr1 05h) command sequence 9.3.2 read status regi ster-2 (rdsr2 07h) the read status register-2 (rdsr2) command allows the status register-2 contents of quad spi-1 to be read from io1 and quad spi-2 to be read from io5. the status regi ster-2 contents may be read at any time, ev en while a program, er ase, or write operat ion is in progress. it is possible to read the status register-2 c ontinuously by providing multiple s of eight clock cycles. the sta tus is updated for each eight cycle read. the maximum clock frequency for the rdsr2 command is 133 mhz. figure 35. dual-quad read status register-2 (rdsr2 07h) command sequence table 40. res values device device id (hex) S79FL256S 19 s79fl512s 20 cs# sck io0 io1 io2-io3 io4 io5 io6-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction status updated status cs# sck io0 io1 io2-io3 io4 io5 io6-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction status updated status document number: 002-00518 rev. *d page 62 of 111 S79FL256S/s79fl512s 9.3.3 read configurati on register (rdcr 35h) the read configuration register (rdcr) command allows the configuration register contents of quad spi-1 to be read from io1 and quad spi-2 to be read from io5. it is po ssible to read the configuration register continuously by providing multiples of ei ght clock cycles. the configuration regi ster contents may be read at any time, even while a program, erase, or write operation is i n progress. figure 36. dual-quad read configuration register (rdcr 35h) command sequence 9.3.4 bank register read (brrd 16h) the read the bank register (brrd) command allows the bank address regi ster contents to be read from so. the instruction is first shifted in from si. then the 8-bit bank register is shifte d out on so. it is possible to read the bank register continuou sly by providing multiples of eight clock cycles. the maximum operating clock frequency for the brrd command is 133 mhz. figure 37. read bank register (brrd 16h) command 9.3.5 bank register write (brwr 17h) the bank register write (brwr) command is used to write address bits above a23, into the bank address register (bar). the command is also used to write the extended address control bit ( extadd) that is also in bar[7 ]. bar provides the high order addresses needed by devices having more than 128 mbits (16 mb ytes), when using 3-byte add ress commands without extended addressing enabled (bar[7] extadd = 0). because this command is part of the addressing method and is not changing data in the flash memory, this command does not r equire the wren command to precede it. the brwr instruction is entered, followed by the data byte on si. the bank register is one data byte in length. the brwr command has no effect on the p_err, e_err or wip bits of the status and configuratio n registers. any bank address bit reserved for the future should always be written as a 0. cs# sck io0 io1 io2-io3 io4 io5 io6-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction register read repeat register read cs# sck io0 io1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 phase instruction register read repeat register read io4 7 6 5 4 3 2 1 0 io5 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 document number: 002-00518 rev. *d page 63 of 111 S79FL256S/s79fl512s figure 38. bank register write (brwr 17h) command 9.3.6 bank register access (brac b9h) the bank register read and write commands provide full access to the bank address register (bar) but they are both commands that are not present in legacy spi memory devices. host system spi memory controlle r interfaces may not be able to easily suppo rt such new commands. the bank register access (brac) command us es the same command code and format as the deep power down (dpd) command that is available in legacy spi memories. t he fl-s family does not support a dpd feature but assigns this legacy command code to the brac command to enable write access to the bank address register for legacy systems that are able to send the legacy dpd (b9h) command. when the brac command is sent, the s25fl-s family device will then interpret an immediately following write register (wrr) command as a write to the lower address bits of the bar. a wren command is not used between the brac and wrr commands. only the lower two bits of the first data byte following the wrr command code are used to load bar[1:0]. the upper bits of that byte and the content of the optional wrr comma nd second data byte are ignored. following the wrr command the access to bar is closed and the device interface returns to the standby state. the co mbined brac followed by wrr command sequence has no affect on the value of the extadd bit (bar[7]). commands other than wrr may immediately follow brac and exec ute normally. however, any command other than wrr, or any other sequence in which cs# goes low and returns high, following a brac command, will close the access to bar and return to the normal interpretation of a wrr command as a write to status register-1 and the configuration register. the brac + wrr sequence is allowed only when the device is in standby, program suspend, or erase suspend states. this command sequence is illegal when the device is performing an embedded algorithm or when t he program (p_err) or erase (e_err) status bits are set to 1. figure 39. brac (b9h) command sequence cs# sck si_io0 so_io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data cs# sck io0 io1-io 3 io4 io5-io 7 phas e 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction document number: 002-00518 rev. *d page 64 of 111 S79FL256S/s79fl512s 9.3.7 write registers (wrr 01h) the write registers (wrr) command allows new values to be writ ten to both the status registe r-1 and configuration register. before the write registers (wrr) command can be accepted by the device, a write enable (wren) command must be received. after the write enable (wren) command has been decoded successfu lly, the device will set the write enable latch (wel) in the status register to enab le any write operations. the write registers (wrr) command is entered by shifting the instruction and the data bytes for quad spi-1 on io0 and for quad spi-2 on io4. the stat us register is one data byte in length. the write registers (wrr) command will set th e p_err or e_err bits if there is a failu re in the wrr operation. any status or configuration register bit reserved fo r the future must be written as a 0. cs# must be driven to the logic high state after the eighth or sixteenth bit of data has been la tched. if not, the write regist ers (wrr) command is not executed. if cs# is driven high after the eigh th cycle then only the status regi ster-1 is written; otherwise, af ter the sixteenth cycle both the status and configurat ion registers are written. when the confi guration register quad bit cr[1] is 1, o nly the wrr command format with 16 data bits may be used. as soon as cs# is driven to the logic hi gh state, the self-tim ed write registers (wrr) operation is initiated. while the write registers (wrr) operation is in progress, t he status register may still be read to c heck the value of the write-in progress (wi p) bit. the write-in progress (wip) bit is a 1 during the self-timed writ e registers (wrr) operation, and is a 0 when it is completed. when the write registers (wrr) operation is comple ted, the write enable latch (wel) is set to a 0. the maximum clock frequency for t he wrr command is 133 mhz. figure 40. dual-quad write registers figure 41. dual-quad write registers (wrr 01h) command sequence the write registers (wrr) command allows th e user to change the values of the block protect (bp2, bp1, and bp0) bits to define the size of the area that is to be treated as read-only. the writ e registers (wrr) command also a llows the user to set the stat us register write disable (srwd) bit to a 1 or a 0. the status register wr ite disable (srwd) bit allows the bp bits to be hardware protected. cs# sck io0 so_io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input status register-1 cs# sck io0 so_io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input status register-1 input conf register-1 document number: 002-00518 rev. *d page 65 of 111 S79FL256S/s79fl512s when the status register write disable (srw d) bit of the status register is a 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previous ly been set by a write enable (wren) command. the wrr command has an alternate function of loading the bank address register if the command immediately follows a brac command. see bank register access (brac b9h) on page 63 . 9.3.8 write enable (wren 06h) the write enable (wren) command sets the write enable latch (w el) bit of the status register-1 (sr1[1]) to a 1. the write enable latch (wel) bit must be set to a 1 by issuing the wr ite enable (wren) command to enable write, program and erase commands. cs# must be driven into the logic high state after the eighth bi t of the instruction byte has be en latched in on io0 for quad s pi-1 and io4 for quad spi-2. without cs# being driven to the logic high st ate after the eighth bit of the instruction byte has been latc hed in on io0 for quad spi-1 and io4 for quad spi-2., t he write enable operation will not be executed. figure 42. dual-quad write enable (wren 06h) command sequence 9.3.9 write disable (wrdi 04h) the write disable (wrdi) command sets the write enable latch (wel) bit of the status re gister-1 (sr1[1]) to a 0. the write enable latch (wel) bit may be set to a 0 by issuing the write disable (wrdi) command to disable page program (pp), sector erase (se), bulk erase (be), writ e registers (wrr), otp program (otpp), and other commands, that require wel be set to 1 for execution. the wrdi command can be used by the user to protect memory ar eas against inadvertent writes that can possibly corrupt the contents of the memory. the wrdi command is ignored during an embedded operation while wip bit =1. cs# must be driven into the logic high state after the eighth bi t of the instruction byte has be en latched in on io0 for quad s pi-1 and io4 for quad spi-2. without cs# being driven to the logic high st ate after the eighth bit of the instruction byte has been latc hed in on io0 for quad spi-1 and io4 for quad spi-2, the write disable operation will not be executed. figure 43. dual-quad write di sable (wrdi 04h) command sequence cs# sck io0 io1-io 3 io4 io5-io 7 phas e 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction cs# sck io0 io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction document number: 002-00518 rev. *d page 66 of 111 S79FL256S/s79fl512s 9.3.10 clear status register (clsr 30h) the clear status register command resets bi t sr1[5] (erase fail flag) and bit sr1[6] (p rogram fail flag). it is not necessary t o set the wel bit before the clear sr command is executed. the cle ar sr command will be accepted even when the device remains busy with wip set to 1, as the device doe s remain busy when either error bit is set. the wel bit will be unchanged after this command is executed. figure 44. dual-quad clear status register (clsr 30h) command sequence 9.3.11 ecc status regi ster read (eccrd 18h) to read the ecc status register, the command is followed by the ecc unit (32 bit) addres s, the five least significant bits (lsb ) of address must be set to ze ro. this is followed by eight dummy cycles. then the 8-bit content s of the ecc register, for the ecc u nit selected, are shifted out on so 16 times, once for each byte in the ecc unit. if cs# remains low the next ecc unit status is se nt through so 16 times, once for each byte in the ecc unit, this continues until cs# goes hi gh. the maximum operating clock frequency for the ecc read command is 133 mhz. see section 9.5.1.1, automatic ecc on page 77 for details on ecc unit. figure 45. ecc status register read command sequence cs# sck io0 io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction cs# sck io0 io1 7 6 5 4 3 2 1 0 phase instruction 32-bit address 8-bit dummy cycles data out 1 data out 2 io4 7 6 5 4 3 2 1 0 io5 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 31 30 29 3 2 1 0 31 30 29 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 6 5 7 document number: 002-00518 rev. *d page 67 of 111 S79FL256S/s79fl512s 9.3.12 autoboot spi devices normally require 32 or more cycles of command and address shifting to initiate a read command. and, in order to rea d boot code from an spi device, the host me mory controller or processor must supply the read command from a hardwired state machine or from some host processor internal rom code. parallel nor devices need only an initial address, supplied in para llel in a single cycle, and in itial access time to start rea ding boot code. the autoboot feature allows the host memory controller to take boot code from an s25fl-s devic e immediately after the end of reset, without having to send a read command. this saves 32 or more cycles and simplifies the logic needed to initiate the read ing of boot code. ? as part of the power up reset, hardware reset, or command reset process the autoboot feature automatically starts a read access from a pre-specified address. at the time the reset process is completed, the device is ready to deliver code from the starting address. the host memory controller only needs to drive cs# signal from high to low and begin toggling the sck signal. the s25fl-s device will delay code output for a pre-specif ied number of clock cycles before code streams out. ? the auto boot start delay (absd) field of the autoboot regi ster specifies the in itial delay if any is needed by the host. ? the host cannot send commands during this time. ? if absd = 0, the maximum sck frequency is 50 mhz. ? if absd > 0, the maximum sck frequency is 133 mhz if the quad bit cr1[1] is 0 or 104 mhz if the quad bit is set to 1. ? the starting address of the boot code is selected by the value programmed into the autoboot start addr ess (absa) field of the autoboot register which specifies a 512 byte boundar y aligned location; the default address is 00000000h. ? data will continuously shift out until cs# returns high. ? at any point after the first data byte is transferred, when cs# returns high, the spi device will reset to standard spi mode; a ble to accept normal command operations. ? a minimum of one byte must be transferred. ? autoboot mode will not initiate again unt il another power cycle or a reset occurs. ? an autoboot enable bit (abe) is set to enable the autoboot feature. the autoboot register bits are non-volatile and provide: ? the starting address (512-byte boundary), set by the autoboot start address (absa). the si ze of the absa field is 23 bits for devices up to 32-gbit. ? the number of initial delay cycles, set by the autoboot start delay (absd) 8-bit count value. ? the autoboot enable. with the configuration register quad bit cr1 [1] is set to 1, the boot code will be pr ovided 4 bits per cycle in the same manner as a read quad out command. figure 46. autoboot sequence (cr1[1]=1) cs# sck phase wait states (absd) d1 d2 d3 d4 d5 ... io0 io1 io2 io3 0 4 1 5 2 6 3 7 io4 io5 io6 io7 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 d6 d7 0 1 2 3 0 1 2 3 4 5 6 7 4 5 6 7 0 1 2 3 4 5 6 7 document number: 002-00518 rev. *d page 68 of 111 S79FL256S/s79fl512s 9.3.13 autoboot regist er read (abrd 14h) the autoboot register read command is shifted into si. then the 32-bit autoboot register is shifted out on so, least significan t byte first, most significant bit of each byte first. it is po ssible to read the autoboot regist er continuously by providing mul tiples of 32 clock cycles. the maximum operating clock frequency for abrd command is 104 mhz. figure 47. autoboot regist er read (abrd 14h) command 9.3.14 autoboot register write (abwr 15h) before the abwr command can be accepted, a write enable (wre n) command must be issued and decoded by the device, which sets the write enable latch (wel) in the stat us register to enable any write operations. the abwr command is entered by shifting the instruction and the data bytes on si, least sign ificant byte first, most significan t bit of each byte first. the abwr data is 32 bits in length. the abwr command has status reported in st atus register-1 as both an erase and a programming operation. an e_err or a p_err may be set depending on whether the erase or pr ogramming phase of updat ing the register fails. cs# must be driven to the logic high state after the 32nd bit of data has been latched. if not, the abwr command is not execute d. as soon as cs# is driven to the logic hi gh state, the self-tim ed abwr operation is initiated. while the abwr operation is in progress, status register-1 may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bit is a 1 during the self-timed abwr operation, and is a 0. when it is completed. when the ab wr cycle is completed, the write enable latch (wel) is set to a 0. the maximum clock frequency for the abwr command is 133 mhz. figure 48. autoboot regi ster write (abwr) command cs# sck si_io0 so_io1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 phase instruction data 1 data n io4 7 6 5 4 3 2 1 0 io5 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 cs# sck si_io0 so_io1-io3 io4 io5-io7 phas3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data 1 document number: 002-00518 rev. *d page 69 of 111 S79FL256S/s79fl512s 9.3.15 program nvdlr (pnvdlr 43h) before the program nvdlr (pnvdlr) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded successfully, the device will set the write enable latch (wel) to enable the pnvdlr operation. the pnvdlr command is entered by shifting the instruction and the data byte on si-i o0 for quad spi-1 and io4 for quad spi-2. cs# must be driven to the logic high state after the eighth (8th) bit of data has bee n latched. if not, the pnvdlr command is n ot executed. as soon as cs# is driven to t he logic high state, the self-timed pnvdlr operation is initiated. while the pnvdlr operation is in progress, the status regi ster may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bit is a 1 during the self-timed pnvdlr cycle, and is a 0. when it is completed. the pnvdlr operation can report a program error in the p_err bit of the status register. when the pnvdlr operation is completed, the write enable latch (wel) is set to a 0 the maximum clock frequency for the pnvdlr command is 133 mhz. figure 49. program nvdlr (pnvdlr 43h) command sequence 9.3.16 write vdlr (wvdlr 4ah) before the write vdlr (wvdlr) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) comman d has been decoded successfully, the device will set the write enable latch (wel) to enable wvdlr operation. the wvdlr command is entered by shifting the instruction and the data byte on si-io0 for quad spi-1 and io4 for quad spi-2. cs# must be driven to the logic high state after the eighth (8th) bit of data has bee n latched. if not, the wvdlr command is no t executed. as soon as cs# is driven to the logic high state, the wvdlr operation is initiated with no delays. the maximum clock frequency for the pnvdlr command is 133 mhz. figure 50. write vdlr (wvdlr 4ah) command sequence cs# sck si_io0 so_io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data cs# sck si_io0 so_io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data document number: 002-00518 rev. *d page 70 of 111 S79FL256S/s79fl512s 9.3.17 data learning pa ttern read (dlprd 41h) the instruction is shifted on si_io0, then th e 8-bit dlp is shifted out on so_io1 and io 5. it is possible to read the dlp conti nuously by providing multiples of eight clock cycles. the maximum operating clock frequency for the dlprd command is 133 mhz. figure 51. dual-quad dlp read (dlprd 41h) command sequence 9.4 read memory array commands read commands for the main flash array provide many options for prior generation spi compatib ility or enhanced performance spi: ? some commands transfer address or data on each rising edge of sck. these are called single data rate commands (sdr). ? some sdr commands transfer address one bit per rising edge of sck and return data 2, or 8 bits of data per rising edge of sck. these are called read or fast read for 2-bit data; quad output for 8-bit data. ? some sdr commands transfer both address and data 8 bits per rising edge of sck. these are called quad i/o for 8 bit. ? some commands transfer address and data on both the rising edge and falling edge of sck. these are called double data rate (ddr) commands. ? there are ddr commands for 4 bits of address per each die or 8 bi t data per sck edge. these are called quad i/o ddr for 8-bit per edge transfer. all of these commands begin with an instru ction code that is transferred one bit per sck rising edge. the instruction is follow ed by either a 3- or 4-byte address transferred at sdr or ddr. comma nds transferring address or data 4-bits per clock edge per die ar e called multiple i/o (mio) co mmands. for fl-s devices at 256 mbits or higher density, the traditiona l spi 3-byte addresses are unable to directly address all locations in the memory ar ray. these device have a bank address register that is used with 3-by te address commands to supply the high order address bits beyon d the address from the host system. the default bank address is zero. commands are pr ovided to load and read the bank address register. these devices may also be configur ed to take a 4-byte address from the host system with the tradi tional 3-byte addres s commands. the 4-byte address mode for traditional commands is ac tivated by setting the external address (extadd) bit in the bank address register to 1. the quad i/o commands provide a performanc e improvement option controlled by mode bits that are sent following the address bits. the mode bits indicate whether the command following the end of the current read will be another read of the same type, without an instruction at the beginning of the read. these mode bits give the option to eliminate the instruction cycles when d oing a series of quad i/o read accesses. some commands require delay cycles following the address or mode bits to allow time to a ccess the memory a rray. the delay cycles are traditionally called dummy cycles. the dummy cycles are ignored by the memory thus any da ta provided by the host during these cycles is ?don?t care? and the host may also leav e the si signal at high impedance during the dummy cycles. when m io commands are used the host must stop driving the io signals (out puts are high impedance) before the end of last dummy cycle. when ddr commands are used the host must not drive the i/o signals during any dummy cycle. the number of dummy cycles varies with the sck frequency or performance option selected vi a the configuration register-1 (cr1) latency code (lc). dummy cycles are measured from sck falling edge to next sck falling edge. spi ou tputs are traditiona lly driven to a new value on the falling edge of each sck. zero dummy cycles means the returning data is driven by the memory on the same falling edge of sck that the host stops driving address or mode bits. cs# sck si_io0 so_io1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 phase instruction data 1 data n io4 7 6 5 4 3 2 1 0 io5 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 document number: 002-00518 rev. *d page 71 of 111 S79FL256S/s79fl512s the ddr commands may optionally have an 8-edge data learning patter n (dlp) driven by the memory, on all data outputs, in the dummy cycles immediately before the start of data. the dlp can help the ho st memory controller dete rmine the phase shift from sck to data edges so that the memory controller can capture data at the center of the data eye. when using sdr i/o commands at higher sck frequencies (>50 mh z), an lc that provides 1 or more dummy cycles should be selected to allow additional time for the host to stop driving bef ore the memory starts driving data, to minimize i/o driver co nflict. when using ddr i/o commands with the dlp enab led, an lc that provides 5 or more dummy cycles should be selected to allow 1 cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle dlp. each read command ends when cs# is returned high at any point during data return. cs# must not be returned high during the mode or dummy cycles before data returns as this may cause mode bi ts to be captured in correctly; making it indeterminate as to whether the device remains in enhanced high performance read mode. 9.4.1 read (read 03h or 4read 13h) the instruction ? 03h (extadd=0) is followed by a 3-byte address (a23-a0) or ? 03h (extadd=1) is followed by a 4-byte address (a31-a0) or ? 13h is followed by a 4-byte address (a31-a0) then the memory contents, at the address gi ven, are shifted out on io1 and io5. th e maximum operating clock frequency for the read command is 50 mhz. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. figure 52. dual-quad read command sequence (read 03h or 13h) note: 1. a = msb of address = 23 for command 03h, or 31 for command 13h. cs# sck io0 io1 io2-io3 io4 io5 io6-io7 phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address data 1 data n document number: 002-00518 rev. *d page 72 of 111 S79FL256S/s79fl512s 9.4.2 fast read (fast_read 0bh or 4fast_read 0ch) the instruction ? 0bh (extadd=0) is followed by a 3-byte address (a23-a0) or ? 0bh (extadd=1) is followed by a 4-byte address (a31-a0) or ? 0ch is followed by a 4-byte address (a31-a0) the address is followed by zero or eight dummy cycles depending on the la tency code set in the configuration register. the dumm y cycles allow the device internal circuits additional time for accessing the initial address locati on. during the dummy cycles t he data value on io1 and io5 is ?don?t care? and may be high impedance. th en the memory contents, at the address given, are shifted out on io1 and io5. the maximum operating clock frequency for fast read command is 133 mhz. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. figure 53. dual-quad spi fast read (fast_read) command sequence 9.4.3 quad output read (qor 6bh or 4qor 6ch) the instruction ? 6bh (extadd=0) is followed by a 3-byte address (a23-a0) or ? 6bh (extadd=1) is followed by a 4-byte address (a31-a0) or ? 6ch is followed by a 4-byte address (a31-a0) then the memory contents, at the address given, is sh ifted out eight bits at a time through io0-io7. each nibble (4 bits) is sh ifted out at the sck frequency by the falling edge of the sck signal. the maximum operating clock frequency for quad output read command is 104 mhz. for quad output read mode, there may be dummy cycles required after the last address bit is shifted into si befor e data begins shifting out of io0-io3. this latency pe riod (i.e., dummy cycles) allows the device?s internal circuitry enough time to set up for the initial address. during the dummy cycles, th e data value on io0-io7 is a ?don?t care? and may be high impedance. the number of dummy cycles is determined by the frequency of sck (refer to table 21, latency codes for sdr enhanced high performance on page 39 ). the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. cs# sclk io0 io1 io2-io3 io4 io5 io6-io7 phase 7 6 5 4 3 2 1 0 31 1 0 3 2 1 0 3 2 1 0 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 7 6 5 4 instruction address dummy cycles data 1 data 2 document number: 002-00518 rev. *d page 73 of 111 S79FL256S/s79fl512s figure 54. dual-quad, quad output read (qor 6bh or 4qor 6ch) command sequence note: 1. a = msb of address = 23 for command 6bh, or 31 for command 6ch. 9.4.4 quad i/o read (q ior ebh or 4qior ech) the instruction ? ebh (extadd=0) is followed by a 3-byte address (a23-a0) or ? ebh (extadd=1) is followed by a 4-byte address (a31-a0) or ? ech is followed by a 4-byte address (a31-a0) the quad i/o read command improves throughput with eight i/o si gnals ? io0-io7. it is simila r to the quad output read command but allows input of the address bits eight bits per seri al sck clock. in some applications, the reduced instruction ove rhead might allow for code execution (xip) directly from the s25fl-s device. the maximum operating clock frequency for quad i/o read is 104 mhz. for the quad i/o read command, there is a latency required after the m ode bits (described below) before data begins shifting ou t of io0-io7. this latency period (i.e., dummy cycles) allows the de vice?s internal circuitry enough time to access data at the init ial address. during latency cycles, the data value on io0-io7 are ?don?t care? and may be high impedance. the number of dummy cycles is determined by the frequency of sc k and the latency code table (refer to table 21, latency codes for sdr enhanced high performance on page 39 ). the number of dummy cycles is set by the lc bits in the configuration register (cr1). however, both latency code tables use the same latency values for the quad i/o read command. following the latency period, the memory contents at the address given, is shifted out eight bits at a time through io0-io7. ea ch byte (8 bits) is shifted out at the sck frequency by the falling edge of the sck signal. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. address jumps can be done without the need for additional quad i/o read instructions. this is controlled through the setting of the mode bits (after the address sequence, as shown in figure 55 on page 74 or figure 56 on page 74 ). this added feature removes the need for the instruction sequenc e and greatly improves code exec ution (xip). the upper nibble (bits 7-4) of the mode bits c ontrol the length of the next quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower ni bble (bits 3-0) of the mode bits are ?don?t care? (?x ?). if the mode bits equal axh, then the de vice remains in quad i/o high performance read mode and the next address can be entered (after cs# is raised high and then asserted low) wi thout requiring the ebh or ech instruction, as shown in figure 55 on page 74 ; thus, eliminating eight cycles for the command sequence. the following sequences will release the device from quad i/o high performance read mo de; after which, the device ca n accept standard spi commands: cs# sck io0 io1 io2 io3 io4 io5 io6 io7 phase 7 6 5 4 3 2 1 0 a 1 0 0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 7 6 5 4 3 2 1 0 a 1 0 4 4 4 4 4 5 5 5 5 5 6 6 6 6 6 7 7 7 7 7 instruction address dummy d1 d2 d3 d4 d5 document number: 002-00518 rev. *d page 74 of 111 S79FL256S/s79fl512s 1. during the quad i/o read command sequence, if the mode bits are any value other than axh, then the next time cs# is raised high the device will be released from quad i/o high performance read mode. 2. during any operation, if cs# toggles high to low to high for eight cycles (or less) and data input (io0-io3) are not set for a valid instruction sequence, then t he device will be released from quad i/o high performance read mode. note that the two mode-bit clock cycles and additional wait stat es (i.e., dummy cycles) allow t he device?s internal circuitry l atency time to access the initial addr ess after the last address cycle that is clocked into io0-io3. it is important that the io0-io7 signals be set to high-impedanc e at or before the falling edge of the first data out clock. at higher clock speeds the time available to turn off the host outputs befo re the memory device begins to drive (bus turn around) is dimi nished. it is allowed and may be helpful in preventing io0-io7 signal cont ention, for the host system to turn off the io0-io7 signal ou tputs (make them high impedance) during the last ?don ?t care? mode cycle or during any dummy cycles. cs# should not be driven high during mode or dummy bi ts as this may make the mode bits indeterminate. figure 55. dual-quad i/o read command seque nce (3-byte address, ebh [extadd=0], lc=00b) note: 1. a = msb of address = 23 for command ebh, or 31 for command ech. figure 56. dual-quad continuous quad i/o read command sequence (3-byte address), lc=00b note: 1. a = msb of address = 23 for command ebh, or 31 for command ech. cs# sclk io0 io1 io2 io3 io4 io5 io6 io7 phase 7 6 5 4 3 2 1 0 a-3 4 0 4 0 0 0 0 0 a-2 5 1 5 1 1 1 1 1 a-1 6 2 6 2 2 2 2 2 a 7 3 7 3 3 3 3 3 7 6 5 4 3 2 1 0 a-3 4 0 4 0 4 4 4 4 a-2 5 1 5 1 5 5 5 5 a-1 6 2 6 2 6 6 6 6 a 7 3 7 3 7 7 7 7 instruction address mode dummy d1 d2 d3 d4 cs# sck io0 io1 io2 io3 io4 io5 io6 io7 phase 0 0 a-3 4 0 4 0 0 0 0 0 1 1 a-2 5 1 5 1 1 1 1 1 2 2 a-1 6 2 6 2 2 2 2 2 3 3 a 7 3 7 3 3 3 3 3 4 4 a-3 4 0 4 0 4 4 4 4 5 5 a-2 5 1 5 1 5 5 5 5 6 6 a-1 6 2 6 2 6 6 6 6 7 7 a 7 3 7 3 7 7 7 7 dn-1 dn address mode dummy d1 d2 d3 d4 document number: 002-00518 rev. *d page 75 of 111 S79FL256S/s79fl512s 9.4.5 ddr quad i/o read (edh, eeh) the read ddr quad i/o command is similar to the quad i/o read co mmand but allows input of the address four bits on every edge of the clock. in some applications, the r educed instruction overhead might allow for co de execution (xip) directly from the s25 fl-s devices. the quad bit of the configuration register is set (cr[1]=1) to enable the quad capa bility in the s25fl-s device. the instruction ? edh (extadd=0) is followed by a 3-byte address (a23-a0) or ? edh (extadd=1) is followed by a 4-byte address (a31-a0) or ? eeh is followed by a 4-byte address (a31-a0) the address is followed by mode bits. then the memory contents, at the address given, is shifted out, in a ddr fashion, with fo ur bits at a time on each clock edge through io0-io7. the maximum operating clock frequency for read ddr quad i/o command is 80 mhz. for read ddr quad i/o, there is a latency required after the last address and mode bits are shifted into the io0-io7 signals be fore data begins shifting out of io0-io7. this latency period (dummy cycles) allows the device?s in ternal circuitry enough time to a ccess the initial address. during these latency cycles, the data value on io0-io7 are ?don?t care? and may be high impedance. when th e data learning pattern (dlp) is enabled the host system must not drive the io signals during the dummy cycles. the io signals mu st be left high impedance by the host so that the memory device can dr ive the dlp during the dummy cycles. the number of dummy cycles is determined by the frequency of sc k. the number of dummy cycles is set by the lc bits in the configuration register (cr1). both latency tables provide cycles for mode bits so a series of quad i/o ddr commands may elimi nate the 8-bit instruction after the first command sends a complementary mode bit pattern, as shown in figure 57 . this feature removes the need for the eight bit sdr instruction sequence and dramatically reduces initial access ti mes (improves xip performance). th e mode bits control the length of the next read ddr quad i/o operation through the inclusion or e xclusion of the first byte instruction code. if the upper nibble (io[7:4]) and lower nibble (io[3:0]) of the mode bits are comple mentary (i.e. 5h and ah) the device transitions to continuous r ead ddr quad i/o mode and the next address can be entered (after cs # is raised high and then asserted low) without requiring the edh or eeh instruction, as shown in figure 58 thus, eliminating eight cycles from the command sequence. the following sequences will release the device from continuous read ddr quad i/o mode ; after which, the device can accept standard spi commands: 1. during the read ddr quad i/o command sequence, if the mode bits are not complementary the next time cs# is raised high and then asserted low the device will be released from read ddr quad i/o mode. 2. during any operation, if cs# toggles high to low to high for eight cycles (or less) and data input (io0 - io7) are not set fo r a valid instruction sequence, then the device w ill be released from read ddr quad i/o mode. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. cs# should not be driven high during mode or du mmy bits as this may make the mode bits indeterminate. the hold function is not valid during quad i/o ddr commands. note that the memory devices drive the ios with a preamble prior to the first data value. the preamble is a pattern that is use d by the host controller to optimize data capture at higher frequencies. the preamble drives t he io bus for the four clock cycles immedi ately before data is output. the host must be sure to stop driving the io bus prior to the time that the memory starts outputting the preamble. document number: 002-00518 rev. *d page 76 of 111 S79FL256S/s79fl512s the preamble is intended to give the host controller an indicati on about the round trip time from when the host drives a clock edge to when the corresponding data value returns from the memory device. the host controller will skew the data capture point during t he preamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read operation. the optimized capture point wil l be determined during the preamble period of every read operation. this optimization strategy is intended to compensate for both the pvt (process, vo ltage, temperature) of both t he memory device and the host controller as well as any system level de lays caused by flight time on the pcb. al though the data learning pattern (dlp) is programmable, the following example shows example of the dlp of 34h. the dlp 34h (or 00110100) will be driven on each of the active outputs (i.e. all eight ios). this pattern was chosen to cover both dc and ac data trans ition scenarios. the two dc tran sition scenarios include data low for a long period of time (two half clocks) follow ed by a high going transition (001) and the comple mentary low going transition (110). the two ac transition scenarios include data low for a short period of time (one half clock) follow ed by a high going transition (101) and the complem entary low going transition (010). the dc transitions will typically occur with a st arting point closer to the supply rail than the ac transitions that ma y not have fully settled to their steady state (dc) levels. in m any cases the dc transitions will bound the beg inning of the data valid period and the ac transitions will bound the ending of the data v alid period. these transitions will allow the host controller to ident ify the beginning and ending of the valid data eye. once the d ata eye has been characterized the optimal da ta capture point can be chosen. see spi ddr data learning registers on page 45 for more details. figure 57. dual-quad spi ddr quad i/o read initial access notes: 1. a = msb of address = 23 for command edh, or 31 for command eeh. 2. example dlp of 34h (or 00110100). figure 58. dual-quad continuous ddr quad i/o read subsequent access notes: 1. a = msb of address = 23 for command edh, or 31 for command eeh. 2. example dlp of 34h (or 00110100). cs# sck io0 io1 io2 io3 io4 io5 io6 io7 phas e 7 6 5 4 3 2 1 0 a-3 8 4 0 4 0 7 6 5 4 3 2 1 0 0 0 a-2 9 5 1 5 1 7 6 5 4 3 2 1 0 1 1 a-1 10 6 2 6 2 7 6 5 4 3 2 1 0 2 2 a 11 7 3 7 3 7 6 5 4 3 2 1 0 3 3 7 6 5 4 3 2 1 0 a-3 8 4 0 4 0 7 6 5 4 3 2 1 0 4 4 a-2 9 5 1 5 1 7 6 5 4 3 2 1 0 5 5 a-1 10 6 2 6 2 7 6 5 4 3 2 1 0 6 6 a 3 7 3 7 3 7 6 5 4 3 2 1 0 7 7 instruction address mode dummy dlp d1 d2 cs# sc k io0 io1 io2 io3 io4 io5 io6 io7 phase a-3 8 4 0 4 0 7 6 5 4 3 2 1 0 0 0 a-2 9 5 1 5 1 7 6 5 4 3 2 1 0 1 1 a-1 10 6 2 6 2 7 6 5 4 3 2 1 0 2 2 a 11 7 3 7 3 7 6 5 4 3 2 1 0 3 3 a-3 8 4 0 4 0 7 6 5 4 3 2 1 0 4 4 a-2 9 5 1 5 1 7 6 5 4 3 2 1 0 5 5 a-1 10 6 2 6 2 7 6 5 4 3 2 1 0 6 6 a 11 7 3 7 3 7 6 5 4 3 2 1 0 7 7 addres s mode dummy dlp d1 d2 document number: 002-00518 rev. *d page 77 of 111 S79FL256S/s79fl512s 9.5 program flash array commands 9.5.1 program granularity 9.5.1.1 automatic ecc each 16 byte aligned and 16 byte length programming block has an automatic error correction code (ecc) value. the data block plus ecc form an ecc unit. in combination with error detection a nd correction (edc) logic the ecc is used to detect and correct any single bit error found during a read access. when data is fi rst programmed within an ecc unit the ecc value is set for the entire ecc unit. if the same ecc unit is programmed more than once the ecc value is changed to disable the error detection and correction (edc) function. a sector erase is needed to again enable automatic ecc on that programming block. the 16 byte program block is the smallest program granularity on which automatic ecc is enabled. these are automatic operations transparent to the user. the transparency of the au tomatic ecc feature enhances data accuracy for typical programming operations which write data once to ea ch ecc unit but, facilitates software compatibility to previous generations of fl-s family of products by allowing for single byte programming and bit walking in which the same ecc unit is programmed more than once. when an ecc unit has automatic ecc disabled, edc is not done on data read from the ecc unit location. an ecc status register is provided for determining if ecc is en abled on an ecc unit and whether any errors have been detected and corrected in the ecc unit data or the ecc (see section 7.5.6, ecc status register (eccsr) on page 42 .) the ecc status register read (eccrd) command is used to read the ecc status on any ecc unit. edc is applied to all parts of the flash address spaces other th an registers. an ecc is calculated for each group of bytes prot ected and the ecc is stored in a hidden area related to the group of bytes. the group of protected bytes and the related ecc are toge ther called an ecc unit. ecc is calculated for each 16 byte aligned and length ecc unit. ? single bit edc is supported with 8 ecc bits per ecc unit, plus 1 bit for an ecc disable flag. ? sector erase resets all ecc bits and ecc disable flags in a sector to the default state (enabled). ? ecc is programmed as part of th e standard program commands operation. ? ecc is disabled automatically if multiple progra mming operations are done on the same ecc unit. ? single byte programming or bit walking is allowed but disabl es ecc on the second program to the same 16-byte ecc unit. ? the ecc disable flag is programmed when ecc is disabled. ? to re-enable ecc for an ecc unit that has been disabled, th e sector that includes the ecc unit must be erased. ? to ensure the best data int egrity provided by edc, each ecc unit should be pr ogrammed only once so that ecc is stored for that unit and not disabled. ? the calculation, programming, and disablin g of ecc is done automatically as part of a programming operation. the detection and correction, if needed, is done automatically as part of read operat ions. the host system sees only corrected data from a read operation. ? ecc protects the otp region - however a second program operation on the same ecc unit will disable ecc permanently on that ecc unit (otp is one time programmable, hence an erase operat ion to re-enable the ecc enable/indicator bit is prohibited). 9.5.1.2 page programming page programming is done by loading a page buffer with data to be programmed and issuing a programming command to move data from the buffer to the memory array. this sets an upper limit on the amount of data that can be programmed with a single programming command. page programming allows up to a page size (either 512 bytes or 1024 bytes) to be programmed in one operation. the page is aligned on the page size address boundary. it is possible to program from one bit up to a page size in e ach page programming operation. it is recommended that a multiple of 16 byte length and aligned program blocks be written. for the very best performance, programming should be done in full pages of 1024 bytes aligned on 1024-byte boundaries with each page being programmed only once. document number: 002-00518 rev. *d page 78 of 111 S79FL256S/s79fl512s 9.5.1.3 single byte programming single byte programming allows full back ward compatibility to the standard spi pa ge programming (pp) command by allowing a single byte to be programmed anywhere in the memory array. while single byte programming is supported, this will disable automatic ecc on the 16 byte ecc unit where the byte is located 9.5.2 page program (pp 02h or 4pp 12h) the page program (pp) commands allows bytes to be programmed in the memory (changing bits from 1 to 0). before the page program (pp) commands can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded successfully, the device sets the write enable latch (wel) in the status register to enable any write operations. the instruction ? 02h (extadd=0) is followed by a 3-byte address (a23-a0) or ? 02h (extadd=1) is followed by a 4-byte address (a31-a0) or ? 12h is followed by a 4-byte address (a31-a0) and at least one data byte on io0 and io4. up to a page can be provided on io0 and io4 after the 3-byte address with instructio n 02h or 4-byte address with instruction 12h has been provided. if the 9 least significant address bits (a8-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 9 least significant bits (a8-a0) are all zero) i. e. the address wraps within the page aligned address boundaries. this is a result of only requiring the user to enter one single page address to cover the entire page boundary. if less than a page of data is sent to the device, these data bytes will be programmed in sequence, starting at the provided ad dress within the page, without having any affect on the other bytes of the same page. for optimized timings, using the page program (pp) command to load the entire page size program buffer within the page boundary will save overall programming time versus loading less than a page size into the program buffer. the programming process is managed by the flash memory device internal control logic. after a programming command is issued, the programming operation status can be checked using the read status register-1 command. the wip bit (sr1[0]) will indicate when the programming operation is completed. the p_err bit (sr1[6]) will indicate if an error occurs in the programming operati on that prevents successful completion of programming. figure 59. dual-quad page program (pp 02h or 4pp 12h) command sequence cs# sck io0 io1-io 3 io4 io5-io 7 phas e 7 6 5 4 3 2 1 0 a 5 4 3 2 1 0 3 2 1 0 3 2 1 0 7 6 5 4 3 2 1 0 a 5 4 3 2 1 0 7 6 5 4 7 6 5 4 instruction address input data 1 input data 2 document number: 002-00518 rev. *d page 79 of 111 S79FL256S/s79fl512s 9.5.3 quad page prog ram (qpp 32h or 38h, or 4qpp 34h) the quad-input page program (qpp) command allo ws bytes to be programmed in the memory (changing bits from 1 to 0). the quad-input page program (qpp) command allows up to a page size (either 512 bytes or 1024 bytes) of data to be loaded into the page buffer using eight signals: io0-io7. qpp can improve performance for prom progr ammer and applications that have slower clock speeds (< 12 mhz) by loading 8 bits of data per clock cycl e. systems with faster clock speeds do not realize as much bene fit for the qpp command since the inherent page program time becomes greater than the time it takes to clock-in the data. the maximum frequency for the qpp command is 80 mhz. to use quad page program the quad enable bit in the config uration register must be set (q uad=1). a write enable command must be executed before the device will accept the qpp command (status register-1, wel=1). the instruction ? 32h (extadd=0) is followed by a 3-byte address (a23-a0) or ? 32h (extadd=1) is followed by a 4-byte address (a31-a0) or ? 38h (extadd=0) is followed by a 3-byte address (a23-a0) or ? 38h (extadd=1) is followed by a 4-byte address (a31-a0) or ? 34h is followed by a 4-byte address (a31-a0) and at least two data bytes, into the io signals. data must be programmed at previously erased (ffh) memory locations. qpp requires programming to be done one full page at a time. wh ile less than a full page of data may be loaded for programming, the entire page is considered programm ed, any locations not filled with data will be left as ones, the same page must not be programmed more than once. all other functions of qpp are identical to page program. the qpp command sequence is shown in the figure below. figure 60. dual-quad, quad page program command sequence note: 1. a = msb of address = a23 for pp 02h, or a31 for pp 02h, or for 4pp 12h. cs# sck io0 io1 io2 io3 io4 io5 io6 io7 phase 7 6 5 4 3 2 1 0 a 1 0 0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 7 6 5 4 3 2 1 0 a 1 0 4 4 4 4 4 5 5 5 5 5 6 6 6 6 6 7 7 7 7 7 instruction address d1 d2 d3 d4 ... document number: 002-00518 rev. *d page 80 of 111 S79FL256S/s79fl512s 9.5.4 program suspend (pgsp 85h) and resume (pgrs 8ah) the program suspend command allows the system to interrupt a pr ogramming operation and then re ad from any other non-erase- suspended sector or non-program-suspended-page. program suspend is valid only during a programming operation. commands allowed after the program suspend command is issued: ? read status register-1 (rdsr1 05h) ? read status register-2 (rdsr2 07h) the write in progress (wip) bit in status register-1 (sr1[0]) must be checked to know when the programming operation has stopped. the program suspend status bit in th e status register-2 (sr2[0]) can be used to determine if a programming operation has been suspended or was completed at the time wip changes to 0. the time required for the suspend operation to complete is t psl , see table 43, program suspend ac parameters on page 93 . see table 41, commands allowed during program or erase suspend on page 84 for the commands allowed while programming is suspend. the program resume command 8ah must be written to resume the programming operation after a program suspend. if the programming operation was completed during the suspend operation, a resume command is not needed and has no effect if issued. program resume commands will be ignored unless a program operation is suspended. after a program resume command is issued, the wip bit in the status r egister-1 will be set to a 1 and the programming operation will resume. program operations may be interrupted as often as necessary e.g. a program sus pend command could immediately follow a program resume command but, in order for a program oper ation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to t prs . see table 43, program suspend ac parameters on page 93 . figure 61. dual-quad program suspend command sequence figure 62. dual quad prog ram resume command sequence cs# sck io0 io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction cs# sck io0 io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction document number: 002-00518 rev. *d page 81 of 111 S79FL256S/s79fl512s 9.6 erase flash array commands 9.6.1 parameter 8-kb sector erase (p4e 20h or 4p4e 21h) the p4e command is implemented only in S79FL256S and s79f l512s. the p4e command is ignored when the device is configured with the 256-kb sector option. the parameter 8-kb sector erase (p4e) command sets all the bits of a 8-kbyte parameter sector to 1 (all bytes are ffh). before the p4e command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the stat us register to enable any write operations. the instruction ? 20h [extadd=0] is followed by a 3-byte address (a23-a0), or ? 20h [extadd=1] is followed by a 4-byte address (a31-a0), or ? 21h is followed by a 4-byte address (a31-a0) cs# must be driven into the logic high st ate after the twenty-fourth or thirty-second bit of the address has been latched in on si. this will initiate the beginnin g of internal erase cycle, which involves the preprogrammi ng and erase of the ch osen sector of the fl ash memory array. if cs# is not driven high after the last bi t of address, the sector eras e operation will not be executed. as soon as cs# is driven high, the internal erase cycle will be initiated. with the internal erase cycle in progress, the user can read the value of the write-in progress (wip) bit to determine when the operation has been completed. the wip bit will indicate a 1. when the erase cycle is in pr ogress and a 0 when the eras e cycle has been completed. a p4e command applied to a sector that has been write protected through the block protec tion bits or asp, will not be executed and will set the e_err status. a p4e command applied to a sector that is larger than 8 kbytes will not be executed and will not set the e_err status. figure 63. dual-quad parameter sector erase command sequence (p4e 20h or 4p4e 21h) note: 1. a = msb of address = a23 for p4e 20h, or a31 for 4p4e 21h. 9.6.2 sector erase ( se d8h or 4se dch) the sector erase (se) command sets all bits in the addressed se ctor to 1 (all bytes are ffh). before the sector erase (se) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the instruction ? d8h [extadd=0] is followed by a 3-byte address (a23-a0), or ? d8h [extadd=1] is followed by a 4-byte address (a31-a0), or ? dch is followed by a 4-byte address (a31-a0) cs# must be driven into the logic high state after the twenty-f ourth or thirty-second bit of address has been latched in on io0 and io4. this will initiate the erase cycle, whic h involves the pre-programmi ng and erase of the chosen se ctor. if cs# is not drive n high after the last bit of address, the sector erase operation will not be executed. cs# sck io0 io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 a 1 0 instruction address document number: 002-00518 rev. *d page 82 of 111 S79FL256S/s79fl512s as soon as cs# is driven into the logic high state, the internal erase cycle will be in itiated. with the internal erase cycle i n progress, the user can read the value of the write- in progress (wip) bit to check if the operation has been completed. the wip bit will i ndicate a 1 when the erase cycle is in progress and a0 when the er ase cycle has been completed. a sector erase (se) command applied to a se ctor that has been write prot ected through the block prot ection bits or asp, will no t be executed and will set the e_err status. a device ordering option determines whether the se command erases 12 8 kbytes or 512 kbytes. the option to use this command to always erase 512 kbytes provides for software compatibilit y with higher density and future s79fl family devices. asp has a ppb and a dyb protection bit for each sector. if a sector erase command is applied to a 128-kb range that includes a protected 8-kb sector, or to a 512-kb range that includes a 128- kb protected address range, the erase will not be executed on t he range and will set the e_err status. figure 64. dual-quad sector erase (se 20h or 4se 21h) command sequence note: 1. a = msb of address = a23 for se d8h, or a31 for 4se dch. 9.6.3 bulk erase (be 60h or c7h) the bulk erase (be) command sets all bits to 1 (all bytes are ff h) inside the entire flash memory array. before the be command can be accepted by the device, a write enable (wren) command must be issued an d decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. cs# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on io0 and io4. t his will initiate the erase cycle, which in volves the pre-programmi ng and erase of the entire flash memory array. if cs# is not driven h igh after the last bit of instruction, the be operation will not be executed. as soon as cs# is driven into the logic high state, the erase cycle will be initiate d. with the erase cycle in progress, the us er can read the value of the write-in progress (wip) bit to determine when the operation has been completed. the wip bit will indicate a 1 when the erase cycle is in pr ogress and a 0 when the eras e cycle has been completed. a be command can be executed only when the block protection (bp2, bp 1, bp0) bits are set to 0?s. if the bp bits are not zero, t he be command is not executed and e_err is not set. the be co mmand will skip any sectors prot ected by the dyb or ppb and the e_err status will not be set. figure 65. bulk erase command sequence cs# sck io0 io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 a 1 0 instruction address cs# sck io0 io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction document number: 002-00518 rev. *d page 83 of 111 S79FL256S/s79fl512s 9.6.4 erase suspend and resume co mmands (ersp 75h or errs 7ah) the erase suspend command, allows the system to interrupt a sect or erase operation and then read from or program data to, any other sector. erase suspend is valid only during a sector erase operation. the erase suspend comma nd is ignored if written duri ng the bulk erase operation. when the erase suspend command is writ ten during the sector erase operation, the device requires a maximum of t esl (erase suspend latency) to suspend the erase ope ration and update the status bits. see table 44, erase suspend ac parameters on page 93 . commands allowed after the erase suspend command is issued: ? read status register-1 (rdsr1 05h) ? read status register-2 (rdsr2 07h) the write in progress (wip) bit in status register-1 (sr1[0]) must be checked to kn ow when the erase operation has stopped. the erase suspend bit in status register-2 (sr2[1]) can be used to determine if an erase operation has been suspended or was completed at the time wip changes to 0. if the erase operation was completed during t he suspend operation, a resume command is not needed and has no effect if issued. erase resume commands will be ignored unless an erase operation is suspended. see table 41, commands allowed during program or erase suspend on page 84 for the commands allowed while erase is suspend. after the erase operation has been suspended, the sector enters the erase-suspend mo de. the system can read data from or program data to the device. reading at any address within an erase-suspended sector produces undetermined data. a wren command is required before any command that will change non-volatile data, even during erase suspend. the wrr and ppb erase commands are not allowed during erase suspe nd, it is therefore not possibl e to alter the block protection or ppb bits during erase suspend. if there are sectors that may need programming duri ng erase suspend, these sectors should be protected only by dyb bits that can be turned off during erase su spend. however, wrr is allowed immediately following the brac command; in this special case the wrr is interpreted as a wr ite to the bank address register, not a write to sr1 or cr1. if a program command is sent for a location within an erase susp ended sector the program operation will fail with the p_err bit set. after an erase-suspended program operation is complete, the device returns to the erase-suspend mode. the system can determine the status of the program operati on by reading the wip bit in the status r egister, just as in the standard program operation. the erase resume command 7ah must be written to resume the erase operation if an erase is suspend. erase resume commands will be ignored unless an erase is suspend. after an erase resume command is sent, the wip bit in the status register will be se t to a 1 and the erase operation will conti nue. further resume commands are ignored. erase operations may be interrupted as often as necessary e.g. an erase suspend command could immediately follow an erase resume command but, in order for an erase operation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to t ers . see table 44, erase suspend ac parameters on page 93 . figure 66. dual-quad erase suspend command sequence cs# sck io0 io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction document number: 002-00518 rev. *d page 84 of 111 S79FL256S/s79fl512s figure 67. dual-quad erase resume command sequence sck io0 io1-io3 io4 io5-io7 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 table 41. commands allowed during program or erase suspend instruction name instruction code (hex) allowed during erase suspend allowed during program suspend comment brac b9 x x bank address register may need to be changed duri ng a suspend to reach a sector for read or program. brrd 16 x x bank address register may need to be changed duri ng a suspend to reach a sector for read or program. brwr 17 x x bank address register may need to be changed duri ng a suspend to reach a sector for read or program. clsr 30 x clear status may be used if a program operation fails during erase suspend. dybrd e0 x it may be necessary to remove and restore dynamic protection during erase suspend to allow programming during erase suspend. dybwr e1 x it may be necessary to remove and restore dynamic protection during erase suspend to allow programming during erase suspend. errs 7a x required to resume from erase suspend. fast_read 0b x x all array reads allowed in suspend. 4fast_read 0c x x all array reads allowed in suspend. mbr ff x x may need to reset a read operation during suspend. pgrs 8a x x needed to resume a program operation. a program resume may also be used during nested program suspend within an erase suspend. pgsp 85 x program suspend allowed during erase suspend. pp 02 x required for array program during erase suspend. 4pp 12 x required for array program during erase suspend. ppbrd e2 x allowed for checking persistent protection before attempting a program command during erase suspend. qpp 32, 38 x required for array program during erase suspend. 4qpp 34 x required for array program during erase suspend. 4read 13 x x all array reads allowed in suspend. rdcr 35 x x ddrqior ed x x all array reads allowed in suspend. ddrqior4 ee x x all array reads allowed in suspend. qior eb x x all array reads allowed in suspend. 4qior ec x x all array reads allowed in suspend. qor 6b x x all array reads allowed in suspend. 4qor 6c x x all array reads allowed in suspend. rdsr1 05 x x needed to read wip to determine end of suspend process. rdsr2 07 x x needed to read suspend status to determine whether the operation is suspended or complete. read 03 x x all array reads allowed in suspend. reset f0 x x reset allowed anytime. wren 06 x required for program command within erase suspend. document number: 002-00518 rev. *d page 85 of 111 S79FL256S/s79fl512s 9.7 one time program array commands 9.7.1 otp program (otpp 42h) the otp program command programs data in the one time program region, which is in a different address space from the main array data. the otp region is 2048 bytes so, the address bits fr om a25 to a10 must be zero for this command. refer to section 7.4, otp address space on page 35 for details on the otp region. the protocol of the otp program command is the same as the page program command. before the otp program command can be accept ed by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latc h (wel) in the status register to enable any write operations . to program the otp array in bit granularity, the rest of the bits within a data byte c an be set to 1. each region in the otp me mory space can be programmed one or more times, pr ovided that the region is not locked. atte mpting to program zeros in a region that is locked will fail with the p_err bit in sr1 set to 1 programming one s, even in a protected area doe s not cause an error and does not set p_err. subsequent otp programming can be performed only on th e un-programmed bits (that is, 1 data). the protocol of the otp program command is the same as the page program command. see section 9.5.2, page program (pp 02h or 4pp 12h) on page 78 for the command sequence. 9.7.2 otp read (otpr 4bh) the otp read command reads data from the otp region. the otp regi on is 2048 bytes so, the address bits from a25 to a10 must be zero for this command. refer to otp address space on page 35 for details on the otp region. the protocol of the otp read command is similar to the fast read command except that it will not wrap to the starting address after the otp address is at it s maximum; instead, the data beyond the maxi mum otp address will be undefined. also, the otp read command is not affected by the latency code. the otp read command always has one dummy byte of latency as shown below. figure 68. read otp (otpr 4bh) command sequence wrr 01 x x bank register may need to be changed during a suspend to reach a sector needed for read or program. wrr is allowed when following brac. table 41. commands allowed during program or erase suspend (continued) instruction name instruction code (hex) allowed during erase suspend allowed during program suspend comment cs# sclk io0 io1 io2-io3 io4 io5 io6-io7 phase 7 6 5 4 3 2 1 0 31 1 0 3 2 1 0 3 2 1 0 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 7 6 5 4 instruction address dummy cycles data 1 data 2 document number: 002-00518 rev. *d page 86 of 111 S79FL256S/s79fl512s 9.8 advanced sector protection commands 9.8.1 asp read (asprd 2bh) the asp read instruction 2bh is shifted into si by the rising edge of the sck signal. then the 16 -bit asp register contents is shifted out on the serial output so, least significant byte first. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to read the asp register continuously by providing multiples of 16 clock cycles. the maximum operating c lock frequency for the asp read (asprd) command is 133 mhz. figure 69. dual-quad spi asprd command sequence 9.8.2 asp program (aspp 2fh) before the asp program (aspp) command can be accepted by the dev ice, a write enable (wren) command must be issued. after the write enable (wren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the aspp command is entered by driv ing cs# to the logic low state, followed by the instruction and two data bytes on si, least significant byte first. the asp regist er is two data bytes in length. the aspp command affects the p_err and wip bits of the status and configuration registers in the same manner as any other programming operation. cs# input must be driven to the logic high state after the sixteenth bit of data has been latched in. if not, the aspp command is not executed. as soon as cs# is driven to the logic high state, the self-timed aspp operation is initiated. while the aspp operatio n is in progress, the status register may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bi t is a 1 during the self-timed aspp operation, and is a 0 when it is completed. when the aspp operation is complet ed, the write enable latch (wel) is set to a 0. figure 70. aspp (2fh) command cs# sck si_io0 so_io1 io2-io3 io4 io5 io6-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction register read repeat register read cs# sck io0 io1-io 3 io4 io5-io 7 phas e 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input aspr low byt e input irp high byte document number: 002-00518 rev. *d page 87 of 111 S79FL256S/s79fl512s 9.8.3 dyb read (dybrd e0h) the instruction e0h is latched into si by the rising edge of the sck signal. followed by the 32-bit address selecting location zero within the desired sector (note, the high order address bits no t used by a particular density device must be zero). then the 8- bit dyb access register contents are shifted out on the serial output so . each bit is shifted out at the sck frequency by the falling e dge of the sck signal. it is possible to read the same dyb access regist er continuously by providing multiples of eight clock cycles. the address of the dyb register does not increment so this is not a means to read the entire dyb array. each location must be read with a separate dyb read command. the maximum operating clock frequency for read command is 133 mhz. figure 71. dybrd command sequence 9.8.4 dyb write (dybwr e1h) before the dyb write (dybwr) command can be accepted by the dev ice, a write enable (wren) command must be issued. after the write enable (wren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the dybwr command is entered by driving cs# to the logic low st ate, followed by the instruction, the 32-bit address selecting location zero within the desired sector ( note, the high order address bits not used by a particular density device must be zero ), then the data byte on si. the dyb access register is one data byte in length. the dybwr command affects the p_err and wip bits of the status and configuration re gisters in the same manner as any other programming operation. cs# must be driven to the logic high state after the eighth bit of data has been latc hed in. if not, the dybwr command is not executed. as soon as cs# is driven to the logic high state, the self-timed dybwr operation is initiated. while t he dybwr operation is in progress, the status register may be read to check the va lue of the write-in progress (wip) bit. the writ e- in progress (wip) bit is a 1 during the self-timed dybwr operatio n, and is a 0 when it is comple ted. when the dybwr operation i s completed, the write enable latch (wel) is set to a 0. figure 72. dybwr (e1h) command sequence cs# sck io0 io1 io2-io3 io4 io5 io6-io7 phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address register repeat register cs# sck io0 io1-io 3 io4 io5-io 7 phas e 7 6 5 4 3 2 1 0 a 5 4 3 2 1 0 3 2 1 0 3 2 1 0 7 6 5 4 3 2 1 0 a 5 4 3 2 1 0 7 6 5 4 7 6 5 4 instruction address input data 1 input data 2 document number: 002-00518 rev. *d page 88 of 111 S79FL256S/s79fl512s 9.8.5 ppb read (ppbrd e2h) the instruction e2h is shifted into si by the rising edges of the sck signal, followed by the 32-bit address selecting location zero within the desired sector (not e, the high order address bits not used by a particular density device must be zero) then the 8-b it ppb access register contents are shifted out on so. it is possible to read the same ppb access re gister continuously by providing multiple s of eight clock cycles. the address of t he ppb register does not increment so this is not a means to read the entire ppb array. each location must be read with a separate ppb read command. the maximum operating clock frequency for the ppb read command is 133 mhz. figure 73. ppbrd (e2h) command sequence 9.8.6 ppb program (ppbp e3h) before the ppb program (ppbp) command can be accepted by the dev ice, a write enable (wren) command must be issued. after the write enable (wren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the ppbp command is entered by dr iving cs# to the lo gic low state, followed by the instru ction, followed by the 32-bit address selecting location zero within the desired se ctor (note, the high order address bits no t used by a particular density device mu st be zero). the ppbp command affects the p_err and wip bits of the status and configuration registers in the same manner as any other programming operation. cs# must be driven to the logic high stat e after the last bit of address has been latched in. if not, the ppbp command is not executed. as soon as cs# is driven to the logic high state, the self-timed ppbp operation is initiated. while the ppbp operatio n is in progress, the status register may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bi t is a 1 during the self-timed ppbp operation, and is a 0 when it is completed. when the ppbp operation is complet ed, the write enable latch (wel) is set to a 0. figure 74. ppbp (e3h) command sequence cs# sck si_io0 so_io1 io2-io3 io4 io5 io6-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction dy register read repeat register read cs# sck io0 io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 a 1 0 instruction address document number: 002-00518 rev. *d page 89 of 111 S79FL256S/s79fl512s 9.8.7 ppb erase (ppbe e4h) the ppb erase (ppbe) command sets all ppb bits to 1. before the ppb erase command can be ac cepted by the device, a write enable (wren) command must be issued and decoded by the devi ce, which sets the write enable latch (wel) in the status register to enable any write operations. the instruction e4h is shifted into si by the rising edges of the sck signal. cs# must be driven into the logic high state after the eighth bi t of the instruction byte has been latched in on si. this will initiate the beginning of internal erase cycl e, which involves the pre-prog ramming and erase of the entire ppb memory array. without cs# being driven to the logic high state after the eighth bit of the instruction, the ppb eras e operation will not be executed. with the internal erase cycle in progress, the user can read th e value of the write- in progress (wip) bit to check if the opera tion has been completed. the wip bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been complet ed. erase suspend is not allowed during ppb erase. figure 75. ppb erase ( ppbe e4h) command sequence 9.8.8 ppb lock bit read (plbrd a7h) the ppb lock bit read (plbrd) command allows the ppb lock register contents to be read out of so. it is possible to read the ppb lock register continuously by providing multiples of eight clock cycles. the ppb lo ck register contents may only be read wh en the device is in standby state with no other operation in progress. it is recommended to check the write-in progress (wip) bit of the status register before issui ng a new command to the device. figure 76. ppb lock register read command sequence cs# sck io0 io1-io 3 io4 io5-io 7 phas e 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction cs# sck si_io0 so_io1 io2-io3 io4 io5 io6-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction dy register read repeat register read document number: 002-00518 rev. *d page 90 of 111 S79FL256S/s79fl512s 9.8.9 ppb lock bit write (plbwr a6h) the ppb lock bit write (plbwr) co mmand clears the ppb lock regist er to zero. before the pl bwr command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, whic h sets the write enable latch (wel) in the status register to enable any write operations. the plbwr command is entered by driving cs# to the logic low state, followed by the instruction. cs# must be driven to the logic high state after the eighth bit of instruction has b een latched in. if not, the plbwr command i s not executed. as soon as cs# is dr iven to the logic high state, th e self-timed plbwr operation is initiated. while the plbwr operat ion is in progress, the status register may st ill be read to check the value of the writ e-in progress (wip) bit. the write-in progr ess (wip) bit is a 1 during the self-timed plbwr op eration, and is a 0 when it is complete d. when the plbwr o peration is completed, the write enable latch (wel) is set to a 0. the maximum clock frequency for the plbwr command is 133 mhz. figure 77. ppb lock bit write (plbwr a6h) command sequence 9.8.10 password r ead (passrd e7h) the correct password value may be read only after it is pr ogrammed and before the password mode has been selected by programming the password protection mode bi t to 0 in the asp register (a sp[2]). after the password pr otection mode is selected the passrd command is ignored. the passrd command is shifted into si. then th e 64-bit password is shifted out on the serial output so, least significant byte first, most significant bit of each byte first. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to read the password continuously by pr oviding multiples of 64 cloc k cycles. the maximum operati ng clock frequency for the passrd command is 133 mhz. figure 78. password read (passrd e7h) command sequence cs# sck io0 io1-io 3 io4 io5-io 7 phas e 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction cs# sck si_io0 so_io1 io2-io3 io4 io5 io6-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data 8 document number: 002-00518 rev. *d page 91 of 111 S79FL256S/s79fl512s 9.8.11 password program (passp e8h) before the password program (passp) comma nd can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded, the device sets the write enable latch (wel) to enabl e the passp operation. the password can only be programmed before the password mode is selected by programming th e password protection mode bit to 0 in the asp register (asp[2]). af ter the password protection mode is selected the passp command is ignored. the passp command is entered by driving cs# to the logic low stat e, followed by the instruction and the password data bytes on si, least significant byte first, most signi ficant bit of each byte first. the passwo rd is sixty-four (64) bits in length. cs# must be driven to the logic hi gh state after the sixty-fourth (64 th ) bit of data has been latched. if not, the passp command is not executed. as soon as cs# is driven to the logic high state, the se lf-timed passp operation is init iated. while the passp operat ion is in progress, the status register may be read to check the va lue of the write-in progress (wip ) bit. the write-in progress (w ip) bit is a 1 during the self-timed passp cycle, and is a 0 when it is complet ed. the passp command can repo rt a program error in the p_err bit of the status register. when the passp operation is co mpleted, the write enable latch (wel) is set to a 0. the maximum clock frequency for the passp command is 133 mhz. figure 79. password program (passp e8h) command sequence 9.8.12 password unlock (passu e9h) the passu command is entered by driving cs# to the logic low st ate, followed by the instruction and the pa ssword data bytes on si, least significant byte first, most signi ficant bit of each byte first. the passwo rd is sixty-four (64) bits in length. cs# must be driven to the logic high state after the sixty-fourth (64 th ) bit of data has been latched. if not, the passu command is not executed. as soon as cs# is driven to the logic high state, the self-timed passu oper ation is initiated. while the passu operat ion is in progress, the status register may be read to check the va lue of the write-in progress (wip ) bit. the write-in progress (w ip) bit is a 1 during the self-timed passu cycle, and is a 0 when it is completed. if the passu command supplied password does not match the hidden password in the password register, an error is reported by setting the p_err bit to 1. the wip bit of the status register al so remains set to 1. it is nece ssary to use the clsr command t o clear the status register, the reset comman d to software reset the device, or drive th e reset# input low to initiate a hardware reset, in order to return the p_err and wip bits to 0. this returns the device to standby state, ready for new commands such as a retry of the passu command. if the password does match, the ppb lock bi t is set to 1. the maximum clock fr equency for the passu command is 133 mhz. figure 80. password unlock (passu e9h) command sequence cs# sck io0 io1-io 3 io4 io5-io 7 phas e 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction password byte 1 password byte 8 cs# sck io0 io1-io 3 io4 io5-io 7 phas e 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction password byte 1 password byte 8 document number: 002-00518 rev. *d page 92 of 111 S79FL256S/s79fl512s 9.9 reset commands 9.9.1 software reset command (reset f0h) the software reset command (reset) restores th e device to its init ial power up state, except for the volatile freeze bit in the configuration register cr1[1] and the volatile ppb lock bit in the ppb lock register. the freeze bit and the ppb lock bit will remain set at their last value prior to t he software reset. to clear the freeze bit and set the ppb lock bit to its protection mode selected power on state, a full power-on-reset sequence or hardware reset must be done. note that the non-volatile bits in the configuration register, tbprot, tbparm, and bpnv, retain their pr evious state after a software reset. the block protection bits bp2, bp1, and bp0, in the status register w ill only be reset if they are configured as volatile via the bpnv bit in the configu ration register (cr1[3]) and freeze is cleared to zero . the software reset cannot be us ed to circumvent the freeze or ppb lock bit protection mechanisms for the other security configuration bits. the reset command is executed when cs# is brought to high stat e and requires t rph time to execute. figure 81. dual-qua d software reset (reset f0h) command sequence 9.9.2 mode bit reset (mbr ffh) the mode bit reset (mbr) command can be used to return the device from continuous high performance read mode back to normal standby awaiting any new command. becaus e some device packages la ck a hardware reset# input a nd a device that is in a continuous high performance read mode may not recognize any norma l spi command, a system hardwa re reset or so ftware reset command may not be recognized by the device. it is recomme nded to use the mbr command after a system reset when the reset# signal is not available or, before sending a software rese t, to ensure the device is released from continuous high performance read mode. the mbr command sends ones on io 0 and io4 for 8 sck cycles. io 1 - io3 and io5 - io7 are ?don ?t care? during these cycles. figure 82. dual-quad spi mode bit (mbr ffh) reset command sequence cs# sck io0 io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction cs# sck io0 io1-io3 io4 io5-io7 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction document number: 002-00518 rev. *d page 93 of 111 S79FL256S/s79fl512s 9.10 embedded algorithm performance tables notes: 1. typical program and erase times assume the following conditions: 25c, v cc = 3.0v; random data pattern. 2. under worst case conditions of 90c; 100,000 cycles max. 3. maximum value also applies to otpp, ppbp, asp p, passp, abwr, and pnvdlr programming commands. 4. maximum value also applies to the ppbe erase command. table 42. program and erase performance symbol parameter min typ (1) max (2) unit t w wrr write time 560 2000 ms t pp page programming (1024 bytes) 340 750 (3) s page programming (512 bytes) 250 750 s t se sector erase time (512-kb logical sectors = 4 x 128 kb physical sectors) 520 2600 ms sector erase time (128-kb /8-kb physical sectors) 130 650 (4) ms sector erase time (128-kb /8-kb top / bottom: logica l sector = 16 x 8-kb physical sectors) 2080 10400 ms t be bulk erase time (S79FL256S) 33 165 sec bulk erase time (s79fl512s) 66 330 sec table 43. program suspend ac parameters parameter min typical max unit comments program suspend latency (t psl ) 40 s the time from program suspend command until the wip bit is 0 program resume to next program suspend (t prs ) 0.06 100 s minimum is the time needed to issue the next program suspend command but typical periods are needed for program to progress to completion table 44. erase suspend ac parameters parameter min typical max unit comments erase suspend latency (t esl ) 45 s the time from erase suspend command until the wip bit is 0 erase resume to next erase suspend (t ers) 0.06 100 s minimum is the time needed to issue the next erase suspend command but typical periods are needed for the erase to progress to completion document number: 002-00518 rev. *d page 94 of 111 S79FL256S/s79fl512s 10. data integrity 10.1 erase endurance note: 1. each write command to a non-volatile register causes a pe cycle on the entire non-volatile register array. 10.2 data retention contact cypress sales and fae for further information on th e data integrity. an application note is available at: www.cypress.com/appnotes . table 45. erase endurance parameter minimum unit program/erase cycles per main flash array sectors 100k pe cycle program/erase cycles per ppb array or non-volatile register array (1) 100k pe cycle table 46. data retention parameter test conditions minimum time unit data retention time 10k program/erase cycles 20 years 100k program/erase cycles 2 years document number: 002-00518 rev. *d page 95 of 111 S79FL256S/s79fl512s 11. software interface reference 11.1 command summary table 47. S79FL256S/s79fl512s instruction set (sorted by instruction) instruction (hex) command name command description maximum frequency (mhz) 01 wrr write register (status-1, configuration-1) 133 02 pp page program (3- or 4-byte address) 133 03 read read (3- or 4-byte address) 50 04 wrdi write disable 133 05 rdsr1 read status register-1 133 06 wren write enable 133 07 rdsr2 read status register-2 133 0b fast_read fast read (3- or 4-byte address) 133 0c 4fast_read fast read (4-byte address) 133 12 4pp page program (4-byte address) 133 13 4read read (4-byte address) 50 14 abrd autoboot register read 133 15 abwr autoboot register write 133 16 brrd bank register read 133 17 brwr bank register write 133 18 eccrd ecc read 133 20 p4e parameter 8-kb sector erase (3- or 4-byte address) 133 21 4p4e parameter 8-kb sector erase (4-byte address) 133 2b asprd asp read 133 2f aspp asp program 133 30 clsr clear status register - erase/program fail reset 133 32 qpp quad page program (3- or 4-byte address) 80 34 4qpp quad page program (4-byte address) 80 35 rdcr read configuration register-1 133 38 qpp quad page program (3- or 4-byte address) 80 41 dlprd data learning pattern read 133 42 otpp otp program 133 43 pnvdlr program nv data learning register 133 4a wvdlr write volatile data learning register 133 4b otpr otp read 133 60 be bulk erase 133 6b qor read quad out (3- or 4-byte address) 104 6c 4qor read quad out (4-byte address) 104 75 ersp erase suspend 133 7a errs erase resume 133 85 pgsp program suspend 133 8a pgrs program resume 133 90 read_id (rems) read electronic manufacturer signature 133 9f rdid read id (jedec manufacturer id and jedec cfi) 133 a3 mpm reserved for multi-i/o-high perf mode (mpm) 133 a6 plbwr ppb lock bit write 133 document number: 002-00518 rev. *d page 96 of 111 S79FL256S/s79fl512s a7 plbrd ppb lock bit read 133 ab res read electronic signature 50 b9 brac bank register access (legacy command formerly used for deep power down) 133 c7 be bulk erase (alternate command) 133 d8 se erase 128 kb or 512 kb (3- or 4-byte address) 133 dc 4se erase 128 kb or 512 kb (4-byte address) 133 e0 dybrd dyb read 133 e1 dybwr dyb write 133 e2 ppbrd ppb read 133 e3 ppbp ppb program 133 e4 ppbe ppb erase 133 e5 reserved-e5 reserved e6 reserved-e6 reserved e7 passrd password read 133 e8 passp password program 133 e9 passu password unlock 133 eb qior quad i/o read (3- or 4-byte address) 104 ec 4qior quad i/o read (4-byte address) 104 ed ddrqior ddr quad i/o read (3- or 4-byte address) 80 ee 4ddrqior ddr quad i/o read (4-byte address) 80 f0 reset software reset 133 ff mbr mode bit reset 133 table 47. S79FL256S/s79fl512s instruction set (sorted by instruction) (continued) instruction (hex) command name command description maximum frequency (mhz) document number: 002-00518 rev. *d page 97 of 111 S79FL256S/s79fl512s 11.2 device id and common flash interface (id-cfi) address map 11.2.1 field definitions table 48. manufacturer and device id byte address data description 00h 01h manufacturer id for cypress 01h 79h device id most significant byte ? memory interface type 02h 19h (256 mb) 20h (512 mb) device id least significant byte ? density 03h xxh id-cfi length - number bytes following. adding this value to the current location of 03h gives the addr ess of the last valid location in the id-cfi address map. a value of 00h indicates the entire 512-byte id-cfi space must be read because the actual length of the id-cfi information is longer than can be indicated by this legacy single byte field. the value is opn dependent. 04h 00h (uniform 512-kb sectors) 01h (8-kb parameter sectors with uniform 128-kb sectors) sector architecture 05h 80h (fl-s family) family id 06h xxh ascii characters for model refer to ordering information on page 108 for the model number definitions. 07h xxh 08h xxh reserved 09h xxh reserved 0ah xxh reserved 0bh xxh reserved 0ch xxh reserved 0dh xxh reserved 0eh xxh reserved 0fh xxh reserved table 49. cfi query identification string byte address data description 10h 11h 12h 51h 52h 59h query unique ascii string ?qry? 13h 14h 02h 00h primary oem command set fl-p backward compatible command set id 15h 16h 40h 00h address for primary extended table 17h 18h 53h 46h alternate oem command set ascii characters ?fs? for spi (f) interface, s technology 19h 1ah 51h 00h address for alternate oem extended table document number: 002-00518 rev. *d page 98 of 111 S79FL256S/s79fl512s table 50. cfi system interface string byte address data description 1bh 27h v cc min. (erase/progr am): 100 millivolts 1ch 36h v cc max. (erase/progr am): 100 millivolts 1dh 00h v pp min. voltage (00h = no v pp present) 1eh 00h v pp max. voltage (00h = no v pp present) 1fh 06h typical timeout per single byte program 2 n s 20h 08h (512b page) 09h (1024b page) typical timeout for min. size page program 2 n s (00h = not supported) 21h 08h (8 kb or 128 kb) 09h (512 kb) typical timeout per individual sector erase 2 n ms 22h 0fh (256 mb) 10h (512 mb) typical timeout for full chip erase 2 n ms (00h = not supported) 23h 02h max. timeout for byte program 2 n times typical 24h 02h max. timeout for page program 2 n times typical 25h 03h max. timeout per individual sector erase 2 n times typical 26h 03h max. timeout for full chip erase 2 n times typical (00h = not supported) table 51. device geometry definition for 256-mbi t and 512-mbit bottom boot initial delivery state byte address data description 27h 19h (256 mb) 1ah (512 mb) device size = 2 n bytes; 28h 03h flash device interface description; 0000h = x8 only 0001h = x16 only 0002h = x8/x16 capable 0003h = x32 only 0004h = single i/o spi, 3-byte address 0005h = multi i/o spi, 3-byte address 0102h = multi i/o spi, 3- or 4-byte address 0103h = dual-quad spi, 3 or 4-byte address 29h 01h 2ah 09h max. number of bytes in multi-byte write = 2 n (0000 = not supported 0008h = 256b page) 0009h = 512b page) 0000a = 1024b page 2bh 00h 2ch 02h number of erase block regions within device 1 = uniform device, 2 = boot device 2dh 1fh erase block region 1 information (refer to jedec jep137) 32 sectors = 32-1 = 001fh 8-kb sectors = 256 bytes x 0010h 2eh 00h 2fh 10h 30h 00h document number: 002-00518 rev. *d page 99 of 111 S79FL256S/s79fl512s 31h fdh erase block region 2 information: 254 sectors = 254-1 = 00fdh (256 mb) 510 sectors = 510-1 = 01fdh (512 mb) 128-kb sectors = 0100h x 256 bytes 32h 00h (256 mb) 01h (512 mb) 33h 00h 34h 01h 35h thru 3fh ffh rfu table 51. device geometry definition for 256-mbit and 512-mbit bottom boot initial delivery state (continued) byte address data description table 52. device geometry definition for 256-mbit and 512-mbit uniform sector devices byte address data description 27h 19h (256 mb) 1ah (512 mb) device size = 2 n bytes 28h 03h flash device interface description: 0000h = x8 only 0001h = x16 only 0002h = x8/x16 capable 0003h = x32 only 0004h = single i/o spi, 3-byte address 0005h = multi i/o spi, 3-byte address 0102h = multi i/o spi, 3- or 4-byte address 0103h = dual-quad spi, 3 or 4-byte address 29h 01h 2ah 0ah max. number of bytes in multi-byte write = 2 n (0000 = not supported 0008h = 256b page 0009h = 512b page 0000a = 1024b page 2bh 00h 2ch 01h number of erase block regions within device 1 = uniform device, 2 = boot device 2dh 3fh (256 mb) 7fh (512 mb) erase block region 1 information (refer to jedec jep137): 64 sectors = 64-1 = 003fh (256 mb) 128 sectors = 128-1 = 007fh (512 mb) 512-kb sectors = 256 bytes x 0400h 2eh 00h 2fh 00h 30h 04h 31h thru 3fh ffh rfu document number: 002-00518 rev. *d page 100 of 111 S79FL256S/s79fl512s table 53. cfi primary vendor-specific extended query byte address data description 40h 50h query-unique ascii string ?pri? 41h 52h 42h 49h 43h 31h major version number = 1, ascii 44h 33h minor version number = 3, ascii 45h 21h address sensitive unlock (bits 1-0) 00b = required 01b = not required process technology (bits 5-2) 0000b = 0.23 m floating gate 0001b = 0.17 m floating gate 0010b = 0.23 m mirrorbit 0011b = 0.11 m floating gate 0100b = 0.11 m mirrorbit 0101b = 0.09 m mirrorbit 1000b = 0.065 m mirrorbit 46h 02h erase suspend 0 = not supported 1 = read only 2 = read and program 47h 01h sector protect 00 = not supported x = number of sectors in group 48h 00h temporary sector unprotect 00 = not supported 01 = supported 49h 08h sector protect/unprotect scheme 04 = high voltage method 05 = software command locking method 08 = advanced sector protection method 09 = secure 4ah 00h simultaneous operation 00 = not supported x = number of sectors 4bh 01h burst mode (synchronous sequential read) support 00 = not supported 01 = supported 4ch 05h page mode type, model dependent 00 = not supported 01 = 4 word read page 02 = 8 read word page 03 = 256-byte program page 04 = 512-byte program page 05 = 1024-byte program page 4dh 00h acc (acceleration) supply minimum 00 = not supported, 100 mv document number: 002-00518 rev. *d page 101 of 111 S79FL256S/s79fl512s the alternate vendor-specific extended query provides informati on related to the expanded command set provided by the s25fl- s family. the alternate query parameters use a format in which ea ch parameter begins with an identifier byte and a parameter le ngth byte. driver software can check each parameter id and can use t he length value to skip to the next parameter if the parameter i s not needed or not recognized by the software. 4eh 00h acc (acceleration) supply maximum 00 = not supported, 100 mv 4fh 00h wp# protection 00 = none 01 = whole chip 04 = uniform device with bottom wp protect 05 = uniform device with top wp protect 07 = uniform device with top or bottom write protect (user select) 50h 01h program suspend 00 = not supported 01 = supported table 53. cfi primary vendor-specific extended query (continued) byte address data description table 54. cfi alternate vendor-specific extended query header byte address data description 51h 41h query-unique ascii string ?alt? 52h 4ch 53h 54h 54h 32h major version number = 2, ascii 55h 30h minor version number = 0, ascii table 55. cfi alternate vendor-specific extended query parameter 0 parameter relative byte address offset data description 00h 00h parameter id (ordering part number) 01h 10h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 53h ascii ?s? for manufacturer (cypress) 03h 37h ascii ?79? for product characters (dual-quad spi) 04h 39h 05h 46h ascii ?fl? for interface characters (spi 3 volt) 06h 4ch 07h 32h (256 mb) 35h (512 mb) ascii characters for density 08h 35h (256 mb) 31h (512 mb) 09h 36h (256 mb) 32h (512 mb) document number: 002-00518 rev. *d page 102 of 111 S79FL256S/s79fl512s 0ah 53h ascii ?s? for technology (65nm mirrorbit) 0bh xxh reserved for future use (rfu) 0ch xxh 0dh xxh 0eh xxh 0fh xxh 10h xxh 11h xxh table 56. cfi alternate vendor-specific extended query parameter 80h address options parameter relative byte address offset data description 00h 80h parameter id (ordering part number) 01h 01h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h f0h bits 7:4 - reserved = 1111b bit 3 - autoboot support - ye s= 0b, no = 1b bit 2 - 4-byte address instructions supported - yes = 0b, no = 1b bit 1 - bank address + 3-byte address instructions supported - yes = 0b, no = 1b bit 0 - 3-byte address instructions supported - yes = 0b, no = 1b table 55. cfi alternate vendor-specific extended query parameter 0 (continued) parameter relative byte address offset data description table 57. cfi alternate vendor-specific extended query parameter 84h suspend commands parameter relative byte address offset data description 00h 84h parameter id (suspend commands 01h 08h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 85h program suspend instruction code 03h 28h program suspend latency maximum (s) 04h 8ah program resume instruction code 05h 64h program resume to next suspend typical (s) 06h 75h erase suspend instruction code 07h 28h erase suspend latency maximum (s) 08h 7ah erase resume instruction code 09h 64h erase resume to ne xt suspend typical (s) document number: 002-00518 rev. *d page 103 of 111 S79FL256S/s79fl512s table 58. cfi alternate vendor-specific extended query parameter 88h data protection parameter relative byte address offset data description 00h 88h parameter id (data protection) 01h 04h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 0bh otp size 2 n bytes, ffh = not supported 03h 01h otp address map format, 01h = fl-s format, ffh = not supported 04h xxh block protect type, model dependent 00h = fl-p, fl-s, ffh = not supported 05h 01h advanced sector protection type, model dependent 01h = fl-s asp table 59. cfi alternate vendor-specific extended query parameter 8ch reset timing parameter relative byte address offset data description 00h 8ch parameter id (reset timing) 01h 06h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 96h por maximum value 03h 01h por maximum exponent 2 n s 04h 23h hardware reset maximum value, ffh = not supported 05h 00h hardware reset maximum exponent 2 n s 06h 23h software reset maximum value, ffh = not supported 07h 00h software reset maximum exponent 2 n s table 60. cfi alternate vendor-specific extended query parameter 90h - ehplc (sdr) parameter relative byte address offset data description 00h 90h parameter id (latency code table) 01h 56h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 06h number of rows 03h 0eh row length in bytes 04h 46h start of header (row 1), ascii ?f? for frequency column header 05h 43h ascii ?c? for code column header 06h 03h read 3-byte address instruction 07h 13h read 4-byte address instruction 08h 0bh read fast 3-byte address instruction 09h 0ch read fast 4-byte address instruction 0ah ffh read dual out 3-byte address instruction 0bh ffh read dual out 3-byte address instruction document number: 002-00518 rev. *d page 104 of 111 S79FL256S/s79fl512s 0ch 6bh read quad out 3-byte address instruction 0dh 6ch read quad out 4-byte address instruction 0eh ffh dual i/o read 3-byte address instruction 0fh ffh dual i/o read 4-byte address instruction 10h ebh quad i/o read 3-byte address instruction 11h ech quad i/o read 4-byte address instruction 12h 32h start of row 2, sck frequency limit for this row (50 mhz) 13h 03h latency code for this row (11b) 14h 00h read mode cycles 15h 00h read latency cycles 16h 00h read fast mode cycles 17h 00h read fast latency cycles 18h ffh read dual out mode cycles 19h ffh read dual out mode cycles 1ah 00h read quad out mode cycles 1bh 00h read quad out latency cycles 1ch ffh dual i/o read mode cycles 1dh ffh dual i/o read latency cycles 1eh 02h quad i/o read mode cycles 1fh 01h quad i/o read latency cycles 20h 50h start of row 3, sck frequency limit for this row (80 mhz) 21h 00h latency code for this row (00b) 22h ffh read mode cycles (ffh = command not supported at this frequency) 23h ffh read latency cycles 24h 00h read fast mode cycles 25h 08h read fast latency cycles 26h 00h read dual out mode cycles 27h ffh read dual out latency cycles 28h 00h read quad out mode cycles 29h 08h read quad out latency cycles 2ah ffh dual i/o read mode cycles 2bh ffh dual i/o read latency cycles 2ch 02h quad i/o read mode cycles 2dh 04h quad i/o read latency cycles 2eh 5ah start of row 4, sck frequency limit for this row (90 mhz) 2fh 01h latency code for this row (01b) 30h ffh read mode cycles (ffh = command not supported at this frequency) 31h ffh read latency cycles 32h 00h read fast mode cycles 33h 08h read fast latency cycles 34h ffh read dual out mode cycles 35h 08h read dual out latency cycles 36h 00h read quad out mode cycles 37h 08h read quad out latency cycles 38h 00h dual i/o read mode cycles table 60. cfi alternate vendor-specific extended query parameter 90h - ehplc (sdr) (continued) parameter relative byte address offset data description document number: 002-00518 rev. *d page 105 of 111 S79FL256S/s79fl512s note: 1. ffh = not supported. 39h ffh dual i/o read latency cycles 3ah 02h quad i/o read mode cycles 3bh 04h quad i/o read latency cycles 3ch 68h start of row 5, sck frequency limit for this row (104 mhz) 3dh 02h latency code for this row (10b) 3eh ffh read mode cycles (ffh = command not supported at this frequency) 3fh ffh read latency cycles 40h 00h read fast mode cycles 41h 08h read fast latency cycles 42h ffh read dual out mode cycles 43h ffh read dual out latency cycles 44h 00h read quad out mode cycles 45h 08h read quad out latency cycles 46h ffh dual i/o read mode cycles 47h ffh dual i/o read latency cycles 48h 02h quad i/o read mode cycles 49h 05h quad i/o read latency cycles 4ah 85h start of row 6, sck frequency limit for this row (133 mhz) 4bh 02h latency code for this row (10b) 4ch ffh read mode cycles (ffh = command not supported at this frequency) 4dh ffh read latency cycles 4eh 00h read fast mode cycles 4fh 08h read fast latency cycles 50h ffh read dual out mode cycles 51h ffh read dual out latency cycles 52h ffh read quad out mode cycles 53h ffh read quad out latency cycles 54h ffh dual i/o read mode cycles 55h ffh dual i/o read latency cycles 56h ffh quad i/o read mode cycles 57h ffh quad i/o read latency cycles table 61. cfi alternate vendor-specific extended query parameter 9ah - ehplc (ddr) parameter relative byte address offset data description 00h 9ah parameter id (latency code table) 01h 2ah parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 05h number of rows 03h 08h row length in bytes 04h 46h start of header (row 1), ascii ?f? for frequency column header 05h 43h ascii ?c? for code column header 06h ffh read fast ddr 3-byte address instruction 07h ffh read fast ddr 4-byte address instruction table 60. cfi alternate vendor-specific extended query parameter 90h - ehplc (sdr) (continued) parameter relative byte address offset data description document number: 002-00518 rev. *d page 106 of 111 S79FL256S/s79fl512s note: ffh = not supported. 08h ffh ddr dual i/o read 3-byte address instruction 09h ffh ddr dual i/o read 4-byte address instruction 0ah edh read ddr quad i/o 3-byte address instruction 0bh eeh read ddr quad i/o 4-byte address instruction 0ch 32h start of row 2, sck frequency limit for this row (50 mhz) 0dh 03h latency code for this row (11b) 0eh ffh read fast ddr mode cycles 0fh ffh read fast ddr latency cycles 10h ffh ddr dual i/o read mode cycles 11h ffh ddr dual i/o read latency cycles 12h 01h read ddr quad i/o mode cycles 13h 03h read ddr quad i/o latency cycles 14h 42h start of row 3, sck frequency limit for this row (66 mhz) 15h 00h latency code for this row (00b) 16h ffh read fast ddr mode cycles 17h ffh read fast ddr latency cycles 18h ffh ddr dual i/o read mode cycles 19h ffh ddr dual i/o read latency cycles 1ah 01h read ddr quad i/o mode cycles 1bh 06h read ddr quad i/o latency cycles 1ch 42h start of row 4, sck frequency limit for this row (66 mhz) 1dh 01h latency code for this row (01b) 1eh ffh read fast ddr mode cycles 1fh ffh read fast ddr latency cycles 20h ffh ddr dual i/o read mode cycles 21h ffh ddr dual i/o read latency cycles 22h 01h read ddr quad i/o mode cycles 23h 07h read ddr quad i/o latency cycles 24h 42h start of row 5, sck frequency limit for this row (66 mhz) 25h 02h latency code for this row (10b) 26h ffh read fast ddr mode cycles 27h ffh read fast ddr latency cycles 28h ffh ddr dual i/o read mode cycles 29h ffh ddr dual i/o read latency cycles 2ah 01h read ddr quad i/o mode cycles 2bh 08h read ddr quad i/o latency cycles table 61. cfi alternate vendor-specific extended query parameter 9ah - ehplc (ddr) (continued) parameter relative byte address offset data description document number: 002-00518 rev. *d page 107 of 111 S79FL256S/s79fl512s this parameter type (param eter id f0h) may appear multiple times and have a di fferent length each time. the parameter is used t o reserve space in the id-cfi map or to force space (pad) to align a following parameter to a required boundary. 11.3 initial delivery state the device is shipped from cypress with non-volatile bits set as follows: ? the entire memory array is erased: i.e. all bits are set to 1 (each byte contains ffh). ? the otp address space has the first 16 bytes programmed to a random number. all other bytes are erased to ffh. ? the id-cfi address space contains the values as defi ned in the description of the id-cfi address space. ? the status register-1 contains 00h (all sr1 bits are cleared to 0?s). ? the configuration register-1 contains 02h. ? the autoboot register contains 00h. ? the password register contains ffffffff-ffffffffh. ? all ppb bits are 1. ? the asp register contents are shown below. table 62. cfi alternate vendor-specific extended query parameter f0h rfu parameter relative byte address offset data description 00h f0h parameter id (rfu) 01h 0fh parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h ffh rfu ... ffh rfu 10h ffh rfu table 63. asp register content ordering part number model aspr default value g0 fe7fh document number: 002-00518 rev. *d page 108 of 111 S79FL256S/s79fl512s ordering information 12. ordering informatio n S79FL256S/s79fl512s the ordering part number is formed by a valid combination of the following: notes: 1. parameter with 128-kb sectors = a parameter of 32 x 8-kb se ctors with all remaining sectors being 128 kb, with a 512b program ming buffer. 2. uniform 512-kb sectors = all sectors are uniform 512-kb with a 1024b programming buffer. s79fl 256 s ds m f v g 0 0 packing type 0 = tray 1 = tube 3 = 13? tape and reel model number (sector type) 0 = parameter 8kb with 128-kb sectors (1) 1 = uniform 512-kb sectors (2) model number (latency type, package details, reset#) g = ehplc, so footprint with reset# temperature range i = industrial (?40c to + 85c) v = industrial plus (?40c to + 105c) a = automotive, aec-q100 grade 3(?40c to + 85c) b = automotive, aec-q100 grade 2 (?40c to + 105c) package materials f = lead (pb)-free package type m = 16-pin so package speed ds = 80 mhz ddr device technology s = 65 nm mirrorbit process technology density 256 = 256 mbit 512 = 512 mbit device family s79fl cypress memory 3.0 volt-only, dual-quad se rial peripheral interface (spi) flash memory document number: 002-00518 rev. *d page 109 of 111 S79FL256S/s79fl512s valid combinations valid combinations list configurations planne d to be supported in volume for this device. consult your local sales office to co nfirm availability of specific valid combinations and to check on newly released combinations. valid combinations - au tomotive grade / aec-q100 the table below lists configurations that are automotive grade / aec-q100 qualified and are planned to be available in volume. the table will be updated as new combinations are released. consult your local sales representative to confirm availability of spec ific combinations and to check on newly released combinations. production part approval process (ppap) suppor t is only provided for aec-q100 grade products. products to be used in end-use applications that requir e iso/ts-16949 compliance must be aec-q100 grade products in combination with ppap. non?aec-q100 grade products are no t manufactured or documented in full compliance with iso/ts-16949 requirements. aec-q100 grade products are also offered without ppap suppor t for end-use applications that do not require iso/ts-16949 compliance. valid combinations base ordering part number speed option package and temperature model number packing type package marking S79FL256S ds mfi, mfv g0 0, 1, 3 79fl256s + s + (temp) + f + (model number) s79fl512s ds mfi, mfv g0 0, 1, 3 79fl512s + s + (temp) + f + (model number) valid combinations base ordering part number speed option package and temperature model number packing type package marking S79FL256S ds mfa, mfb g0 0, 1, 3 79fl256s + s + (temp) + f + (model number) s79fl512s ds mfa, mfb g0 0, 1, 3 79fl512s + s + (temp) + f + (model number) document number: 002-00518 rev. *d page 110 of 111 S79FL256S/s79fl512s 13. revision history document history page document title: S79FL256S/s79fl512s, 256 mbit ( 32 mb)/512 mbit (64 mb), 3 v, dual-quad spi flash document number: 002-00518 rev. ecn no. orig. of change submission date description of change ** ? ansi 09/25/2014 initial release. *a 4973702 ansi 10/20/2015 updated to cypress template. *b 5353089 bwha 08/09/2016 changed status from preliminary to final. updated overview : updated other resources : added cypress flash memory roadmap . updated timing specifications : updated ac test conditions : updated capacitance characteristics : updated table 8 : changed maximum value of c in parameter from 8 pf to 14 pf. changed maximum value of c out parameter from 8 pf to 20 pf. updated address space maps : updated registers : updated configuration register-1 (cr1) : updated table 20 : updated details in all columns corresponding to bit 2. updated ordering information S79FL256S/s79fl512s : updated details corresponding to ?0? under ?model number (sector type)? and also updated the corresponding note. removed note ?ehplc = enhanced high performance latency code table?. updated to new template. completing sunset review. *c 5617675 ecao 03/10/2017 updated soic 16 physical diagram : updated so3016 to ss3016. updated ordering information S79FL256S/s79fl512s : added support for industrial, industrial plus, automotive aec-q100 grade 2 and 3 temperature range options. added ecc information. added data integr ity information. updated cypress logo and sales page. *d 5962279 aesatmp8 11/09/2017 updated logo and copyright. document number: 002-00518 rev. *d revised november 09, 2017 page 111 of 111 ? cypress semiconductor corporation, 2014-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information pr ovided in this document, includ ing any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. S79FL256S/s79fl512s sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless connectivity cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support |
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