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rev. 1.10 1 may 19, 2017 rev. 1.00 pb may 19, 2017 BC7601/bc7602 ble transparent transmission controller block diagram rfio vddrf_15 spi_cs/ur_cts spi_mosi/ur_rxd dcdc_sw vout_15 spi-ur_n wakeup dvdd_12 spi_miso/ur_txd spi_clk/ur_rts iic_sda expose pad : rfgnd xi vddif_15 iic_clk vddlo_15 int_ext pvin state ee_wp rst_n xo lna switch balun vco frequency synthesizer mixer +gain if filter & demod aci eeprom (bc7602 only) pa dc/dc converter ldo xtal osc a[2:0] sda wp scl pdn ble controller spi_int features ? 3.3v operating voltage ? integrate d high performance rf and modem for enhanced ble. ? few external components required a s well as on-chip 32 mhz crystal capacitors to reduce the bom cost. ? integrate d dc/ dc converter and ldos allowing a wide r supply range with a single power supply ? over 75db rx of gain in programmable gain steps ? integrate d spi and uart for aci interfaces ? includes sleep and power down mode s for low power consumption ? embedded patch memory to reduce system development effort and cost C bc7602 only ? package types : ? BC7601: 32-pin qfn C 4mmx4mm ? bc7602: 46-pin qfn C 6.5mmx4.5mm applications ? health care products ? smart h ome appliances ? beacon s general description the BC7601/bc7602 devices are fully-integrated, single-chip bluetooth low ener gy , ble , controller s. t he devices are specially designed to act as ble slave controllers in accordance with the bluetooth specifcation v4.1. t he devices can be controlled by any external microcontroller t hrough t he a pplication c ontroller interface , aci , which is designed to allow the devices to easily communicate with external c ircuitry . t he uart and spi interfaces are available as the aci transport layers. additionally , during intervals where there is no active ble rf connection, the devices will enter a s leep m ode thus further reducing power consumption. in general practice , the BC7601/bc7602 de vices will be required to download a patch code for full ble optimi s ation . for convenience a nd syst em c ost reduction, t he bc7602 device a lready support s an internal patch code and so does not need to patch from the external microcontroller.
rev. 1.10 2 may 19, 2017 BC7601/bc7602 p in assignment rfio vddrf_15 spi_cs/ur_cts spi_mosi/ur_rxd nc dcdc _sw vout _15 spi- ur _n wakeup nc dvdd _12 spi_miso/ur_txd nc pdn ee _wp spi_clk/ur_rts iic _ sda rfgnd xi dft vddif_15 nc iic_clk rfgnd vddlo_15 int_ ext pvin spi_ int state rst_n dc _test x o BC7601 32 qfn-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 252627 2829 30 3132 rfgnd bc7602 46 qfn-a 1 2 3 4 5 6 7 8 9 10111213 1415 16171819 202122 343536373839 23 24 25 26 27 28 29 30 31 32 33 40414243444546 rfio vddrf_15 spi_cs/ur_cts spi_mosi/ur_rxd a0 dcdc _sw vout _15 wakeup nc dvdd _12 spi_miso/ur_txd nc pdn spi_clk/ur_rts iic _sda rfgnd xi vdd vddif_15 iic_clk rfgnd vddlo_15 int_ext vss spi_int state rst_n dc_test xo spi- ur _n nc nc nc nc nc nc a1 a2 ee_wp vddrf_15 nc sda wp scl nc pvin rfgnd
rev. 1.10 3 may 19, 2017 BC7601/bc7602 pin description BC7601 name no t ype description dft 1 di for normal operation connect to rfgnd. spi_cs/ur_cts 2 di spi cs or uart cts; selected by spi-ur_n during the power-on period spi_clk/ur_rts 3 di spi clk or uart rts; selected by spi-ur_n during the power-on period spi_mosi/ur_rxd 4 di spi mosi or uart rxd; selected by spi-ur_n during the power-on period spi_miso/ur_txd 5 do spi miso or uart txd; selected by spi-ur_n during the power-on period nc 6 no connection C connect to rfgnd pdn 7 di power down control pin when low the device e nters the power down mode pvin 8 p power-supply; 2.2v~3.6v nc 9 no connection C connect to rfgnd dcdc_sw 10 p switching output C connect to the switching end of the inductor vout_15 11 p 1.5v power output spi_int 12 do spi interrupt request when spi mode is selected spi-ur_n 13 di spi/uart mode select pin during the power-on period 1: spi pins selected 0: uart pins selected wakeup 14 di wake-up pin enters the sleep mode when low int_ext 15 do external interrupt state 16 do ic state pin indicator 1: operating mode 0: sleep mode rst_n 17 di hardware reset, active low nc 18 no connection C connect to rfgnd iic_clk 19 dio connect to external host or eeprom scl pin. iic_clk pin is baud rate selection when uart mode is selected. where 0: 9600bps, 1: 115200bps. rfgnd 20 p rf power ground vddif_15 21 p analog power for if section C connect to vout_15 vddrf_15 22 p analog power for rf section C connect to vout_15 rfio 23 aio rf input or output rfgnd 24 p rf power ground dc_test 25 ao rf function test pin vddlo_15 26 p analog power for rf section, connect to vout_15 xi 27 ai crystal oscillator input xo 28 ao crystal oscillator output dvdd_12 29 p 1.2v internal digital power C connect 0.1f capacitor to rfgnd nc 30 no connection C connect to rfgnd iic_sda 31 dio connect to external host or eeprom sda pin ee_wp 32 do connect to external host or eeprom wp pin rfgnd ep p exposed pad on package lower side . internally connected to rfgnd. solder this exposed pad to a pcb pad that uses multiple ground vias to provide heat transfer out of the device into the pcb ground planes. these multiple ground vias are also required to achieve the noted rf performance. legend : ai=analog input; ao=analog output; aio=analog in/out ; di=digital input; do=digital output; di o =digital in /out ; p=power
rev. 1.10 4 may 19, 2017 BC7601/bc7602 bc7602 name pin t ype description vdd 1 p eeprom power supply; 1.8v~3.6v nc 2 no connection C connect to rfgnd nc 3 no connection C connect to rfgnd nc 4 no connection C connect to rfgnd nc 5 no connection C connect to rfgnd a0 6 di eeprom address a0 input a1 7 di eeprom address a1 input a2 8 di eeprom address a2 input vss 9 p eeprom digital ground - connect to rfgnd nc 10 no connection - connect to rfgnd pdn 11 di power down control pin when low the device enters the power down mode spi_int 12 do spi interrupt request when spi mode is selected spi_miso/ur_txd 13 do spi miso or uart txd; selected by spi-ur_n during the power-on period spi_mosi/ur_rxd 14 di spi mosi or uart rxd; selected by spi-ur_n during the power-on period spi_clk/ur_rts 15 di spi clk or uart rts; selected by spi-ur_n during the power-on period spi_cs/ur_cts 16 di spi cs or uart cts; selected by spi-ur_n during the power-on period nc 17 no connection C connect to rfgnd nc 18 no connection C connect to rfgnd rfgnd 19 p rf power ground vddif_15 20 p analog power for if section C connect to vout_15 vddrf_15 21 p analog power for rf section C connect to vout_15 rfio 22 aio rf input or output rfgnd 23 p rf power ground vddrf_15 24 p analog power for rf section C connect to vout_15 dc_test 25 ao rf function test pin vddlo_15 26 p analog power for rf section C connect to vout_15 xi 27 ai crystal oscillator input xo 28 ao crystal oscillator output dvdd_12 29 p 1.2v internal digital power C connect 0.1f capacitor to rfgnd iic_sda 30 dio externally connected to sda pin ee_wp 31 dio externally connected to wp pin iic_clk 32 do externally connected to scl pin rst_n 33 di hardware reset input, active low state 34 do ic state pin indicator 1: operating mode 0: sleep mode int_ext 35 do external interrupt wakeup 36 di wake-up pin enters the sleep mode when low spi-ur_n 37 di s pi/uart mode select pin during the power-on period 1: spi pins selected 0: uart pins selected nc 38 no connection C connect to rfgnd pvin 39 p power-supply; 2.2v~3.6v dcdc_sw 40 p switching output - connect to the switching end of the inductor vout_15 41 p 1.5v power output nc 42 no connection C connect to rfgnd sda 43 dio eeprom sda
rev. 1.10 5 may 19, 2017 BC7601/bc7602 name pin t ype description scl 44 di eeprom scl nc 45 no connection C connect to rfgnd wp 46 di eeprom wp rfgnd ep p exposed pad on the lower side of the package. internally connected to rfgnd. solder this exposed pad to a pcb pad that uses multiple ground vias to provide heat transfer out of the device into the pcb ground planes. these multiple ground vias are also required to achieve the noted rf performance. legend : ai=analog input; ao=analog output; aio=analog in/out ; di=digital input; do=digital output; di o =digital in /out ; p=power absolute maximum ratings supply v oltage ........................... v in -0.3v to v in +4.3v input v oltage .............................. v in -0.3v to v in +0.3v storage t emperature .......................... -50c to 125c operating t emperature ............................ 0c to 70c note: these are stress ratings only. stresses exceeding the range specifed under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics symbol parameter test conditions min. typ. max. unit v in power supply voltage ( * ) 2.2 ( * ) 3.3 3.6 v digital inputs v ih high level input voltage 0.7 v in v v il low level input voltage 0.2 v in v i ih high level input current 10 a i il low level input current 10 a c i input capacitance 5 pf digital outputs v oh high level output voltage i oh = 1ma v in -0.5 v v ol low level output voltage i ol = 1ma 0.5 v i oz high impedance output current 1 a supply current (ta=25 c, v in =3.3v, unless otherwise specifed) i rx rx mode 14.5 ma i tx tx mode, 0 dbm output power 9 ma i sleep idle mode when mcu sleep 13 20 ua i act idle mode when mcu active 2 ma i pdn power down 280 360 na note: if the bc760x device is operating under the condition where v in <2.2v, the ld o mode must be s elected. however this will consume more power.
rev. 1.10 6 may 19, 2017 BC7601/bc7602 a.c. characteristics symbol parameter min. typ. max. unit crystal oscillator f frequency 32 mhz frequency accuracy requirement -40 40 ppm esr equivalent series resistance 100 c0 crystal shunt capacitance 1.5 7 pf cl crystal load capacitance 8 12 16 pf rx characteristics p sens sensitivity -90 dbm sensitivity (dirty on) -88 dbm p in maximum input power -5 dbm ci0 in-band blocking co-channel interference 12 db ci1 interferer at f offs = +/- 1mhz -2/4 db ci2 interferer at f offs = +/- 2mhz -25/-35 db ci3 interferer at f offs = +/- 3mhz -40/-40 db ci4 interferer at f image -35 db ci5 interferer at f image +/- 1mhz 4/-38 db out-of-band blocking f = 30~2000mhz -20 dbm f = 2000~2399mhz -25 dbm f = 2484~3000mhz -25 dbm f = 3000~12750mhz -30 dbm intermodulation performance for desired signal at -64dbm and 1 mbps ble, 3rd, 4th and 5th offset channel -40 dbm tx characteristic p tx output power -18 +3 dbm tx rf output steps 6 db f2avg average frequency deviation for 10101010 pattern 230 khz f1avg average frequency deviation for 11110000 pattern 260 khz eo eye opening = f2avg/f1avg 0.88 frequency accuracy -50 +50 khz maximum frequency drift 30 khz initial frequency drift 10 khz fdr drift rate 0.2 khz/50us spurious emissions frequency < 2.4ghz -50 dbm frequency in 2.4-12 ghz -40 dbm in-band emissions < f 2mhz ( f=2400~2483.5mhz, p tx =0dbm ) -51 dbm > f 3mhz ( f=2400~2483.5mhz, p tx =0dbm ) -55 dbm
rev. 1.10 7 may 19, 2017 BC7601/bc7602 function al description introduction the se devices a re fu lly-integrated, si ngle-chip bluetooth low ener gy , ble, controller s. t he devices are specially designed to act as ble slave devices in accordance with the b luetooth sp ecification v 4.1. t he d evices can be controlled by any external microcontroller through the a pplication c ontroller i nterface , aci, which is specially de signed to allow easy communication with external circuit ry. t he uart and s pi interfaces are available as the aci transport layers. additionally, during any time intervals where there is no active ble rf connection, the devices will enter the s leep m ode which c an further r educe t he p ower c onsumption. as the complexity of ble rf controller s does not permit comprehensive rf operation information to be provided i n t his da tasheet, t he re ader shoul d t herefore refer to the corresponding user manual s for a detailed understanding of the ble rf . controller interface application controller interface the bc760x device includes an application control - ler int erface which supports two dif ferent transport layers selected according to the logic level of the state and spi-ur_n pins during power-on. ? state/spi-ur_n with pull-high resistor C select s the spi interface ? state/spi-ur_n with pull-down resistor C select s the uart interface for the spi interf ace , the w rite fifo command must be sent first for each cmd from the host to the de - vices while the read fifo command must be sent frst for e ach re turn op eration. for t he uar t i nterface the write fifo and read fifo commands are not required . d ata follows the little-endian format whose c ommands are shown in figure 1. packet type payload ctrl cmd 0x25 8 bit s ctrlcode 8 bit s ctrldatalength 8 bit s ctrldatalength *8 bit s read ctrl info cmd 0x20 8 bit s ctrlcode 8 bit s ctrl i nfo return 0x21 8 bit s ctrlcode 8 bit s datalength 8 bit datalength *8 bit s data packet cmd 0x22 8 bit s datalength 8 bit s datalength *8 bit s return packet 0x26 8bit ctrlcode 8 bit s datareturn 8 bit s write phy cmd 0x55 8 bit s datalength 8bit(<62) reserved 16bit address 32bit datalength *32bit read phy cmd 0x56 8 bit s datalength 8 bit s (<62) address 32 bit s read phy return 0x57 8 bit s datalength 8 bit s reserved 16 bit address 32 bit s datalength *32 bit s figure 1. BC7601/bc7602 aci protocol
rev. 1.10 8 may 19, 2017 BC7601/bc7602 spi interface the bc760x d evices i nclude a 5-wire, 8-bit, m sb-frst, motorola-compatible w ith cpol=0 a nd c pha=0 s lave spi interface. the s lave spi interface has the following characteristics. ? spi clock s peed up t o 1 0 m hz ? supports mode 0 o nly ? integrated 32 byte rx/tx fifos for continuous spi bursts. pin name in/out spi description spi_clk in spi clock spi_mosi in spi master output slave input spi_miso out spi master input slave output spi_cs in spi cs, active low. spi_int out spi interrupt request note: the spi-ur_n pin is pulled high during power-on period. table 1 . spi pin function ? protocol and timing the spi timing diagram is shown in figure 2. spi_clk cpol=0 spi_mosi spi_miso spi_cs msb 6 5 4 3 2 1 lsb msb 6 5 4 3 2 1 lsb figure 2. spi t iming diagram ? spi command format and timing the spi registers can be accessed by both the host and controller for reading or to confgur e the device registers spi register name spi register address parameter value description threshold 0x0 bit[11:6]: spi tx fifo threshold bit[5:0]: spi rx fifo threshold int_status 0x01 interrupt status: bit[4]: spi rx fifo not empty elw>63,5;),)2rhurz bit[2]: spi rx fifo over threshold bit[1]: spi rx fifo empty bit[0]: spi rx fifo under threshold int_en 0x02 interrupt enable control: bit[4]: spi rx fifo not empty interrupt elw>63,5;),)2rhurzlwhuuxsw bit[2]: spi rx fifo over threshold interrupt bit[1]: spi rx fifo empty interrupt bit[0]: spi rx fifo under threshold interrupt * set 1 to enable the corresponding interrupt int_clr 0x03 interrupt clear control, write only bit[4]: spi rx fifo not empty status clear elw>63,5;),)2rhurzvwdwxvfohdu bit[2]: spi rx fifo over threshold status clear bit[1]: spi rx fifo empty status clear bit[0]: spi rx fifo under threshold status clear * set 1 to clear the corresponding status bit irrxw 0x04 bit [11:6]: spi rx fifo count bit [5:0]: spi tx fifo count table 2. spi interface register description
rev. 1.10 9 may 19, 2017 BC7601/bc7602 spi cmd format cmd name bit [7:5] bit[4:0] read register 000b bit [4:1] = spi register address, bit[0] =1 write register 001b bit [4:1] = spi register address, bit[0] =1 read fifo 011b bit [4:0] = n, n means n bytes where n=0 means 32bytes. write fifo 101b bit [4:0] = n, n means n bytes where n=0 means 32bytes. table 3 . spi register and fifo operation list d7 d6 d5 d4 d3 d2 d1 d0 spi_cs spi_clk spi_mosi d7 d6 d5 d4 d3 d2 d1 d0 spi_miso d7 d6 d5 d4 d3 d2 d1 d0 read reg cmd reg value high 8 bits reg value low 8 bits figure 3. read spi register operation d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 d7 write reg cmd reg value high 8 bits reg value low 8 bits spi_cs spi_clk spi_mosi spi_miso figure 4. write spi register operation d7 d6 d5 d4 d3 d2 d1 d0 spi_cs spi_clk spi_mosi d7 d6 d5 d4 d3 d2 d1 d0 spi_miso d7 d6 d5 d4 d3 d2 d1 d0 read fifo cmd fifo data 0 fifo data n figure 5. read spi fifo operation spi_cs spi_clk spi_miso fifo data 0 fifo data n d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 d7 write fifo cmd spi_mosi figure 6. write fifo operation
rev. 1.10 10 may 19, 2017 BC7601/bc7602 uart interface the uar t interface support s h ardware fo w c ontrol signals, rts and cts, with the following features. ? 16 byte t ransmit and receive fifos ? hardware fow control support (cts/rts) ? 8 data bits per character ? programmable serial data baud rate from 2400 to 256000 ? connect cts to vss when fow control is not used pin name in/out uart description uart_rts out uart required to send uart_rxd in uart rx data uart_txd out uart tx data uart_cts in uart clear to send note: the spi-ur_n pin is pulled low during power-on period. table 4 . uart pin function i 2 c interface the iic_sda, iic_ s cl pins can be used as the i 2 c interface when the iic_sda line is pull ed high . sleep and wake -up the w akeup pin is used to select the device operation m ode whi le t he st ate pi n i s use d t o indicate the device operation status. t he external host controller can check the device operation mode by monitoring t he st ate pi n. w hen t he w akeup pi n is pulled low , the device w ill enter the s leep mode and the st ate pin will go low . if the device is in the sleep m ode, it can be w oken up using the wakeup pin. w hen the w akeup pin is pulled high, the device will be woken up and the state pin will go high. w hen the device enters the sleep m ode, the external master spi request can also wake up the device. i f a high-to-low si gnal a ppears o n t he spi _cs p in i n t he sleep m ode, the device will be woken up and respond to the external host request. a fter the external master spi access requests have been served, the device may stay in the operating mode or enter the sleep m ode again depending upon the w akeup pin status. power down mode the pdn pin is used to power down the device . if the pdn pin is pulled low, the device will enter the power down m ode a nd a ll i nternal c locks wi ll be di sabled. a fter the device has been powered down, there is only one way to reactivate the devic e which is to reset the device by pulling the rst_n pin low and then re- initiali sing the device. external interrupt the devices provide an int_ext pin to output the interrupt signal to an external microcontroller . if the int_ext pin status is low , this means that the valid data is ready.
rev. 1.10 11 may 19, 2017 BC7601/bc7602 application circuits BC7601 32qfn expose pad rfgnd rfio vddrf_15 spi_cs/ur_cts spi_mosi/ur_rxd nc d c d c _ s w v o u t _ 1 5 s p i - u r _ n w a k e u p n c d v d d _ 1 2 spi_miso/ur_txd n c pdn e e _ w p spi_clk/ur_rts i i c _ s d a rfgnd x i dft vddif_15 nc iic_clk rfgnd v d d l o _ 1 5 i n t _ e x t 1 2 3 4 5 6 7 8 pvin s p i _ i n t s t a t e rst_n d c _ t e s t x o 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 32 3 1 3 0 2 9 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 2 0 1 9 1 8 1 7 to mcu v dd c1 0.1f 4.7f v dd15 h 2.2 c2 l1 0.1f c8 v dd15 0.1f bead c4 l3 3.3pf antenna c6 ant1 2.4pf 4.7nh c5 l4 0.1f bead c7 l5 32mhz x1 v dd15 0.1f bead c3 l2 v dd15
rev. 1.10 12 may 19, 2017 BC7601/bc7602 v dd15 v dd v dd15 v dd15 v dd15 bc7602 46qfn expose pad a0 d c d c _ s w v o u t _ 1 5 w a k e u p nc d v d d _ 1 2 ii c _ s d a x i vdd iic_clk vddlo_15 i n t _ e x t 1 2 3 4 5 6 7 8 vss s t a t e rst_n dc_test x o rfgnd 9 s p i - u r _ n nc nc nc nc a1 a2 ee_wp vddrf_15 nc sda wp scl nc pvin rfio vddrf_15 spi_cs/ur_cts spi_mosi/ur_rxd spi_miso/ur_txd n c pdn spi_clk/ur_rts rfgnd vddif_15 rfgnd s p i _ i n t n c n c 17 1 0 1 1 1 2 1 3 1 4 1 5 1 6 21 1 8 1 9 2 0 2 2 2 3 46 4 5 4 4 4 3 4 2 4 1 4 0 39 3 8 3 7 3 6 3 5 3 4 3 3 31 3 0 2 9 2 8 2 7 2 6 2 5 2 4 3 2 to mcu 0.1f 32mhz 0.1f bead 0.1f bead 3.3pf antenna 2.4pf 4.7nh 4.7f 0.1f 0.1f h 2.2 c1 c2 c3 c5 c6 c7 c8 c9 l1 l3 l4 l5 x1 ant1 4.7k 4.7k r1 r2 0.1f bead c4 l2 pdn v dd note: all decoupling capacitors should be located as close as possible to the device pins.
rev. 1.10 13 may 19, 2017 BC7601/bc7602 package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/ carton information . additional supplementary information with regard to packaging is liste d below . click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product t ape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.10 14 may 19, 2017 BC7601/bc7602 saw type 32-pin (4mm4mm) qfn outline dimensions symbol dimensions in inch min. nom. max. a 0.028 0.030 0.031 a1 0.000 0.001 0.002 a3 0.008 bsc b 0.006 0.008 0.010 d 0.157 bsc e 0.157 bsc e 0.016 bsc d2 0.104 0.106 0.108 e2 0.104 0.106 0.108 l 0.014 0.016 0.018 k 0.008 symbol dimensions in mm min. nom. max. a 0.700 0.750 0.800 a1 0.000 0.020 0.050 a3 0.203 bsc b 0.150 0.200 0.250 d 4.000 bsc e 4.000 bsc e 0.40 bsc d2 2.65 2.70 2.75 e2 2.65 2.70 2.75 l 0.35 0.40 0.45 k 0.20
rev. 1.10 15 may 19, 2017 BC7601/bc7602 saw type 46-pin (6.5mm4.5mm) qfn outline dimensions symbol dimensions in inch min. nom. max. a 0.031 0.033 0.035 a1 0.000 0.001 0.002 a3 0.008 bsc b 0.006 0.008 0.010 d 0.254 0.256 0.258 e 0.175 0.177 0.179 e 0.016 bsc d2 0.197 0.201 0.205 e2 0.118 0.122 0.126 l 0.012 0.016 0.020 k symbol dimensions in mm min. nom. max. a 0.800 0.850 0.900 a1 0.000 0.020 0.040 a3 0.200 bsc b 0.150 0.200 0.250 d 6.450 6.500 6.550 e 4.450 4.500 4.550 e 0.40 bsc d2 5.00 5.10 5.20 e2 3.00 3.10 3.20 l 0.30 0.40 0.50 k
rev. 1.10 16 may 19, 2017 BC7601/bc7602 copyright ? 2017 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com/en/.

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