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| copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. 20w stereo digital class-d audio power amplifier with eq and drc apa3175 the apa3175 is a digital input, stereo, high efficiency, class-d audio amplifier available in a tqfp7x7-48p package. the apa3175 accepts the digital serial audio data and using the digital audio processor to convert the audio data becomes the stereo class-d output speaker amplifier. this provides the seamless integration between the codec and the speaker amplifier. the apa3175 is a slave device receiving clocks from ex- ternal source, and the class-d s pwm switching fre- quency is 352.8khz for the sampling rate 44.1khz or 384 khz for sampling 48khz, depend on the input signal s sampling rate. operating voltage: 4.5v~24v for pvdd C 3.0v~3.6v for dvdd and avdd high efficiency class-d operation eliminate the need of heatsinks digital serial audio input (stereo output) i 2 c control interface sampling rate can support from 32khz to 192khz separated volume control from 24db to mute soft mute (50% duty cycle) programmable dynamic range compression C power limiter C speaker protection C night-mode listening programmable biquads for speaker eq shutdown and mute function thermal and over-current protections with auto- recovery space saving package tqfp7x7-48p lead free and green devices available (rohs compliant) features general description applications lcd tv pin configuration simplified application circuit a v d d 1 3 / e r r o r 1 4 m c l k 1 5 t p 1 1 6 t p 2 1 7 1 v 8 _ d v 1 8 l r c k 2 0 s c l k 2 1 s d i n 2 2 s d a 2 3 s c l 2 4 abs 4 avss 9 tm 8 pll_lf 10 nc 11 gdreg 5 nc 6 pvdd_a 2 pvdd_a 3 nc 7 nc 12 out_a 1 33 dbs 28 dvss 35 pvdd_d 32 gdreg 27 dvdd 34 pvdd_d 36 out_d 25 /rst 31 dvreg 30 agnd 26 tp3 29 gnd top view (apa3175) 4 8 p g n d _ a b 4 7 p g n d _ a b 4 6 o u t _ b 4 5 p v d d _ b 4 4 p v d d _ b 4 3 b b s 4 2 c b s 4 1 p v d d _ c 4 0 p v d d _ c 3 9 o u t _ c 3 8 p g n d _ c d 3 7 p g n d _ c d s d 1 9 apa3175 left channel speaker right channel speaker out_a out_c out_b out_d digital audio source i 2 c control sda scl mclk lrclk sclk sdin
copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 2 apa3175 symbol parameter rating unit supply voltage (pvdd_x to pgnd_xx) -0.3 to 26 supply voltage (dvdd to dvss) -0.3 to 3.6 supply voltage (avdd to avss) -0.3 to 3.6 input voltage (mclk to avss) -0.5 to avdd+2.5 input voltage (sd, rst, lrclk, sclk, sdin, sda, scl to dvss) -0.5 to dvdd+2.5 input voltage (out_x to pgnd_xx) -0.3 to +26 input voltage (xbs to pgnd_xx) -0.3 to +31 input voltage (avss, dvss, agnd to pgnd_xx) -0.3 to +0.3 v t j maximum junction temperature 150 o c t stg storage temperature range -65 to +150 o c t sdr soldering temperature range, 10 seconds 260 o c p d power dissipation internally limited w ordering and marking information absolute maximum ratings (note 1) note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note : anpec lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with rohs. anpec lead-free products meet or exceed the lead-free requirements of ipc/jedec j-std-020d for msl classification at lead-free peak reflow temperature. anpec defines green to mean lead-free (rohs compliant) and halogen free (br or cl does not exceed 900ppm by weight in homogeneous material and total of br and cl does not exceed 1500ppm by weight). symbol parameter typical value unit q ja junction-to-ambient resistance in free air (note 2) tqfp7x7-48p 25 c/w q jc thermal resistance junction-to-case (note 3) tqfp7x7-48p 3 c/w thermal characteristics note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. the exposed pad of tqfp7x7-48p is soldered directly on the pcb. note 3: the case temperature is measured at the center of the exposed pad on the underside of the tqfp7x7-48p package. handling code temperature range package code package code qca : tqfp7x7-48p operating ambient temperature range i : -40 to 85 o c handling code tr : tape & reel assembly material g : halogen and lead free device apa3175 qca : apa3175 xxxxx xxxxx - date code assembly material apa3175 copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 3 apa3175 range symbol parameter min. max. unit v dd supply voltage 3 3.6 pv dd full bridge stage supply voltage (pvdd_x) 4.5 24 v ih high level threshold voltage sd, mclk, lrclk, sclk, sdin, sda, scl, rst 2 5 v il low level threshold voltage sd, mclk, lrclk, sclk, sdin, sda, scl, rst 0 1 v t a ambient temperature range -40 85 t j junction temperature range -40 125 o c pvdd>15v 4.8 - r l speaker resistance pvdd< 15v 3.2 - w l o output low pass filter inductance 10 - m h recommended operating conditions pwm operating conditions pll input parameters and external filter components apa3175 symbol parameter test conditions min. typ. max. unit f mclk mclk frequency 2.8224 - 24.576 mhz mclk duty cycle 40 50 60 % tr/tf (mclk) rise/fall time for mclk - - 5 ns lrclk allowable drift before lrclk reset - - 4 mclks external pll filter capacitor c1 smd 0603 y5v - 47 - external pll filter capacitor c2 smd 0603 y5v - 4.7 - nf external pll filter resistor r - 470 - w electrical characteristics t a =25 o c, pv dd =18v, v dd =3.3v (avdd and dvdd), r l =8 w , bd mode, f s =48khz (unless otherwise noted) apa3175 symbol parameter test conditions min. typ. max. unit dc characteristics normal mode (no load) - 10 20 i dd 3.3v supply current (avdd, dvdd) reset (no load) - 7.2 14.5 normal mode (no load) - 18 36 i pvdd full bridge stage supply curren t (pvdd_x) reset (no load) - 0.5 1 ma i il low level input current v i copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 5 apa3175 serial audio ports slave mode apa3175 symbol parameter test conditions min. typ. max. unit t setup2 setup time, sdin to sclk rising edge 10 - - t hold hold time, sdin to sclk rising edge 10 - - ns lrclk frequency 8k 48k 48k khz lrclk duty cycle 40 50 60 sclk duty cycle 40 50 60 % sclk rising edges between lrclk riding edges 32 - 64 sclk edges t (edge) lrclk clock edge with respect to the falling edge of sclk -1/4 - 1/4 sclk period tr/tf (sclk/lrclk) rise/fall time for sclk/lrclk - - 8 ns over recommended operating conditions (unless otherwise noted) reset timing control signal parameters over recommended operating conditions (unless otherwise noted). please refer to rec- ommended use model section on usage of all terminals. apa3175 symbol parameter test conditions min. typ. max. unit t p(rst) pulse duration, rst active. no load 100 - - m s t d(12c_ready) time to enable i 2 c - - 13.5 ms serial audio ports slave mode apa3175 symbol parameter test conditions min. typ. max. unit v n noise output voltage with a-weighting filter (a v =0db) - 150 - m v rms f sclk frequency, sclk 32xf s , 48xf s , 64xf s c l =30pf 1.024 - 12.288 mhz t setup1 setup time, lrclk to sclk rising edge 10 - - t hold1 hold time, lrclk to sclk rising edge 10 - - ns over recommended operating conditions (unless otherwise noted) electrical characteristics (cont.) t a =25 o c, pv dd =18v, v dd =3.3v (avdd and dvdd), r l =8 w , bd mode, f s =48khz (unless otherwise noted) apa3175 symbol parameter test conditions min. typ. max. unit ac characteristics s/n signal to noise ratio r l =8 w , p o =16w, with a-weighting filter (a v =0db) - 97 - db v n noise output voltage with a-weighting filter (a v =0db) - 150 - m v rms copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 6 apa3175 i 2 c serial control port operation timing characteristics for i 2 c interface signals over recommended operating conditions (unless otherwise noted) apa3175 symbol parameter test conditions min. typ. max. unit f scl frequency, scl no wait states - - 400 khz t w(h) pulse duration, scl high 0.6 - - t w(l) pulse duration, scl low 1.3 - - m s t r rise time, scl and sda - - 300 t f fall time, scl and sda - - 300 t setup1 setup time, scl to sda 100 - - t hold1 hold time, scl to sda 0 - - ns t (buf) bus free time between stop and start condition 1.3 - - t setup2 setup time, scl to start condition 0.6 - - t hold2 hold time, start condition to scl 0.6 - - t setup3 setup time, scl to stop condition 0.6 - - m s c l load capacitance for each bus line - - 400 pf copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 7 apa3175 typical operating characteristics thd+n vs. frequency frequency (hz) t h d + n ( % ) pv dd =18v r l =8 w aux-0025 aes-17(20khz) po=5w po=1w 10 0.1 1 20 20k 50 100 500 1k 2k 5k 0.01 0.001 thd+n vs. frequency frequency (hz) t h d + n ( % ) pv dd =12v r l =8 w aux-0025 aes-17(20khz) po=2.5w po=0.5w 20 20k 50 100 500 1k 2k 5k 10 0.1 1 0.01 0.001 thd+n vs. frequency pv dd =8v r l =8 w aux-0025 aes-17(20khz) po=2.5w po=1w po=0.5w t h d + n ( % ) 10 0.1 1 0.001 frequency (hz) 20 20k 50 100 500 1k 2k 5k thd+n vs. frequency t h d + n ( % ) 10 0.1 1 0.001 frequency (hz) 20 20k 50 100 500 1k 2k 5k pv dd =4.5v r l =8 w aux-0025 aes-17(20khz) po=1w po=0.1w output power (w) t h d + n ( % ) thd+n vs. output power v dd =18v r l =8 w aux-0025 aes-17(20khz) fin=20hz fin=1khz fin=10khz 0.001 0.01 0. 1 1 10 10m 50 100m 1 2 5 1020 thd+n vs. output power v dd =12v r l =8 w aux-0025 aes-17(20khz) fin=20hz fin=1khz fin=10khz t h d + n ( % ) 0.001 0.01 0.1 1 10 output power (w) 10m 50 100m 1 2 5 1020 copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 8 apa3175 typical operating characteristics thd+n vs. output power v dd =8v r l =8 w aux-0025 aes-17(20khz) fin=20hz fin=1khz fin=10khz t h d + n ( % ) 0.001 0.01 0.1 1 10 output power (w) 10m 50 100m 1 2 5 1020 thd+n vs. output power t h d + n ( % ) 0.01 0.1 1 10 0.001 output power (w) 10m 100m 1 5 v dd =4.5v r l =8 w aux-0025 aes-17(20khz) output power vs. supply voltage supply voltage(v) o u t p u t p o w e r / p e r c h a n n e l ( w ) r l =8 w duty=97.7% thd+n=10% thd+n=1% 2 4 6 8 10 12 14 16 18 20 4 5 6 11 12 1314 15 161718 0 19 20 8 9 10 7 0 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 10121416182022242628 output power / per channel (w) e f f i c i e n c y ( % ) efficiency vs. output power r l =8 w duty=97.7% pvdd=4.5v pvdd=8v pvdd=12v pvdd=18v pvdd=24v crosstalk vs. frequency c r o s s t a l k ( d b ) frequency (hz) pv dd =18v p o =0.25w r l =8 w aux-0025 10~22khz left to right right to left -120 0 -100 -80 -60 -40 -20 20 20k 50 100 200 500 1k 2k 5k frequency (hz) c r o s s t a l k ( d b ) crosstalk vs. frequency pv dd =12v p o =0.25w r l =8 w aux-0025 10~22khz left to right right to left -120 0 -100 -80 -60 -40 -20 20 20k 50 100 200 500 1k 2k 5k copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 9 apa3175 typical operating characteristics crosstalk vs. frequency c r o s s t a l k ( d b ) frequency (hz) pv dd =8v p o =0.25w r l =8 w aux-0025 10~22khz left to right right to left -120 0 -100 -80 -60 -40 -20 20 20k 50 100 200 5001k 2k 5k crosstalk vs. frequency c r o s s t a l k ( d b ) -120 0 -100 -80 -60 -40 -20 frequency (hz) 20 20k 50 100 200 500 1k 2k 5k left to right right to left pv dd =4.5v p o =0.25w r l =8 w aux-0025 10~22khz copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 10 apa3175 pin no. name i/o/p function 1 out_a o output of half bridge a. 2, 3 pvdd_a p power supply for half bridge a. 4 abs i/o high side bootstrap supply for half bridge a. 5, 32 gdreg o/p internal regulator output of gate driver. 6,7,11,12 nc - no connection. 8 tm i test mode digital input pin. 10 pll_lf o pll negative loop filter pin. 13 avdd p analog powers supply and connects to 3.3v. 14 error o when over temperature, over current over voltage and under voltage occur, this pin will be pull low; and it will be reset to high when the fault condition has be remove. 15 mclk i master clock input. 16 tp1 i/o test mode digital input/output pin. 17 tp2 i/o test mode digital input/output pin. 18 1v8_dv o/p internal regulated 1.8v for digital block s supply, not for power external device. 19 sd i active low, shutting down the noise shaper and initiating pwm stop sequence. 20 lrclk i input serial audio data left/right clock. (sample rate clock), it s weak pull down terminal. 21 sclk i serial audio data clock (shift clock). sclk is the serial audio port input data bit clock. 22 sdin i serial audio data input. 23 sda io i 2 c serial control data interface input/output. 24 scl i i 2 c serial control clock input. 25 rst i reset control, place a logic low to this pin, will reset the apa3175 to its default condition. it s weak pull-up terminal. 26 tp3 i/o test mode digital input/output pin. 27 dvdd p digital powers supply and connects to 3.3v. 28 dvss p digital power supply s ground. 29 gnd p power stage s analog ground. 30 agnd p power stage s analog ground. 31 dvreg o/p digital voltage regulator s output, only for internal used. 33 dbs i/o high side bootstrap supply for half bridge d. 34, 35 pvdd_d p power supply for half bridge d. 36 out_d o output of half bridge d. 37, 38 pgnd_cd p power ground connection for half bridge c and d. 39 out_c o output of half bridge c. 40, 41 pvdd_c p power supply for half bridge c. 42 cbs i/o high side bootstrap supply for half bridge c. 43 bbs i/o high side bootstrap supply for half bridge b. pin description copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 11 apa3175 pin no. name i/o/p function 44, 45 pvdd_b p power supply for half bridge b. 46 out_b o output of half bridge b. 47, 48 pgnd_ab p power ground connection for half bridge a and b. pin description (cont.) block diagram pgnd_a pgnd_c pgnd_b pgnd_d serial audio port inter polarization half bridge a fet output pvdd_a out_a bs_a lrclk sdin pll_lf avdd sda dvdd eq 7xbq sampling rate serial control regulator 3.3v to 1.8v fifth order noise shaper and pwm scl pll mclk sclk pvdd_b pvdd_c pvdd_d out_b out_c out_d bs_b bs_c bs_d drc & volume eq 7xbq register bank regulator 3.3v to 1.8v control logic 1v8_av 1v8_dv agnd error rst sd dgnd avcc vcmp_ab vcmp_cd bypass analog power stage avss half bridge b fet output half bridge c fet output half bridge d fet output central control copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 12 apa3175 typical application circuit 8 8 1 3 1 3 7 2 5 /reset avdd scl lrck sclk sdin apa3175 sda 0 10 f 4700pf t m a v s s p l l _ l f n c n c p v d d _ a a b s g d r e g n c n c o u t _ a p v d d _ a a v d d / e r r o r m c l k t p 1 t p 2 s c l 1 v 8 _ d v / s d l r c l k s c l k s d i n s d a 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 g n d d v s s d v d d t p 3 / r s t p v d d _ d d b s g d r e g d v r e g a g n d o u t _ d p v d d _ d p g n d _ a b p g n d _ a b o u t _ b p v d d _ b p v d d _ b p g n d _ c d b b s d b s p v d d _ c p v d d _ c o u t _ c p g n d _ c d 0.1 f 10k mclk a_sel 0.1 f 4.7 f 10k av dd /pdn dvdd 0.1 f 10 f 0.1 f 1 f 0.033 f pvdd 0.1 f 220 f 22 h 0.68 f 0.68 f 22 h 0.033 f 0.033 f 0.1 f 0.1 f pvdd 22 h 22 h 0.68 f 0.68 f pvdd 220 f 0.1 f 0.033 f 1 f 470 0.047 f copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 13 apa3175 function description clock and pll the apa3175 is a slave device and receives signals from mclk, sclk, and lrclk. the digital audio processor (dap) provides all sample rates and mclk rates which defined in the clock control register. the apa3175 checks to verify that sclk is a particular value of 32f s , 48f s , or 64f s . the dap only provides a 1 f s lrclk. the timing relationship of these clocks to sdin is shown in subsequent sections. serial data interface serial data is an input transmitted to sdin. the pwm outputs are derived from sdin. besides, the apa3175 dap receives left-justified, right-justified, and i 2 s serial data formats with 16, 20, or 24 bit. pwm section the apa3175 dap device is a high power efficiency and high-performance digital audio reproduction. a noise shaper is used to increase dynamic range and snr in the audio band. the pwm section receives 24bit pcm data from the dap and outputs two btl pwm audio output channels. the pwm section has individual channel dc blocking filters that can be enabled and disabled. the low pass filter cutoff frequency is less than 1hz. besides, the pwm section includes individual channel de-emphasis filters for 44.1 and 48 khz and can be enabled and disabled. the adjustable maximum modulation limit of pwm section is from 93.8% to 98.4%. i 2 c compatible serial control interface the apa3175 dap receives commands from a system controller through an i 2 c serial control slave interface. the serial control interface supports both normal-speed 100khz and high-speed 400khz operations without waiting states. as an added feature, even though the mclk is absent, the interface operates. for status registers, the serial control interface provides both single-byte and multi-byte read and write operations; and for the general control registers, they associated with the pwm. copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 14 apa3175 function description (cont.) figure 1. i 2 s 64 f s format figure 2. i 2 s 48 f s format 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 32 clks 32 clks lrclk (note reversed phase) left channel right channel sclk sclk msb msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 24-bit mode 20-bit mode 16-bit mode 15 14 12 11 9 8 5 4 16 clks 16clks lrclk (note reversed phase) left channel right channel sclk sclk msb lsb lsb 16-bit mode 3 2 1 0 msb 16-bit mode 13 10 15 14 12 11 9 8 5 4 3 2 1 13 10 figure 3. i 2 s 32 f s format serial interface control and timing i 2 s timing i 2 s timing uses lrclk to define the data for the left channel and the right channel when the data being transmitted. for the left channel, the lrclk is low; for the right channel, the lrclk is high. a bit clock running at 32, 48, or 64 f s is used to clock in the data. when the lrclk signal changes state, there is a delay of one bit clock from the time which the first bit of data on the data lines. the data is written msb first and is valid on the rising edge of bit clock. the dap masks unused trailing data bit positions. 23 22 17 16 9 8 5 4 19 18 13 12 5 4 15 14 9 8 24 clks 24 clks lrclk (note reversed phase) left channel right channel sclk sclk msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 1 0 1 0 3 2 1 0 23 22 17 16 9 8 5 4 19 18 13 12 5 4 15 14 9 8 msb 24-bit mode 20-bit mode 16-bit mode 1 0 1 0 3 2 1 copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 15 apa3175 function description (cont.) left-justified left-justified (lj) timing uses lrclk to define the data for the left channel and the right channel when the data being transmitted. for the left channel, the lrclk is high; for the right channel, the lrclk is low. a bit clock running at 32, 48, or 64 f s is used to clock in the data. the first bit of data appears on the data lines when lrclk toggles. the data is written msb first and is valid on the rising edge of the bit clock. the dap masks unused trailing data bit positions. figure 4. left-justified 64 f s format figure 5. left-justified 48 f s format figure 6. left-justified 32 f s format 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 32clks 32clks lrclk left channel right channel sclk sclk msb msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 24-bit mode 20-bit mode 16-bit mode 23 22 17 16 9 8 5 4 19 18 13 12 5 4 15 14 9 8 24clks 24 clks lrclk left channel right channel sclk sclk msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 1 0 1 0 3 2 1 0 23 22 17 16 9 8 5 4 19 18 13 12 5 4 15 14 9 8 msb 24-bit mode 20-bit mode 16-bit mode 1 0 1 0 3 2 1 15 14 12 11 9 8 5 4 16clks 16clks lrclk left channel right channel sclk sclk msb lsb lsb 16-bit mode 3 2 1 0 msb 16-bit mode 13 10 15 14 12 11 9 8 5 4 3 2 1 13 10 0 copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 16 apa3175 function description (cont.) right-justified right-justified (rj) timing uses lrclk to define the data for the left channel and the right channel when the data being transmitted. for the left channel, the lrclk is high; for the right channel, the lrclk low. a bit clock running at 32, 48, or 64 f s is used to clock in the data. after lrclk toggles, for 24bit data, the first bit of data appears on the data 8 bit-clock. in rj mode, the lsb of data is always clocked by the last bit clock before lrclk transitions. the data is written msb first and is valid on the rising edge of bit clock. the dap masks unused leading data bit positions. figure 7. right-justified 64 f s format figure 8. right-justified 48 f s format figure 9. right-justified 32 f s format 23 22 19 18 15 14 1 0 19 18 15 14 1 0 15 14 1 0 32 clks 32 clks lrclk left channel right channel sclk sclk msb msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 23 22 19 18 15 14 1 0 19 18 15 14 1 0 15 14 1 0 24-bit mode 20-bit mode 16-bit mode 23 22 19 18 15 14 1 0 19 18 15 14 1 0 1 0 24 clks 24 clks lrclk left channel right channel sclk sclk msb msb ls b ls b 24-bit mode 20-bit mode 16-bit mode 24-bit mode 6 5 2 6 5 2 15 14 6 5 2 23 22 19 18 15 14 1 0 19 18 15 14 1 0 1 0 20-bit mode 16-bit mode 6 5 2 6 5 2 15 14 6 5 2 15 14 12 11 9 8 5 4 16clks 16clks lrclk left channel right channel sclk sclk msb lsb lsb 16-bit mode 3 2 1 0 msb 16-bit mode 13 10 15 14 12 11 9 8 5 4 3 2 1 13 10 0 copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 17 apa3175 function description (cont.) i 2 c serial control interface the apa3175 dap has a bidirectional i 2 c interface that compatible with the i 2 c (inter ic) bus protocol. besides, it provides both 100khz and 400khz data transfer rates to single and multiple bytes write and read operations. this is a slave only device, and it doesn t support a multi-master bus environment or wait state insertion. the function of the control interface is to read device status and to program the registers of the device. the dap supports the standard-mode i 2 c bus operation (100khz maximum) and the fast i 2 c bus operation (400khz maximum). without i 2 c wait cycles, the dap performs i 2 c operations. general i 2 c operation the i 2 c bus uses sda (data) and scl (clock) to communicate between integrated circuits in a system. data is transferred on the bus serially one bit at a time. with the most significant bit (msb) transferred first, the address and data can be transferred in byte (8bit) format. in addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. the bus uses transitions on the sda when the clock is high to indicate start and stop conditions. a high-to-low transition on sda indicates a start, and a low-to-high transition indicates a stop. normal data bit transitions must occur within the low time of the clock. these conditions are shown in figure 10. the master generates the 7bit slave address and the read/write (r/w) bit to open communication with another device and then waits for an acknowledge condition. the apa3175 holds sda low during the acknowledge clock to indicate an acknowledgment. when this occurs, the master transmits the next byte of the sequence. each device is addressed by a unique 7bit slave address plus r/w bit (1 byte). all compatible devices share the same signals via a bidirectional bus using a wired-and connection. an external pull-up resistor must be used for the sda and scl signals to set the high level for the bus. figure 10. typical i 2 c sequence 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7-bit slave address r/ w a 8-bit register address (n) 8-bit register data for address (n) a a a 8-bit register data for address (n) sda scl start stop there is no limit on the number of bytes that can be transmitted between start and stop conditions. when the last word transfers, the master generates a stop condition to release the bus. a generic data transfer sequence is shown in figure 10. the 7bit address for apa3175 is 0011 010 (0x34). apa3175 address can be changed from 0x34 to 0x38 by writing 0x38 to device address register 0xf9. copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 18 apa3175 single- and multiple-byte transfers function description (cont.) the serial control interface supports single-byte and multiple-byte (r/w) operations for sub-addresses 0x00 to 0x1f. however, for the sub-addresses 0x20 to 0xff, the serial control interface supports only multiple-byte read/write operations (in multiples of 4 bytes). during multiple-byte read operations, the dap responds with data, a byte at a time, starting at the sub-address assigned, as long as the master device continues to respond with acknowledges. if a particular sub-address does not contain 32 bits, the unused bits are read as logic 0. during multiple-byte write operations, the dap compares the number of bytes transmitted to the number of bytes that are required for each specific sub-address. supplying a sub-address for each sub-address transaction is referred to as random i 2 c addressing. the apa3175 also supports sequential i 2 c addressing. for write transactions, if a sub-address is issued and followed by data for that sub-address and the 15 sub-addresses that follow, a sequential i 2 c write transaction has taken place, and the data for all 16 sub-addresses is successfully received by the apa3175. for i 2 c sequential write transactions, the sub- address then serves as the start address, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many sub-addresses are written. as was true for random addressing, sequential addressing requires that a complete set of data be transmitted. if only a partial set of data is written to the last sub- address, the data for the last sub-address is discarded. however, if all other data written is accepted, only the incomplete data is discarded. single-byte write as shown in figure 11, a single-byte data write transfer begins with the master device transmitting a start condition followed by the i 2 c device address and the r/w bit. the r/w bit determines the direction of the data transfer. for a write data transfer, the r/w bit will be a 0. after receiving the correct i 2 c device address and the r/w bit, the dap responds with an acknowledge bit. and then, the master transmits the address byte or bytes corresponding to the apa3175 internal memory address being accessed. after receiving the address byte, the apa3175 responds with an acknowl- edge bit again. next, the master device transmits the data byte to be written to the memory address being accessed. after receiving the data byte, the apa3175 again responds with an acknowledge bit. finally, the master device trans- mits a stop condition to complete the single-byte data write transfer. a6 a5 a4 a3 a2 a1 a0 ack r/w a6 a5 a4 a3 a2 a1 a0 ack a7 d6 d5 d4 d3 d2 d1 d0 ack d7 start condition stop condition i 2 c device address and read/ write bit sub-address data byte acknowledge acknowledge acknowledge figure 11. single-byte write transfer copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 19 apa3175 function description (cont.) multiple-byte write a multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the dap as shown in figure 12. after receiving each data byte, the apa3175 responds with an acknowledge bit. a6 a5 a1 a0 ack r/w a6 a2 a1 a0 ack a7 d0 ack d7 start condition stop condition i 2 c device address and read/ write bit sub-address first data byte acknowledge acknowledge acknowledge d0 ack acknowledge d7 acknowledge d0 ack d7 last data byte other data bytes figure 12. multiple-byte write transfer single-byte read as shown in figure 13, a single-byte data read transfer begins with the master device transmitting a start condition followed by the i 2 c device address and the r/w bit. for the data read transfer, both a write followed by a read are actually done. initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. as a result, the r/w bit becomes a 0. after receiving the apa3175 address and the read/write bit, apa3175 responds with an acknowledge bit. besides, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the apa3175 address and the read/write bit again. this time the read/ write bit becomes a 1, indicating a read transfer. after receiving the address and the read/write bit, the apa3175 again responds with an acknowledge bit. and then, the apa3175 transmits the data byte from the memory address being read. after receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer. figure 13. single-byte read transfer multiple-byte read a multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the apa3175 to the master device as shown in figure 14. except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. figure 14. multiple-byte read transfer a6 a0 ack r/w a6 a1 a0 ack a7 start condition i 2 c device address and read/ write bit sub- address acknowledge acknowledge a6 a0 r/w i 2 c device address and read/ write bit ack acknowledge repeat start condition d0 ack d7 stop condition first data byte acknowledge d0 ack not acknowledge d7 acknowledge d0 ack d7 last data byte other data bytes a6 a5 a1 a0 ack r/w a6 a1 a0 ack a7 start condition stop condition i 2 c device address and read/ write bit sub-address acknowledge acknowledge a6 a5 a1 a0 r/w i 2 c device address and read/ write bit ack d6 d1 d0 ack d7 data byte acknowledge not acknowledge repeat start condition copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 20 apa3175 function description (cont.) dynamic range control (drc) the drc scheme has a single threshold, offset, and slope (all programmable). there is one ganged drc for the left/ right channels. the drc input/output diagram is shown in figure 15. figure 15. dynamic range control biquad structure all biquads use a 2nd order iir filter structure as shown below. each biquad has 3 coefficients on the direct path (b0, b1, b2) and 2 coefficients on feedback path (a1 and a2) which is shown in the diagram. s z -1 z -1 z -1 z -1 magnitude trunction x(n) y(n) b 0 b 1 b 2 a 1 a 2 figure 17. biquad filter time limit level limit level v i n time v o u t gain release time attack time a b c d e f limit level limit level figure 16. drc structure copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 21 apa3175 function description (cont.) 26bit 3.23 number format all mixer gain coefficients are 26 bit coefficients and use a 3.23 number format. numbers formatted as 3.23 numbers means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point. this is shown in figure 18. figure 18. 3.23 format the decimal value of a 3.23 format number can be found by following the weighting and is shown in figure 18. if the msb is logic 0, the number is a positive number, and the weighting shown yields the correct number. if the msb is a logic 1, and then the number is a negative number. in this case, every bit must be inverted, a 1 added to the result, and then the weighting shown in figure 19 applied to obtain the magnitude of the negative number. figure 19. conversion weighting facroes 3.23 format to floating point gain coefficients, entered via the i 2 c bus, must be entered as 32 bit binary numbers. the format of the 32 bit number (4 byte or 8 digit hexadecimal number) is shown in figure 20. figure 20. alignment of 3.23 coefficient in 32bit i 2 c word 2 -23 bit 2 0 bit 2 1 bit 2 -1 bit 2 -4 bit (1 or 0) x2 1 + (1 or 0) x2 0 + (1 or 0) x2 -1 + (1 or 0) x2 -4 + (1 or 0) x2 -23 s_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx 2 -23 bit 2 -5 bit 2 -1 bit 2 0 bit 2 1 bit sign bit u u u u u u s x x x x x x x x x x x x x x x x x x x x x x x x 0 fraction digit 6 fraction digit 5 fraction digit 4 fraction digit 2 fraction digit 3 fraction digit 1 integer digit 1 sign bit coefficient digit 8 coefficient digit 7 coefficient digit 6 coefficient digit 5 coefficient digit 4 coefficient digit 3 coefficient digit 2 coefficient digit 1 x copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 22 apa3175 function description (cont.) sample calculation for 3.23 format db linear decimal hex (3.23 format) 0 1 8388608 00800000 5 1.7782794 14917288 00e39ea8 -5 0.5623413 4717260 0047facc x l = 10 (x/20) d = 8388608 l h = dec2hex (d, 8) sample calculation for 9.17 format db linear decimal hex (9.17 format) 0 1 131072 00020000 5 1.7782794 233082.6 00038e7a -5 0.5623413 73707.2 00011feb x l = 10 (x/20) d = 131072 l h = dec2hex (d, 8) recommended use model figure 21. recommended command sequence avdd/dvdd sd mclk lrclk sclk sdin i 2 s scl sda i 2 c rst pvdd/avcc trim dap config other config exit sd volume and mute commands clock errors and rate changes ok enter sd stable and valid clocks stable and valid clocks 3v t entersd t autodetect t por t por t exitsd t vdd-pvccl 10v 7.5v 10v 7.5v t rl-pvcch t pvccl-vddh t vddh-dl 3v reconfigure dap after shutdown reconfigure dap after shutdown normal operation shutdown power down t dl-vddh t rl-dv intialization t rh-i2c t dv-rh t pvcch-i2c t autodetect copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 23 apa3175 recommended use model (cont.) function description (cont.) apa3175 parameter description min. typ. max. unit t vddh-dl time digital inputs must remain low after avdd/dvdd goes above 3v 0 - - t dl-vddh time digital inputs must be low before avdd/dvdd goes below 3v 0 - - t vddh-pvddl time pvdd/avcc remains below 7.5v after avdd/dvdd goes above 3v 100 - - t pvddl-vddh time pvdd/avcc must be below 7.5v before avdd/dvdd goes below 3v 0 - - t pvddh-i2c time pvdd/avcc must be above 10v before i 2 c commands may address device 10 - - t rl-pvddh time pvdd/avcc must remain above 10v after rst goes low 2 - - m s t rh-i2c time reset must be high before i 2 c commands may address device 13.5 - - ms t dv-rh time digital inputs must be valid (driven as recommended) before rst goes high 100 - - t rl-dv time digital inputs must remain valid (driven as recommended) after rst goes low 2 - - m s t autodetect auto-detect completion wait time (given stable and valid clocks) before issuing further commands 50 - - t exitsd exit shutdown wait time bef ore issuing further commands to device (t start given by register 0x1a) 1+1.3 x t start - - t entersd enter shutdown wait time before issuing further commands to device (t stop given by register 0x1a) 1+1.3 x t stop - - t por power-on-reset wait time after 1st trim following avdd/dvdd power-up (t start given by register 0x1a) (does not apply to trim commands following subsequent resets) 240 + 1.3 x t start - - ms figure 22. power loss sequence 3v 10v 7.5v t rl-pvcch t pvccl-vddh avdd/dvdd sd mclk lrclk sclk sdin i 2 s scl sda i 2 c rst pvdd/avcc t pl-hl t dl-vddh sudden power loss (bd) copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 24 apa3175 function description (cont.) apa3175 parameter description min. typ. max. unit t rl-dv time digital inputs must remain valid (driven as recommended) after rst goes low 2 - - t dl-vddh time digital inputs must be low before avdd/dvdd goes below 3v 0 - - t rl-pvddh time pvdd/avcc must remain above 10v after rst goes low 2 - - t pvddl-vddh time pvdd/avcc must be below 7.5v before avdd/dvdd goes below 3v 0 - - m s recommended use model (cont.) recommended command sequences the dap has two groups of commands. one set is for configuration and is intended for use only during initialization. the other set has built-in click and pop protection and may be used during normal operation while audio is streaming. the following supported command sequences illustrate how to initialize, operate, and shutdown the device. initialization sequence use the following sequence to power-up and initialize the device: 1. hold all digital inputs low and ramp up avdd/dvdd to at least 3v. 2. initialize digital inputs and pvdd supply as follows: ? drive rst=0, sd=1, and other digital inputs to their desired state while ensuring that all are never more than 2.5v above avdd/dvdd. provide stable and valid i 2 s clocks (mclk, lrclk, and sclk). wait at least 100 m s, drive rst=1, and wait at least another 13.5ms. ? ramp up pvdd to at least 4.5v while ensuring that it remains below 3.5v for at least 100 m s after avdd/dvdd reaches 3v. then wait at least another 10 m s. 3. configure the dap via i 2 c (see users s guide for typical values): biquads (0x29-36)drc parameters (0x3a-3c, 0x40-42, and 0x46) bank select (0x50). 4. configure remaining registers. 5. exit shutdown (sequence defined below). normal operation the following are the only events supported during normal operation: (a) writes to master/channel volume registers (b) writes to soft mute register (c) enter and exit shutdown (sequence defined below) (d) clock errors and rate changes note: events (c) and (d) are not supported for 240ms+1.3xt 0 0after trim following avdd/dvdd power up ramp (where tstart is specified by register 0x1a). copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 25 apa3175 function description (cont.) shutdown sequence enter: 1. ensure i 2 s clocks have been stable and valid for at least 50ms. 2. write 0x40 to register 0x05. 3. wait at least 1ms+1.3xt stop (where t stop is specified by register 0x1a). 4. once in shutdown, stable clocks are not required while device remains idle. 5. if desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before returning to step 4 of initialization sequence. exit: 1. ensure i 2 s clocks have been stable and valid for at least 50ms. 2. write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240ms after trim following avdd/dvdd powerup ramp). 3. wait at least 1ms+1.3xt start (where t start is specified by register 0x1a). 4. proceed with normal operation. power-down sequence use the following sequence to power-down the device and its supplies: 1. if time permits, enter shutdown (sequence defined above); else, in case of sudden power loss, assert sd=0 and wait at least 2ms. 2. assert rst=0. 3. drive digital inputs low and ramp down pvdd supply as follows: ? drive all digital inputs low after rst has been low for at least 2 m s. ? ramp down pvdd while ensuring that it remains above 8v until rst has been low for at least 2 m s. 4. ramp down avdd/dvdd while ensuring that it remains above 3v until pvdd is below 6v and that it is never more than 2.5v below the digital inputs. sub address register name no. of bytes contents initialization values a u indicates unused bits. 0x00 clock control register 1 description shown in subsequent section 0x6c 0x01 device id register 1 description shown in subsequent section 0x00 0x02 error status register 1 description shown in subsequent section 0x00 0x03 system control register 1 1 description shown in subsequent section 0x80 0x04 serial data interface 1 description shown in subsequent section 0x05 0x05 1 description shown in subsequent section 0x40 0x06 soft mute register 1 description shown in subsequent section 0x00 0x07 master volume 1 description shown in subsequent section 0xff (mute) 0x08 channel 1 vol 1 description shown in subsequent section 0x30 (0db) 0x09 channel 2 vol 1 description shown in subsequent section 0x30 (0db) 0x0a fine master volume 1 description shown in subsequent section 0x00 (0db) 0x0b - 0x0d reserved (1) 0x0e volume configuration register 1 description shown in subsequent section 0x91 table 1. serial control interface register summary copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 26 apa3175 function description (cont.) sub address register name no. of bytes contents initialization values 0x0f 1 reserved (1) 0x10 modulation limit register 1 description shown in subsequent section 0x02 0x15-0x19 1 reserved (1) 0x1a start/stop period register 1 description shown in subsequent section 0x0a 0x1b 1 reserved (1) 0x1c 1 reserved (1) 0x1d C 0x1f 1 reserved (1) 0x20 input mux register 4 description shown in subsequent section 0x 0089 777a 0x21-0x24 4 reserved (1) 0x25 pwm mux register 4 description shown in subsequent section 0x0102 1345 0x26-0x28 4 reserved (1) u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x29 ch1_bq [0] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x2a ch1_bq [1] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x2b ch1_bq [2] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x2c ch1_bq [3] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x2d ch1_bq [4] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 0x2e ch1_bq [5] 20 u [31:26], b1 [25:0] 0x0000 0000 table 1. serial control interface register summary (cont.) copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 27 apa3175 function description (cont.) sub address register name no. of bytes contents initialization values u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x2e ch1_bq [5] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x2f ch1_bq [6] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x30 ch2_bq [0] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x31 ch2_bq [1] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x32 ch2_bq [2] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x33 ch2_bq [3] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x34 ch2_bq [4] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 0x35 ch2_bq [5] 20 u [31:26], a1 [25:0] 0x0000 0000 table 1. serial control interface register summary (cont.) copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 28 apa3175 function description (cont.) sub address register name no. of bytes contents initialization values 0x35 ch2_bq [5] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x36 ch2_bq [6] 20 u [31:26], a2 [25:0] 0x0000 0000 0x37~ 0x45 reserved (2) 0x46 drc control 4 description shown in subsequent section 0x0000 0000 0x47-0x4f reserved (2) 0x50 eq control reserved (2) 0x0f70 8000 0x51-0x5f reserved (2) 0x60 drc attack threshold 4 u [31:24], attackth [23:0] 0x0003 2d64 0x61 drc release threshold 4 u [31:24], attackth [23:0] 0x0002 ffe4 0x62 drc winidx 1 description shown in subsequent section 0x01 0x63-0xf8 reserved (2) 0xf9 update device address 4 u [31:8], new dev id[7:0] (new dev id=0x38) 0x00000034 0xfa-0xff reserved (2) table 1. serial control interface register summary (cont.) note (1): reserved register should not be accessed. note (2): reserved register should not be accessed. note (3): ae stands for a of energy filter, aa stands for a of attack filter and ad stands for a of decay filter and 1- a = w . copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 29 apa3175 function description (cont.) clock control register (0x00) the clocks and data rates are automatically determined by the apa3175. the clock control register contains the auto- detected clock status. bits d7-d5 reflect the sample rate. bits d4-d2 reflect the mclk frequency. d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 - - - - - f s =32khz sample rate 0 0 1 - - - - - f s =88.2khz/96khz sample rate 0 1 0 - - - - - f s =176.4khz/192khz sample rate 0 1 1 - - - - - f s =44.1/48khz sample rate (5) - - - 0 0 0 - - mclk frequency=64xf s (6) - - - 0 0 1 - - mclk frequency=128xf s (6) - - - 0 1 0 - - mclk frequency=192xf s (7) - - - 0 1 1 - - mclk frequency=256xf s (5) (8) - - - 1 0 0 - - mclk frequency=384xf s - - - 1 0 1 - - mclk frequency=512xf s - - - 1 1 0 - - reserved (4) - - - 1 1 1 - - reserved (4) - - - - - - 0 - reserved (4) - - - - - - - 0 reserved (4) table 2. clock control register (0x00) note (4): reserved registers should not be accessed. note (5): italic is default. note (6): only available for 44.1khz and 48khz rates. note (7): rate only available for 32/44.1/48khz sample rates. note (8): not available at 8khz. device id register (0x01) the device id register contains the id code for the firmware revision. d7 d6 d5 d4 d3 d2 d1 d0 function x - - - - - - - reserved - 0 0 0 0 0 0 0 identification code table 3. general status register (0x01) note: italic is default. copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 30 apa3175 function description (cont.) error status register (0x02) the error bits are sticky and are not cleared by the hardware. this means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors. error definitions: mclk error : mclk frequency is changing. the number of mclks per lrclk is changing. sclk error: the number of sclks per lrclk is changing. lrclk error: lrclk frequency is changing. table 4. error status register (0x02) d7 d6 d5 d4 d3 d2 d1 d0 function 1 - - - - - - - mclk error - 1 - - - - - - pll auto clock error - - 1 - - - - - sclk error - - - 1 - - - - lrclk error - - - - 1 - - - reserved - - - - - 1 - - reserved - - - - - - 1 - over temperature warning (sets around 145 o c ) por error, ocp, thermal shutdown error 0 0 0 0 0 0 0 0 no errors system control register 1 (0x03) the system control register 1 has several functions: bit d7: if 0, the dc-blocking filter for each channel is disabled. if 1, the dc-blocking filter ( -3db cutoff < 1hz ) for each channel is enabled (default). bit d5: if 0, use soft unmute on recovery from clock error. this is a slow recovery. unmute takes same time as volume ramp defined in reg 0x0e. if 1, use hard unmute on recovery from clock error (default). this is a fast recovery, a single step volume ramp bits d1-d0: select de-emphasis. table 5. system control register 1 (0x03) d7 d6 d5 d4 d3 d2 d1 d0 function 0 - - - - - - - pwm high-pass (dc blocking) disenabled 1 - - - - - - - pwm high-pass (dc blocking) enabled - 0 - - - - - - reserved - - 0 - - - - - reserved - - 0 - - - - - reserved - - - 0 - - - - reserved - - - - 0 - - - reserved - - - - - 0 - - reserved - - - - - - 0 0 no de-emphasis - - - - - - 0 1 reserved - - - - - - 1 0 de-emphasis for f s =44.1khz - - - - - - 1 1 de-emphasis for f s =48khz note: italic is default. note: italic is default. copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 31 apa3175 function description (cont.) serial data interface register (0x04) as shown in table 6, the apa3175 supports 9 serial data modes. the default is 24bit, i 2 s mode. table 6. serial data interface control register (0x04) format d7 d6 d5 d4 d3 d2 d1 d0 word length receive serial data interface format 0 0 0 0 0 0 0 0 16 right-justified 0 0 0 0 0 0 0 1 20 right-justified 0 0 0 0 0 0 1 0 24 right-justified 0 0 0 0 0 0 1 1 16 i 2 s 0 0 0 0 0 1 0 0 20 i 2 s 0 0 0 0 0 1 0 1 24 i 2 s 0 0 0 0 0 1 1 0 16 left-justified 0 0 0 0 0 1 1 1 20 left-justified 0 0 0 0 1 0 0 0 24 left-justified 0 0 0 0 1 - 1 0 - reserved 0 0 0 0 1 - - 1 - reserved 0 0 0 0 1 1 1 1 - reserved note: italic is default. system control register 2 (0x05) when bit d6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs are shut down (hard mute). table 7. system control register 2 (0x05) d7 d6 d5 d4 d3 d2 d1 d0 function 0 - - - - - - - reserved - 1 - - - - - - enter all channel shut down (hard mute) - 0 - - - - - - exit all channel shut down (normal operation) - - 0 0 0 0 0 0 reserved note: italic is default. soft mute register (0x06) writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute). d7 d6 d5 d4 d3 d2 d1 d0 function - - - - - - - 1 soft mute channel 1 - - - - - - - 0 soft un-mute channel 1 - - - - - - 1 - soft mute channel 2 - - - - - - 0 - soft un-mute channel 2 0 0 0 0 0 0 - - reserved table 8. soft mute register (0x06) note: italic is default. copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 32 apa3175 function description (cont.) volume registers (0x07, 0x08, 0x09) step size is 0.5 db. master volume - 0x07 (default is mute) channel-1 volume - 0x08 (default is 0 db) channel-2 volume - 0x09 (default is 0 db) table 9. volume registers (0x07, 0x08, 0x09) d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 0 0 0 0 24db 0 0 1 1 0 0 0 0 0db 1 1 0 0 1 1 0 1 -78.5db 1 1 0 0 1 1 1 0 -79.0db 1 1 0 0 1 1 1 1 values between 0xcf and 0xfe are reserved 1 1 1 1 1 1 1 1 mute (default for master volume) master fine volume register (0x0a) this register can be used to provide precision tuning of master volume. table 10. master fine volume register (0x0a) d7 d6 d5 d4 d3 d2 d1 d0 function - - - - - - 0 0 0db - - - - - - 0 1 0.125db - - - - - - 1 0 0.25db - - - - - - 1 1 0.345db 1 - - - - - - - write enable bit - - - - - - - - ignore write to register 0x0a volume configuration register (0x0e) bits volume slew rate (used to control volume change and mute ramp rates). these bits control the d2-d0: number of steps in a volume ramp. volume steps occur at a rate that depends on the sample rate of the i 2 s data as follows. sample rate (khz) approximate ramp rate 8/16/32 125 m s/step 11.025/22.05/44.1 90.7 m s/step 12/24/48 83.3 m s/step d7 d6 d5 d4 d3 d2 d1 d0 function 1 0 0 1 0 - - - reserved - - - - - 0 0 0 volume slew 512 steps (43ms volume ramp time at 48khz) table 11. volume control register (0x0e) note: italic is default. note: italic is default. copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 33 apa3175 function description (cont.) d7 d6 d5 d4 d3 d2 d1 d0 function - - - - - 0 0 1 volume slew 1024 steps (85ms volume ramp time at 48khz) - - - - - 0 1 0 volume slew 2048 steps (171ms volume ramp time at 48khz) - - - - - 0 1 1 volume slew 256 steps (21ms volume ramp time at 48khz) - - - - - 1 x x reserved table 11. volume control register (0x0e) note: italic is default. modulation limit register (0x10) table 12. modulation limit register (0x10) d7 d6 d5 d4 d3 d2 d1 d0 modulation limit - - - - - 0 0 0 reserved - - - - - 0 0 1 98.4% - - - - - 0 1 0 97.7% - - - - - 0 1 1 96.9% - - - - - 1 0 0 96.1% - - - - - 1 0 1 95.3% - - - - - 1 1 0 94.5% - - - - - 1 1 1 93.8% 0 0 0 0 0 - - - reserved note: italic is default. volume configuration register (0x0e) (cont.) start/stop period register (0x1a) this register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down command or change in the sd state. this helps reduce pops and clicks at start-up and shutdown. the times are only approximate and vary depending on device activity level and i 2 s clock stability. table 13. start/stop period register (0x1a) d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 - - - - - reserved - - - 0 0 - - - no 50% duty cycle start/stop period - - - 0 1 0 0 0 16.5ms 50% duty cycle start/stop period - - - 0 1 0 0 1 23.9ms 50% duty cycle start/stop period - - - 0 1 0 1 0 31.4ms 50% duty cycle start/stop period - - - 0 1 0 1 1 40.4ms 50% duty cycle start/stop period - - - 0 1 1 0 0 53.9ms 50% duty cycle start/stop period - - - 0 1 1 0 1 70.3ms 50% duty cycle start/stop period - - - 0 1 1 1 0 94.2ms 50% duty cycle start/stop period - - - 0 1 1 1 1 125.7ms 50% duty cycle start/stop period copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 34 apa3175 function description (cont.) d7 d6 d5 d4 d3 d2 d1 d0 function - - - 1 0 0 0 0 164.6ms 50% duty cycle start/stop period - - - 1 0 0 0 1 239.4ms 50% duty cycle start/stop period - - - 1 0 0 1 0 314.2ms 50% duty cycle start/stop period - - - 1 0 0 1 1 403.9ms 50% duty cycle start/stop period - - - 1 0 1 0 0 538.6ms 50% duty cycle start/stop period - - - 1 0 1 0 1 703.4ms 50% duty cycle start/stop period - - - 1 0 1 1 0 942.5ms 50% duty cycle start/stop period - - - 1 0 1 1 1 1256.6ms 50% duty cycle start/stop period - - - 1 1 0 0 0 1728.1ms 50% duty cycle start/stop period - - - 1 1 0 0 1 2513.6ms 50% duty cycle start/stop period - - - 1 1 0 1 0 3299.1ms 50% duty cycle start/stop period - - - 1 1 0 1 1 4241.7ms 50% duty cycle start/stop period - - - 1 1 1 0 0 5655.6ms 50% duty cycle start/stop period - - - 1 1 1 0 1 7383.7ms 50% duty cycle start/stop period - - - 1 1 1 1 0 9897.3ms 50% duty cycle start/stop period - - - 1 1 1 1 0 13196.4ms 50% duty cycle start/stop period start/stop period register (0x1a) (cont.) table 13. start/stop period register (0x1a) note: italic is default. input multiplexer register (0x20) this register controls the modulation scheme (bd mode) as well as the routing of i 2 s audio to the internal channels. table 14. input multiplexer register (0x20) d31 d30 d29 d28 d27 d26 d25 d24 function 0 0 0 0 0 0 0 0 reserved d23 d22 d21 d20 d19 d18 d17 d16 function 0 - - - - - - - reserved 1 - - - - - - - channel 1 bd mode - 0 0 0 - - - - sdin-l to channel 1 - 0 0 1 - - - - sdin-r to channel 1 - 0 1 0 - - - - reserved - 0 1 1 - - - - reserved - 1 0 0 - - - - reserved - 1 0 1 - - - - reserved - 1 1 0 - - - - ground (0) to channel 1 - 1 1 1 - - - - reserved - - - - 0 - - - reserved - - - - 1 - - - channel-2 bd mode copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 35 apa3175 d23 d22 d21 d20 d19 d18 d17 d16 function - - - - - 0 0 0 sdin-l to channel 2 - - - - - 0 0 1 sdin-r to channel 2 - - - - - 0 1 0 reserved - - - - - 0 1 1 reserved - - - - - 1 0 0 reserved - - - - - 1 0 1 reserved - - - - - 1 1 0 ground (0) to channel 2 - - - - - 1 1 1 reserved d15 d14 d13 d12 d11 d10 d9 d8 function 0 1 1 1 0 1 1 1 reserved d7 d6 d5 d4 d3 d2 d1 d0 function 0 1 1 1 0 0 1 0 reserved function description (cont.) input multiplexer register (0x20) (cont.) table 14. input multiplexer register (0x20) note: italic is default. pwm output mux register (0x25) this dap output mux selects which internal pwm channel is output to the external pins. any channel can be output to any external output pin. bits d21-d20: selects which pwm channel is output to out_a bits d17-d16: selects which pwm channel is output to out_b bits d13-d12: selects which pwm channel is output to out_c bits d09-d08: selects which pwm channel is output to out_d note that channels are enclosed so that channel 1=0x00, channel 2=0x01, channel 1=0x02, and channel 2=0x03. table 15. pwm output mux register (0x25) d31 d30 d29 d28 d27 d26 d25 d24 function 0 0 0 0 0 0 0 0 reserved d23 d22 d21 d20 d19 d18 d17 d16 function 0 0 - - - - - - reserved - - 0 0 - - - - multiplex channel 1 to out_a - - 0 1 - - - - multiplex channel 2 to out_a - - 1 0 - - - - multiplex channel 1 to out_a - - 1 1 - - - - multiplex channel 2 to out_a - - - - 0 0 - - reserved - - - - - - 0 0 multiplex channel 1 to out_b - - - - - - 0 1 multiplex channel 2 to out_b - - - - - - 1 0 multiplex channel 1 to out_b copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 36 apa3175 function description (cont.) pwm output mux register (0x25) (cont.) table 15. pwm output mux register (0x25) d23 d22 d21 d20 d19 d18 d17 d16 function - - - - - - 1 1 multiplex channel 2 to out_b d15 d14 d13 d12 d11 d10 d9 d8 function 0 0 - - - - - - reserved - - 0 0 - - - - multiplex channel 1 to out_c - - 0 1 - - - - multiplex channel 2 to out_c - - 1 0 - - - - multiplex channel 1 to out_c - - 1 1 - - - - multiplex channel 2 to out_c - - - - 0 0 - - reserved - - - - - - 0 0 multiplex channel 1 to out_d - - - - - - 0 1 multiplex channel 2 to out_d - - - - - - 1 0 multiplex channel 1 to out_d - - - - - - 1 1 multiplex channel 2 to out_d d7 d6 d5 d4 d3 d2 d1 d0 function 0 1 0 0 0 1 0 1 reserved note: italic is default. drc control (0x46) d31 d30 d29 d28 d27 d26 d25 d24 function 0 0 0 0 0 0 0 0 reserved d23 d22 d21 d20 d19 d18 d17 d16 function 0 0 0 0 0 0 0 0 reserved d15 d14 d13 d12 d11 d10 d9 d8 function 0 0 0 0 0 0 0 0 reserved d7 d6 d5 d4 d3 d2 d1 d0 function - - - - - - - 0 drc turned off - - - - - - - 1 drc turned on 0 0 0 0 0 0 0 - reserved note: italic is default. copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 37 apa3175 function description (cont.) fault description error 0 over-current (oc) or under-voltage (uvp) or over-temperature (otp) 1 no faults (normal operation) over-current (oc) protection with current-limiting the device has independent, fast-reacting current detectors on all high-side and low-side power-stage fets. the detector outputs are closely monitored by two protection systems. the first protection system controls the power stage in order to prevent the output current further increasing, i.e., it performs a cycle-by-cycle current-limiting function, rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load impedance drops. if the high-current condition situation persists, i.e., the power stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (hi-z) state. the device returns to normal operation once the fault condition (i.e., a short circuit on the output) is removed. current limiting and overcurrent protection are not independent for half-bridges. that is, if the bridge-tied load between half-bridges a and b causes an overcurrent fault, half-bridges a, b, c, and d are shut down. over-temperature protection the apa3175 has over-temperatureprotection system. if the device junction temperature exceeds 150 c (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (hi-z) state and fault being asserted low. the apa3175 recovers automatically once the temperature drops approximately 30 . under-voltage protection (uvp) and power-on-reset (por) the uvp and por circuits of the apa3175 fully protect the device in any power-up/down and brownout situation. while powering up, the por circuit resets the overload circuit (olp) and ensures that all circuits are fully operational when the pvdd and avdd supply voltages reach 4.2v and 2.7v, respectively. although pvdd and avdd are indepen- dently monitored, a supply voltage drop below the uvp threshold on avdd or either pvdd pin results in all half-bridge outputs immediately being set in the high-impedance (hi-z) state and error being asserted low. error reporting any fault resulting in device shutdown is signaled by the error pin going low (see table 18). a sticky version of this pin is available on d1 of register 0x02. table 16. error output states copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 38 apa3175 application information layout recommendation 1 3 1 3 7 2 5 /reset avdd scl lrck sclk sdin sda 0 10 f 4700pf t m a v s s p l l _ l f n c n c p v d d _ a a b s g d r e g n c n c o u t _ a p v d d _ a a v d d / e r r o r m c l k t p 1 t p 2 s c l 1 v 8 _ d v / s d l r c l k s c l k s d i n s d a 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 g n d d v s s d v d d t p 3 / r s t p v d d _ d d b s g d r e g d v r e g a g n d o u t _ d p v d d _ d p g n d _ a b p g n d _ a b o u t _ b p v d d _ b p v d d _ b p g n d _ c d b b s c b s p v d d _ c p v d d _ c o u t _ c p g n d _ c d 0.1 f 10k mclk a_sel 0.1 f 4.7 f 10k av dd /pdn dvdd 0.1 f 10 f 0.1 f 1 f 0.033 f pvdd 0.1 f 220 f 22 h 0.68 f 0.68 f 22 h 0.033 f 0.033 f 0.1 f 0.1 f pvdd 22 h 22 h 0.68 f 0.68 f pvdd 220 f 0.1 f 0.033 f 1 f 470 0.047 f avdd cap. & dvdd cap. should be close to the chip. thermal pad should be soldered on ground plane of the pcb. pvdd cap. and bootstrap cap. should be close to the chip. power stage block, please use high voltage-bearing component. output & vdd traces width 40mil, should be as short as they can, and symmetric. 8 8 copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 39 apa3175 application information(cont.) layout recommendation 0.28mm via diameter =0.3mm x16 ground plane for thermalpad 1.7mm 5.5mm exposed for thermal pad connected 5 . 0 m m 0.5mm tqfp7x7-48 land pattern recommendation copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 40 apa3175 application information(cont.) layout recommendation pcb referance (top layer) copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 41 apa3175 application information(cont.) layout recommendation pcb referance (bottom layer) copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 42 apa3175 package information tqfp7x7-48p 0 l 0 . 2 5 seating plane gauge plane l 0.006 0 o 7 o 0 o 7 o 0.50 bsc 0.020 bsc 0.45 0.75 0.018 0.030 s y m b o l min. max. 1.20 0.05 0.17 0.27 0.09 0.20 0.15 a a1 b c d d1 e e1 e millimeters a2 0.95 1.05 tqfp7x7-48p min. max. inches 0.047 0.002 0.037 0.041 0.007 0.011 0.004 0.008 d2 e2 3.00 0.118 3.00 5.50 5.50 0.177 0.118 0.177 8.80 9.20 0.346 0.362 6.90 7.10 0.272 0.280 8.80 6.90 7.10 9.20 0.346 0.272 0.362 0.280 note : 1. followed from jedec ms-026 abc. 2. dimension "d1" and "e1" do not include mold protrusions. allowable protrusions is 0.25 mm per side. "d1" and "e1" are maximun plasticbody size dimensions including mold mismatch. d1 d e 1 e e b d2 e 2 exposed pad a 2 a 1 a c copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 43 apa3175 application a h t1 c d d w e1 f 330.0 2.00 50 min. 16.4+2.00 - 0.00 13.0+0.50 -0.20 1.5 min. 20.2 min. 16.0 0.30 1.75 0.10 7.5 0.10 p0 p1 p2 d0 d1 t a0 b0 k0 tqfp7x7-48p 4.0 0.10 12.0 0.10 2.0 0.10 1.5+0.10 -0.00 1.5 min. 0.6+0.00 -0.40 9.4 0.20 9.4 0.20 1.8 0.20 (mm) carrier tape & reel dimensions devices per unit package type unit quantity tqfp7x7-48p tape & reel 2500 h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 44 apa3175 taping direction information tqfp7x7-48p classification profile user direction of feed copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 45 apa3175 profile feature sn-pb eutectic assembly pb-free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) (t s ) 100 c 150 c 60-120 seconds 150 c 200 c 60-120 seconds average ramp-up rate (t smax to t p ) 3 c/second max. 3 c/second max. liquidous temperature (t l ) time at liquidous (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak package body temperature (t p )* see classification temp in table 1 see classification temp in table 2 time (t p )** within 5 c of the specified classification temperature (t c ) 20** seconds 30** seconds average ramp-down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. classification reflow profiles table 1. snpb eutectic process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 220 c 3 2.5 mm 220 c 220 c table 2. pb-free process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350-2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm C 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c reliability test program test item method description solderability jesd-22, b102 5 sec, 245 c holt jesd-22, a108 1000 hrs, bias @ t j =125 c pct jesd-22, a102 168 hrs, 100 % rh, 2atm, 121 c tct jesd-22, a104 500 cycles, -65 c~150 c hbm mil-std-883-3015.7 vhbm R 2kv mm jesd-22, a115 vmm R 200v latch-up jesd 78 10ms, 1 tr R 100ma copyright ? anpec electronics corp. rev. a.3 - aug., 2016 www.anpec.com.tw 46 apa3175 customer service anpec electronics corp. head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 2f, no. 11, lane 218, sec 2 jhongsing rd., sindian city, taipei county 23146, taiwan tel : 886-2-2910-3838 fax : 886-2-2917-3838 |
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