spsemi ... www.spsemi.cn page 1 of 3 AUSD12CB ultra low capacitance tvs/esd protection diode features package optimized for high-speed lines ultra-small package (1.0mm0.6mm0.55mm) protects one data, control or power line low capacitance low leakage current low clamping voltage esd/AUSD12CB iec compatibility iec61000-4-2 (esd) 20kv (air), 15kv (contact) iec61000-4-4 (eft) 40a (5/50s) mechanical characteristics dfn1006 package flammability rating: ul 94v-0 packaging: tape and reel high temperature soldering guaranted:260 /10s quantity per reel : 10,000pcs reel size: 7 inch material: halogen free applications serial ata usb ports pci express cellular phones desktops, severs and notebooks dfn1006 pin configuration electro-static discharge for aotomobile rev 2017 09 08
spsemi www.spsemi.cn page 2 of 3 maximum ratings (t =25 unless otherwise specified ) a electrical characteristics (t =25 unless otherwise specified ) a electrical characteristics curve ... esd/AUSD12CB parameter symbol conditions units min. typ. max. (marking: c5 ) reverse stand-off voltage reverse breakdown voltage reverse leakage current clamping voltage junction capacitance v rwm v br r i c v c j 12 1 20 0.8 i=1ma t @v rwm i =1a,tp=8/20s pp v =0v,f=1mhz r 16 18 v v a v f p parameter symbol value units peak pulse power(tp=8/20s) lead soldering temperature operating temperature range storage temperature range p pp t l t opt t stg 20 260(10 sec.) -55~125 -55~150 watts fig.2 normalized capacitance vs.reverse voltage 0.0 reverse voltage( ) v 0 1.0 normalized capacitance(pf) 2.0 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 3 1 2 4 5 fig.1 pulse waveform 5 010 30 15 0 10 time( ) s 20 25 20 30 40 50 60 70 80 90 100 110 percent of i pp t=i /2 d pp waveform parameters: tr=8s t =20s d e -1 rev 2017 09 08 AUSD12CB
www.spsemi.cn page 3 of 3 ... spsemi esd/AUSD12CB dimensions(dfn1006) dfn1006 a b c e d f g dim a b c d e f g millimeters min 0.95 0.55 0.45 0.20 0.40 0.00 max 1.07 0.65 0.55 0.30 0.55 0.10 min 0.037 0.022 0.017 0.008 0.015 0.000 max 0.042 0.026 0.022 0.012 0.022 0.004 inches 0.65bsc 0.026bsc recommended mounting pad layout 0.39 0.015 0.89 0.035 0.64 0.025 0.49 0.019 0.25 0.010 rev 2017 09 08 pcb layout recommendations the location and circuit board layout is critical to maximize the effectiveness of the rf protection circuit. the following guidelines are recommended: locate the protection devices as close as possible to the rf connector. this allows the protection devices to absorb the energy of the transient voltage before it can be coupled into the adjacent traces on the pcb. minimize the loop area for the high.speed data lines, power and ground lines to reduce the radiated emissions. avoid running protection conductors in parallel with unprotected conductors use ground planes wherever possible to reduce the parasitic capacitance and inductance of the pcb that degrades the effectiveness of a filter device. using shared transient return paths to a common ground point. rf protection rf amplifier AUSD12CB in rf out
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