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- 1 - nuvoton technology corp. release date: jun . 2013 http:// www.nuvoton.com/ revi sion a 3 n3291x ux dn data sheet a rm926ej - s based media processor with video decode accelerator
n3291x ux dn data sheet - 2 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 the information in this document is subject to change without notice. the nuvoton technology corp. shall not be liable for te chnical or editorial errors or omissions contained herein; nor for incidental or consequential damages resulting from the furnishing, performance, or use of this material. this documentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine readable form without prior consent, in writing, from the nuvoton technology corp. nuvoton technology corp. all rights reserved.
n3291x ux dn data sheet - 3 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 table of c ontent s 1. general description ................................................................................................... 4 1.1 applications ....................................................................................................................... 4 2. features ........................................................................................................................... 5 3. pin diagram .................................................................................................................... 12 3.1 n3291xux dn (lqfp - 128) ............................................................................................... 12 4. pin description ............................................................................................................. 13 4.1 pin description ................................................................................................................ 13 4.2 pin type description ........................................................................................................ 26 5. electrical specifica tion ......................................................................................... 27 5.1 absolute maximum rating ............................................................................................... 27 5.2 dc characteristics (normal i/o) ...................................................................................... 27 5.3 audio dac characteristics .............................................................................................. 29 5.4 adc characteristic s ........................................................................................................ 30 5.5 ac characteristic s ( digital interface ) ............................................................................... 30 5.6 thermal characteristics of s lqfp - 128 package ............................................................. 31 6. o r dering information ............................................................................................... 32 6.1 part number definition .................................................................................................... 32 6.2 difference between n3291xu1dn and n32916xu2dn ................................................... 32 7. package outline .......................................................................................................... 33 7.1 128l lqfp (14x14x1.4mm body, 0.4mm pitch) ............................................................. 33 8. revision history .......................................................................................................... 34
n3291x ux dn data sheet - 4 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 1. general description the n3291xux dn is specially designed for accelerating video str eam decoding performance while off - loading the cpu to save power consumption. it is embedded h/w video decoder to deliver high - quality video playback in different formats, like h.264 / mpeg - 4 / h.263. t he n3291xux dn is built on the arm926ej - s cpu core and integrated with video encoder, jpeg codec, cmos image sensor interface , sound processing unit (spu), adc, dac, and tv encoder for meeting various kinds of application needs while saving the bom cost. the combination of arm926 @ 3 0 0 mhz, ddr 2 , h/w video deco der, and usb2.0 hs device makes the n3291 x u1dn the best choice for high performance media processing devices. the n3291x u1dn also integrates an aes cipher/de - cipher cryptography engine for stream protection consi derations. the stream stored in sd card, sp i nor flash , or nand flash is encrypted . it is decrypted when the stream is read back and decrypted for playback . the n32916u x dn is ported with linux os to leverage the driver availability of emerging functionalities, like wi - fi connectivity . on the other hand, the open source code environment also gives the product development more flexibility. moreover, hybrid platform is introduced to best utilize the performance advantage at native c programming while enjoying the inher ent benefit at application firmwar e/software development. maximum resolution for the n3291 x u x dn is d1 (720x 480) @ tv output and 1,024x768 @ tft lcd panel . with increasing popularity of the application image resolution , the n3291xux dn is the best fit for the application that requires fast t urn - around time of development. the n3291 x u x dn is well - positioned in the cost effective & high performance media player market where video streams are extensively used. to reduce system complexity while cutting the bom cost, the n3291 x u x dn is particularly designed with the 128- pin slqfp mcp (multi - chip package) . for n3291xuxdn , the 32 mbitx16 ddr 2 chip is stacked inside the mcp to ensure higher performance , lower power consumption and to minimize the s ystem design efforts, like emi and noise coupling. t he n 3291xuxdn is incorporated with a reliable linux os kernel and board support package (bsp) to help customers shorten the design cycle time. t h e fast booting time (under 3 seconds) , fr om power on to application running , is another extra feature to help elimi nate power consumption . 1.1 applications ? e - reader for kids ? ela (education al learning aid) ? tv game ? hmi ? home applicance ? advertisement
n3291x ux dn data sheet - 5 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 2. features ? cpu ? a rm926ej - s 32 - bit risc cpu with 16 kb i - cache & 16 kb d - cache . ? frequency up to 300mhz ( worse case ) . ? jtag inte rface supported for development and debug ging . ? internal sram & rom ? 8kb internal sram and 1 6 kb ibr (i nternal b ooting rom ) supported . ? ibr booting messages displayed by uart console for debug ging . ? different system booting modes supported: ? memory card ? sd card ? sd - to - nand flash bridge ? nand interface ? raw nand flash ? otp rom (n23512t / n231gt) ? spi flash ? usb ? memory controller ? sdram interface ? sdr, ddr , lpddr & ddr2 type sdram supported . ? frequency up to 1 5 0 mhz . ? 16 - bit data bus width supported . ? 2 external sdram banks (2 chip select pins) supported . ? total memory size up to 256mb (128mb x 2) . ? edma (enhanced dma) ? totally 6 dma channels supported ? 4 peripheral dma channels for transfer between memory and on - chip peripherals, such as adc, uart and spi . ? two dedicated channel s for memory - to - memory transfer . ? byte, half - word and word data width types supported . ? single and burst transfer modes supported . ? block transfer supported in memory - to - memory transfer channel . ? color format transformation supported in memory - to - memory transf er channel . ? source color format could be rgb555, rgb565 and ycbcr422 . ? destination color format could be rgb555, rgb565 and ycbcr422 . ? auto reload supported for continuous data transfer . ? interrupt generation supported in the half - of - transfer or end - of - transf er . ? capture (cmos image sensor i/f) ? ccir601 and ccir656 interfaces supported for connection to cmos image sensor . ? r esolution up to 2 m pixel s . ? yuv422 and rgb565 color format supported for data - in from cmos sensor . ? yuv422, rgb565, rgb555 and y - only color fo rmat supported for data storing to system memory . ? planar and packet data format s supported for data storing to system memory . ? image cropping supported with the cropping window up to 4096x2048 .
n3291x ux dn data sheet - 6 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 ? image scaling - down supported . ? vertical and horizontal scaling - d own for preview mode supported . ? the scaling factor is n/m . ? two pairs of configurable 8 - bit n and 8 - bit m for vertical and horizontal scaling - down . ? the value of n has to equal to or less than m . ? frame rate control supported . ? combines two interlace fields to a single frame supported for data in from tv - decoder ? 3 kinds of color processing effects: ? negative p icture ? sepia picture ? posterization ? jpeg codec ? baseline sequential mode jpeg codec function compliant with iso/iec 10918 - 1 international jpeg standard supp orted. ? planar format ? support to encode interleaved ycbcr 4:2:2/4:2:0 and gray - level (y only) format image . ? support to decode interleaved ycbcr 4:4:4/4:2:2/4:2:0/4:1:1 and gray - level (y only) format image . ? support to decode ycbcr 4:2:2 transpose format . ? sup port arbitrary width and height image encode and decode . ? support three programmable quantization - tables . ? support standard default huffman - table and programmable huffman - table for decode . ? support arbitrarily 1x~8x image up - scaling function for encode mode . ? support down - scaling function for encode and decode modes . ? support specified window decode mode . ? support quantization - table adjustment for bit - rate and quality control in encode mode . ? support rotate function in encode mode . ? support on - the - fly interface wit h video data processor. ? packet format ? support to encode interleaved yuyv format input image, output bitstream 4:2:2 and 4:2:0 format . ? support to decode interleaved ycbcr 4:4:4/4:2:2/4:2:0 format image . ? support decoded output image rgb555 , rgb565 and rgb888 format s . ? the encoded jpeg bit - stream format is fully compatible with jfif and exif standards . ? support arbitrary width and height image encode and decode . ? support three programmable quantization - tables . ? support standard default huffman - table and programmab le huffman - table for decode . ? support arbitrarily 1x~8x image up - scaling function for encode mode . ? support down - scaling function 1x~ 16x for y422 and y420, 1x~ 8x for y444 for decode mode . ? support specified window decode mode . ? support quantization - table adj ustment for bit - rate and quality control in encode mode . ? support on - the - fly interface with video data processor. ? support scatter - gather mode for output frame buffer.
n3291x ux dn data sheet - 7 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 ? video decoder ? support h.264 avc baseline profile level - 3 and compliant with iso/iec 1449 6 - 10 visual standard , svga (800x600) @ 30fps . ? support mpeg - 4 part - ii simple profile level - 3 decoder and compliant with iso/iec 14496 - 2 visual standard , svga (800x600) @ 30fps . ? support h.263 p3 decoder , svga (800x600) @ 30fps . ? support sorenson spark decoder , d1 (720x480) @ 30fps . ? support real - time 30fps video decompress ion and resolution can up to 720 480 . ? error resilience: slice resynchronization, data partitioning and reversible vlc . ? vpost ? 8/16/18/24 - bit sync type and 8/9/16/18/24 - bit mpu type tft lcd sup ported . ? color format supported: ? ycbcr422, rgb565, rgb555, and rgb888 color formats supported for data in . ? ycbcr422, rgb565, rgb555, and rgb888 color formats supported for data out . ? xga ( 1024x768 ) , svga (800x600), wvga (800x480), d1 (720x480), vga (640x480) , wqvga (480x272), qvga (320x240) and hvga (320x48 0) resolution supported . ? the maximum resolution is up to d1 (720x480) for tv output . ? the maximum resolution is up to 1024x 768 for tft lcd panel . ? display scaler ? to fit different size of lcd panels . ? horizon tal: at most 4.0x scale . ? vertical: at most 3.0x scale . ? for sync type lcd: ? for 8 - bit bus ? ccir601 ycbcr422 packet mode (ntsc/pal) supported . ? ccir601 rgb dummy mode (ntsc/pal) supported . ? ccir656 interface supported . ? rgb through mode supported . ? for 16/18/24 - bi t bus ? parallel pixel data output mode (1 - pixel/1 - clock) . ? ntsc/pal interlace & non - interlace output supported . ? color format transform supported: ? color format transform between ycbcr422 and rgb565 . ? color format transform from ycbcr422 to rgb888 . ? tv encoder s upported . ? dual screen, outputs to tv and lcdwith same content, supported . ? lcd panel should be 320x240 mpu - type, or 8 - bit sync - type lcd panel with tv timing ? notch filter for ntsc supported to remove the rainbow color effect . ? support osd function to overlap system information like battery life, brightness tuning, volume tuning or muting, etc. ? spu (sound process ing unit ) ? 7 - bit volume control supported . ? 5 - bit pan control supported . ? 10 - band equalizer supported . ? 13 - bit dfa supported for source sampling rate cont rol. ? audio dac
n3291x ux dn data sheet - 8 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 ? 16 - bit stereo dac supported with headphone driver output . ? h/w volume control supported . ? built - in pll for supporting various sampling rate. ? i 2 s controller ? i 2 s interface supported to connect external audio codec . ? 16/18/20/24 - bit data format supported . ? storage interface controller ? interface to nand flash: ? 8 - bit data bus width supported . ? slc and mlc type nand flash supported . ? 512b, 2kb , 4kb , and 8kb page size nand flash supported . ? ecc4 , ecc8 , ecc12, ecc15 and ecc24 algorithm supported for ecc generation, error detection and error correction . ? interface to sd/mmc/sdio/sdhc/micro - sd cards supported . ? sd - to - nand flash bridge supported . ? dma function supported to accelerate the data transfer between system memory and nand flash or sd/mmc/sdio/sdhc/mi cro - sd . ? usb device controller ? usb2.0 hs ( high - speed) x 1 port . ? 6 configurable endpoints supported . ? control, bulk, interrupt and isochronous transfers supported . ? suspend and remote wakeup supported . ? usb host controller ? usb1.1 host x 2 ports . ? fully complia nt with usb revision 1.1 specification . ? open host controller interface (ohci) revision 1.0 compatible . ? full - speed (12mbps) and low - speed (1.5mbps) usb devices supported . ? control, bulk, interrupt and isochronous transfers supported . ? timer & watch - dog timer ? two 32 - bit with 8 - bit pre - scalar timers supported . ? one programmable 24 - bit watch - dog timer supported . ? pwm ? 4 pwm channel outputs supported . ? 16 - bit counter supported for each pwm channel . ? two 8 - bit pre - scalars supported and each pre - scalar shared by two pw m channels . ? two clock - dividers supported and each divider shared by two pwm channels . ? two dead - zone generators supported and each generator shared by two pwm channels . ? auto reloaded mode and one - shot pulse mode supported . ? capture function supported .
n3291x ux dn data sheet - 9 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 ? uart ? a high speed uart supported: ? baud rate is up to 1m bps . ? 4 signals tx, rx, cts and rts supported . ? a normal uart supported: ? baud rate is up to 115.2k bps . ? 2 signals tx and rx supported only . ? spi ? two spi interfaces are supported . ? both master and slave mode are supported in spi interface 0 . ? only master mode is supported in spi interface 1 . ? byte transfer with configurable stop interval supported . ? i2c ? one i2c channel supported . ? compatible with philips?s i 2 c standard and only master mode supported . ? multi - master operation supported . ? advanced interrupt controller ? total 32 interrupt source supported . ? configurable interrupt type: ? low - active level triggered interrupt . ? high - active level triggered interrupt . ? low - active edge (falling edge) triggered interrupt . ? high - act ive edge (rising edge) triggered interrupt . ? individual interrupt mask bit for each interrupt source . ? 8 different priority levels supported . ? daisy - chain priority mechanism supported for interrupts with same priority level . ? low priority interrupt automatic m asking supported for interrupt nesting . ? rtc ? independent power plane supported ? dual clock source are supported, accurate 32.768 khz cryst al oscillation circuit and built - in coarse 32khz rc - oscillator. ? time counter (second, minute, hour) and calendar counte r (day, month, year) supported . ? alarm supported (second, minute, hour, day, month and year) . ? 12/24 - hour mode and leap year supported . ? alarm to wake chip up from standby mode or from power - down mode supported . ? wake chip up from power - down mode by input pin supported . ? power - off chip by register setting supported . ? power - on timeout is supported for low battery protection . ? gpio ? 8 8 programmable general purpose i/os supported and separated into 5 groups . ? individual configuration supported for each i/o signal . ? con figurable interrupt control functions supported . ? configurable de - bounce circuit supported for interrupt function .
n3291x ux dn data sheet - 10 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 ? general - purpose adc ? multi - channel, 10 - bit adc supported ? 2 channels dedicated for 4 - wire resistive touch sensor inputs . ? 3 channel s reserved f o r various purposes , like lvd (low voltage detection) , keypad input , and light sensor . ? input voltage range from 0 v ~ 3.3 v supported . ? maximum 25mhz input clock supported . ? maximum 150 k/s conversion rate supported . ? lvr (low voltage reset) supported . ? microphon e adc ? built - in programmable gain control (pgc) circuit ? built - in bias circuit ? 10 - bit adc supported ? keypad interface (kpi) ? matrix key pad interface supported. ? maximum 8x8 and minimum 3x3 keypad matrix supported. ? configurable key de - bounce supported. ? low pow er wakeup mode supported. ? configurable three - key reset supported. ? aes (advance encryption standard) engine ? support both encryption and decryption. ? support only cbc (cipher block chaining) mode. ? all three kinds of key length: 128, 192, 256 bits are support ed. ? built - in dma supported. ? power management ? advanced power management including power down, deep standby, cpu standby , and normal operating modes . ? normal operating mode ? core power is 1. 2 v and chip is in normal operation . ? cpu standby mode ? core power is 1. 2 v and only arm cpu clock is turned off . ? deep standby mode ? core power is 1. 2 v and all ip clocks are turned off . ? power down mode ? only the rtc power is on. other 3.3v and 1. 2 v power are off . ? software support ? development tools ? bootloader / diagnostic program / nand writer program: ads 1.2 or rvds 2.x or 3.x ? linux kernel (2.6.17.14) / system manager : gcc 4.2 ? turbowriter / sync tool: microsoft vc 6.0 ? nand flash file system ? fat12, fat16 and fat32 with long filename are supported . ? hidden disk is supported . ? ram di sk is supported .
n3291x ux dn data sheet - 11 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 ? s/w audio library ? decoders with adpcm / mp3 / acc / ogg / w ma format support . ? 32 - polyphony wavetable midi synthesizer . ? programmable sampling rate and target bit rate . ? usb driver ? ms ( mass s torage ) c lass ? hid (human interface device) class ? f a st booti ng time (from power - on to application running) ? within 3 seconds ? operating voltage ? i/o: 3. 3v ? core : 1. 2 v for 3 00mhz . ? package ? lqfp - 128 (mcp, stacked with 32 mb x16 ddr 2 @ 1.8v )
n3291x ux dn data sheet - 12 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 3. pin diagram 3.1 n3291x ux dn ( lqfp - 128) adac_hpout_l adac_vss33 tvdac_avdd33 adac_vmid tvdac_tvout tvdac_comp tvdac_vref tvdac_rext mvdd18 ud_cdet trst_ rst_ rtc_vdd33 rtc_rpwr rtc_rwake_ rtc_xin rtc_xout adac_avdd33 nd[0] nd[1] nd[2] nd[3] nd[4] nd[5] nd[6] nd[7] nbusy1_ vss vdd33 / hur_rts / spi0_cs1_ / gpd[4]/ s2hsync/ uhl_dm0 tdo / hur_cts / pwm3 / gpd[3]/ s2vsync/ uhl_dp0/ lvd_out tdi / hur_rxd / pwm2 / gpd[2]/ s2clko tms / hur_txd / pwm1 / gpd[1]/ s2pclk tck / spi1_cs1_ / pwm0 / gpd[0] / gpd[6] / sddat2[2] nbusy0_ / gpd[5] / sddat2[3] nwr_ / sdcmd2 nre_ / uhl_dp0 / sdclk2 ncle / gpe[11] nale / gpe[10] ncs1_ / gpe[9] / sddat2[1] ncs0_ / gpe[8] / sddat2[0] urtxd / gpa[10] / spi1_cs1_ urrxd / gpa[11] / lmvsync gpb[6] / i2s_din/ / sddat1[2] /i2s_dout/ gpb[5] / sddat1[3] / i2s_ws/ gpb[4] / sdcmd1 / i2s_bclk/ gpb[3] / sdclk1 / i2s_mclk/ gpb[2] spclk sclko isda isck spi0_do spi0_di spi0_cs0_ spi0_clk sddat[0] sddat[1 ] sddat[2] sddat[3] sdclk sdcmd xin xout vdd33 ud_vdd12 ud_dm ud_dp ud_vdd33 ud_rext lvdata[17] gpa[5] gpa[6] uhl_dm1 / sddat1[0] / gpb[1] / uhl_dp1 / sddat1[1] / gpb[0] / lmvsync / gpb[14] / gpb[13] / / gpd[15] gpd[12] / / gpd[13] / gpd[14] gpe[7] / gpe[4] / gpe[5] / gpe[6] / gpe[3] / gpe[2] / gpe[1] / s2vsync / lvdata[16] lvdata[15] lvdata[14] lvdata[13] lvdata[12] lvdata[11] lvdata[10] lvdata[9] lvdata[8] lvdata[7] lvdata[6] lvdata[5] lvdata[4] lvdata[3] lvdata[2] lvdata[1] lvdata[0] lvde lvsync lhsync vdd12 lpclk vdd33 adc_vss33 adc_tp_ym adc_tp_xm adc_tp_xp adc_tp_yp adc_vdd33 adc_ain[0] adc_ain[1] adc_ain[2] s2hsync / s2data[7] / s2data[6] / s2data[5] / s2data[4] / s2data[3] / s2data[2] / s2data[1] / s2data[0] / gpe[0] / gpc[15] / gpc[14] / gpc[13] / gpc[12] / gpc[11] / gpc[10] / gpc[9] / gpc[8] / gpc[7] / gpc[6] / gpc[5] / gpc[4] / gpc[3] / gpc[2] / gpc[1] / gpc[0] / gpd[11] / gpd[10] / gpd[9] / gpb[15] / n 3 2 9 1 x u x d n l q f p - 1 2 8 1 10 20 30 40 50 60 70 80 90 100 110 120 128 / mic_p / mic_n vdd12 spdata[7] spdata[6] vdd12 mvddq18 mvddq18 vdd12 spdata[5] spdata[4] spdata[3] spdata[2] spdata[1] spdata[0] sfield svsync shsync vss gpa[3] gpa[4] gpa[0] gpa[1] adc_ain[3] mic_bias pgc_vref mvdd18 divider_fb adac_hpout_r adac_hpvdd33 vdd12 / spi0_do / spi0_di / spi0_cs0_ / spi0_clk / gpa[12] / gpa[13] / gpa[14] / gpa[15] / uhl_dm0 / spi1_clk/ /spi1_cs0_/ / spi1_di/ / spi1_do/ /lvdata[18] / gpb[7] /lvdata[19] / gpb[8] /lvdata[20] gpb[9] /lvdata[21] gpb[10] /lvdata[22] gpb[11] /lvdata[23] gpb[12] lvd_out / kpi_so[0]/ kpi_so[1]/ kpi_so[2]/ kpi_so[3]/ kpi_so[4]/ kpi_so[5]/ kpi_so[6]/ kpi_so[7]/ kpi_so[8]/ kpi_so[9]/ kpi_so[10]/ kpi_so[11]/ kpi_so[12]/ kpi_so[13]/ kpi_so[14]/ kpi_so[15]/ / uhl_dp1 / uhl_dm1 / isck / isda / s2field / uhl_dp0 / uhl_dm0 / lvd_out s2pclk / sd_cd_ / s2clko / kpi_si[0] / kpi_si[1] / spi0_cs 1 / / uhl_dp0 / uhl_dm0 /kpi_si[2] /kpi_si[3] / gpg[1] / gpg[0] / i2s_dout / i2s_ws / i2s_mclk / i2s_bclk / spi1_clk / spi1_di / spi1_do / spi1_cs0_ / gpg[2] / gpg[4] / gpg[5] / gpg[3] / isck / isda / gpg[7] / i2s_di / i2s_ws / i2s_bclk / spi1_clk / i2s_mclk / spi1_cs0_ / spi1_di / spi1_do / isck / isda / gpg[8] / gpg[12] / gpg[13] / gpg[14] / gpg[15] / gpg[11] / gpg[9] / gpg[10] / gph[0] / lvd_out / gph[5] / gpd[8] / gpd[7] / lvro_ / poro_
n3291x ux dn data sheet - 13 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 4. pin des cription 4.1 pin description pin name i/o type description clock & reset xin i 27mhz/12mhz crystal input xout o 27mhz/12mhz crystal output rst_ iosu system reset, input, low active watch - dog reset, output, low active jtag interface tck iod jtag interfac e test clock, input spi1_cs1_ spi port 1 device select 1, output, low active pwm0 pwm channel 0 gpd[0] gpio port d bit 0 tms iou jtag interface test mode select, input hur_txd high - speed uart tx data, output pwm1 pwm channel 1 s2pclk cmos came ra module port 2 pclk signal gpd[1] gpio port d bit 1 tdi iou jtag interface test data in, input hur_rxd high - speed uart rx data, input pwm2 pwm channel 2 s2clko cmos camera module port 2 mclk signal gpd[2] gpio port d bit 2 tdo iou jtag interf ace test data out, output hur_cts high - speed uart clear - to - send, input, low active pwm3 pwm channel 3
n3291x ux dn data sheet - 14 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 pin name i/o type description lvd_out low voltage dection indicator s2vsync the 2 nd cmos camera module vsync signal uhl_dp0 usb 1.1 host like port 0 d+ signal gpd[3] gpio p ort d bit 3 trst_ iou jtag interface test reset, input, low active hur_rts high - speed uart reset - to - send, output, low active spi0_cs1_ spi port 0 device select 1, output, low active uhl_dm0 usb 1.1 host like port 0 d - signal s2hsync the 2 nd cmos c amera module hsync signal gpd[4] gpio port d bit 4 nand interface ncs0_ iou nand interface chip select 0, output, low active gpe[8] gpio port e bit 8 ncs1_ iou nand interface chip select 1, output, low active gpe[9] gpio port e bit 9 nale iou nan d interface address - latch - enable, output, high active sddat2[0] sd port 2 data bit 0 gpe[10] gpio port e bit 10 ncle iou nand interface command - latch - enable, output, high active sddat2[1] sd port 2 data bit 1 gpe[11] gpio port e bit 11 nbusy0_ io u nand interface busy 0, input, low active sddat2[2] sd port 2 data bit 2 gpd[5] gpio port d bit 5 nbusy1_ iou nand interface busy 1, input, low active gpd[6] gpio port d bit 6 nre_ iou nand interface read enable, output, low active sdclk2 sd por t 2 clock, output
n3291x ux dn data sheet - 15 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 pin name i/o type description gpd[7] gpio port d bit 7 nwr_ iou nand interface write enable, output, low active sdcmd2 sd port 2 command/response gpd[8] gpio port d bit 8 nd[7] iou nand interface data bit 7 spi0_cs0_ spi port 0 cs0, active low gpa[15] gpio port a bit 15 nd[6] iou nand interface data bit 6 spi0_clk spi port 0 serial clock signal gpa[14] gpio port a bit 14 nd[5] iou nand interface data bit 5 spi0_di spi port 0 serial data input uhl_dm0 usb 1.1 host like port 0 d - signal gpa[13] gp io port a bit 13 nd[4] iou nand interface data bit 4 spi0_do spi port 0 serial data output uhl_dp0 usb 1.1 host like port 0 d+ signal gpa[12] gpio port a bit 12 nd[3] iou nand interface data bit 3 sddat2[3] sd port 3 data bit 3 nd[2] iou nand in terface data bit 2 nd[1] iou nand interface data bit 1 nd[0] iou nand interface data bit 0 sensor/video - in interface sclko iou clock to sensor module, output uhl_dp1 usb host like interface, dp sddat1[1] sd port 1 data bit 1 gpb[0] gpio port b bi t 0
n3291x ux dn data sheet - 16 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 pin name i/o type description spclk iou sensor interface pixel clock, input uhl_dm1 usb host like interface, dm sddat1[0] sd port 1 data bit 0 gpb[1] gpio port b bit 1 shsync iou sensor interface hsync, input i2s_mclk clock to i2s codec, output sdclk1 sd port 1 clock, o utput gpb[2] gpio port b bit 2 svsync iou sensor interface vsync, input i2s_bclk i2s interface clock, input sdcmd1 sd port 1 command/response gpb[3] gpio port b bit 3 sfield iou sensor interface even/odd field indicator, input i2s_ws i2s interf ace word select, output sddat1[3] sd port 1 data bit 3 gpb[4] gpio port b bit 4 spdata[0] iou sensor interface data bit 0, input i2s_dout i2s interface data output sddat1[2] sd port 1 data bit 2 gpb[5] gpio port b bit 5 spdata[1] iou sensor int erface data bit 1, input i2s_din i2s interface data input gpb[6] gpio port b bit 6 spdata[2] iou sensor interface data bit 2, input lvdata[18] lcd interface data bit 18 gpb[7] gpio port b bit 7 spdata[3] iou sensor interface data bit 3, input lv data[19] lcd interface data bit 19
n3291x ux dn data sheet - 17 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 pin name i/o type description gpb[8] gpio port b bit 8 spdata[4] iou sensor interface data bit 4, input spi1_clk spi port 1 clock output in master mode input in slave mode lvdata[20] lcd interface data bit 20 gpb[9] gpio port b bit 9 spdata [5] iou sensor interface data bit 5, input spi1_cs0_ spi port 1 select 0, low active output in master mode input in slave mode lvdata[21] lcd interface data bit 21 gpb[10] gpio port b bit 10 spdata[6] iou sensor interface data bit 6, input spi1_di spi port 1 data input lvdata[22] lcd interface data bit 22 gpb[11] gpio port b bit 11 spdata[7] iou sensor interface data bit 7, input spi1_do spi port 1 data output lvdata[23] lcd interface data bit 23 gpb[12] gpio port b bit 12 i2c interface isck iou i2c interface clock, output gpb[13] gpio port b bit 13 isda iou i2c interface data lmvsync mpu mode vsync, output gpb[14] gpio port b bit 14 lcd/display interface
n3291x ux dn data sheet - 18 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 pin name i/o type description lpclk iou lcd interface pixel clock, output gpb[15] gpio port b bit 15 lhsync iou lcd interface hsync, output, high active gpd[9] gpio port d bit 9 lvsync iou lcd interface vsync, output, high active gpd[10] gpio port d bit 10 lvde iou lcd interface data enable, output, high active gpd[11] gpio port d bit 11 lvdata[ 0] iou lcd interface data bit 0 kpi_so[0] kpi scan out bit 0 gpc[0] gpio port c bit 0 lvdata[1] iou lcd interface data bit 1 kpi_so[1] kpi scan out bit 1 gpc[1] gpio port c bit 1 lvdata[2] iou lcd interface data bit 2 kpi_so[2] kpi scan out bit 2 gpc[2] gpio port c bit 2 lvdata[3] iou lcd interface data bit 3 kpi_so[3] kpi scan out bit 3 gpc[3] gpio port c bit 3 lvdata[4] iou lcd interface data bit 4 kpi_so[4] kpi scan out bit 4 gpc[4] gpio port c bit 4 lvdata[5] iou lcd interface d ata bit 5 kpi_so[5] kpi scan out bit 5 gpc[5] gpio port c bit 5 lvdata[6] iou lcd interface data bit 6 kpi_so[6] kpi scan out bit 6
n3291x ux dn data sheet - 19 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 pin name i/o type description gpc[6] gpio port c bit 6 lvdata[7] iou lcd interface data bit 7 kpi_so[7] kpi scan out bit 7 gpc[7] gpio port c bit 7 lvdata[8] iou lcd interface data bit 8 kpi_so[8] kpi scan out bit 8 spdata[0] sensor interface data bit 0, input gpc[8] gpio port c bit 8 lvdata[9] iou lcd interface data bit 9 kpi_so[9] kpi scan out bit 9 spdata[1] sensor interface dat a bit 1, input gpc[9] gpio port c bit 9 lvdata[10] iou lcd interface data bit 10 kpi_so[10] kpi scan out bit 10 spdata[2] sensor interface data bit 2, input gpc[10] gpio port c bit 10 lvdata[11] iou lcd interface data bit 11 kpi_so[11] kpi scan out bit 11 spdata[3] sensor interface data bit 3, input gpc[11] gpio port c bit 11 lvdata[12] iou lcd interface data bit 12 kpi_so[12] kpi scan out bit 12 spdata[4] sensor interface data bit 4, input gpc[12] gpio port c bit 12 lvdata[13] iou l cd interface data bit 13 kpi_so[13] kpi scan out bit 13 spdata[5] sensor interface data bit 5, input gpc[13] gpio port c bit 13
n3291x ux dn data sheet - 20 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 pin name i/o type description lvdata[14] iou lcd interface data bit 14 kpi_so[14] kpi scan out bit 14 spdata[6] sensor interface data bit 6, input gpc[14] gpio port c bit 14 lvdata[15] iou lcd interface data bit 15 kpi_so[15] kpi scan out bit 15 spdata[7] sensor interface data bit 7, input gpc[15] gpio port c bit 15 lvdata[16] iou lcd interface data bit 16 shsync sensor interface hsync, i nput gpe[0] gpio port e bit 0 lvdata[17] iou lcd interface data bit 17 svsync sensor interface vsync, input lvd_out low voltage detect output gpe[1] gpio port e bit 1 uart interface urtxd iou uart tx data, output spi1_cs1_ spi port 1 device se lect 1, output, low active uhl_dp1 usb 1.1 host lite port 1, d+ isck i2c serial clock gpa[10] gpio port a bit 10 urrxd iou uart rx data, input lmvsync mpu mode vsync, output s2field cmos image sensor field indicator uhl_dm1 usb 1.1 host lite p ort 1, d - isda i2c serial data gpa[11] gpio port a bit 11 spi 0 interface
n3291x ux dn data sheet - 21 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 pin name i/o type description spi0_clk iou spi port 0 clock output in master mode input in slave mode gpd[12] gpio port d bit 12 spi0_cs0_ iou spi port 0 device select 0, low active output in master mode input in slave mode gpd[13] gpio port d bit 13 spi0_di iou spi port 0 data input uhl_dp0 usb 1.1 host lite port 0, d+ gpd[14] gpio port d bit 14 spi0_do iou spi port 0 data output uhl_dm0 usb 1.1 host lite port 0, d - lvd_out low voltage detect output gpd[15] gpio port d bit 15 sd card interface sdclk iou sd port 0 clock, output gpe[7] gpio port e bit 7 sdcmd iou sd port 0 command/response gpe[6] gpio port e bit 6 sddat[0] iou sd port 0 data bit 0 gpe[2] gpio port e bit 2 sddat[1] i ou sd port 0 data bit 1 gpe[3] gpio port e bit 3 sddat[2] iou sd port 0 data bit 2 gpe[4] gpio port e bit 4 sddat[3] iou sd port 0 data bit 3 gpe[5] gpio port e bit 5
n3291x ux dn data sheet - 22 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 pin name i/o type description gpio a gpa[0] iou gpio port a bit 0 s2pclk cmos image sensor pclk gpa[1] iou gpio port a bit 1 s2clko cmos image sensor mclk sd_cd_ sd card detect, input, low active gpa[3] iou gpio port a bit 3 kpi_si[0] kpi scan in bit 0 gpa[4] iou gpio port a bit 4 spi0_cs1_ spi port 0 chip select 1 kpi_si[1] kpi scan out bit 2 gpa [5] iou gpio port a bit 5 uhl_dp0 usb host 1.1 lite port 0, d+ kpi_si[2] kpi scan in bit 2 gpa[6] iou gpio port a bit 6 uhl_dm0 usb host 1.1 lite port 0, d - kpi_si[3] kpi scan in bit 3 rtc (real time clock) rtc_xin (32768hz) i 32768hz crystal in put rtc_xout (32768hz) o 32768hz crystal output rtc_rwake_ i wakeup enable, input, low active rtc_rpwr od power enable, open - drain usb 2.0 device interface ud_cdet i usb device connect detect, input, high active ud_dp io usb 2.0 device d+ ud_dm io u sb 2.0 device d - ud_rext io external resistor connect recommend to connect 12.1k ? resistor to ground for usb 2.0 phy
n3291x ux dn data sheet - 23 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 pin name i/o type description tv out tvdac_tvout o composite/chroma o utput connect an external 75 ? resistor to ground of tvdac as tv terminal impedence spi1_clk o sp i port 1 serial clock i2s_dout o i2s serial data output isck io i2c serial clock gpg[2] io gpio port g bit 2 tvdac_rext io external r esistor c onnection recommend to connect 160 ? resistor to ground of tvdac spi1_cs0_ o spi port 1 chip select i2s_bclk i i2s bit clock gpg[3] io gpio port g bit 3 tvdac_comp o external c apacitor c onnection c onnect 0.1uf capacitor to vdd33 of tvdac spi1_di i spi port 1 serial data input i2s_ws o i2s interface word select, output gpg[4] io gpio port g bit 4 tvdac_vref o reference v oltage o utput c onnect 0.1uf capacitor to ground of tvdac spi1_do o spi port 1 serial data output i2s_mclk o i2s master clock isda io i2c serial data gpg[5] io gpio port g bit 5 adc & touch panel mic_bias i mic adc bias voltage i2s_bclk i i2s bit clock gpg[11] i gpio port g bit 11
n3291x ux dn data sheet - 24 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 pin name i/o type description pgc_vref i pgc voltage reference i2s_mclk o i2s master clock gph[0] io gpio port h bit 0 adc_ain[3] i adc analog input channel 3 adc_ain[2] i adc analog input channel 2 adc_ain[1] i adc analog input chann el 1 mic_n i microphone negative input i2s_di i i2s serial data input gpg[9] i gpio port g bit 9 adc_ain[0] i adc analog input channel 0 mic_p i microphone positive input i2s_ws o i2s interface word select, output gpg[10] io gpio port g bit 10 adc_ tp_yp i touch panel yp spi1_clk o spi port 1 serial clock isck io i2c serial clock gpg[12] io gpio port g bit 12 adc_tp_xp i touch panel xp spi1_cs0_ o spi port 1 chip select gpg[13] io gpio port g bit 13 adc_tp_xm i touch panel xm spi1_di i spi po rt 1 serial data input gpg[14] io gpio port g bit 14 adc_tp_ym i touch panel ym spi1_do o spi port 1 serial data output isda io i2c serial data gpg[15] io gpio port g bit 15 audio dac
n3291x ux dn data sheet - 25 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 pin name i/o type description adac_hpout_r o audio headphone right channel output adac_hpout_l o audio headphone left channel output adac_vref o audio dac reference voltage output recommend to connect 1uf capacitor to ground of audio dac pow er/ground mvdd18 p sdram i/f power (1.8v) mvddq18 p sdram i/f power (1.8v) rtc_vdd33 p rtc core, i/f & 3 2768hz crystal power ud_vdd33 p usb 2.0 phy power (3.3v) ud_vdd12 p usb 2.0 phy power (1.8v) tvdac_vdd33 p tv dac power (3.3v) adc_vdd33 p adc power (3.3v) adc_vss33 g adc ground (0v) adac_hpvdd33 p audio dac headphone driver power (3.3v) adac_hpvss 33 g audio dac headphone driver ground (0v) adac_avdd33 p audio dac power (3.3v) adac_vss33 g audio dac ground (0v) vdd33 p i/o power (3.3v) vdd18 p core logic power (1.8v) vss g ground (0v)
n3291x ux dn data sheet - 26 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 4.2 pin type description type description i input o outpu t od open drain o utput io input / output iod input with pull - d own / output iou input with pull - up / output iosu input with schmitt trigger & pull - up / output p power g ground
n3291x ux dn data sheet - 27 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 5. electrical specifica tion 5.1 absolute maximum rating parameters values ambi ent t emperature - 2 0 c ~ 85 c storage t emperature - 40 c ~ 125 c voltage on any pin - 0.3v ~ 3.6v power s upply v oltage ( c ore l ogic) - 0.5v ~ 1.8 v power s upply v oltage ( i/o buffer ) - 0.5v ~ 4.6v injection c urrent ( l atch - u p t esting) 100ma crystal freque ncy 2mhz ~ 27mhz 5.2 dc characteristics (normal i/o) symbol parameter condition min. typ. max. unit vdd33 i/o buffer post - driver voltage 3.0 3.3 3.6 v vdd12 core logic and i/o buffer pre - driver voltage 3 00mhz 1.08 1.2 1.32 v mvdd18 dram power voltage 1 .7 1.8 1.9 v rtc_vdd rtc power supply 2.0 - 3.6 v i rtc_vdd rtc supply current - 4 - ua v ih input high voltage 2.0 - vdd33+0.3 v v il input low voltage - 0.3 - 0.8 v v t+ schmitt trigger low to high threshold point 1. 5 1.7 1. 9 v v t - schmitt trigger high to low threshold point 0. 9 1. 1 1.2 v
n3291x ux dn data sheet - 28 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 symbol parameter condition min. typ. max. unit i cc core power supply current f cpu = 3 0 0mhz , mclk = 1 5 0mhz, vdd 12 = 1. 2 v - tbd - ma i l input leakage current - 20 ma i oz tri - state output leakage current tbd ua r pu pull - up resistor 61 76 112 k ? r pd pull - down resistor 57 80 156 k ? v ol output low voltage - - 0.4 v v oh output high voltage 2.4 - - v i ol low level output current 4 w i/o, v ol = 0.4v 4.2 6.5 8 ma 8 w i/o, v ol = 0.4v 8.4 13.0 16.0 ma i oh high level output current 4 w i/o, v oh = 2.4v 4.7 9.6 14.9 ma 8 w i/o, v oh = 2.4v 9.4 19.2 29.8 ma
n3291x ux dn data sheet - 29 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 5.3 audio dac characteristic s c onditions: avdd: 3.3v, vdd: 1.2v, t a : 25 , fsignal: 1khz , fsampling: 48k hz , mclk:256xfsampling parameter min typ max unit operating voltage avdd 3.0 3.3 3.6 v operating voltage vdd 1.08 1.2 1.34 v reference voltage - a vdd/2 - v line output resolution - 16 - bit l - channel total harmonic disto rtion (thd) - - 90 - 76 db r - channel total harmonic distortion (thd) - - 90 - 76 db dynamic range ( - 60db input, a - weighted) 90 101.6 - db snr (a - weighted) 90 101.6 - db channel separation - 100 - db channel matching - 0.2 - db full scale output voltage - avdd(3.3) - vrms load resistor 10 - - kohm load capacitor - - 50 pf analog mute - 100 - db headphone output maximum output power (po) @ 32ohm load - - 31 mw maximum output power (po) @ 16ohm load - - 62 mw l - channel snr (a - weighted) 90 96 - db r - c hannel snr (a - weighted) 90 96 - db l - channel thd @ 32ohm load , po=10mw - - 76 - 70 db r - channel thd @ 32ohm load, po=10mw - - 76 - 70 db power supply current in normal mode (including pll, no loading) avdd(3.3v) - 8.7 - mw vdd (1.2v) - 0.7 - mw
n3291x ux dn data sheet - 30 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 5.4 adc chara cteristic s parameter min. typ. max. unit sar adc input voltage range 3.0 - 3.6 v resolution of adc - - 10 bit signal - to - noise plus distortion of adc from line in - - 60 - db integral non - linearity of adc - 2.0 - lsb differential non - linearity of adc - 0. 8 - lsb no missing code - 10 - bit ad conversion rate=adcclk/16 - - 150 k hz 5.5 ac characteristic s ( digital interface ) 5.5.1 clock input characteristics xin t xin t xinwl t xinwh f xin = 1 / t xin xin duty = t xinwh / ( t xinwh + t xinwl ) symbol parameter min. typ. max. unit f xin clock input frequency - 12 / 27 - mhz xin duty clock input duty cycle 45 50 55 %
n3291x ux dn data sheet - 31 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 5.6 thermal characteristics of s lqfp - 128 package
n3291x ux dn data sheet - 32 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 6. o r dering information par t no. package type description n32916u1 dn lqf p - 128 , mcp cost - effective package with 32mbx16 ddr2 insid e, without ovg accelerator . n32916u2dn lqfp - 128, mcp cost - effective package with 32mbx16 ddr2 inside and ovg accelerator . n32915 u3 dn lqfp - 128, mcp cost - effective package with 16 mbx16 ddr2 insid e, without ovg accelerator . n32915 u4 dn lqfp - 128, mcp cost - effective packag e with 16 mbx16 ddr2 inside and ovg accelerator . 6.1 part number definition 6.2 differen ce between n3291x u1 (3) dn and n3291 xu2 (4) dn n3291x u1dn /n3291xu3dn n3291x u2dn /n3291xu4dn openvg(ovg) accelerator - v
n3291x ux dn data sheet - 33 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 7. package outline 7.1 128 l lqfp ( 14x14 x1.4mm body, 0.4mm pi tch)
n3291x ux dn data sheet - 34 - nuvoton technology corp. release date : jun . 201 3 http:// www.nuvoton.com/ revision a 3 8. revision history version date description a 0 aug . 1 , 20 1 2 ? ? initial release . a1 oct. 1, 2012 ? ? change operation temperature range ? ? add n32916u2dn ordering information. a2 oct. 25, 2012 ? ? add part number definition a3 j un. 1, 2013 ? ? add n32915uxdn parts information ? ? add mvdd18 votage range important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily inju ry or severe property damage. such applications are deemed , ?insecure usage?. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or opera tion of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customer?s risk, and in the even t that third parties lay claims to nuvoton as a result of customer?s insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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