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fn6329 rev 2.00 page 1 of 14 jul 29, 2013 fn6329 rev 2.00 jul 29, 2013 isl58328 5v wide optical spectrum laser power monitor ic datasheet the isl58328 photo sensor ic has a wide optical spectral sensitivity from 400nm to 1000nm. it is good for multiple light sources application, such as laser based projectors. isl58328 has two banks of three sets of gain registers. for a pico- projector application, the two banks of gain resistors can be used to monitor bias level and peak level of each wavelength. bank switching is done by applying a ttl compatible logic signal to hl pin. the three sets of gain registers can be used to adjust optical-to-electrical conversion gain for each red, green, and blue laser or any wavelength in a spectral range for application. the isl58328 is a single die device that has a photo detector of 0.7mm diameter in the center of the die. photo current signal is amplified through tia, fine gain amplifier, and output drivers to convert from current to voltage. the output of isl58328 can be configured to be either differential or single -ended. gain changing according to each wavelength is done through 3-wire interface. registers can be updated in real time while the device is in operation. the isl58328 operates from a single +5.0v supply. it is available in a space-saving 9 ball glass top bga package. related literature ? an1356 , ?serial bus specification? ? an1448 , ?bd/hd-dvd/dvd/cd pmic? features ? high sensitivity from 400nm to 1000nm with patented technology for improved blue photo response ? differential voltage output or single-ended output ? internal output reference or external output reference ? single +5v power supply ? serial interface for gain calibration ? fast settling time < 20ns ? wide signal bandwidth > 80mhz ? wide signal gain dynamic range > 25db ?low power consumption ? low output offset < 50mv ? small 9-ball optical chip scale package (ocsp) (2.2mmx2.2mm) ? spi 3-wire serial interface applications ? optical power monitoring ? laser based pico-proje ctors or projection tv ? laser auto power control for laser based application ? white balance for led based lcos and dlp pico-projectors ito driver lcos driver laser diode driver power converter digital circuits dc/dc laser diode video front end and video processor 3.3v 2.5v 1.8v 1.2v 5.0v mcu oeic isl58328 optic feedback lcos panels figure 1. application block diagram o b s o l e t e p r o d u c t n o r e c o m m e n d e d r e p l a c e m e n t co n t a c t o u r t e ch n i ca l s u p p o r t c e n t er a t 1 - 88 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t sc
isl58328 fn6329 rev 2.00 page 2 of 14 jul 29, 2013 block diagram iv amp slow tail control outn vdd vref 0.1f gnd 0.1f +5.0v outp 10k serial interface sclk sdata gnd gnd sen power & control slowtail_red 0x1a 0 1 2 3 4 5 6 7 12 7 0x10-5 1 0 0 0x10-4 x 1 0 blu red grn select 12 12 slowtail_blu 0x1e 0 1 2 3 4 5 6 7 slowtail_ grn 0x1b 0 1 2 3 4 5 6 7 7 7 tia_gain 0x1ch 0 1 2 3 4 5 6 7 tia gain control gain control slow tail reference control 0x10h 0 1 2 3 4 5 6 7 + - + - + - + - 0 1 blue gain hi (12bits) reg 0x12[7:0] +reg 0x11[7:4] 0 1 blue gain lo (12bits) reg 0x13[7:0] +reg 0x11[3:0] 0 1 red gain hi (12bits) reg 0x15[7:0] +reg 0x14[7:4] red gain lo (12bits) reg 0x16[7:0] +reg 0x14[3:0] green gain hi (12bits) reg 0x18[7:0] +reg 0x17[7:4] green gain lo (12bits) reg 0x19[7:0] +reg 0x17[3:0] 0 1 2 h/l hl chip_en tia_h tia_l select latch latch
isl58328 fn6329 rev 2.00 page 3 of 14 jul 29, 2013 pin configuration isl58328 (9 ball ocsp) top view 3 2 1 b a c vdd outn outp vss hl vref sen sclk sdata pd pin descriptions pin number pin name type description a1 sdata digital i/o serial interface data, bi-directional b1 vref analog input reference voltage input c1 outp analog output positive swing analog output a2 sclk digital input serial interface clock b2 hl digital input high/low gain mode selection, h = high gain, l = low gain. use in conjunction with reg 0x10 bit 7. * for hardware switching, reg 0x10 bit 7 must be set to 1. * for soft switching, this pin must be high. c2 outn analog output negative swing analog output a3 sen digital input serial interface enable b3 vss power gnd c3 vdd power +5.0v supply pd optical input photo diode ordering information part number (notes 1, 2, 3, 4) part marking package tape & reel (pb-free) pkg. dwg. # ISL58328CIZ-T7 123z (backside of die) 9 ball ocsp s3x3.9 ISL58328CIZ-T7a 123z (backside of die) 9 ball ocsp s3x3.9 isl58328ciz-eval evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free wlcsp and bga packaged products employ special pb-free material sets; molding compounds/die attach mat erials and snagcu - e1 solder ball terminals, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free wlcsp and bga packaged products are msl classified at pb-free pe ak reflow temperatures that meet or exceed the pb-free requirem ents of ipc/jedec j std-020. 3. please refer to tb478 for solder profile. 4. for moisture sensitivity level (msl), please see device information page for isl58328 . for more information on msl please see tech brief tb363 .
isl58328 fn6329 rev 2.00 page 4 of 14 jul 29, 2013 absolute maximum rating s thermal information supply voltage (+5.0v to gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0v maximum cmos input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.6v maximum output voltage . . . . . . . . . . . . . . . . . . . . . . v ss - 0.3 to v dd + 0.3 esd rating human body model (per mil-std-883 method 3015.7) . . . . . . . . . . 2kv machine model (per eiaj ed-4701 method c-111) . . . . . . . . . . . . . 200v latch up (tested per jesd-78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 9 ld ocsp (note 5). . . . . . . . . . . . . . . . . . . . 125 na storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-25c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty note: 5. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. dc electrical specifications v dd = 5.0v, t a = +25c unless otherwise specified. parameter description conditions min (note 6) typ max (note 6) unit v dd +5.0v supply voltage range 4.5 5.0 5.5 v i vdd1 supply current no incident light, in nomal mode 20 25 ma i vdd2 supply current no incident light, in sleep mode 600 a v ofs output p offset referenced to vref no incident light -50 10 +50 mv v ref_i common mode output voltage internal vref generator 1.75 2.10 2.35 v v il cmos input low sen, sdata, sclk, and hl pins 0 0.8 v vi h cmos input high sen, sdata, sclk and hl pins 2.4 3.6 v v ol cmos output low sdata; i load = 3ma 0.8 v v oh cmos output high sdata; i load = 3ma 2.5 v note: 6. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. ac electrical specifications v dd = 5.0v, t a = +25c unless otherwise specified. parameter description conditions min typ max unit bw bandwidth outp, outn (not differential) -3db rbw = 30khz 85 mhz v outmax differential mode output voltage (outp) ? (outn) linear output 2.95 v p-p
isl58328 fn6329 rev 2.00 page 5 of 14 jul 29, 2013 sensitivity v dd = 5.0v, t a = +25c unless otherwise specified. parameter description conditions min typ max unit gain 00 tia lowest gain 0db fine gain adjustment, 7ffh differential output 350 450 550 mv/a gain 01 tia 2nd lowest gain 0db fine gain adjustment, 7ffh differential output 700 890 1110 mv/a gain 10 tia 2nd highest gain 0db fine gain adjustment, 7ffh differential output 1400 1790 2170 mv/a gain 11 tia highest gain 0db fine gain adjustment, 7ffh differential output 3700 4850 6020 mv/a gain fine_max maximum fine gain for both high gain and low gain channels compared to 0db fine gain setting, 7ffh 19 db gain fine_min minimum fine gain for both high gain and low gain channels compared to 0db fine gain setting, 7ffh -5.5 db current to optical conversion: optical sensitivity is not tested in production. gain parameters were obtained using input test currents. following factors are used to convert current to optical power. i2o 450nm current to optical conversion (450nm) bench data; measured on typical devices 0.27 a/w i2o 530nm current to optical conversion (530nm) bench data; measured on typical devices 0.26 a/w i2o 640nm current to optical conversion (640nm) bench data; measured on typical devices 0.38 a/w serial interface ac performance v dd = 5.0v, t a = +25c unless otherwise specified. parameter description conditions min typ max unit f ser1 sclk operating range deglitch disable(control[6]=0) 50 mhz f ser2 sclk operating range deglitch enable(control[6]=1) 2 mhz t eh sen ?h? time 320 ns t el sen ?l? time 40 ns t ersr sen rising edge to the first sclk rising edge 10 ns t cds sdio set up time 10 ns t cdh sdio hold time 10 ns t sref last sclk rising edge to sen falling edge 10 ns t cc sclk cycle time 20 ns duty sclk ?h? duty cycle 50 % t cdd sdio output delay 4ns t edh sdio output hold time 2ns input leakage input leakage for sclk, sdata, and sen pin -10 10 a
isl58328 fn6329 rev 2.00 page 6 of 14 jul 29, 2013 i/o pins equivalent circuits pins type equivalent circuit sdata sclk sen digital i/o digital input digital input h/l digital input vref analog input outp outn analog output vdd power vdd pad vss vdd pad vss 500 vdd pad vss 20k vdd pad vss 50 vdd vss esd clamp
isl58328 fn6329 rev 2.00 page 7 of 14 jul 29, 2013 application information input optical power the isl58328 has a photo detector in an octagon shape (shown in pd pattern) with 700m diameter. it is sensitive from 400nm to 1000nm for light monitoring application, which is a perfect choice for light automatic power control. this wide range of sensitivity also allows the isl5832 8 to be used for white balance control in led systems such as led based lcos or dlp pico projectors. current generated by the photo detector, is amplified by a trans-impedance amplifier (tia). the tia has four feedback resistors. users can choose which feedback resistor is used for high or low gain applications by setting the tia_gain register. once a proper resistor is selected for the required tia gain, optical signal is then amplified by the tia that feeds into the fine gain stage. high gain channel and low gain channel tia gains can be individually set through the tia register. the high gain and low gain channels have the same gain adjustment range (25db) and can be individually controlled. in applications where laser power is modulated between 2 power levels, users can choose between high gain channel for the low power level and low gain channel for the high power. it can provide the best resolution when power is low and not saturate the amplifier circuit when power is high. if users don?t need to monitor two power levels, there is no need to switch between high gain channel and low gain channel.the selection of high gain or low gain signal path can be done with fast hardware switching or by setting register bit ?h/l?. when changing high gain or low gain signal paths by hardware switching, ?h/l? bit (reg 0x10 bit [7]) needs to be ?1?. when changing it with register (soft switching), hl pin needs to be driven by digital high because hl and ?h/l? are and for tia gain control. regardless of channel gain settings, the dynamic range of tia is determined by the photo detector sensitivity with respect to wavelength. for example in 445nm application when tia = 01b gain is selected, the maximum input optical power is limited to 2mw for blue light laser; but this limitation is re duced to 1.45mw with 638nm laser. this is because the photo detector has higher optical-to-electrical conversion efficiency to longer wavelength. higher than the maximum input limitation, the tia or whole device will still be working but it may yield distorted output and a long fall time, increasing the time that the circuit used to recover from saturation. detector pattern gain control the isl58328 channel gain is set through a 12-bit dac, separated into 2 registers. each wavelength has two 12-bit gain registers, one for high gain application and the other for low gain application. the selection of high gain or low gain is done by fast hardware switching through hl pin or ?h/l? register bit. all gain registers of high gain and low gain channels are capable of update at anytime through the serial interface. the 12-bit gain registers provides total 25db of adjustment range, +19db to - 5.5db reference to fine gain setting 7ffh. all settings will be reset to default at power-on. users need to load gain settings after isl58328 is powered up. over all differential output signal gain can be obtained by using equations 1 through 3: blue laser diode(445nm) red laser diode (638nm) green laser diode(530nm) where: code is 12 bits gain code in decimal (0 ~ 4095) table 1. maximum input power vs tia resistor tia_gain (tia_h/tia_l) (445nm) mw (638nm) mw (532nm) mw 00b 5.0 3.65 5.30 01b 2.5 1.82 2.65 10b 1.25 0.91 1.33 11b 0.44 0.32 0.47 table 2. tia_h, tia_l settings tia factor in equation 00b 500 01b 1000 10b 2000 11b 5400 300m 300m 700m 700m gain (mv/ ? w ? 1.88 tia ? 256 code + ------------------------------ - = (eq. 1) gain (mv/ ? w ? 2.57 tia ? 256 code + ------------------------------ - = (eq. 2) gain (mv/ ? w ? 1.76 tia ? 256 code + ------------------------------ - = (eq. 3)
isl58328 fn6329 rev 2.00 page 8 of 14 jul 29, 2013 output configuration the isl58328 has two differential outputs: outp is a positive and outn is a negative swing output. outp and outn outputs are referenced to vref. vref can be externally supplied or internally generated 2.1v. with respect to the input optical signal, outp swings up from re ference voltage and outn swings down from reference voltage. both outp and outn have the same linear output dynamic range up to 1.4v swing from reference voltage. when using external reference voltage, users need to adjust gain registers to set proper channel gain to prevent output saturation. to use isl58328 as a single-ended output, users can take either outp or outn signal and load another output with equivalent resistor and capacitor load to keep both outputs with the same load condition. however, it won?t be an issue to leave anot her output floating. when using isl58328 as a single-ended output device, external reference voltage is necessary because the vref pin doesn?t have strong driving capability. it is not recommended to use vref as a reference source to drive other devi ces. to obtain the best signal quality at the input of the afe or video processor, it is recommended to keep outp and outn traces in parallel and to keep them with same length, same width, and route. if output signals from isl58328 need to travel through a flex cable to afe or video processor, to match with the impedance of flex cable, a 50 ? serial termination resistor cl ose to outp and outn output pins may be necessary; thus the best value should be determined according to the actual application. slow tail compensation photons at longer wavelength wi ll penetrate deeper into the photo detector structure than shorter wavelengths. it takes longer for electron-hole pairs to become photo current and results in a longer tail for the pulse output, called slow tail. longer wavelength light such as 638nm or ir has more visible slow tail effect than blue laser. to minimize the slow tail effect, isl58328 has incorporated intersil?s proprietary slow tail compensation technology. there are three registers for slow tail compensation adjustment for each wavelength (such as 638nm, 532nm, and 445nm). the slow tail compensation function is not limited to the specific wavelength listed previously; it is used in conjunction with the selected fine gain registers. users can disable slow tail compensation by setting bit 7 (msb) of the register to ?0?. this function can also be used to improve the quality of pulse output waveforms due to impedance mismatch from oeic outputs to the flex connector. one example is to improve tr/tf or to minimize overshoot. layout consideration when using differential output, layout outp and outn traces next to each other and ground traces should be placed to other side of outp and outn traces. when using single-ended, layout reference trace needs to be next to output signal trace and layout a ground trace at the other side of the output. for best result, dual layer flex with signal on one side and ground plane on other side is a must. reference voltage the isl58328 has a reference vo ltage generator intended to generate 2.1v reference voltage for all circuit blocks. output is biased at internal reference volt age automatically when vref pin is left floating. when a dc voltage is applied to vref pin, outp and outn will be biased at exte rnal reference automatically. external reference is limited to a range from 1.5v to 2.5v. using voltage outside of this range will yield distorted outputs. when using external reference voltage, good decoupling is very important to prevent noise coupling into vref. a 0.1f ceramic capacitor placed as close to vref pin as possible is recommended to decouple vref to ground. power supply decoupling due to the current being switched rapidly at outp and outn, it is important to ensure that the power supply is well decoupled to ground. during output switching, the v dd undergoes severe current transients, thus every effo rt should be made to decouple the v dd as close to the package as possible. without proper power supply decoupling there could make poor rise/fall times, overshoot, and poor settling response. outp outn > 1v >1v offset < 50mv v ref = 2.1v figure 2. outp/outn above minimal of 1v, linearity is no longer guaranteed
isl58328 fn6329 rev 2.00 page 9 of 14 jul 29, 2013 sensitivity curves figure 3. normalized spectral response vs wavelength figure 4. optical power input vs output (red led 620nm; green led 532nm; blue led 460nm) 0 0.2 0.4 0.6 0.8 1.0 1.2 300 400 500 600 700 800 900 1000 wavelength (nm) spectral response 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 100 200 300 400 500 600 700 800 input (w) v out v rt gnd (v) 450nm p 530nm p 640nm p 450nm n 530nm n 640nm n register map addr name b7 b6 b5 b4 b3 b2 b1 b0 default access 00h id0 device id 28h r 01h id1 device option device version e0h r 02h id2 reserved 00h r 03h dsr device select register (dsr) 43h rw 04h reserved for multi-chip protocol 05h reserved for multi-chip protocol 06h reserved for multi-chip protocol 07h reserved for multi-chip protocol 08h reserved for multi-chip protocol 09h reserved for multi-chip protocol 0ah reserved for multi-chip protocol 0bh reserved for multi-chip protocol 0ch reserved for multi-chip protocol 0dh reserved for multi-chip protocol 0eh reserved for multi-chip protocol 0fh reserved for multi-chip protocol 10h control h/l deglitch blue red/green test_en x x chip_en 46h rw 11h b _gain0 blue_h[3: 0] blue_l[3:0] ffh rw 12h b_h_gain blue_h[11:4] 7fh rw 13h b_l_gain blue_l[11:4] 7fh rw 14h r_gain0 red_h[3:0] red_l[3:0] ffh rw 15h r_h_gain red_h[11:4] 7fh rw 16h r_l_gain red_l[11:4] 7fh rw 17h green_gain0 green_h[3:0] green_l[3:0] ffh rw 18h green_h_gain green_h[11:4] 7fh rw 19h green_l_gain green_l[11:4] 7fh rw
isl58328 fn6329 rev 2.00 page 10 of 14 jul 29, 2013 register description 1ah st_red st_en_red st_time_red[2:0] x st_mag_red[2:0] 00h rw 1bh st_green st_en_green st_time_gr een[2:0] x st_mag_green[2:0] 00h rw 1ch tia_gain x x x x tia_h[1:0] tia_l[1:0] 00h rw 1dh reserved 1eh st_blue st_en_blue st_time_blue[2:0] x st_mag_blue[2:0] 00h rw note: all gain registers in this table can be used for any wave length in spectral range from 390nm to 1000nm, not limited to wa velengths specified. register map (continued) addr name b7 b6 b5 b4 b3 b2 b1 b0 default access table 3. id0 (addr = 00h) register description id0 device id, read only, code = 28h table 4. id1 (addr = 01h) register description device option device option code, read only, code = e0h device version device version code, read only, code = 0h table 5. dsr (addr = 03h) register description dsr (note 7) device selection code, used for intersil universal serial interface protocol, code = 43h note: 7. dsr register is to allow multiple devices to share same the spi interface. each device on the spi interface bus has its own dsr value, like a device address in i 2 c protocol. master sends dsr to the spi bus, only one device with a matched dsr will response to the following commands and data, remaining devices on the bus will ignore commands and data; pull the interface to hi-z. for more information please contact intersil for universal serial interface specification document. table 6. control (addr = 10h) register description h/l bit [7] high gain or low gain channels selection. used in conjunction with hl pin. 1b: high gain channel 0b: low gain channel default: 0b deglitch bit [6] 1b: enable serial interface deglitch function 0b: disable serial interface deglitch function default: 0b blue bit [5] 1b: device works in blue mode (regardless of red/green bit setting) 0b: device works in either red or green mode, depends on red/green register bit setting default: 0b red/green bit [4] 0b: green 1b: red default: 0b (green mode) test_en bit [3] to enable a chip test function (for intersil internal use only) 1b: enable test function 0b: disable test function default: 0b chip_en bit [0] to enable or disable is l58328. when disabled all outputs are in hi-z 1b: enable 0b: disable (sleep mode) table 7. b_gain0 (addr = 11h) register description blue_h[3: 0] bits [7:4] lower 4 bits of blue light high gain channel fine gain control blue_l[3: 0] bits [3:0] lower 4 bits of blue light low gain channel fine gain control table 8. b_h_gain (addr = 12h) register description blue_h[11:4] bits [7:0] high 8 bits of blue light high gain channel fine gain control
isl58328 fn6329 rev 2.00 page 11 of 14 jul 29, 2013 table 9. b_l_gain (addr = 13h) register description blue_l[11:4] bits [7:0] high 8 bits of blue light low gain channel fine gain control table 10. red_gain0 (addr = 14h) register description red_h[3: 0] bits [7:4] lower 4 bits of red light high gain channel fine gain control red_l[3: 0] bits [3:0] lower 4 bits of red light low gain channel fine gain control table 11. red_h_gain (addr = 15h) register description red_h[11:4] bits [7:0] high 8 bits of red light hi gh gain channel fine gain control table 12. red_l_gain (addr = 16h) register description red_l[11:4] bits [7:0] high 8 bits of red light low gain channel fine gain control table 13. green_gain0 (addr = 17h) register description green_h[3:0] bits [7:4] lower 4 bits of green light high gain channel fine gain control green_l[3:0] bits [3:0] lower 4 bits of green light low gain channel fine gain control table 14. green_h_gain (addr = 18h) register description green_h[11:4] bits [7:0] high 8 bits of green light high gain channel fine gain control table 15. green_l_gain (addr = 19h) register description green_l[11:4] bits [7:0] high 8 bits of green light low gain channel fine gain control table 16. st_red (addr = 1ah) register description st_en_red bit [7] red light slow tail compensation control 1b: enable 0b: disable (when disable, st_time_red and st_mag_red are reset to 000b) st_time_red bits [6:4] red light slow tail compensa tion time constant control st_mag_red bits [2:0] red light slow tail compensation magnitude control table 17. st_green (addr = 1bh) register description st_en_green bit [7] green light slow tail compensation control 1b: enable 0b: disable (when disabled, st_time_green and st_mag_green are reset to 000b) st_time_green bits [6:4] green light slow tail compensation time constant control st_mag_green bits [2:0] green light slow tail compensation magnitude control table 18. tia_gain (addr = 1ch) register description tia_l[1:0] bits [3:2] tia gain selection in high gain channel application 00b: lowest gain 01b: 2nd lowest gain 10b: 2nd highest gain 11b: highest gain tia_h[1:0] bits [1:0] tia gain selection in low gain channel application 00b: lowest gain 01b: 2nd lowest gain 10b: 2nd highest gain 11b: highest gain table 19. st_blue (addr = 1eh) register description st_en_blue bit [7] blue light slow tail compensation control 1b: enable 0b: disable (when disable, st_time_blue and st_mag_blue are reset to 000b) st_time_blue bits [6:4] blue light slow tail comp ensation time constant control st_mag_blue bits [2:0] blue light slow tail compensation magnitude control
isl58328 fn6329 rev 2.00 page 12 of 14 jul 29, 2013 serial interface protocol writing cycle into isl58328 d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 0 t cds t cdh t cc t ch t cl t ersr sen sclk sdata t sref r/w bit, address bits, and data bits are cloc ked into isl58328 at rising edge of sclk. r/w reading cycle fr om isl58328 d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 1 t cds t cdh t cc t ch t cl t ersr sen sclk sdata t sref hi-z t cdd r/w bit and address bits are clocked into isl58328 at rising edge of sclk. data bits are clocked out from is l58328 at falling edge of sclk. the last bit (d0) of data is clocked by the falling edge of sen. t eh t eh t el t el
fn6329 rev 2.00 page 13 of 14 jul 29, 2013 isl58328 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2006-2013. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change july 29, 2013 fn6329.2 change products information verbiage to about intersil. february 21, 2012 fn6329.1 added ISL58328CIZ-T7a to ?ordering information? on page 3. december 8, 2010 fn6329.0 initial release
isl58328 fn6329 rev 2.00 page 14 of 14 jul 29, 2013 package outline drawing s3x3.9 3x3 array 9 bump optical chip scale package (ocsp) rev 7, 10/10 notes: bottom view side view typical recommended land pattern top view seating plane 31 2 b c a b a a1 a1 c 0.10 c 0.10 c c cab m m 0.15 0.08 5 2.155 0.025 2.155 0.025 1.30 0.65 1.30 0.65 0.825 0.045 1.045 max 0.30 0.03 (1.30) (0.65) (1.30) (0.65) (0.30) 0.16 0.03 dimensions are in millimeters. dimensioning and tolerancing conform to asme y 14.5m-1994 primary datum c and seating plan e are defined by the spherical 1. 3. 2. 4. pin "a1" is marked on the top and bottom side adjacent to the 5. crowns of the contact balls. dimensions in ( ) for reference only. dimension is measured at the maximum ball diameter. a1 ball. corner corner

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