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9.3 ghz latched comparator with rspecl output stage data sheet HMC674LC3C / hmc674lp3e rev. k document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2016 analog devices, inc. all rights reserved. technical support www.analog.com features equivalent input b andwidth: 9.3 ghz typical propagation delay: 85 ps typical overdrive and slew rate dispersion: 10 ps typical input signal m inimum pulse width: 60 ps typical resistor programmable hysteresis differential latch control power dissipation: 140 mw typical 16- terminal , 3 mm 3 mm , ceramic leadless chip carrier (lcc) 1 6 - lead lead frame chip scale package ( l fcsp) applications automatic test equipment (ate) applicat ions high speed instrumentation digital receiver systems pulse spectroscopy high speed trigger circuits clock and data restoration functional block dia gram 12 11 10 1 3 4 9 2 6 5 7 8 16 15 14 13 vtp 50 50 inp inn vtn v cco v ee hys rtn v cci q q v cco v cci le le nic v ee package base HMC674LC3C/hmc674lp3e 14861-001 figure 1. HMC674LC3C / hmc674lp3e functional block diagram general description the HMC674LC3C / hmc674lp3e are silicon germanium ( sige ), monolithic, ultrafast comparator s that feature reduced swing positive emitter - coupled logic (rspecl) output drivers and latch inputs . th e s e comparator s support 10 gbps operation and provid e 85 ps propagation delay and an input signal minimum pulse width of 60 ps with 0.2 ps rms of r andom jitter (rj) . overdrive and slew rate dispersion is typically 10 ps, making the HMC674LC3C / hmc674lp3e ideal for a wide range of applications from ate to broadband communications. the rspecl output stages directly drive 400 mv into a 50 ? resistor terminated to v tt = (v cco ? 2.0 v) , where v tt is the pecl termination voltage (s ee figure 16 ) . the HMC674LC3C / hmc674lp3e feature a high speed latch and programmable hysteresis . th e s e device s can operate in either latch mode or as a tracking comparator.
HMC674LC3C/hmc674lp3e data sheet rev. k | page 2 of 14 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision h istory ............................................................................... 2 specifications ..................................................................................... 3 latch enable (le/ le ) specifications ......................................... 3 dc output specifications ........................................................... 3 ac specifications .......................................................................... 4 power supply specifications ........................................................ 4 timing descriptions .................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution ...................................................................................6 pin configurations and function descriptions ............................7 interface schematics .....................................................................8 typical performance characteristics ..............................................9 theory of operation ...................................................................... 10 power sequencing ...................................................................... 10 applications information .............................................................. 11 evaluation printed circuit board (pcb) ................................. 11 application circuits ................................................................... 12 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 revision hi story two hittit e mircrowave product data sheet s ha ve been reformatted to the styles and standards of analog devices, inc. , and combined into one data sheet. 1 2 /2016 v 1 2.0 6 1 6 (HMC674LC3C and hmc674lp3e) to rev. k updated format .................................................................. universal changes to title, features section, and general description section ................................................................................................ 1 changes to table 7 ............................................................................ 6 changes to table 8 ............................................................................ 7 changes to figure 10 ........................................................................ 9 changed operational description section to theory of operation section ........................................................................... 10 changes to figure 15 and table 9 ................................................. 12 updated outline dimensions ....................................................... 1 3 changes to ordering guide .......................................................... 1 3
data sheet HMC674LC3C/hmc674lp3e rev. k | page 3 of 14 specifications t a = 25 c, v cci = 3.3 v, v cco = 2.0 v, v ee = ? 3 v, v tt = 0 v, unless other wise not ed. table 1 . parameter min typ max unit input voltage range ?2 +2 v differential voltage ?1.75 +1.75 v offset voltage (v os ) 5 mv temperature coefficient 15 v/c bias current 15 a temperature coefficient 50 na/c offset current 4 a impedance 50 ? common - mode 350 k? differential 15 k? active gain 48 db common - mode rejection ratio (cmrr) 80 db hysteresis, r hys = i nfinity 1 mv latch enable (le/ le ) specification s table 2 . parameter symbol min typ max unit test conditions/comments latch enab le ( le/ le ) input impedance 8 k? each pin to output delay t plol , t plo h 85 ps input overdrive voltage ( v od ) = 200 mv minimum pulse width t pl 20 ps v od = 200 mv input range 1.6 2.4 v v od = 200 mv latch enable ( le/ le ) time setup t s 45 ps v od = 200 mv hold t h ? 42 ps dc output specifications v cco = 2.00 v, v tt = 0 v , unless otherwise noted. table 3 . parameter symbol min typ max unit output voltage high level v oh 1.03 1.09 1.14 v low level v ol 0.65 0.71 0.81 v differential swing 440 760 980 mv p -p
HMC674LC3C/hmc674lp3e data sheet rev. k | page 4 of 14 ac specifications table 4 . parameter min typ max unit test conditions/comments propagation delay ( t pdl, t pd , t pdh ) 80 85 110 ps v od = 500 mv temperature coefficient 0.45 ps/c skew (rising to falling transition) 10 ps v od = 500 mv v od 1 dispersion 10 ps 50 mv < v od < 1 v propagation delay (t pd ) vs. input common - mode v o ltage (v cm ) dispersion 8 ps v od = 500 mv , ?1.75 v < v cm < +1.75 v noise (return to input, rti) 5.9 nv/hz equivalent input bandwidth (bw eq ) 2 8.6 9.3 12 ghz jitter 10 gbps with 100 mv over drive deterministic 2 ps p -p random 0.2 ps rms input signal minimum pulse width 60 ps v cm = 0 v, 100 mv overdrive q/ q time from 20% to 80% rise 24 ps fall 15 ps 1 v od is the input overdrive volta ge, for example, (v inp ? v inn ? v os ), where v os is the input offset voltage. 2 equivalent input bandwidth is calculated by ) ( 2 2 eq trin trcomp bw ? 0.22/ = where: trin is the 20%/80% transition time of a quasi gaussian signal applied to the comparator input. trcomp is the effective transition time digitized by the comparator. power supply specifications table 5 . parameter symbol min typ max unit v o ltage power supply voltage input stage v cci 3.135 3.3 3.465 v power supply voltage output stage v cco 1.8 3.3 3.465 v negative power supply (?3 v) v ee ?3.15 ?3.0 ?2.85 v current supply input i cci 9 ma supply output i cco 45 ma v ee i ee 19 ma power dissipation p d 140 mw power supply rejection ratio psrr v cci 38 db v ee 38 db
data sheet HMC674LC3C/hmc674lp3e rev. k | page 5 of 14 timing descriptions table 6 . parameter symbol description input to output high delay t pdh the p ropa gation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low to high transition. input to output low delay t pdl the p rop agation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high to low transition. latch enable ( le/ le ) to output high delay t ploh the p ropagation delay measured from the 50% point of the latch enable ( le/ le ) signal high to low transition to the 50% point of an output low to high transition. latch enable ( le/ le ) to output low delay t plol the p ropagation delay measured from the 50% point of the latch enable ( le/ le ) signal high to low transition to the 50% point of an output high to low transition. minimum hold time t h the m inimum time after the positive transition of the latch enable ( le/ le ) signal that the input signal must remain unchanged to be acquired and held at the outputs. minimum latch enable ( le/ le ) pulse width t pl the m inimum time that the latch enable ( le/ le ) signal must be low to acquire an input signal change. minimum setup time t s the m inimum time before the positive transition of the latch enable ( le/ le ) signal that an input signal change must be present to be acquired and held at the outputs. output rise time t r the a mount of time required to transition from a low to a high output as measured at the 20% and 80% points. output fall time t f the a mount of time require d to transition from a high to a low output as measured at the 20% and 80% points. input overdrive voltage v od the d ifference between the input voltages ( v inp and v inn ). timing diagram latch enable (le) differential input voltage latch enable (le) q output q output latch track latch latch 50% 50% 50% v cm v os track t h v in v od t f t s t pl t pdl t pdh t ploh t plol t r 14861-002 figure 2. timing diagram
HMC674LC3C/hmc674lp3e data sheet rev. k | page 6 of 14 absolute maximum rat ings table 7 . parameter rating supply voltage input (v cci to gnd) ?0.5 v to +4 v output (v cco to gnd) ?0.5 v to +4 v positive differential (v cci to v cco ) ?0.5 v to +3.3 v v ee supply to gnd ?3.3 v to +0.5 v input voltage ?2 v to +2 v differential ?2 v to +2 v latch enable (le/ le ) ?0.5 v to v cci + 0.5 v applied voltage (hys) v ee to gnd current maximum input 20 ma output 40 ma continuous power dissipation ( p diss ), t a = 85c derate 43.5 mw/c above 85c ( hmc674lp3e ) 1.74 w derate 20.4 mw/c above 85c ( HMC674LC3C ) 0.816 w junction temperature 125c maximum peak reflow temperature 1 msl1 and msl3 260c thermal resistance ( jc ) hmc674lp3e 23 c/w HMC674LC3C 49c/w storage temperature range ?65c to +150c operating temperature range ?40c to +85c esd sensitivity, human body model (hbm) class 1a 1 see the ordering guide section. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress r ating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect produc t reliability. esd caution
data sheet HMC674LC3C/hmc674lp3e rev. k | page 7 of 14 pin configuration s and function descrip tions 12 11 10 1 3 4 9 2 6 5 7 8 16 15 14 13 vtp inp inn vtn v cco v ee hys rtn v cci q q v cco v cci le le nic v ee package base notes 1. nic = not internally connected. connect this pin to ground for improved noise. 2. exposed pad. the exposed pad must be connected to v ee . HMC674LC3C top view (not to scale) 14861-003 figure 3. HMC674LC3C pin configuration 12 11 10 1 3 4 9 2 6 5 7 8 16 15 14 13 vtp inp inn vtn v cco v ee hys rtn v cci q q v cco v cci le le nic hmc674lp3e top view (not to scale) v ee package base notes 1. nic = not internally connected. connect this pin to ground for improved noise. 2. exposed pad. the exposed pad must be connected to v ee . 14861-004 figure 4. hmc674lp3e pin configuration table 8 . HMC674LC3C / hmc674lp3e pin function descriptions pin no. mnemonic description 1 vtp termination resistor return pin for v p input. see figure 5 for the interface schematic. 2 inp noni nverting analog input . see figure 5 for the interface schematic. 3 inn i nverting analog input . see figure 5 for the interface schematic. 4 vtn termination r esistor return pi n for v n i nput . see figure 5 for the interface schematic. 5, 16 v cci positive supply voltage input stage. see figure 6 for the interface schematic. 6 le latch enable input pi n, inverting si de. see the theory of operation section for additional information . see figure 6 for the interface schematic. 7 le latch enable input pin, noninverting side. see the theory of operation section for additional information . see figure 6 for the interface schematic. 8 nic not internally connected. conne ct this pin to ground for improved noise. 9, 12 v cco positive supply voltage for the output stage. see figure 7 for the interface schematic. 10 q inverting output. q is at logic low if the analog voltage at the noninverting input, i np, is greater than the analog voltage at the inverting input, inn, provided that the comparator is in track mode. see the theory of operation section for additional information . see figure 7 for the interface schematic. 11 q non i nverting o utpu t. q is at logic high if the analog voltage at the noninverting input, inp, is greater than the analog voltage at the inverting input, inn, provided that the comparator is in track mode. see the theory of operation section for additional information . see figure 7 for the interface schematic. 13 v ee negative power supply, ? 3 v. see figure 6 for the interface schematic. 14 hys hys teresis control pin. leave this pin disconnected for zero hysteresis. connect this pin to v ee with a resistor to add the desire d amount of hysteresis. see figure 12 to determine the correct size of the r hys hysteresis control resistor. see fi gure 8 for the interface schematic. 15 rtn return for esd p rotection. epad exposed pad. the e xposed pad must be connected to v ee .
HMC674LC3C/hmc674lp3e data sheet rev. k | page 8 of 14 interface schematics inp, inn vtp, vtn 50 14861-005 figure 5 . vtp, vtn and inp, inn interface schematic v ee v cci le, le 14861-006 figure 6. le , le interface schematic q, q v cco 14861-007 figure 7. q , q interface schematic hys 14861-008 figure 8 . hys interface schematic
data sheet HMC674LC3C/hmc674lp3e rev. k | page 9 of 14 typical performance characteristics 11 ?1 1 3 5 7 9 0 10 30 20 40 50 60 70 80 90 100 dispersion (ps) overdrive voltage (mv) rising edge falling edge 14861-009 figure 9 . dispersion vs. overdrive voltage 2.8 1.8 2.0 2.2 2.4 2.6 ?45 ?32 ?6 ?19 7 20 33 46 59 72 85 output voltage (v) temperature (c) v oh v ol 14861-010 figure 10 . output voltage vs. temperature 15.0 ?5.0 ?2.5 0 5.0 10.0 2.5 7.5 12.5 ?2.0 ?1.5 ?0.5 ?1.0 0 0.5 1.0 1.5 2.0 normalized t pd (ps) common-mode voltage (v) rising edge falling edge 14861-0 1 1 figure 11 . normalized propagation delay (t pd ) vs. common - mode voltage 15 0 5 10 100 1k 10k hysteresis (mv) resistance () 14861-012 figure 12 . comparator hysteresis vs. r hys control resistance
HMC674LC3C/hmc674lp3e data sheet rev. k | page 10 of 14 theory of operation the HMC674LC3C / hmc674lp3e are latched co mparator s with a 9.3 ghz equivalent input bandwidth. the se device s are comprised of three blocks : a n input amplifier, a latch, and a n output buf fer. the latching circuit is level sensitive and consists of a single , high speed latch. the HMC674LC3C / hmc674lp3e comparator s support 10 gb p s operation. the input signal minimum pulse width is 60 ps. the HMC674LC3C / hmc674lp3e operate in either track (tra nsparent) m ode, where the output follows the logical value of the input, or l atch ( hold) mod e, where the output value is held to the logical value of the comparison result of the input just prior to (le ? le ) going high . select t rack m ode operation by either setting (le ? le ) low or by floating the le and le inputs. select l atch m ode by setting (le ? le ) high . the input impedance of the le and le inpu ts is 8 k ? ; however, these inputs can be terminated with 50 ? external resistors , if desired. wh en the clock inputs are dc - coupled, they operate at an input common - mode voltage of 2 v. in this case, any termination resistors ideally return to 2 v. if the clock inputs are ac - coupled to the HMC674LC3C / hmc674lp3e , return the input termination resistors to ground. power sequencing as long as the input signal is not near the ? 2 v extreme, either v cc or v ee c an be power ed on first. however, if the input voltage is more negat ive than ? 1.8 v, use the following power - up sequenc e: 1. v ee 2. v cci and v cco ( i f v cco = v cci ) 3. v cco ( if different than g round) note that the p ower - down sequence is the reverse of this sequence. it is recommended to power up the HMC674LC3C or the hmc674lp3e before applying the input signal and to remove the input signal prior to powe r ing either down. t h e s e recommendations are important if any of the inputs are more negative than ? 1.8 v.
data sheet HMC674LC3C/hmc674lp3e rev. k | page 11 of 14 applications information evaluation printed c ircuit board (pcb) figure 13 shows the front side of the evaluation pcb, and figure 14 shows the back side of the evaluation pcb. the evaluation pcb used in the application must use rf circuit design techniques. signal lines must have 50 ? impedance , and t he package ground leads must be connected directly to the ground pl ane s imilar to that shown in figure 15. use a sufficient number of via holes to connect the top and bottom ground planes to provid e good rf grounding to 10 ghz. the evaluation pcb shown in figure 13 is available from analog devices, inc., upon request. 14861-013 figure 13 . front side of the evaluation pcb 14861-014 figure 14 . back side of the evaluation pcb
HMC674LC3C/hmc674lp3e data sheet rev. k | page 12 of 14 application circuit s see figure 15 f or the typical a pplication circuit, table 9 for the bill of materials, and figure 16 for the output interfacing application circui t. j8 gnd v ee 12 11 10 1 3 4 9 2 6 5 7 8 16 15 14 13 50 50 v ee package base c6 100pf tp4 c5 100pf c7 330pf c8 100pf jp1 c13 4.7f j1 v cci j1 v cci c12 4.7f c2 100pf c3 100pf c4 330pf c14 4.7f c11 330pf c1 100pf j1 v ee tp3 hys tp1 vtp j2 inp j6 le j3 inn j4 q c9 100pf c10 100pf jp2 tp2 vtn j7 le j5 q j1 v cco 14861-015 figure 15 . typical application circuit table 9 . bill of mat erials for the evaluatio n pcb ( 1259 29 - 3 ) item description j1 eight position vertical header j2 to j7 2.92 mm, 40 ghz jacks j8 terminal strip, single row, 3 - pin surface mount (smt) jp1, jp2 two position vertical header c1 to c3, c5, c6, c8 to c10 100 pf capacitors, 0402 package c4, c7, c11 330 pf capacitors, 0402 package c12 to c14 4.7 f tantalum capacitors tp1 to t p4 dc pin, swage mount test points u1 HMC674LC3C / hmc674lp3e comparator pcb 125929 -3 1 evaluation pcb , circuit board material is rogers 4350 or arlon 25fr 1 reference this number when ordering complete evaluation pcb. 50 ? 50 ? ch1 50 ? gnd (v tt ) gnd (v tt ) ch2 q q v cm_out ~0.9v v ee = ?3.0v oscilloscope input v cco = +2.0v 50 ? 14861-016 figure 16 . output interfacing application circuit , output to oscilloscope
data sheet HMC674LC3C/hmc674lp3e rev. k | page 13 of 14 outline dimensions t o p view side view se a ting plane 0.92 max 04-25-2016- a pkg-000000 pin 1 indic a t or 3.03 2.90 sq 2.77 pin 1 (0.32 0.32) exposed pad 0.36 0.30 0.24 1.60 1.50 sq 1.40 1 0.50 bsc bot t om view 16 5 8 9 12 13 4 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1.50 ref 2.10 bsc figure 17 . 16 - terminal ceramic leadless chip carrier [lcc] (e - 16 - 1) dimensions shown in millime ters 3.10 3.00 sq 2.90 0.30 0.25 0.18 1.950 1.725 sq 1.500 1 0.50 bsc bot t om view t op view 16 5 8 9 12 13 4 exposed pad pin 1 indic a t or 0.45 0.40 0.35 sea ting plane 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indic a t or 1.00 0.90 0.80 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 02-13-2015- a pkg-000000 compliant with jedec standards mo-220-veed-4. figure 18 . 1 6- lead lead frame chip scale package [l fcsp ] 3 mm 3 mm body and 0.90 mm package height ( hcp - 16 - 1) dimensions shown in millime ters ordering guide model 1 temperature range package body material lead finish msl rating 2 package description package option branding HMC674LC3C ?40c to +85c alumina, white gold over nickel msl3 16- terminal lcc e -16-1 h674 xxxx HMC674LC3Ctr ?40c to +85c alumina, white gold over nickel msl3 16- terminal lcc e -16-1 h674 xxxx HMC674LC3Ctr -r5 ?40c to +85c alumina, white gold over nickel msl3 16- terminal lcc e -16-1 h674 xxxx
HMC674LC3C/hmc674lp3e data sheet rev. k | page 14 of 14 model 1 temperature range package body material lead finish msl rating 2 package description package option branding hmc674 lp3e ?40c to +85c low stress, injection molded plastic 100% matte sn msl1 16- lead lfcsp hcp -16-1 h674 xxxx hmc674 lp3etr ?40c to +85c low stress, injection molded plastic 100% matte sn msl1 16- lead lfcsp hcp -16-1 h674 xxxx 125932 - HMC674LC3C HMC674LC3C evaluation board 125932 - hmc674 lp3e hmc674lp3e evaluation board 1 th e HMC674LC3C, the HMC674LC3Ctr, the HMC674LC3Ctr - r5, the hmc674lp3e, and the hmc674lp3etr are rohs compliant parts. 2 see the absolute maximum ratings section. ? 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d14861 - 0 - 12/16(k)

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