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fn3612 rev 10.00 page 1 of 25 june 27, 2006 fn3612 rev 10.00 june 27, 2006 HI7190 24-bit, high precision, sigma delta a/d converter datasheet the intersil HI7190 is a monol ithic instrumentation, sigma delta a/d converter which oper ates from 5v supplies. both the signal and reference inputs are fully differential for maximum flexibility and performance. an internal programmable gain instrumen tation amplifier (pgia) provides input gains from 1 to 128 eliminating the need for external pre-amplifiers. the on-demand converter auto- calibrate function is capable of removing of fset and gain errors existing in external and internal circuitry. the on-boar d user programmable digital filter provides over 120db of 60/50hz noise rejection and all ows fine tuning of resolution and conversion speed over a wide dynamic range. the HI7190 and hi7191 are functionally the same device, but the HI7190 has tighter linea rity specifications. the HI7190 contains a serial i /o port and is compatible with most synchronous transfer f ormats including both the motorola 6805/11 series spi and intel 8051 series ssr protocols. a sophisticated se t of commands gi ves the user control over calibration, pgia ga in, device selection, standby mode, and several other featu res. the on-chip calibration registers allow the user to re ad and write calibration data. pinout HI7190 20 ld soic, pdip top view features ? 22-bit resolution with no missing code ? 0.0007% integral non-linearity (typ) ? 20mv to 2.5v full scale input ranges ? internal pgia with gains of 1 to 128 ? serial data i/o interface, spi compatible ? differential analog and reference inputs ? internal or system calibration ? 120db rejection of 60/50hz line noise ? settling time of 4 conversions (max) for a step input ? pb-free plus anneal available (rohs compliant) applications ? process control and measurement ? industrial weight scales ? part counting scales ? laboratory instrumentation ? seismic monitoring ? magnetic field monitoring ? additional reference literature - technical brief, tb348 hi 7190/1 negative full scale error vs conversion frequency - application note, an9504 a brief intro to sigma delta conversion - technical brief, tb329 intersil sigma delta calibration technique - application note, an9505 using the HI7190 evaluation kit - technical brief, tb331 using the HI7190 serial interface - application note, an9527 interfacing HI7190 to a microcontroller - application note, an9532 using HI7190 in a multiplexed system - application note, an9601 u sing HI7190 with a single +5v supply 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 sclk sdo sdio cs drdy dgnd v rlo av ss v rhi v cm mode reset osc 1 osc 2 sync dv dd agnd av dd v inhi v inlo
HI7190 fn3612 rev 10.00 page 2 of 25 june 27, 2006 functional block diagram ordering information part number part marking temp. range (c) package pkg. dwg. # HI7190ip HI7190ip -40 to 85 20 ld pdip e20.3 HI7190ipz HI7190ipz -40 to 85 20 ld pdip* (pb-free) e20.3 HI7190ib HI7190ib -40 to 85 20 ld soic m20.3 HI7190ibz (note) HI7190ibz -40 to 85 20 ld soic (pb-free) m20.3 HI7190ibz-t (note) HI7190ibz -40 to 85 20 ld soic tape and reel (pb-free) m20.3 HI7190eval evaluation kit *pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ? digital filter ????? modulator pgia ? 1-bit d/a 1 control and serial interface unit control register serial interface unit clock generator av dd transducer burn-out current v inhi v inlo v cm osc 1 osc 2 drdy reset sync cs mode s clk sdio sdo v rhi v rlo reference inputs ??
HI7190 fn3612 rev 10.00 page 3 of 25 june 27, 2006 typical application schematic 10mhz osc 1 osc 2 v rhi v rlo +2.5v av dd +5v 0.1 ? f v cm v inhi v inlo agnd dv dd dgnd sclk cs drdy sync sdo sdio +5v 4.7 ? f + 0.1 ? f 4.7 ? f + reset input input av ss -5v 0.1 ? f 4.7 ? f + data i/o data out sync cs drdy reset 13 17 16 15 12 11 10 9 8 7 14 6 18 5 4 19 2 3 1 mode 20 reference + - r 1
HI7190 fn3612 rev 10.00 page 4 of 25 june 27, 2006 absolute maximum ratings thermal information supply voltage av dd to agnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5v av ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5v dgnd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? 0.3v analog input pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . av ss to av dd digital input, output and i/o pins . . . . . . . . . . . . . . dgnd to dv dd esd tolerance (no damage) human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100v charged device model. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000v operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 c to 85c thermal resistance (typical, note 1) ? ja (c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 maximum junction temperature plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering, 10s). . . . . . . . . . . . . 300c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ? ja is measured with the component mounted on a low effective ther mal conductivity test board in fr ee air. see tech brief tb379 f or details. electrical specifications av dd = +5v, av ss = -5v, dv dd = +5v, v rhi = +2.5v, v rlo = agnd = 0v, v cm = agnd, pgia gain = 1, osc in = 10mhz, bipolar input range selected, f n = 10hz parameter test conditions min typ max units system performance integral non-linearity, inl end point line method (notes 3, 5, 6 )- ? 0.0007 ? 0.0015 %fs differential non-linearity (note 2) no missing codes to 22-bits ls b offset error, v os see table 1 - - - - offset error drift v inhi = v inlo (notes 3, 8) - 1 - ? v/c full scale error, fse v inhi - v inlo = +2.5v (notes 3, 5, 8, 10) - - - - noise, e n see table 1 - - - - common mode rejection ratio, cmrr v cm = 0v, v inhi = v inlo from -2v to +2v - 70 - db normal mode 50hz rejection filter notch = 10hz, 25hz, 50hz (note 2) 120 - - db normal mode 60hz rejection filter notch = 10hz, 30hz, 60hz (note 2) 120 - - db step response settling time - 2 4 conversions analog inputs input voltage range unipolar mode (note 9) 0 - v ref v input voltage range bipolar mode (note 9) - v ref -v ref v common mode input range (note 2) av ss -av dd v input leakage current, i in v in = av dd (note 2) - - 1.0 na input capacitance, c in -5.0- pf reference voltage range, v ref (v ref = v rhi - v rlo ) 2.5 - 5 v transducer burn-out current, i bo - 200 - na calibration limits positive full scale ca libration limit - - 1.2(v ref /gain) - negative full scale calibration limit - - 1.2(v ref /gain) - offset calibration limit - - 1.2(v ref /gain) - input span 0.2(v ref /gain) - 2.4(v ref /gain) - digital inputs input logic high voltage, v ih (note 11) 2.0 - - v input logic low voltage, v il --0.8 v input logic current, i i v in = 0v, +5v - 1.0 10 ? a
HI7190 fn3612 rev 10.00 page 5 of 25 june 27, 2006 input capacitance, c in v in = 0v - 5.0 - pf digital outputs output logic high voltage, v oh i out = -100 ? a (note 7) 2.4 - - v output logic low voltage, v ol i out = 3ma (note 7) - - 0.4 v output three-state leakage current, i oz v out = 0v, +5v (note 7) -10 1 10 ? a digital output capacitance, c out -10- pf timing characteristics sclk minimum cycle time, t sclk 200 - - ns sclk minimum pulse width, t sclkpw 50 - - ns cs to sclk precharge time, t pre 50 - - ns drdy minimum high pulse width (notes 2, 7) 500 - - ns data setup to sclk rising edge (write), t dsu 50 - - ns data hold from sclk rising edge (write), t dhld 0-- ns data read access from instruction byte write, t acc (note 7) - - 40 ns read bit valid from sclk falling edge, t dv (note 7) - - 40 ns last data transfer to data ready inactive, t drdy (note 7) - 35 - ns reset low pulse width (note 2) 100 - - ns sync low pulse width (note 2) 100 - - ns oscillator clock frequency (note 2) 0.1 - 10 mhz output rise/fall time (note 2) - - 30 ns input rise/fall time (note 2) - - 1 ? s power supply characteristics iav dd --1.5ma iav ss --2.0ma idv dd sclk = 4mhz - - 3.0 ma power dissipation, active pd a sb = 0 - 15 32.5 mw power dissipation, standby pd s sb = 1 - 5 - mw psrr (note 3) - -70 - db notes: 2. parameter guaranteed by design or characterization, not produ ction tested. 3. applies to both bipolar and unipolar input ranges. 4. these errors can be removed by re-calibrating at the desired operating temperature. 5. applies after system calibration. 6. fully differential input signal source is used. 7. see load test circuit, figure 4, r1 = 10k ? , c l = 50pf. 8. 1 lsb = 298nv at 24 bits for a full scale range of 5v. 9. v ref = v rhi - v rlo. 10. these errors are on the order of the output noise shown in t able 1. 11. all inputs except osc 1 . the osc 1 input v ih is 3.5v minimum. electrical specifications av dd = +5v, av ss = -5v, dv dd = +5v, v rhi = +2.5v, v rlo = agnd = 0v, v cm = agnd, pgia gain = 1, osc in = 10mhz, bipolar input range selected, f n = 10hz (continued) parameter test conditions min typ max units
HI7190 fn3612 rev 10.00 page 6 of 25 june 27, 2006 timing diagrams figure 1. data write to HI7190 figure 2. data read from HI7190 figure 3. data read from HI7190 1st bit 2nd bit cs sclk sdio t sclk t dsu t dhld t sclkpw t sclkpw t pre cs sclk sdio sdo t acc t dv 1st bit 2nd bit sclk cs drdy sdio t drdy 8 7 6 5 1
HI7190 fn3612 rev 10.00 page 7 of 25 june 27, 2006 pin descriptions 20 lead dip, soic pin name description 1 sclk serial interface clock. syn chronizes serial data transfers . data is input on the rising edge and output on the falling edge. 2 sdo serial data out. serial data is read from this line when us ing a 3-wire serial protocol such as the motorola serial peripheral interface. 3 sdio serial data in or out. this line is bidirectional programm able and interfaces directly to the intel standard serial interface using a 2-wire serial protocol. 4cs chip select input. used to select the HI7190 for a serial data transfer cycle. this line can be tied to dgnd. 5 drdy an active low interrupt indicating that a new data word is avai lable for reading. 6 dgnd digital supply ground. 7av ss negative analog power supply (-5v). 8v rlo external reference input. shoul d be negative referenced to v rhi . 9v rhi external reference input. shoul d be positive referenced to v rlo . 10 v cm common mode input. should be set to halfway between av dd and av ss . 11 v inlo analog input lo. negative input of the pgia. 12 v inhi analog input hi. positive input of the pgia. the v inhi input is connected to a current source that can be used to che ck the condition of an external transducer. this current source is controlled via the control register. 13 av dd positive analog power supply (+5v). 14 agnd analog supply ground. 15 dv dd positive digital supply (+5v). 16 osc 2 used to connect a crystal source between osc 1 and osc 2 . leave open otherwise. 17 osc 1 oscillator clock input for the device. a crystal connected betw een osc 1 and osc 2 will provide a clock to the device, or an external oscillator can drive osc 1 . the oscillator frequency should be 10mhz (typ). 18 reset active low reset pin. used to i nitialize the HI7190 registers, filter and state machines. 19 sync active low sync input. used to control the synchronization of a number of HI7190s. a logic 0 initializes the converter. 20 mode mode pin. used to selec t between synchronous self clockin g (mode = 1) or synchronous external clocking (mode = 0) for the serial port. load test circuit figure 4. v 1 r 1 c l (includes stray dut capacitance) esd test circuits figure 5a. figure 5b. dut human body c esd = 100pf machine model c esd = 200pf r 1 c esd r 1 = 10m ? r 1 = 10m ? r 2 r 2 = 1.5k ? r 2 = 0 ? ? v charged device model r 1 r 1 = 1g ? r 2 r 2 = 1 ? ? v dut dielectric
HI7190 fn3612 rev 10.00 page 8 of 25 june 27, 2006 table 1. noise performance with inputs connected to analog groun d hertz snr enob p-p noise ( ? v) rms noise ( ? v) gain = 1 10 132.3 21.7 9.8 1.5 25 129.5 21.2 13.6 2.1 30 127.7 20.9 16.6 2.5 50 126.3 20.7 19.5 3.0 60 125.6 20.6 21.2 3.2 100 122.4 20.0 30.7 4.6 250 107.7 17.6 166.7 25.3 500 98.1 16.0 505.3 76.6 1000 85.7 13.9 2101.8 318.5 2000 68.8 11.1 14661.6 2221.4 gain = 2 10 129.2 21.2 14.0 2.1 25 125.7 20.6 20.9 3.2 30 124.5 20.4 24.1 3.7 50 123.4 20.2 27.3 4.1 60 122.5 20.1 30.3 4.6 100 118.1 19.3 50.0 7.6 250 106.1 17.3 199.5 30.2 500 96.9 15.8 580.1 87.9 1000 84.4 13.7 2435.6 369.0 2000 67.8 11.0 16469.7 2495.4 gain = 4 10 125.9 20.6 20.5 3.1 25 123.1 20.1 28.4 4.3 30 121.8 19.9 32.8 5.0 50 119.9 19.6 40.9 6.2 60 119.9 19.6 40.9 6.2 100 116.1 19.0 63.2 9.6 250 105.7 17.3 209.7 31.8 500 96.6 15.8 597.8 90.6 1000 84.3 13.7 2469.5 374.2 2000 68.2 11.0 15656.1 2372.1 gain = 8 10 124.7 20.4 23.4 3.5 25 120.6 19.7 37.8 5.7 30 119.2 19.5 44.3 6.7 50 117.5 19.2 53.8 8.2 60 116.8 19.1 58.6 8.9 100 112.1 18.3 100.0 15.2 250 101.4 16.5 345.2 52.3 500 95.3 15.5 691.1 104.7 1000 83.1 13.5 2838.6 430.1 2000 68.3 11.1 15494.7 2347.7 gain = 16 10 120.1 19.7 39.8 6.0 25 114.8 18.8 73.4 11.1 30 113.5 18.6 85.1 12.9 50 111.0 18.1 114.4 17.3 60 109.6 17.9 134.0 20.3 100 105.5 17.2 214.8 32.5 250 95.2 15.5 699.1 105.9 500 89.1 14.5 1417.7 214.8 1000 83.5 13.6 2686.0 407.0 2000 62.6 10.1 30110.0 4562.1 gain = 32 10 113.2 18.5 88.8 13.5 25 109.0 17.8 142.7 21.6 30 108.2 17.7 157.4 23.8 50 104.7 17.1 235.8 35.7 60 105.0 17.1 227.8 34.5 100 102.3 16.7 310.5 47.0 250 93.4 15.2 861.1 130.5 500 87.1 14.2 1782.7 270.1 1000 78.2 12.7 4990.4 756.1 2000 57.0 9.2 57311.1 8683.5 gain = 64 10 106.7 17.4 186.2 28.2 25 102.9 16.8 288.4 43.7 30 101.9 16.6 325.8 49.4 50 98.5 16.1 479.8 72.7 60 98.9 16.1 459.8 69.7 100 96.3 15.7 620.2 94.0 250 85.5 13.9 2133.5 323.3 500 78.1 12.7 5025.0 761.4 1000 66.7 10.8 18693.5 2832.3 2000 50.5 8.1 120163.0 18206.5 gain = 128 10 101.1 16.5 356.5 54.0 25 96.0 15.7 638.3 96.7 30 95.2 15.5 704.8 106.8 50 93.2 15.2 882.2 133.7 60 92.2 15.0 996.7 151.0 100 91.4 14.9 1086.6 164.6 250 79.4 12.9 4346.4 658.5 500 71.8 11.6 10439.2 1581.7 1000 60.1 9.7 39923.0 6048.9 2000 44.8 7.1 233238.2 35339.1 hertz snr enob p-p noise ( ? v) rms noise ( ? v)
HI7190 fn3612 rev 10.00 page 9 of 25 june 27, 2006 definitions integral non-linearity, inl, is the maximum deviation of any digital code from a strai ght line passing through the endpoints of the tr ansfer function. the endpoints of the transfer function are zero scale (a point 0.5 lsb below the first code transition 000...000 and 000...001) and full scale ( a point 0.5 lsb above the last co de transition 111...110 to 111...111). differential non-linearity, dnl, is the deviation from the actual difference between midpoints and the ideal difference between midpoints (1 lsb) for adjacent codes. if this difference is equal to or mor e negative than 1 lsb, a code will be missed. offset error, v os , is the deviation of the first code transition from the ideal input voltage (v in - 0.5 lsb). this error can be calibrated to the order of the noise level shown in table 1 . full scale error, fse, is the deviation of the last code transition from the ideal input full scale voltage (v in -+v ref /gain - 1.5 lsb). this error can be calibrated to the order of the noise level shown in table 1. input span, defines the minimum and maximum input voltages the device can handle while still calibrating properly for gain. noise, e n , table 1 shows the peak- to-peak and rms noise for typical notch and -3db frequencies. the device programming was for bipolar input with a v ref of +2.5v. this implies the input range is 5v. the analysis was performed on 100 conversions with the peak -to-peak output noise being the difference between the maximum and minimum readings over a rolling 10 conversion window. the equation to convert the peak-to-peak noise data to enob is: enob = log 2 (v fs /v nrms ) where: v fs = 5v, v nrms = v np-p /cf and cf = 6.6 (empirical crest factor) the noise from the part com es from two sources, the quantization noise from the analog-to-digital conversion process and device noise. device noise (or wideband noise) is independent of gain a nd essentially flat across the frequency spectrum. quantizati on noise is ratiometric to input full scale (and hence gain) and its frequency response is shaped by the modulator. looking at table 1, as the cut off frequency increases the output noise increases. this is due to more of the quantization noise of the part coming thr ough to the output and, hence, the out put noise increases with increasing -3db frequencies. for the lower notch settings, the output noise is dominated by the dev ice noise and, hence , altering the gain has little effect on the out put noise. at higher notch frequencies, the quantizatio n noise dominat es the output noise and, in this case, the o utput noise tends to decrease with increasing gain. since the output noise comes from two sources, the effective resolution of the device (i.e., the ratio of the input full sca le to the output rms noise) does not remain constant with increasing gain or with increasing bandwidth. it is possible to do post-filtering (suc h as brick wall filtering) on the data to improve the overall resolution for a given -3db frequency and also to further reduce the output noise. circuit description the HI7190 is a monolithic, sigma delta a/d converter which operates from ? 5v supplies and is intended for measurement of wide dynamic range, low frequency signals. it contains a programmable gain instrumentation amplifier (pgia), sigma delta adc, digital filter, bidirectional serial p ort (compatible with many industry standard protocols), clock oscillator, and an on-chip controller. the signal and reference inputs are fully differential for maximum flexibility and performance. normally v rhi and v rlo are tied to +2.5v and agnd respectively. this allows for input ranges of 2.5v and 5v when operating in the unipolar and bipolar modes res pectively (assuming the pgia is configured for a gain of 1). the internal pgia provides input gains from 1 to 128 and eliminates the need for external pre-amplifi ers. this means the device will convert signals ranging from 0v to + 20mv and 0v to +2.5v when operating in the unipolar mo de or signals i n the range of ? 20mv to ? 2.5v when operating in the bipolar mode. the input signal is continuous ly sampled at the input to the HI7190 at a clock rate set by the oscillator frequency and the selected gain. this signal t hen passes through the sigma delta modulator (which includes the pgia) and emerges as a pulse train whose code densit y contains the analog signal information. the output of the modulator is fed into the sinc 3 digital low pass filt er. the filter output passes into the calibration block where offset and gain errors are removed. the calibrated data is then c oded (2s complement, offset binary or binary) before being stored in the data output register. the data outpu t register update rate is determined by the first notch f requency of the digital filter. this first notch frequency is programmed into HI7190 via the control register and has a range of 10hz to 1.953khz which corresponds to -3db frequ encies of 2.62hz and 512hz respectively. output data coding on the hi 7190 is programmable via the control register. when operat ing in bipolar mode, data output can be either 2s complement or offset binary. in unipolar mode output is binary. the drdy signal is used to alert t he user that new output data is available. convert ed data is read vi a the HI7190 serial i/o port which is compat ible with most synchronous transfer formats including both the motorola 6805/11 series
HI7190 fn3612 rev 10.00 page 10 of 25 june 27, 2006 spi and intel 8051 series ssr p rotocols. data integrity is always maintained at the hi 7190 output port. this means that if a data read of conversion n is begun but not finished before the next conversion (conv ersion n + 1) is complete, the drdy line remains active (low) and the data being read is not overwritten. the HI7190 provides many ca libration modes that can be initiated at any time by writing to the control register. the device can perform system calibration where external components are included with the HI7190 in the calibration loop or self-calibration where on ly the HI7190 itself is in the calibration loop. the on-chip calibration registers are read/write registers which allow the user to read calibration coefficients as well as wr ite previously determined calibration coefficients. circuit operation the analog and digital supp lies and grounds are separate on the HI7190 to minimize digital noise coupling into the analog circuitry. nominal supply voltages are av dd = +5v, dv dd = +5v, and av ss = -5v. if the same supply is used for av dd and dv dd it is imperative that the supply is separately decoupled to the av dd and dv dd pins on the HI7190. separate analog and digital ground planes should be maintained on the system board and the grounds should be tied together back at the power supply. when the HI7190 is powered up it needs to be reset by pulling the reset line low. the reset sets the internal registers of the HI7190 as shown in table 2 and puts the part in the bipolar mode with a gain of 1 and offset binary coding. the filter notch of the digital filter is set at 30hz while the i/o is set up for bidirectional i/o (data is read a nd written on th e sdio line and sdo is three-st ated), descending byte order, and msb first data format. a se lf calibration is performed before the device begi ns converting. drdy goes low when valid data is available at the output. the configuration of the HI7190 is changed by writing new setup data to the control regist er. whenever data is written to byte 2 and/or byt e 1 of the control register the part assumes that a critical setup parameter is being changed which means that drdy goes high and the device is re- synchronized. if the configurat ion is changed such that the device is in any one of the calibration modes, a new calibration is performed before normal conversions continue. if the device is written to the conversion mode, a new calibration is not performed (a new calibration is recommended any time data is written to the control register.). in either case, drdy goes low when valid data is available at the output. if a single data byte is writ ten to byte 0 of the control register, the device assume s the gain has not been changed. it is up to the user to re-calibrate the device if the gain is changed in this manner. for this reason it is recommended that the entire control re gister be written when changing the gain of the device. this ensures that the part is re-calibrate d (if in a calibration mode) before the drdy output goes low indicating that valid data is available. the calibration registers can be r ead via the serial interface at any time. however, care mus t be taken when writing data to the calibration registers. if the HI7190 is internally updating any calibration registe r the user can not write to that calibration register. see the operational modes section for details on which calibration registers are updated for the various modes. since access to the calibration registers is asynchronous to th e conversion process the user is cautioned that new calibration data may not be used on the very next set of valid data after a calibration register write. i t is guaranteed that the new data will take effect on the second set o f output data. non-calibrated data can be obtained from the device by writing 000000 (h) to the offset calibration register , 800000 (h) to the positive ful l scale calibration register, a nd 800000 (h) to the negative full scale calibration register. this sets the offset correction fac tor to 0 and the positive and negat ive gain slope factors to 1. if several HI7190s share a system master clock the sync pin can be used to synchronize their operation. a common sync input to multiple devices will synchronize operation such that all output registers are updated simultaneously. of course the sync pin would normally be activated only after each HI7190 has been calibrat ed or has had calibration coefficients written to it. the sync pin can also be used t o control the HI7190 when an external multiplexer is u sed with a single HI7190. the sync pin in this application can be used to guarantee a maximum settling time of 3 conversion periods when switching channels on the multiplexer. analog section description figure 6 shows a simplified block diagram of the analog modulator front end of a sig ma delta a/d converter. the input signal v in comes into a summing junction (the pgia in this case) where the previous modulator output is subtracted from it. the resulting signal is then integrated and the output of the integrator goe s into the comparato r. the output of the comparator is then fed back vi a a 1-bit dac to the summing table 2. register reset values register value (hex) data output register xxxx (undefined) control register 28b300 offset calibration register self calibration value positive full scale calibration register self calibration value negative full scale calibration register self calibration value
HI7190 fn3612 rev 10.00 page 11 of 25 june 27, 2006 junction. the feedback loop f orces the aver age of the fed back signal to be equa l to the input signal v in . analog inputs the analog input on the HI7190 is a fully differential input with programmable gain capabilit ies. the input accepts both unipolar and bipolar input sig nals and gains range from 1 to 128. the common mode range of this input is from av ss to av dd provided that the absolut e value of the analog input voltage lies within the power supplies. the input impedance of the HI7190 is dependent upon the modulator input sampling rate and the sampling rate varies with the selected pgia gain. table 3 shows the sampling rates and input impedances for the different gain settings of the HI7190. note that this table is valid onl y for a 10mhz master clock. if the input clock frequency is changed, then the input impedance will change accordin gly. the equation used to calculate the input impedance is: where c in is the nominal input capacitance (8pf) and f s is the modulator sampling rate. bipolar/unipolar input ranges the input on the HI7190 can accept either unipolar or bipolar input voltages. bipolar or unipolar options are chosen by programming the b/u bit of the control register. programming the part for either unipolar or bipolar operation does not change the input signal conditioning. the inputs are differential, and as a result are referenced to the voltage on the v inlo input. for example, if v inlo is +1.25v and the HI7190 is configured fo r unipolar operat ion with a gain of 1 and a v ref of +2.5v, the input voltage range on the v inhi input is +1.25v to +3.75v. if v inlo is +1.25v and the HI7190 is configured for bipolar mode with gain of 1 and a v ref of +2.5v, the analog input range on the v inhi input is -1.25v to +3.75v. programmable gain inst rumentation amplifier the programmable gain instrum entation amplifier allows the user to directly interface low l evel sensors and bridges direct ly to the HI7190. the pgia has 4 selectable gain options of 1, 2, 4, 8 which are implemented by m ultiple sampling of the input signal. input signals can be gained up further to 16, 32, 64 or 128. these higher gains are implemented in the digital section of the design to maintain a high signal to noise ratio through the front end amplifiers. the gai n is digitally programmable in the control register via the se rial interface. for optimum pgia performance the v cm pin should be tied to the mid point of the analog supplies. differential reference input the reference inputs of the of the HI7190, v rhi and v rlo , provide a differential referenc e input capability. the nominal differential voltage (v ref = v rhi - v rlo ) is +2.5v and the common mode voltage cab be anywhere between av ss and av dd . larger values of v ref can be used without degradation in performance wi th the maximum reference voltage being v ref = +5v. smaller values of v ref can also be used but performance will be degraded since the lsb size is reduced. the full scale ran ge of the HI7190 is defined as: and v rhi must always be greater than v rlo for proper operation of the device. the reference inputs provi de a high impedance dynamic load similar to the analog inpu ts and the effective input impedance for the refe rence inputs can be calculated in the same manner as it is for the analog input impedance. the only difference in the calculation is that c in for the reference inputs is 10.67pf. therefore, the input impedance range for the reference inputs is from 149k ? in a gain of 8 or higher mode to 833k ? in the gain of 1 mode. v cm input the voltage at the v cm input is the voltage that the internal analog circuitry is referenced to and should always be tied to the midpoint of the av dd and av ss supplies. this point provides a common mode input voltage for the internal operational amplifiers and mus t be driven from a low noise, low impedance source if it is not tied to analog ground. failure to do so will result in degraded HI7190 performance. it is recommended that v cm be tied to analog ground when operating off of av dd = +5v and av ss = -5v supplies. v cm also determines the headroom at the upper and lower ends of the power supplies wh ich is limited by the common mode input range where the inte rnal operational amplifiers remain in the linear, high gain region of operation. the HI7190 is designed to have a range of av ss +1.8v < v cm < table 3. effective in put impedance vs gain gain sampling rate (khz) input impedance (m ? ) 1 78.125 1.6 2 156.25 0.8 4 312.5 0.4 8, 16, 32, 64, 128 625 0.2 pgia integrator comparator v rhi v rlo dac v in + - ? ? + - figure 6. simple modulator block diagram z in = 1/(c in x f s ), fsr bipolar = 2 x v ref /gain fsr unipolar = v ref /gain
HI7190 fn3612 rev 10.00 page 12 of 25 june 27, 2006 av dd - 1.8v. exceeding this range on the v cm pin will compromise the device performance. transducer burn-out current source the v inhi input of the HI7190 contains a 500na (typ) current source which can be turned on/o ff via the control register. this current source can be used in checking whether a transducer has burnt-out or become open before attempting to take measurements on th at channel. when the current source is turned on an additi onal offset will be created indicating the presence of a transducer. the current source is controlled by the bo bit (bit 4) i n the control register and is disabled on power up. see figure 7 for an applications circuit. digital section description a block diagram of the digital section of the HI7190 is shown in figure 8. this section includes a low pass decimation filter, conversion controller, c alibration logic, serial interf ace, and clock generator. digital filtering one advantage of digital filterin g is that it occurs after the conversion process and can remove noise introduced during the conversion. it can not, how ever, remove noise present on the analog signal prior to t he adc (which an analog filter can). one problem with the modulator/ digital filter combination is that excursions outside the f ull scale range of the device could cause the modulat or and digital filter to saturate. this device has headroom built in to the modulator and digital filter which tolerates signal dev iations up to 33% outside of the full scale range of the device. if noise spikes can drive the input signal outside of this extended range, it is recommended that an input an alog filter is used or the overall input signal level is reduced. low pass decimation filter the digital low-pass filt er is a hogenauer (sinc 3 ) decimating filter. this filter was chosen be cause it is a cost effective l ow pass decimating filter that minimizes the need for internal multipliers and extensive storage and is most effective when used with high sampling or ove rsampling rates. figure 9 shows the frequency characteri stics of the filter where f c is the -3db frequency of the input signal and f n is the programmed notch frequency. t he analog modulator sends a one bit data stream to the filter at a rate of that is determined by: f modulator = f osc /128 f modulator = 78.125khz for f osc = 10mhz. the filter then conver ts the serial modulator data into 40-bit words for processing by the hogenauer filter. the data is decimated in the filter at a rate determine d by the code word fp10-fp0 (programed by the user into the control register) and the external c lock rate. the equation is: f notch = f osc /(512 x code). the control register has 11 bits that select the filter cutoff frequency and the first notch o f the filter. the output data update rate is equal to the notch frequency. the notch frequency sets the nyquist sampling rate of the device while the -3db point of the filter determines the frequency spectrum of interest (f s ). the fp bits have a usable range of 10 through 2047 wher e 10 yields a 1.953 khz nyquist rate. the hogenauer filter contains alias components that reflect around the notch frequency. if the spectrum of the frequency of interest reaches the alias component, the data has been aliased and therefore undersampled. filter characteristics please note: we have recently discovered a performance anomaly with the HI7190. the problem occurs when the digital code for the notch filter is programmed within certain fre quencies. we believe the error is caused by the calibr ation logic and the digital notch code not the absolute frequency. the error is seen when the user applies mi d-scale (0v input, bipolar mode). with this input, the expected digital output v rhi v rlo v inhi v inlo av dd av ss current source HI7190 ratiometric configuration load cell figure 7. burn-out current source circuit modulator output serial i/o sdo sdio sclk cs drdy reset sync osc 2 osc 1 modulator clock digital calibration and control clock generator filter figure 8. digital section block diagram
HI7190 fn3612 rev 10.00 page 13 of 25 june 27, 2006 should be mid- scale (800000 h ). instead, ther e is a small probability, of an erroneous negative full scale (000000 h ) output. refer to technical brief tb348 for complete details . the fp10 to fp0 bits programme d into the control register determine the cutoff ( or notch) frequency of the digital filter . the allowable co de range is 00a h . this corre sponds to a maximum and minimum cutoff frequency of 1.953khz and 10hz, respectively when opera ting at a clock frequency of 10mhz. if a 1mhz clock is us ed then the m aximum and minimum cutoff frequencies become 195.3khz and 1hz, respectively. a plot of the (sinx/x) 3 digital filter characteristics is shown in figure 9. this filter provides greater than 120db of 50hz or 60hz rejection. c hanging the clock frequency or the programming of the fp bit s does not chan ge the shape of the filter characteristics, it merely shifts the notch frequency. this low pass digita l filter at the output of the converter has an accompanying s ettling time for step inputs just as a low pass analog fi lter does. new data takes between 3 and 4 conversion periods to settle and update on the serial port with a conversion period t conv being equal to 1/f n . input filtering the digital filter does not provide rejection at integer multiples of the modulator sam pling frequency. this implies that there are frequency bands where noise passes to the output without attenuation. for most cases this is not a problem because the high oversampling rate and noise shaping characteristics of the modulator cause this noise to become a small portion of t he broadband noise which is filtered. however, if an anti-al ias filter is necessary a singl e pole rc filter is usually sufficient. if an input filter is used the user must be careful that the so urce impedance of the filter is low enough not to cause gain errors in the system. the dc input impedance at the inputs is > 1g ? but it is a dynamic load that chang es with clock frequency and selected gain. the input samp le rate, also dependent upon clock frequency and gain, deter mines the allotted time for the input capacitor to charge. the a ddition of external components may cause the charge time of the capacitor to increase beyond the allotted time. the result of the input not settling to the proper value is a system gain error wh ich can be eliminated by system calibration of the HI7190. clocking/oscillators the master clock into the HI7190 can be supplied by either a crystal connected between the osc 1 and osc 2 pins as shown in figure 10a or a cm os compatible clock signal connected to the osc 1 pin as shown in figure 10b. the input sampling frequency, modul ator sampling frequency, filter -3db frequency, output update rate, and calibration time are all directly related to t he master clock frequency, f osc . for example, if a 1mhz clock is used instead of a 10mhz clock, what is normally a 10hz conversion rate becomes a 1hz conversion rate. lowering the clock frequency will also lower the amount of current dra wn from the power supplies. please note that the HI7190 specifications are written for a 10mhz clock only. operational modes the HI7190 contains several operational modes including calibration modes for cancellin g offset and gain errors of both internal and external cir cuitry. a calib ration routine should be initiated whenev er there is a change in the ambient operating temperature or supply voltage. calibration should also be initiated if t here is a change in the gain, filt er notch, bipolar, or unipolar inpu t range. non-calibrated data can be obtained from the dev ice by writing 000000 to the offset calibration register, 800000 (h) to the positive full scale calibration register, and 800000 (h) to the negative full scale calibration register. this sets the offset correction factor to 0 and both the positive and negative gain slope factors to 1. alias band f n ? f c frequency (hz) amplitude (db) f n f c 2f n 3f n 4f n 0 -20 -40 -60 -80 -100 -120 figure 9. low pass filter frequency characteristics figure 10a. figure 10b. figure 10. oscillator configurations HI7190 osc 1 osc 2 10mhz 16 17 HI7190 osc 1 osc 2 10mhz 16 17 no connection
HI7190 fn3612 rev 10.00 page 14 of 25 june 27, 2006 the HI7190 offers several differ ent modes of self-calibration and system calibration. for calibration to occur, the on-chip microcontroller must convert the modulator output for three different input conditions - z ero-scale, positive full scale , and negative full scale. with these readings, the HI7190 can null any offset errors and c alculate the gain slope factor for the transfer func tion of the converter. it is imperative th at the zero-scale calibration be performed before either of the gain calibrations. however, the order of the gain calibrations is not important. the calibration modes are us er selectable in the control register by using the md b its (md2-md0) as shown in table 4. drdy will go low indicating that the calibration is complete and there is valid dat a at the output. conversion mode for conversion mode operatio n the HI7190 converts the differential voltage between v inhi and v inlo . from switching into this mode it ta kes 3 conversion periods (3 x 1/f n ) for drdy to go low and new data to be valid. no calibration coefficients are generated when operating in conversion mode as data is ca librated using the existing calibration coefficients. self-calibration mode please note: self-ca libration is only valid when operating in a gain of one. in addition, the o ffset and gain errors are not reduced as with the fu ll system calibration. the self-calibration mode is a three step process that updates the offset ca libration register, the positive full scale calibration register, a nd the negative full scale calibration register. in this mode an internal offset calibration is done by disconn ecting the external inputs and shorting the inputs of the pgia together. afte r 3 conversion periods the offset calibration register is upd ated with the value that corrects any internal offset errors. after the offset calibration i s completed, the positive and negative full scale calibrat ion registers are updated. the inputs v inhi and v inlo are disconnected and the external reference is applied across the modulator inputs. the HI7190 then takes 3 convers ion cycles to sample the data and update the positive full scal e calibration register. next the polarity of the reference voltage across the modulator input terminals is reversed and after 3 conversion cycles the negative full scale calibrat ion register is updated. the values stored in the posit ive and negativ e full scale calibration registers correct f or any internal gain errors in the a/d transfer function. after 3 more conversion cycles the drdy line will activate signali ng that the calibration is complete and valid data is present in the data output register. system offset calibration mode the system offset calibration mode is a single step process that allows the user to lump offset errors of external circuitr y and the internal errors of the HI7190 together and null them out. this mode will convert the e xternal differential signal applied to the v in inputs and then store that value in the offset calibration register. the user must apply the zero point or offset voltage to the HI7190 analog inputs and allow the signal to settle before selecting this mode. after 4 conversion periods the drdy line will activate signaling that the calibration is complete a nd valid data is present in the data output register. system positive full scale calibration mode the system positive full scale calibration mode is a single step process that a llows the user to lump gain errors of external circuitry and the i nternal errors of the HI7190 together and null them out. this mode will convert the external differential signal applied to the v in inputs and stores the converted value in the positive full scale calibration register. the user must apply the +full scale voltage to the HI7190 analog inputs and allow the signal to settle before selecting this mode. after 4 conversion periods the drdy line will activate signa ling the calibration is complete and valid data is present in the data output register. system negative full scale calibration mode the system negative full sca le calibration mode is a single-step process that allows the user to lump gain errors of external circuitry and the internal errors of the HI7190 together and null them out. this mode will convert the external differential signal applied to the v in inputs and stores the converted value in the negative full scale calibration register. the user must apply the -full scale voltage to the HI7190 analog inputs and allow the signal to settle before selecting this mode. after 4 conversion periods the drdy line will activate signa ling the calibration is complete and valid data is present in the data output register. table 4. HI7190 operational modes md2 md1 md0 operational mode 0 0 0 conversion 0 0 1 self calibration (gain of 1 only) 0 1 0 system offset calibration 0 1 1 system positive full scale calibration 1 0 0 system negative full scale calibration 1 0 1 system offset/internal gain calibration (gain of 1 only) 1 1 0 system gain calibration 111reserved
HI7190 fn3612 rev 10.00 page 15 of 25 june 27, 2006 system offset/interna l gain calibration mode please note: system offset/internal gain is only valid when operating in a gain of one. in addition, the offset and gain er rors are not reduced as with th e full system calibration. the system offset/internal gain calibration mode is a single step process that up dates the offset calibration register, the positive full scale cali bration register, and the negative full scale calibration register. first the external differential signal applied to the v in inputs is converted and that value is stored in the o ffset calibration register. the user must apply the zero point or offset voltage to the HI7190 analog inputs and allow the signal to settle before selecting this mode. after this is completed the po sitive and negative full scale calibration registers are updated. the inputs v inhi and v inlo are disconnected and the external reference is switched in. the HI7190 then takes 3 conversion cycles to sample the data and update the positive full scale ca libration register. next the polarity of the reference voltage across the v inhi and v inlo terminals is rever sed and after 3 c onversion cycles the negative full calibration regi ster is updated. the values stored in the positive and n egative full scale calibration registers correct for any interna l gain errors in the a/d trans fer function. after 3 more conver sion cycles, the drdy line will activate signaling that the calibration is complete and valid d ata is present in the da ta output register. system gain calibration mode the gain calibration mode is a single step process that updates the positive and nega tive full scale calibration registers. this mode will conver t the external differential signal applied to the v in inputs and then store that value in the negative full scale cali bration register. then the polarity of the input is rever sed internally and another conversion is performed. this c onversion result is written to the positive full scale calibr ation register. the user must apply the +full scale voltag e to the HI7190 analog inputs and allow the signal to settle before selecting this mode. after 1 more convers ion period the drdy line will activate signaling the calibration is complete and valid data is present in the data outpu t register. reserved this mode is not used in t he HI7190 and s hould not be selected. there is no internal detection logic to keep this condition from being selected and care should be taken not to assert this bit combination. offset and span limits there are limits to t he amount of offset and gain which can be adjusted out for the HI7190. for both bipolar and unipolar modes the minimum and maximum input spans are 0.2 x v ref /gain and 1.2 x v ref /gain respectively. in the unipolar mode the offset plus the span cannot exceed the 1.2 x v ref /gain limit. so, if the span is at its minimum value of 0.2 x v ref /gain, the offset must be less than 1 x v ref /gain. in bipolar mode the span is equidistant around the voltage used for the zero scale poin t. for this mode the offset plus half the span cannot exceed 1.2 x v ref /gain. if the span is at ? 0.2 x v ref /gain ?? then the offset can not be greater than ?? 2 x v ref /gain. serial interface the HI7190 has a flexible, synchronous serial communication port to allow easy interfacing to many indus try standard microcontrollers and micr oprocessors. t he serial i/o is compatible with most synchro nous transfer formats, including both the motorola 6805/11 spi and intel 8051 ssr protocols. the serial interface is a flexi ble 2-wire or 3-wire hardware interface where the HI7190 c an be configured to read and write on a single bidirectional line (sdio) or configured for writing on sdio and reading on the sdo line. the interface is byte organi zed with each register byte having a specific address and single or multiple byte transfers are supported. in addition, the interface allows flexibility as to the byte and bit access order. that is, the u ser can specify msb/lsb first bi t positioning and can access bytes in ascending/descending order from any byte position. the serial interface allows t he user to communicate with 5 registers that control the operation of the device. data output register - a 24-bit, read only register containing the conversion results. control register - a 24-bit, read/writ e register containing the setup and o perating modes of the device. offset calibration register - a 24-bit, read/write register used for calibrating the zero poi nt of the converter or system. positive full scale calibration register - a 24-bit, read/write register used for calibrating the positive full scal e point of the converter or system. negative full scale calibration register - a 24-bit, read/write register used for c alibrating the negative full scale point of the co nverter or system. two clock modes are supported. the HI7190 can accept the serial interface clock (sclk) a s an input from the system or generate the sclk signal as a n output. if the mode pin is logic low the HI7190 is in ext ernal clocking mode and the sclk pin is configured as an i nput. in this mode the user supplies the serial interface c lock and all interface timing specifications are synchronous to this input. if the mode pin is logic high the HI7190 is in self-c locking mode and the sclk pin is configured as an output. in self-clocking mode, sclk runs at f sclk = osc 1 /8 and stalls high at byte boundaries. sclk does not have the capability to stall low in this mode. all interface timing specifications are synchronous to the sclk output. normal operation in self-clocki ng mode is as follows (see figure 12): cs is sampled low on falling osc 1 edges. the
HI7190 fn3612 rev 10.00 page 16 of 25 june 27, 2006 first sclk transition ou tput is delayed 29 osc 1 cycles from the next rising osc 1 . sclk transitions e ight times and then stalls high for 28 osc 1 cycles. after this stall period is completed sclk will again transition eight times and stall high. this sequence will repea t continuously while cs is active. the extra osc 1 cycle required when coming out of the cs inactive state is a one clo ck cycle latency required to properly sample the cs input. note that the normal stall at byte boundaries is 28 osc 1 cycles thus giving a sclk rising to rising edge stall period of 32 osc 1 cycles. the affects of cs on the i/o are differ ent for self-clocking mode (mode = 1) than for exte rnal mode (mode = 0). for external clocking mode cs inactive disables the i/o state machine, effectively freezing the state of the i/ o cycle. that is, an i/o cycle can be interrup ted using chip select and the HI7190 will continue wit h that i/o cycle when re-enabled via cs . sclk can continue toggling while cs is inactive. if cs goes inactive durin g an i/o cycle, it is up to the user to ensure that the state of sclk is identical when reactivating cs as to what it was when cs went inactive. for read operations in external clocki ng mode, the output will go three-state immediately upon deactivation of cs . for self-clocking mode (mode = 1), the affects of cs are different. if cs transitions high (inactive) during the period when data is being transferred (any non stall time) the HI7190 will complete the data transfer to the byte boundary. that is, once sclk begins the eight transition sequence, it will always complete the eight cycles. if cs remains inactive after the byt e has been transferred it will be sampled and sclk will remain stalled high indefinitely. if cs has returned to active low bef ore the data byte transfer period is completed the HI7190 acts as if cs was active during the entire transfer period. it is important to r ealize that the user c an interrupt a data transfer on byte boundaries . that is, if the instruction register calls for a 3 byte transfer and cs is inactive after only one byte has been tr ansferred, the HI7190, when reactivated, will continue with the remaining two bytes before looking for th e next instruction r egister write cycle. note that the outputs will not go three-state immediately upon cs inactive for read operations i n self-clocking mode. in the case of cs going i nactive during a re ad cycle the outputs remain driving until after the last data bit is transferred. in the case of cs inactive during the clock stall time it takes 1 osc 1 cycle plus prop delay (max) for the outputs to be disabled. i/o port pin descriptions the serial i/o port is a bidir ectional port which is used to read the data register and read or write t he control register and calibration registers. the po rt contains two data lines, a synchronous clock, and a stat us flag. figure 11 shows a diagram of the serial interface lines. sdo - serial data out. data is read from this line using those protocols with separ ate lines for transmi tting and receiving data. an example of such a st andard is the motorola serial peripheral interface (spi) using the 68hc05 and 68hc11 family of microcontrollers, or other similar processors. in the case of using bidirectional data transfer on sdio, sdo does not output data and is set i n a high impedance state. sdio - serial data in or out. da ta is always written to the device on this line. however, this line can be used as a bidirectional data line. this is done by properly setting up th e control register. bidirectional data transfer on this line can be used with intel standard seri al interfaces (ssr, mode 0) in mcs51 and mcs96 family of microcontrollers, or other similar processors. sclk - serial clock. the seria l clock pin is used to synchronize data to and from the HI7190 and to run the port state machines. in synchronou s external clock mode, sclk is configured as an input, is supplied by the user, and can run up to a 5mhz rate. in syn chronous self clocking mode, sclk is configured as an output and runs at osc 1 /8. cs - chip select. this signal is an active low input that allows more than one device on the same serial communication lines. the sdo and sdio will go to a high impedance state when this signal is high. if driven high d uring any commun ication cycle, that cycle will be suspended until cs reactivation. chip select can be tied low in systems t hat maintain control of sclk. chip select sdo sdio sclk cs drdy HI7190 device status bidirectional data data out port clock mode clock mode figure 11. HI7190 serial interface osc 1 cs sclk 29 33 37 41 45 89 121 125 figure 12. sclk output in self-clocking mode
HI7190 fn3612 rev 10.00 page 17 of 25 june 27, 2006 drdy - data ready. this is an ou tput status flag from the device to signal that the dat a output register has been updated with the new con version result. drdy is useful as an edge or level sensitive interrupt signal to a microprocessor or microcontroller. drdy low indicate s that new data is available at the data output register. drdy will return high upon completion of a comp lete data output reg ister read cycle. mode - mode. this input is used to select between synchronous self clocking mode (1) or the synchronous external clocking mode (0). when this pin is tied to v dd the serial port is configured in the synchronous self clocking mode where the synchronous shift clock (sclk) for the serial port is generated by the HI7190 and has a frequency of osc 1 /8. when the pin is tied to dgnd the serial port is configured for the synchron ous external clocking mode where the synchronous shift clo ck for the serial port is generated by an external devic e up to a maximum frequency of 5mhz. programming the se rial interface it is useful to think of the HI7190 interface in terms of communication cycles. each communication cycle happens in 2 phases. the first phase o f every communication cycle is the writing of an instructio n byte. the second phase is the data transfer as described b y the instruction byte. it is important to note that phase 2 of the communication cycle can be a single byte or a mult i-byte transfer of data. for example, the 3-byte data output register can be read using one multi-byte communication cycle rather than three single-byte communication cyc les. it is up to the user to maintain synch ronism with respect to data transfers. if the system processor gets lost th e only way to recover is to reset the HI7190. figures 13a and 13b show both a 2-wire and a 3-wire data transfer. several formats are available for reading from and writing to the HI7190 registers in both t he 2-wire and 3-wire protocols. a portion of these formats is controlled by the cr<2:1> (bd and msb ) bits which control the byt e direction and bit order of a data transfer respectively. these two bits can be written in any combination but only t he two most useful will be discussed here. the first combination is to re set both the bd and msb bits (bd = 0, msb = 0). this sets up the interface for descending byte order and msb first forma t. when this combination is used the user should always writ e the instruct ion register such that the starting byte i s the most significant byte address. for example, read thr ee bytes of dr starting with the most significant byte. the f irst byte read will be the most significant in msb to lsb fo rmat. the next byte will be the next least significant (recall de scending byte order) again in msb to lsb order. the last b yte will be the next lesser significant byte in msb to lsb order. the entire word was read msb to lsb format. the second combination is t o set both the bd and msb bits to 1. this sets up the interface for ascending byte order and lsb first format. when this co mbination is used the user should always write the instru ction register such that the starting byte is the least si gnificant byte address. for example, read three bytes of dr starting with the least significant byte. the first b yte read will be the least significant in lsb to msb forma t. the next byte will be the next greater significant (recall ascending byte order) again in lsb to msb order. the last byt e will be the next greater significant byte in lsb to msb order. the entire word was read msb to lsb format. after completion of each comm unication cycle, the HI7190 interface enters a standby mode while waiting to receive a new instruction byte. instruction byte phase the instruction by te phase initiates a data transfer sequence. the processor writes an 8-bit byte (instruction byte) to the instruction register. the instruction byte informs the HI7190 about the data transfer phase activities and includes the following information: ? read or write cycle ? number of bytes to be transferred ? which register and starting byte to be accessed data transfer phase in the data transfer phase, data transfer takes place as set by the instruction register contents. see write operation and read operation sections for detailed descriptions. instruction byte data byte 1 data byte 2 data byte 3 instruction data transfer cycle cs sdio figure 13a. 2-wire, 3-byte read or write transfer instruction byte data byte 1 data byte 2 data byte 3 instruction data transfer cycle cs sdio sdo figure 13b. 3-wire, 3-byte read transfer
HI7190 fn3612 rev 10.00 page 18 of 25 june 27, 2006 instruction register the instruction register is an 8-bit register which is used during a communications cycle for setting up read/write operations. r/w - bit 7 of the instruction r egister determines whether a read or write operati on will be done followi ng the instruction byte load. 0 = read, 1 = write. mb1, mb0 - bits 6 and 5 of the instruction register determine the number of by tes that will be accessed following the instruction byte load. see table 5 for the number of bytes to transfe r in the tra nsfer cycle. fsc - bit 4 is used to determine whether a positive full scale calibration register i/o transfer (f sc = 0) or a negative full scale calibration register i /o transfer (fsc = 1) is being performed (see table 6). a3, a2, a1, a0 - bits 3 and 2 (a3 and a2) of the instruction register determine which inte rnal register will be accessed while bits 1 and 0 (a1 and a0) determine which byte of that register will be accessed first . see table 6 for the address decode. write operation data can be written to the control register, offset calibration register, positive full scale calibration register, and the negative full scale calibration register. write operations are done using the sdio, cs and sclk lines only, as all data is written in to the HI7190 via the sdio line even when using the 3-wire conf iguration. figures 14 and 15 show typical write timing diagrams. the communication cycle is s tarted by asserting the cs line low and starting the clock from its idle state. to assert a wri te cycle, during the instruction phase of the communication cycle, the instruction byte should be set to a write transfer (r /w = 1). when writing to the serial por t, data is lat ched into the HI7190 on the risi ng edge of sclk. data can then be changed on the falling edge of sclk. data can also be changed on the rising edge of sclk due to the 0ns hold time required on the data. this is u seful in pipelined applications where the data is latched on the rising edge of the clock. read operation - 3-wire transfer data can be read from the dat a output register, control register, offset calibration register, positive full scale calibration register, and the negative full scale calibration register. when configured i n 3-wire transfer mode, read operations are done us ing the sdio, sdo, cs and sclk lines. all data is read via the sdo line. figures 16 and 17 show typical 3-wire read timing diagrams. the communication cycle is s tarted by asserting the cs line and starting the clock from its idle state. to assert a read cycle, during the instruction phase of the communication cycle, the instruction byte should be set to a read transfer (r /w = 0). when reading the serial port, data is driven out of the HI7190 on the falling edge of sclk. data can be registered externally on the nex t rising edge of sclk. read operation - 2-wire transfer data can be read from the dat a output register, control register, offset calibration register, positive full scale calibration register, and the negative full scale calibration register. when configured in two-wire transfer mode, read operations are done using the sdio, cs and sclk lines. all data is read via the sdio li ne. figures 18 and 19 show typical 2-wire read timing diagrams. instruction register msb654321lsb r/w mb1 mb0 fsc a3 a2 a1 a0 table 5. multiple byte access bits mb1 mb0 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes table 6. internal data a ccess decode starting byte fsca3a2a1a0 description x 0000data output register, byte 0 x 0001data output register, byte 1 x 0010data output register, byte 2 x 0100control register, byte 0 x 0101control register, byte 1 x 0110control register, byte 2 x 1000offset cal register, byte 0 x 1001offset cal register, byte 1 x 1010offset cal register, byte 2 0 1100positive full scale cal register, byte 0 0 1101positive full scale cal register, byte 1 0 1110positive full scale cal register, byte 2 1 1100n egative full scale cal register, byte 0 1 1101n egative full scale cal register, byte 1 1 1110n egative full scale cal register, byte 2 table 6. internal data access decode starting byte (continued) fsca3a2a1a0 description
HI7190 fn3612 rev 10.00 page 19 of 25 june 27, 2006 the communication cycle is start ed by asserti ng the cs line and starting the clock from its i dle state. to assert a read cy cle, during the instructi on phase of the comm unication cycl e, the instruction byte should be set t o a read transfer (r/w = 0). when reading the serial port, data is driven out of the HI7190 on the falling edge of sclk . data can be registered externally on the next rising edge of sclk. detailed register descriptions data output register the data output register contains 24 bits of converted data. this register is a read only register. byte 2 msb22212019181716 d23 d22 d21 d20 d19 d18 d17 d16 byte 1 15 14 13 12 11 10 9 8 d15 d14 d13 d12 d11 d10 d9 d8 byte 0 7654321lsb d7 d6 d5 d4 d3 d2 d1 d0 ir write phase data transfe r phase - two-byte write cs sclk sdio sdo three-state three-state i0 i1 i2 i3 i4 i5 i6 i7 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 figure 14. data write cycle, sclk idle low ir write phase data transfe r phase - two-byte write cs sclk sdio sdo i0 i1 i2 i3 i4 i5 i6 i7 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 three-state three-state figure 15. data write cycle, sclk idle high data transfer phase - two-byte read cs sclk sdio sdo i0 i1 i2 i3 i4 i5 i6 i7 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 ir write phase figure 16. data read cycle, 3-w ire configuration, sclk idle low
HI7190 fn3612 rev 10.00 page 20 of 25 june 27, 2006 control register the control register contains 24-bits to control the various sections of the HI7190. this register is a read/write register. dc - bit 23 is the data coding bit used to select between twos complementary and offs et binary data coding. when this bit is set (dc = 1) the dat a in the data output register will be twos complem ent. when cleared ( dc = 0) this data will be offset binary. when oper ating in the unipolar mode the output data is available in straight binary only (the dc bi t is ignored). this bit is cleared after a reset is applied to the part. fp10 through fp0 - bits 22 through 12 are the filter programming bits that determin e the frequency response of the digital filter. these bits determine the filter cutoff frequency, the position of the fi rst notch and the data rate of the HI7190. the firs t notch of the filter is equal to the decimation rate and can be d etermined by the formula: f notch = f osc /(512 x code) where code is the decimal equi valent of the value in fp10 through fp0. the values that can be programmed into these bits are 10 to 2047 decimal, which allows a conversion rate range of 9.54hz to 1.953kh z when using a 10mhz clock. ir write phase dat a transfer phase - two-byte read cs sclk sdio sdo i0 i1 i2 i3 i4 i5 i6 i7 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 figure 17. data read cycle, 3-wire configuration, sclk idle high three-state three-state ir write phase data transfe r phase - two-byte read cs sclk sdio sdo i0 i1 i2 i3 i4 i5 i6 i7 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 figure 18. data read cycle, 2-wire configuration, sclk idle low three-state three-state ir write phase data transfe r phase - two-byte read cs sclk sdio sdo i0 i1 i2 i3 i4 i5 i6 i7 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 figure 19. data read cycle, 2-wire configuration, sclk idle high byte 2 msb22212019181716 dc fp10 fp9 fp8 fp7 fp6 fp5 fp4 byte 1 15 14 13 12 11 10 9 8 fp3 fp2 fp1 fp0 md2 md1 md0 b/u byte 0 7654321lsb g2 g1 g0 bo sb bd msb sdl
HI7190 fn3612 rev 10.00 page 21 of 25 june 27, 2006 changing the filter notch freque ncy, as well as the selected gain, impacts resolution. the ou tput data rate (or effective conversion time) for the dev ice is equal to the frequency selected for the first notch to the filter. for example, if the first notch of the filter is se lected at 50hz then a new word i s available at a 50hz rate or every 20ms. if the first notch is a t 1khz a new word is a vailable every 1ms. the settling-time of the converter to a f ull scale step input change is between 3 and 4 times the data rate. for example, with the first filter notch at 50 hz, the worst case settling ti me to a full scale step input chan ge is 80ms. if the first notch i s 1khz, the settling ti me to a full scale input step is 4ms maximum. the -3db frequency is determi ned by the programmed first notch frequency according to the relationship: f -3db = 0.262 x f notch . md2 through md0 - bits 11 through 9 are the operational modes of the converter. see t able 4 for the operational modes description. after a reset is applied to the part these bits are set to the self calibration mode. b/u - bit 8 is the bipolar/unipolar select bit. when this bit is set the HI7190 is configured for bipolar operation. when this bit is reset the part is in unipo lar mode. this bit is set afte r a reset is applied to the part. g2 through g0 - bits 7 through 5 select the gain of the input analog signal. the gain is accomplished through a programmable gain instrumentat ion amplifier that gains up incoming signals from 1 to 8. this is achieved by using a switched capacitor voltage mult iplier network preceding the modulator. the higher gains (i.e., 16 to 128) are achieved through a combination of a pgi a gain of 8 and a digital multiply after the digital filt er (see table 7). the gain will affect noise and signal to no ise ratio of t he conversion. these bits are cleared to a gain of 1 (g2, g1, g0 = 000) after a reset is applied to the part. bo - bit 4 is the transducer bur n-out current source enable bit. when this bit is set (bo = 1) the burn-out current source connected to v inhi internally is enabled. this current source can be used to detect the presence of an external connection to v inhi . this bit i s cleared after a reset is applied to the part. sb - bit 3 is the standby mode e nable bit used to put the HI7190 in a lower power/stan dby mode. when this bit is set (sb = 1) the filter nodes are halted, the drdy line is set high and the modulator clock is disabled. when this bit is cleared the HI7190 begins operation as described by the contents of the control register. for exampl e, if the control register is programmed for self calibration mode and a notch frequency to 10hz, the hi 7190 will perform the self calibration before providing t he data at the 10h z rate. this bit is cleared after a reset is applied to the part. bd - bit 2 is the byte direction bit used to sel ect the multi- byte access ordering. the bi t determines the either ascending or descending order access for the multi-byte registers. when set (bd = 1) t he user can acce ss multi-byte registers in ascending byte order and when cleared (bd = 0) the multi-byte registers are accessed in descending byte order. this bit is c leared after a reset is applied to the part. msb - bit 1 is used to select whether a serial data transfer is msb or lsb first. this bit all ows the user to change the order that data can be trans mitted or received by the HI7190. when this bit is cleared (msb = 0) the msb is the first bit in a serial data transfer. if set (msb = 1), the lsb is the first bit transferred in the serial data stream. this bit i s cleared after a reset is applied to the part. sdl - bit 0 is the serial data line control bit. this bit selec ts the transfer protocol of the ser ial interface. w hen this bit is cleared (sdl = 0), both read and write data transfers are done using the sdio line. when set (sdl = 1), write transfers are done on the sdio line and read transfers are done on the sdo line. this bi t is cleared after a reset is applied to the part. reading the data output register the HI7190 generates an active low interrupt (drdy ) indicating valid conversion result s are available for reading. at this time the data outpu t register contains the latest conversion result available from the HI7190. data integrity is maintained at the serial output p ort but it is possible to miss a conversion result if the da ta output register is not read within a given period of time. maintaining data integrity means that if a data output register read of conversion n is begun but not finished bef ore the next conversion (conversion n + 1) is complete, the drdy line remains active low and the data bei ng read is not overwritten. in addition to the data output register, the HI7190 has a one conversion result storage buffer. no conversion results will be lost if the followin g constraints are met. 1) a data output register read cycle is started for a given conversion (conv ersion x) 1/f n - (128*1/f osc ) after drdy initially goes active low. failu re to start the read cycle may table 7. gain select bits g2 g1 g0 gain gain achieved 0 0 0 1 pgia = 1, filter multiply = 1 0 0 1 2 pgia = 2, filter multiply = 1 0 1 0 4 pgia = 4, filter multiply = 1 0 1 1 8 pgia = 8, filter multiply = 1 1 0 0 16 pgia = 8, filter multiply = 2 1 0 1 32 pgia = 8, filter multiply = 4 1 1 0 64 pgia = 8, filter multiply = 8 1 1 1 128 pgia = 8, filter multiply = 16
HI7190 fn3612 rev 10.00 page 22 of 25 june 27, 2006 result in conversion x + 1 data overwriting conversion x results. for example, with f osc = 10mhz, f n = 2khz, the read cycle must start w ithin 1/2000 - 128(1/10 6 ) = 487 ? s after drdy went low. 2) the data output register r ead cycle for conversion x must be completed within 2(1/f n )-1440(1/f osc ) after drdy initially goes active low. if t he read cycle for conversion x i s not complete within this time t he results of conversion x + 1 are lost and results from conve rsion x + 2 are now stored in the data output word buffer. completing the data output re gister read cycle inactivates the drdy interrupt. if the one word d ata output buffer is full when this read is complete this data will be immediately transferred to the data out put register and a new drdy interrupt will be issued after the minimum drdy pulse high time is met. writing the control register if data is written to byte 2 and/or byte 1 of the control register the drdy output is taken high and the device re- calibrates if written to a calibration mode. this action is tak en because it is assumed that by writing byte 2 or byte 1 that the user either reprogrammed the filter or changed modes of the part. however, if a single da ta byte is written to byte 0, it is assumed that the gain has not been changed. it is up to the user to re-calibrate the hi 7190 after the gain has been changed by this method. it is r ecommended that the entire control register be written to when chan ging the selected gain. this ensures that the part is re-calibrated before the drdy signal goes low indicating valid data is available. offset calibration register the offset calibration register is a 24-bit register containing the offset correction factor. th is register is indeterminate on power-up but will contain a sel f calibration correction value after a reset has been applied. the offset calibration register holds the value that corrects the filter output data to all 0s when the analog input is 0v. positive full scale calibration register the positive full scale cali bration regist er is a 24-bit register containing the positive full scale correction coefficient. this coefficient is used to determine the positive gain slope factor. this register is indeterminate on power-up but will contain a self calibration correction coefficient afte r a reset has been applied. negative full scale calibration register the negative full scale calibr ation register is a 24-bit register containing the ne gative full scale correction coefficient. this coefficient is used to determine the negative gain slope factor. this register is indeterminate on power-up but will contain a self calibration correction coefficient afte r a reset has been applied. byte 2 msb22212019181716 o23 o22 o21 o20 o19 o18 o17 o16 byte 1 15 14 13 12 11 10 9 8 o15 o14 o13 o12 o11 o10 o9 o8 byte 0 7654321lsb o7 o6 o5 o4 o3 o2 o1 o0 byte 2 msb22212019181716 p23p22p21p20p19p18p17p16 byte 1 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 byte 0 7654321lsb p7 p6 p5 p4 p3 p2 p1 p0 byte 2 msb22212019181716 n23 n22 n21 n20 n19 n18 n17 n16 byte 1 15 14 13 12 11 10 9 8 n15 n14 n13 n12 n11 n10 n9 n8 byte 0 7654321lsb n7 n6 n5 n4 n3 n2 n1 n0
HI7190 fn3612 rev 10.00 page 23 of 25 june 27, 2006 die characteristics die dimensions 3550 ? m x 6340 ? m metallization type: alsicu thickness:metal 2, 16k ? metal 1, 6k ? substrate potential (powered up) av ss passivation type: sandwich thickness:nitride 8k ? usg 1k ? metallization mask layout HI7190 sclk sdo sdio cs drdy dgnd av ss v rlo v rhi v cm v inlo v inhi av dd mode sync reset agnd dv dd osc 2 osc 1
HI7190 fn3612 rev 10.00 page 24 of 25 june 27, 2006 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between eng lish and metric dimensions, t he inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the mo s eries symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated i n jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrus ions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpen- dicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not i nclude dambar protrusions. dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 in ch (0.76 - 1. 14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e20.3 (jedec ms-001-ad issue d) 20 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.55 1.77 8 c 0.008 0.014 0.204 0.355 - d 0.980 1.060 24.89 26.9 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n20 209 rev. 0 12/93
fn3612 rev 10.00 page 25 of 25 june 27, 2006 HI7190 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2003-2006. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. small outline plast ic packages (soic) notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions . interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greate r above the seating plane, shall no t exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m ? m20.3 (jedec ms-013-ac issue c) 20 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.014 0.019 0.35 0.49 9 c 0.0091 0.0125 0.23 0.32 - d 0.4961 0.5118 12.60 13.00 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n20 207 ? 0 8 0 8 - rev. 2 6/05

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