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datasheet 9fgv0841 june 26, 2017 1 ?2017 integrated device technology, inc. 8-output very low-power pcie gen1-2-3-4 clock generator with zo=100ohms 9fgv0841 description the 9fgv0841 is a member of idt's soc-friendly 1.8v very low-power pcie clock family. it has integrated output terminations providing zo = 100 ? for direction connection to 100 ? transmission lines. the device has 8 output enables for clock management, 2 different spread spectrum levels in addition to spread off, and 2 selectable smbus addresses. typical applications pcie gen1?4 clock generation for riser cards, storage, networking, jbod, communications, access points output features ? 8 100mhz low-power (lp) hc sl dif pairs with zo = 100 ? ? 1 1.8v lvcmos ref output with wake-on-lan (wol) support key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-2-3-4 compliant ? ref phase jitter is <1.5ps rms features ? direct connection to 100 ? transmission lines; saves 32 resistors compared to standard pcie devices ? 62mw typical power consum ption; reduced thermal concerns ? outputs can optionally be supplied from any voltage between 1.05 and 1.8v; maximum power savings ? oe# pins; support dif power management ? lp-hcsl differential clock outputs; reduced power and board space ? programmable slew rate for each output; allows tuning for various line lengths ? programmable output amplitude; allows tuning for various application environments ? dif outputs blocked until pll is locked; clean system start-up ? selectable 0%, -0.25% or -0.5% spread on dif outputs; reduces emi ? external 25mhz crystal; supports tight ppm with 0 ppm synthesis error ? configuration can be accomplished with strapping pins; smbus interface not required for device control ? 3.3v tolerant smbus interface works with legacy controllers ? selectable smbus addresses; mu ltiple devices can easily share an smbus segment ? space saving 6 x 6 mm 48-vfqfpn; minimal board space block diagram xin/clkin_25 x2 control logic vss_en_tri ^ckpwrgd_pd# sdata_3.3 ss capable pll osc ref1.8 voe(7:0)# sclk_3.3 vsadr dif0 dif1 dif2 dif3 dif4 dif5 dif6 dif7 8
8-output very low-power pcie gen1-2-3-4 cl ock generator with zo=100ohms 2 june 26, 2017 9fgv0841 datasheet pin configuration smbus address selection table power management table power connections ^ckpwrgd_pd# vddio voe7# dif7# dif7 voe6# dif6# dif6 gnd vddio vdd1.8 voe5# 48 47 46 45 44 43 42 41 40 39 38 37 vss_en_tri 1 36 dif5# gndxtal 2 35 dif5 x1_25 3 34 voe4# x2 4 33 dif4# vddxtal1.8 5 32 dif4 vddref1.8 6 31 vddio vsadr/ref1.8 7 30 vdda1.8 gndref 8 29 gnda gnddig 9 28 voe3# sclk_3.3 10 27 dif3# sdata_3.3 11 26 dif3 vdddig1.8 12 25 voe2# 13 14 15 16 17 18 19 20 21 22 23 24 vddio voe0# dif0 dif0# voe1# dif1 dif1# vdd1.8 vddio gnd dif2 dif2# vv prefix indicates internal 60kohm pull-down resisto r v prefix indicates internal 120kohm pull-down resistor ^ prefix indicates internal 120kohm pull-up resistor 6 x 6 mm 48-vfqfpn, 0.4mm pitch 9fgv0841 sadr address 0 1101000 1 1101010 + read/write bit x x state of sadr on first application of ckpwrgd_pd# oex# true o/p comp. o/p 0xxlowlow hi-z 1 1 1 0 running running running 1 0 1 low low low 1. ref is hi-z until the 1st assertion of ckpwrgd_pd# high. after this, when ckpwrg_pd# is low, ref is low. ref ckpwrgd_pd# smbus oe bit difx pin number vdd vddio gnd 5 2 xtal osc 68ref power 12 9 digital (dirty) power 20,38 13,21,31,39, 47 22,29,40 dif outputs 30 29 pll analog description
june 26, 2017 3 8-output very low-power pcie ge n1-2-3-4 clock generator with zo=100ohms 9fgv0841 datasheet pin descriptions pin # pin name type description 1vss_en_tri latched in latched select input to select spread spectrum amount at initial power up : 1 = -0.5% spread, m = -0.25%, 0 = spread off 2 gndxtal gnd gnd for xtal 3 x1_25 in crystal input, nominally 25.00mhz. 4 x2 out crystal output. 5 vddxtal1.8 pwr power supply for xtal, nominal 1.8v 6 vddref1.8 pwr vdd for ref output. nominal 1.8v. 7vsadr/ref1.8 latched i/o latch to select smbus address/1.8v lvcmos copy of x1/refin pin 8 gndref gnd ground pin for the ref outputs. 9 gnddig gnd ground pin for digital circuitry 10 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant. 11 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 12 vdddig1.8 pwr 1.8v digital power (dirty power) 13 vddio pwr power supply for differential outputs 14 voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 15 dif0 out differential true clock output 16 dif0# out differential complementary clock output 17 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 18 dif1 out differential true clock output 19 dif1# out differential complementary clock output 20 vdd1.8 pwr power supply, nominal 1.8v 21 vddio pwr power supply for differential outputs 22 gnd gnd ground pin. 23 dif2 out differential true clock output 24 dif2# out differential complementary clock output 25 voe2# in active low input for enabling dif pair 2. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 26 dif3 out differential true clock output 27 dif3# out differential complementary clock output 28 voe3# in active low input for enabling dif pair 3. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 29 gnda gnd ground pin for the pll core. 30 vdda1.8 pwr 1.8v power for the pll core. 31 vddio pwr power supply for differential outputs 32 dif4 out differential true clock output 33 dif4# out differential complementary clock output 34 voe4# in active low input for enabling dif pair 4. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 35 dif5 out differential true clock output 36 dif5# out differential complementary clock output 37 voe5# in active low input for enabling dif pair 5. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 38 vdd1.8 pwr power supply, nominal 1.8v 39 vddio pwr power supply for differential outputs
8-output very low-power pcie gen1-2-3-4 cl ock generator with zo=100ohms 4 june 26, 2017 9fgv0841 datasheet pin descriptions (cont.) pin # pin name type description 40 gnd gnd ground pin. 41 dif6 out differential true clock output 42 dif6# out differential complementary clock output 43 voe6# in active low input for enabling dif pair 6. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 44 dif7 out differential true clock output 45 dif7# out differential complementary clock output 46 voe7# in active low input for enabling dif pair 7. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 47 vddio pwr power supply for differential outputs 48 ^ckpwrgd_pd# in input notifies device to sample latched inputs and start up on first high assertion. low enters power down mode, subsequent high assertions exit power down mode. this pin has internal pull-up resistor.
june 26, 2017 5 8-output very low-power pcie ge n1-2-3-4 clock generator with zo=100ohms 9fgv0841 datasheet test loads alternate terminations rs rs low-power hcsl differential output test load 2pf 2pf 5 inches zo=100ohm device ref output 33 ref output test load 5pf zo = 50 ohms rs device rs zo driving lvds cc cc r7a r7b r8a r8b 3.3v lvds clock input driving lvds inputs receiver has termination receiver does not have termination r7a, r7b 10k ohm 140 ohm r8a, r8b 5.6k ohm 75 ohm cc 0.1 uf 0.1 uf vcm 1.2 volts 1.2 volts component value note
8-output very low-power pcie gen1-2-3-4 cl ock generator with zo=100ohms 6 june 26, 2017 9fgv0841 datasheet absolute maximum ratings stresses above the ratings lis ted below can cause permanent damage to the 9f gv0841. these ratings, which are standard values for idt commercially rated parts, are stress ratings on ly. functional operation of the device at these or any other conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods ca n affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. electrical characteristi cs?current consumption electrical characteristics?dif output duty cycle, jitter, and sk ew characteristics parameter symbol conditions min typ max units notes supply voltage vddxx applies to all vdd pins -0.5 2.5 v 1,2 input voltage v in -0.5 v dd +0.5v v 1, 3 input high voltage, smbus v ihsmb smbus clock and data pins 3.6v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 2.5v. ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes i ddaop vdda, all outputs active @100mhz 6 9 ma i ddop all vdd, except vdda and vddio, all outputs active @100mhz 12 16 ma i ddi oop vddio, all outputs active @100mhz 28 35 ma i ddap d vdda, dif outputs off, ref output running 0.4 1 ma 2 i ddpd all vdd, except vdda and vddio, dif outputs off, ref output running 5.3 8 ma 2 i ddi opd vddio, dif outputs off, ref output running 0.04 0.1 ma 2 i ddap d vdda, all outputs off 0.4 1 ma i ddpd all vdd, except vdda and vddio, all outputs off 0.6 1 ma i ddi opd vddio, all outputs off 0.0005 0.1 ma 1 guaranteed by design and characterization, not 100% tested in production. 2 this is the current required to have the ref output runnin g in wake-on-lan mode (byte 3, bit 5 = 1) operating supply current wake-on-lan current (ckpwrgd_pd# = '0' byte 3, bit 5 = '1') powerdown current (ckpwrgd_pd# = '0' byte 3, bit 5 = '0') ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes duty cycle t d c measured differentially, pll mode 45 50 55 % 1,2 skew, output to output t sk3 averaging on, v t = 50% 4350ps1,2 jitter, cycle to cycle t jcyc-cyc 14 50 ps 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 measured from differential waveform
june 26, 2017 7 8-output very low-power pcie ge n1-2-3-4 clock generator with zo=100ohms 9fgv0841 datasheet electrical characteristics?input/supply /common parameters?normal operating conditions ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes supply voltage vddxx supply voltage for core, analog and single-ended lvcmos outputs 1.7 1.8 1.9 v output supply voltage vddio supply voltage for differential low power outputs 0.9975 1.05-1.8 1.9 v commercial range 0 25 70 c industrial range -40 25 85 c input high voltage v ih single-ended inputs, except smbus 0.75 v dd v dd + 0.3 v input mid voltage v im single-ended tri-level inputs ('_tri' suffix) 0.4 v dd 0.5 v dd 0.6 v dd v input low voltage v il single-ended inputs, except smbus -0.3 0.25 v dd v output high voltage v ih single-ended outputs, except smbus. i oh = -2ma v dd -0.45 v output low voltage v il single-ended outputs, except smbus. i ol = -2ma 0.45 v i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua input frequency f in xtal, or x1 input 23 25 27 mhz pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c ou t output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.6 1.8 ms 1,2 ss modulation frequency f mod allowable frequency (triangular modulation) 30 31.6 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 3 clocks 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 20 300 us 1,3 tfall t f fall time of single-ended control inputs 5 ns 2 trise t r rise time of single-ended control inputs 5 ns 2 smbus input low voltage v ilsmb v ddsmb = 3.3v, see note 4 for v ddsmb < 3.3v 0.6 v smbus input high voltage v ihsmb v ddsmb = 3.3v, see note 5 for v ddsmb < 3.3v 2.1 3.6 v 4 smbus output low voltage v olsmb @ i pullup 0.4 v smbus sink current i pullup @ v ol 4ma nominal bus voltage v ddsmb 1.7 3.6 v sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 400 khz 1 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. capacitance 3 time from deassertion until out p uts are >200 mv 4 for v ddsmb < 3.3v, v ihsmb >= 0.65xv ddsmb input current ambient operating temperature t amb
8-output very low-power pcie gen1-2-3-4 cl ock generator with zo=100ohms 8 june 26, 2017 9fgv0841 datasheet electrical characteristics?di f low power hcsl outputs electrical characteristics?fi ltered phase jitter parameters - pc ie common clocked (cc) architectures ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes scope avera g in g on fast settin g 1.6 2.3 3.5 v/ns 1,2,3 scope averaging on slow setting 1.3 1.9 2.9 v/ns 1,2,3 slew rate matchin g trf slew rate matchin g , scope avera g in g on 7 20 % 1,2,4 voltage high v hi gh 660 784 850 7 voltage low v low -150 -33 150 7 max voltage vmax 816 1150 7 min volta g e vmin -300 -42 7 vswin g vswin g scope avera g in g off 300 1634 mv 1,2,7 crossing voltage (abs) vcross_abs scope averaging off 250 427 550 mv 1,5,7 crossing voltage (var) -vcross scope averaging off 12 140 mv 1,6,7 2 measured from differential waveform 7 at default smbus amplitude settin g s. measurement on single ended signal using absolute value. (scope avera g in g off) mv slew rate trf statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv 1 guaranteed by design and characterization, not 100% tested in production. 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. t amb = over the specified operating range. supply voltages per normal operation conditions, see test loads for loading conditions symbol parameter conditions min typ max specification limit units notes t jphpcieg1-cc pcie gen 1 21 25 35 86 ps (p-p) 1, 2, 3 pcie gen 2 low band 10khz < f < 1.5mhz (pll bw of 5-16mhz, 8-16mhz, cdr = 5mhz) 0.9 0.9 1.1 3 ps (rms) 1, 2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) (pll bw of 5-16mhz, 8-16mhz, cdr = 5mhz) 1.5 1.6 1.9 3.1 ps (rms) 1, 2 t jphpcieg3-cc pcie gen 3 (pll bw of 2-4mhz, 2-5mhz, cdr = 10mhz) 0.3 0.37 0.44 1 ps (rms) 1, 2 t jphpcieg4-cc pcie gen 4 (pll bw of 2-4mhz, 2-5mhz, cdr = 10mhz) 0.3 0.37 0.44 0.5 ps (rms) 1, 2 notes on pcie filtered phase jitter table 1 applies to all differential outputs, g uaranteed by desi g n and characterization. phase jitter, pll mode t jphpcieg2-cc 2 calculated from intel-supplied clock jitter tool, with spread on and off. 3 sample size of at least 100k cycles. this figure extrapolates to 108ps pk-pk at 1m cycles for a ber of 1 -12 .
june 26, 2017 9 8-output very low-power pcie ge n1-2-3-4 clock generator with zo=100ohms 9fgv0841 datasheet electrical characteristics?ref clock periods?differential outputs with spread spectrum disabled clock periods?differential outputs with spread spectrum enabled ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbo l conditions min typ max units notes long accuracy ppm see tperiod min-max values ppm 1,2 clock period t p eriod 25 mhz output 40 ns 2 rise/fall slew rate t rf1 byte 3 = 1f, 20% to 80% of vddref 0.6 1 1.6 v/ns 1 rise/fall slew rate t rf1 byte 3 = 5f, 20% to 80% of vddref 0.9 1.4 2.2 v/ns 1,3 rise/fall slew rate t rf1 byte 3 = 9f, 20% to 80% of vddref 1.1 1.7 2.7 v/ns 1 rise/fall slew rate t rf1 byte 3 = df, 20% to 80% of vddref 1.1 1.8 2.9 v/ns 1 duty cycle d t1x v t = vdd/2 v 45 49.1 55 % 1,4 duty cycle distortion d tcd v t = vdd/2 v 0 2 4 % 1,5 jitter, cycle to cycle t j c y c-c y c v t = vdd/2 v 19.1 250 ps 1,4 noise floor t j dbc1k 1khz offset -129.8 -105 dbc 1,4 noise floor t j dbc10k 10khz offset to nyquist -143.6 -115 dbc 1,4 jitter, phase t jphref 12khz to 5mhz 0.63 1.5 ps (rms) 1,4 1 guaranteed by design and characterization, not 100% tested in production. 3 default smbus value 4 when driven by a crystal. 5 when driven by an external oscillator via the x1 pin, x2 should be floating. 2 all lon g term accuracy and clock period specifications are g uaranteed assumin g that ref is trimmed to 25.00 mhz 0 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max dif 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2 measurement wi ndow units ssc off center freq. mhz notes 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max dif 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that ref is trimmed to 25.00 mhz measurement wi ndow units ssc on center freq. mhz notes
8-output very low-power pcie gen1-2-3-4 cloc k generator with zo=100ohms 10 june 26, 2017 9fgv0841 datasheet general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit note: smbus address is latched on sadr pin. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o oo oo o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o oo oo o byte n + x - 1 n not acknowledge pstop bit
june 26, 2017 11 8-output very low-power pcie gen1-2-3-4 clock generator with zo=100ohms 9fgv0841 datasheet smbus table: output enable register 1 byte 0 name control function type 0 1 default bit 7 dif oe7 output enable rw low/low enabled 1 bit 6 dif oe6 output enable rw low/low enabled 1 bit 5 dif oe5 output enable rw low/low enabled 1 bit 4 dif oe4 output enable rw low/low enabled 1 bit 3 dif oe3 output enable rw low/low enabled 1 bit 2 dif oe2 output enable rw low/low enabled 1 bit 1 dif oe1 output enable rw low/low enabled 1 bit 0 dif oe0 output enable rw low/low enabled 1 1. a low on these bits will override the oe# pin and force the differential output low/low smbus table: ss readback and control register byte 1 name control function type 0 1 default bit 7 ssenrb1 ss enable readback bit1 r latch bit 6 ssenrb1 ss enable readback bit0 r latch bit 5 ssen_swcntrl enable sw control of ss rw values in b1[7:6] control ss amount values in b1[4:3] control ss amount. 0 bit 4 ssensw1 ss enable software ctl bit1 rw 1 0 bit 3 ssensw0 ss enable software ctl bit0 rw 1 0 bit 2 1 bit 1 amplitude 1 rw 00 = 0.6v 01 = 0.7v 1 bit 0 amplitude 0 rw 10= 0.8v 11 = 0.9v 0 1. b1[5] must be set to a 1 for these bits to have any effect on the part. smbus table: dif slew rate control register byte 2 name control function type 0 1 default bit 7 slewratesel dif7 adjust slew rate of dif7 rw slow setting fast setting 1 bit 6 slewratesel dif6 adjust slew rate of dif6 rw slow setting fast setting 1 bit 5 slewratesel dif5 adjust slew rate of dif5 rw slow setting fast setting 1 bit 4 slewratesel dif4 adjust slew rate of dif4 rw slow setting fast setting 1 bit 3 slewratesel dif3 adjust slew rate of dif3 rw slow setting fast setting 1 bit 2 slewratesel dif2 adjust slew rate of dif2 rw slow setting fast setting 1 bit 1 slewratesel dif1 adjust slew rate of dif1 rw slow setting fast setting 1 bit 0 slewratesel dif0 adjust slew rate of dif0 rw slow setting fast setting 1 smbus table: nominal vhigh amplitude control/ ref control register byte 3 name control function type 0 1 default bit 7 rw 00 = slowest 01 = slow 0 bit 6 rw 10 = fast 11 = faster 1 bit 5 ref power down function wake-on-lan enable for ref rw ref does not run in power down ref runs in power down 0 bit 4 ref oe ref output enable rw low enabled 1 bit 3 1 bit 2 1 bit 1 1 bit 0 1 byte 4 is reserved reserved 00' for ss_en_tri = 0, '01' for ss_en_tri = 'm', '11 for ss_en_tri = '1' 00' = ss off, '01' = -0.25% ss, '10' = reserved, '11'= -0.5% ss reserved controls output amplitude reserved reserved reserved ref slew rate control
8-output very low-power pcie gen1-2-3-4 cloc k generator with zo=100ohms 12 june 26, 2017 9fgv0841 datasheet recommended crystal char acteristics ( 3225 package) smbus table: revision and vendor id register byte 5 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 0 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: device type/device id byte 6 name control function type 0 1 default bit 7 device type1 r 0 bit 6 device type0 r 0 bit 5 device id5 r 0 bit 4 device id4 r 0 bit 3 device id3 r 1 bit 2 device id2 r 0 bit 1 device id1 r 0 bit 0 device id0 r 0 smbus table: byte count register byte 7 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 0001 = idt vendor id writing to this register will configure how many bytes will be read back, default is = 8 bytes. byte count programming reserved a rev = 0000 revision id 001000 binary or 08 hex device id reserved 00 = fgx, 01 = dbx zdb/fob, 10 = dmx, 11= dbx fob device type reserved parameter value units notes frequency 25 mhz 1 resonance mode fundamental - 1 frequency tolerance @ 25c 20 ppm max 1 frequency stability, ref @ 25c over operating temperature range 20 ppm max 1 temperature range (commercial) 0~70 c 1 temperature range (industrial) -40~85 c 2 equivalent series resistance (esr) 50 ? 5 ppm max 1 notes: 1. fox 603-25-150. 2. for i-temp, fox 603-25-261.
june 26, 2017 13 8-output very low-power pcie gen1-2-3-4 clock generator with zo=100ohms 9fgv0841 datasheet thermal characteristics marking diagrams notes: 1. line 2 is the truncated part number. 2. ?l? denotes rohs compliant package. 3. ?i? denotes industrial temperature grade. 4. ?yyww? is the last two digits of the year and week that the part was assembled. 5. ?coo? denotes country of origin. 6. ?lot? is the lot number. parameter symbol conditions pkg typ. units notes jc junction to case 33 c/w 1 c/w 1 c/w 1 c/w 1 c/w 1 ja5 junction to air, 5 m/s air flow 26 c/w 1 thermal resistance ndg48 1 epad soldered to board ics gv0841ail yyww coo lot ics fgv0841al yyww coo lot
8-output very low-power pcie gen1-2-3-4 cloc k generator with zo=100ohms 14 june 26, 2017 9fgv0841 datasheet package outline and dimensions (6 x 6 mm 48-vfqfpn)
june 26, 2017 15 8-output very low-power pcie gen1-2-3-4 clock generator with zo=100ohms 9fgv0841 datasheet package outline and dimensions (6 x 6 mm 48-vfqfpn), cont.
8-output very low-power pcie gen1-2-3-4 cloc k generator with zo=100ohms 16 june 26, 2017 9fgv0841 datasheet ordering information ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. ?a? is the device revision designator (will not correlate with the datasheet revision). revision history part / order number shipping packaging package temperature 9fgv0841aklf trays 48-pin vfqfpn 0 to +70 c 9fgv0841aklft tape and reel 48-pin vfqfpn 0 to +70 c 9fgv0841akilf trays 48-pin vfqfpn -40 to +85 c 9FGV0841AKLIFT tape and reel 48-pin vfqfpn -40 to +85 c rev. issue date initiator description page # g 11/12/2015 rdw 1. updated pod diagram. 14 h 10/18/2016 rdw removed idt crystal part number j 6/26/2017 rg updated front page gendes to reflect the pcie gen4 updates. updated electrical characteristics - filtered phase jitter parameters - pcie common clocked (cc) architectures and added pcie gen4 data 1,7
disclaimer integrated device technology, in c. (idt) and its affiliated companies (herei n referred to as ?idt?) reserve the righ t to modify the products and/or specificat ions described herein at any time, without notice, at idt?s sole discretion. perfor mance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is prov ided without representation or wa rranty of any kind, whether expr ess or implied, including, but not limited to, the suitab ility of idt's products for any particular purpose, an implied warranty of merchantability, or non-infri ngement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intel- lectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datashee t type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology , inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales tech support www.idt.com/go/support 9fgv0841 june 26, 2017 17 ?2017 integrated device technology, inc.

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