? semiconductor components industries, llc, 2002 october, 2016 ? rev. 13 1 publication order number: nud3124/d nud3124, sznud3124 automotive inductive load driver this micro ? integrated part provides a single component solution to switch inductive loads such as relays, solenoids, and small dc motors without the need of a free ? wheeling diode. it accepts logic level inputs, thus allowing it to be driven by a large variety of devices including logic gates, inverters, and microcontrollers. features ? provides robust interface between d.c. relay coils and sensitive logic ? capable of driving relay coils rated up to 150 ma at 12 volts ? replaces 3 or 4 discrete components for lower cost ? internal zener eliminates need for free ? wheeling diode ? meets load dump and other automotive specs ? sz prefix for automotive and other applications requiring unique site and control change requirements; aec ? q101 qualified and ppap capable ? these are pb ? free devices typical applications ? automotive and industrial environment ? drives window, latch, door, and antenna relays benefits ? reduced pcb space ? standardized driver for wide range of relays ? simplifies circuit design and pcb layout ? compliance with automotive specifications gate (1) 10 k 100 k drain (3) source (2) internal circuit diagrams gate (2) 10 k 100 k drain (6) source (1) gate (5) drain (3) source (4) 10 k 100 k case 318 case 318f www.onsemi.com marking diagrams sot ? 23 case 318 style 21 jw6 m jw6 = specific device code m = date code = pb ? free package (note: microdot may be in either location) sc ? 74 case 318f style 7 jw6 = specific device code m = date code = pb ? free package (note: microdot may be in either location) jw6 m 1 2 3 1 6 device package shipping ? ordering information nud3124lt1g sot ? 23 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. nud3124dmt1g sc ? 74 (pb ? free) 3000 / tape & reel sznud3124lt1g sot ? 23 (pb ? free) 3000 / tape & reel sznud3124dmt1g sc ? 74 (pb ? free) 3000 / tape & reel
nud3124, sznud3124 www.onsemi.com 2 maximum ratings (t j = 25 c unless otherwise specified) symbol rating value unit v dss drain ? to ? source voltage ? continuous (t j = 125 c) 28 v v gss gate ? to ? source voltage ? continuous (t j = 125 c) 12 v i d drain current ? continuous (t j = 125 c) 150 ma e z single pulse drain ? to ? source avalanche energy (for relay?s coils/inductive loads of 80 or higher) (t j initial = 85 c) 250 mj p pk peak power dissipation, drain ? to ? source (notes 1 and 2) (t j initial = 85 c) 20 w e ld1 load dump suppressed pulse, drain ? to ? source (notes 3 and 4) (suppressed waveform: v s = 45 v, r source = 0.5 , t = 200 ms) (for relay?s coils/inductive loads of 80 or higher) (t j initial = 85 c) 80 v e ld2 inductive switching transient 1, drain ? to ? source (waveform: r source = 10 , t = 2.0 ms) (for relay?s coils/inductive loads of 80 or higher) (t j initial = 85 c) 100 v e ld3 inductive switching transient 2, drain ? to ? source (waveform: r source = 4.0 , t = 50 s) (for relay?s coils/inductive loads of 80 or higher) (t j initial = 85 c) 300 v rev ? bat reverse battery, 10 minutes (drain ? to ? source) (for relay?s coils/inductive loads of 80 or more) ? 14 v dual ? volt dual voltage jump start, 10 minutes (drain ? to ? source) 28 v esd human body model (hbm) according to eia/jesd22/a114 specification 2,000 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. nonrepetitive current square pulse 1.0 ms duration. 2. for different square pulse durations, see figure 2. 3. nonrepetitive load dump suppressed pulse per figure 3. 4. for relay?s coils/inductive loads higher than 80 , see figure 4.
nud3124, sznud3124 www.onsemi.com 3 thermal characteristics symbol rating value unit t a operating ambient temperature ? 40 to 125 c t j maximum junction temperature 150 c t stg storage temperature range ? 65 to 150 c p d total power dissipation (note 5) sot ? 23 derating above 25 c 225 1.8 mw mw/ c p d total power dissipation (note 5) sc ? 74 derating above 25 c 380 3.0 mw mw/ c r ja thermal resistance junction?to?ambient (note 5) sot ? 23 sc ? 74 556 329 c/w 5. mounted onto minimum pad board.
nud3124, sznud3124 www.onsemi.com 4 electrical characteristics (t j = 25 c unless otherwise specified) characteristic symbol min typ max unit off characteristics drain to source sustaining voltage (i d = 10 ma) v brdss 28 34 38 v drain to source leakage current (v ds = 12 v, v gs = 0 v) (v ds = 12 v, v gs = 0 v, t j = 125 c) (v ds = 28 v, v gs = 0 v) (v ds = 28 v, v gs = 0 v, t j = 125 c) i dss ? ? ? ? ? ? ? ? 0.5 1.0 50 80 a gate body leakage current (v gs = 3.0 v, v ds = 0 v) (v gs = 3.0 v, v ds = 0 v, t j = 125 c) (v gs = 5.0 v, v ds = 0 v) (v gs = 5.0 v, v ds = 0 v, t j = 125 c) i gss ? ? ? ? ? ? ? ? 60 80 90 110 a on characteristics gate threshold voltage (v gs = v ds , i d = 1.0 ma) (v gs = v ds , i d = 1.0 ma, t j = 125 c) v gs(th) 1.3 1.3 1.8 ? 2.0 2.0 v drain to source on ? resistance (i d = 150 ma, v gs = 3.0 v) (i d = 150 ma, v gs = 3.0 v, t j = 125 c) (i d = 150 ma, v gs = 5.0 v) (i d = 150 ma, v gs = 5.0 v, t j = 125 c) r ds(on) ? ? ? ? ? ? ? ? 1.4 1.7 0.8 1.1 output continuous current (v ds = 0.25 v, v gs = 3.0 v) (v ds = 0.25 v, v gs = 3.0 v, t j = 125 c) i ds(on) 150 140 200 ? ? ? ma forward transconductance (v ds = 12 v, i d = 150 ma) g fs ? 500 ? mmho dynamic characteristics input capacitance (v ds = 12 v, v gs = 0 v, f = 10 khz) ciss ? 32 ? pf output capacitance (v ds = 12 v, v gs = 0 v, f = 10 khz) coss ? 21 ? pf transfer capacitance (v ds = 12 v, v gs = 0 v, f = 10 khz) crss ? 8.0 ? pf switching characteristics propagation delay times: high to low propagation delay; figure 1, (v ds = 12 v, v gs = 3.0 v) low to high propagation delay; figure 1, (v ds = 12 v, v gs = 3.0 v) high to low propagation delay; figure 1, (v ds = 12 v, v gs = 5.0 v) low to high propagation delay; figure 1, (v ds = 12 v, v gs = 5.0 v) t phl t plh t phl t plh ? ? ? ? 890 912 324 1280 ? ? ? ? ns transition times: fall time; figure 1, (v ds = 12 v, v gs = 3.0 v) rise time; figure 1, (v ds = 12 v, v gs = 3.0 v) fall time; figure 1, (v ds = 12 v, v gs = 5.0 v) rise time; figure 1, (v ds = 12 v, v gs = 5.0 v) t f t r t f t r ? ? ? ? 2086 708 556 725 ? ? ? ? ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
nud3124, sznud3124 www.onsemi.com 5 typical performance curves (t j = 25 c unless otherwise noted) figure 1. switching waveforms load dump pulse not suppressed: v r = 13.5 v nominal 10% v s = 60 v nominal 10% t = 300 ms nominal 10% t r = 1 ? 10 ms 10% load dump pulse suppressed: note: max. voltage dut is exposed to is note: approximately 45 v. v s = 30 v 20% t = 150 ms 20% figure 2. maximum non ? repetitive surge power versus pulse width p w , pulse width (ms) 100 10 1 0 5 10 15 20 25 p pk , peak surge power (w) figure 3. load dump waveform definition vs t r 90% 10% t v r , i r 10% of peak; reference = v r , i r v out v in 0 v v oh v ih t r t f t plh t phl 50% 90% 50% 10% v ol
nud3124, sznud3124 www.onsemi.com 6 figure 4. load dump capability versus relay?s coil dc resistance relay?s coil ( ) 350 260 230 200 170 140 110 80 40 60 80 100 120 140 figure 5. drain ? to ? source leakage versus junction temperature figure 6. gate ? to ? source leakage versus junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 75 50 25 0 ? 25 ? 50 0 2 4 6 8 10 14 100 50 25 0 ? 25 ? 50 20 30 40 50 60 70 80 figure 7. breakdown voltage versus junction temperature t j , junction temperature ( c) 125 50 0 ? 25 ? 50 33.6 33.8 34.0 34.4 34.6 34.8 v s , load dump (volts) 320 290 i dss , drain leakage ( a) 125 100 75 125 i gss gate leakage ( a) v gs = 5 v v gs = 3 v 25 100 75 34.2 33.4 bv dss breakdown voltage (v) i d = 10 ma figure 8. output characteristics v ds = 28 v figure 9. transfer function v ds , drain ? to ? source voltage (v) 0.7 0.5 0.4 0.3 0.2 0.0 1e ? 10 1e ? 08 1e ? 06 1e ? 04 0.01 1 0.1 0.6 0.8 i d drain current (a) v gs = 5 v v gs = 3 v 12 v gs = 2 v v gs = 2.5 v v gs = 1 v v gs , gate ? to ? source voltage (v) 4.5 3.0 2.5 2.0 1.5 0.5 1e ? 07 1e ? 05 1e ? 06 1e ? 04 0.1 1 1.0 4.0 5.0 i d drain current (a) 125 c 3.5 0.001 0.01 85 c 25 c ? 40 c v ds = 0.8 v
nud3124, sznud3124 www.onsemi.com 7 figure 10. on resistance variation versus junction temperature figure 11. on resistance variation versus gate ? to ? source voltage v gs , gate ? to ? source voltage (v) 2.2 1.8 1.6 1.4 1.2 1.0 0.00 0.02 0.04 0.06 0.08 0.10 0.12 2.0 2.4 i d = 250 a 0.01 0.1 1.0 10 100 1000 10,000 100,000 1,000,000 d = 0.5 0.2 0.1 0.05 0.02 single pulse 0.01 p d(pk) t 1 t 2 duty cycle = t 1 /t 2 period pw r(t), transient thermal resistance (normalized) 1.0 0.1 0.01 0.001 t1, pulse width (ms) figure 12. zener clamp voltage versus zener current i z , zener current (ma) 10 1.0 0.1 32.0 32.5 33.0 33.5 34.0 34.5 35.0 100 1000 v z zener clamp voltage (v) figure 13. transient thermal response for nud3124lt1g t j , junction temperature ( c) 75 50 25 0 ? 25 ? 50 400 600 800 1000 1200 1400 1800 r ds(on) , drain ? to ? source resistance (m ) 125 100 i d = 0.25 a v gs = 3.0 v 1600 i d = 0.15 a v gs = 5.0 v i d = 0.15 a v gs = 3.0 v 0.14 0.16 0.18 0.20 r ds(on) , drain ? to ? source resistance ( ) 125 c 85 c 25 c ? 40 c 125 c 85 c 25 c ? 40 c 35.5 36.0
nud3124, sznud3124 www.onsemi.com 8 figure 14. applications diagram 12 v battery + ? micro processor signal for relay applications information relay, vibrator, or inductive load no nc nud3124 gate (1) 10 k 100 k drain (3) source (2)
nud3124, sznud3124 www.onsemi.com 9 package dimensions sot ? 23 (to ? 236) case 318 ? 08 issue ar d a1 3 1 2 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of the base material. 4. dimensions d and e do not include mold flash, protrusions, or gate burrs. soldering footprint* view c l 0.25 l1 e e e b a see view c dim a min nom max min millimeters 0.89 1.00 1.11 0.035 inches a1 0.01 0.06 0.10 0.000 b 0.37 0.44 0.50 0.015 c 0.08 0.14 0.20 0.003 d 2.80 2.90 3.04 0.110 e 1.20 1.30 1.40 0.047 e 1.78 1.90 2.04 0.070 l 0.30 0.43 0.55 0.012 0.039 0.044 0.002 0.004 0.017 0.020 0.006 0.008 0.114 0.120 0.051 0.055 0.075 0.080 0.017 0.022 nom max l1 h 2.10 2.40 2.64 0.083 0.094 0.104 h e 0.35 0.54 0.69 0.014 0.021 0.027 c 0 ??? 10 0 ??? 10 t t 3x top view side view end view 2.90 0.80 dimensions: millimeters 0.90 pitch 3x 3x 0.95 recommended style 21: pin 1. gate 2. source 3. drain *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
nud3124, sznud3124 www.onsemi.com 10 package dimensions sc ? 74 case 318f ? 05 issue n 23 4 5 6 d 1 e b e a1 a 0.05 (0.002) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. 318f ? 01, ? 02, ? 03, ? 04 obsolete. new standard 318f ? 05. c l 0.7 0.028 1.9 0.074 0.95 0.037 2.4 0.094 1.0 0.039 0.95 0.037 mm inches scale 10:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h e dim a min nom max min millimeters 0.90 1.00 1.10 0.035 inches a1 0.01 0.06 0.10 0.001 b 0.25 0.37 0.50 0.010 c 0.10 0.18 0.26 0.004 d 2.90 3.00 3.10 0.114 e 1.30 1.50 1.70 0.051 e 0.85 0.95 1.05 0.034 0.20 0.40 0.60 0.008 0.039 0.043 0.002 0.004 0.015 0.020 0.007 0.010 0.118 0.122 0.059 0.067 0.037 0.041 0.016 0.024 nom max 2.50 2.75 3.00 0.099 0.108 0.118 h e ? ? l 0 10 0 10 style 7: pin 1. source 1 2. gate 1 3. drain 2 4. source 2 5. gate 2 6. drain 1 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nud3124/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ?
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