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the following document contains information on cypress products. the document has the series name, product name, and ordering part numbering with the prefix mb. however, cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix cy. how to check the ordering p art n umber 1. g o to www.cypress.com/pcn . 2. enter the keyword ( for example , ordering part number) i n the search pcns field and click apply . 3. click the corresponding title from the search results. 4. download the affected parts list file , which has details of all changes for more information please contact your local sales office for additional information about cypress products and solutions. about cypress cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. cypress' microcontrollers, analog ics, wireless and usb - based connectivity solutions and reliable, high - performance memories help engineers design differentiated products and get them to market first. cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrup t markets by creating new product categories in record time. to learn more, go to www.cypress.com .
MB96330 series f 2 mc-16fx 16-bit proprietary microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-04586 rev. *a revised may 13, 2016 MB96330 series is based on cypress advanced 16fx architecture ( 16-bit with instruction pipeline for risc-like performance). the cpu uses the same instruction set as the established 16lx series - thus allowing for easy migration of 16lx software to the new 16fx products. 16fx improvements compared to the previous genera tion include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. for highest processing speed at optimized power consumption an internal pll can be select ed to supply the cpu with up to 48mhz operation frequency from an exte rnal 4mhz resonator. the result is a minimum instruction cycle time of 20.8ns going together wi th excellent emi behavior. an on-chip clock modulation circuit signi ficantly reduces emission peaks in the frequency spectrum. the emitted power is minimized by the on-chip voltage regulator that reduces the internal cpu voltage. a flexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the cpu speed. note: mb96f336 and mb96f338 devices are under development and spec ification is preliminary. thes e products under development may change its specif ication without notice. features technology 0.18 ? m cmos cpu f 2 mc-16fx cpu up to 48 mhz internal, 20.8 ns instruction cycle time optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; vari ety of pointers) 8-byte instruction execution queue signed multiply (16-bit 16-bit ) and divide (32-bit/16-bit) instructions available system clock on-chip pll clock multiplier (x1 - x25, x1 when pll stop) 3 mhz - 16 mhz external cryst al oscillator clock (maximum frequency when using ceramic resonator depends on q-factor). up to 48 mhz external clock 32-100 khz subsystem quartz clock 100khz/2mhz internal rc clock for quick and safe startup, oscillator stop detection, watchdog clock source selectable from main- and subclock oscillator (part number suffix ?w?) and on-chip rc oscillator, independently for cpu and 2 clock domains of peripherals. low power consumption - 13 operating modes : (different run, sleep, timer modes, stop mode) clock modulator on-chip voltage regulator internal voltage regulator supports reduced internal mcu voltage, offering low emi and low power consumption figures low voltage reset reset is generated when supply voltage is below minimum. code security protects rom content from unintended read-out memory patch function replaces rom content can also be used to implement embedded debug support dma automatic transfer function independent of cpu, can be assigned freely to resources interrupts fast interrupt processing 8 programmable priority levels non-maskable interrupt (nmi) timers three independent clock timers (23-bit rc clock timer, 23-bit main clock timer, 17-bit sub clock timer) watchdog timer
document number: 002-04586 rev. *a page 2 of 122 MB96330 series can supports can protocol version 2.0 part a and b iso16845 certified bit rates up to 1 mbit/s 32 message objects each message object has its own identifier mask programmable fifo mode (concatenation of message objects) maskable interrupt disabled automatic retransmission mode for time triggered can applications programmable loop-back mode for self-test operation usart full duplex usarts (sci/lin) wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c up to 400 kbps master and slave functionality, 8-bit and 10-bit addressing a/d converter sar-type 10-bit resolution signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer reload timers 16-bit wide prescaler with 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 of peripheral clock frequency event count function free running timers signals an interrupt on overflow, supports timer clear upon match with output compare (0, 4), prescaler with 1, 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 , 1/2 7 ,1/2 8 of peripheral clock frequency input capture units 16-bit wide signals an interrupt upon external event rising edge, falling edge or rising & falling edge sensitive output compare units 16-bit wide signals an interrupt when a match with 16-bit i/o timer occurs a pair of compare registers can be used to generate an output signal. programmable pulse generator 16-bit down counter, cycle and duty settin g registers interrupt at trigger, counter borrow and/or duty match pwm operation and one-shot operation internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and reload timer overflow as clock input can be triggered by software or reload timer real time clock can be clocked either from sub oscillator (devices with part number suffix ?w?), main oscilla tor or from the rc oscillator facility to correct oscillation deviation of sub clock or rc oscil- lator clock (clock calibration) read/write accessible se cond/minute/hour registers can signal interrupts every half second/second/minute/hour/day internal clock divider and prescaler provide exact 1s clock external interrupts edge sensitive or level sensitive interrupt mask and pending bit per channel each available can channel rx has an external interrupt for wake-up selected usart channels sin have an external interrupt for wake-up non maskable interrupt disabled after reset once enabled, can not be disabled other than by reset. level high or level low sensitive pin shared with external interrupt 0.
document number: 002-04586 rev. *a page 3 of 122 MB96330 series external bus interface 8-bit or 16-bit bidirectional data up to 24-bit addresses 6 chip select signals multiplexed address/data lines non-multiplexed address/data lines wait state request external bus master possible timing programmable alarm comparator monitors an external voltage and generates an interrupt in case of a voltage lower or hig her than the defined thresholds threshold voltages defined externally or generated internally status is readable, interrupts can be masked separately i/o ports virtually all external pins can be used as general purpose i/o all push-pull outputs (except when used as i2c sda/scl line) bit-wise programmable as input/output or peripheral signal bit-wise programmable input enable bit-wise programmable input levels: automotive / cmos-schmitt trigger / ttl bit-wise programmable pull-up resistor bit-wise programmable output driving strength for emi optimization package 144-pin plastic lqfp m08 flash memory supports automatic progra mming, embedded algorithm write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles: 10,000 times data retention time: 20 years erase can be performed on each sector individually sector protection flash security feature to protect the content of the flash low voltage detection during flash erase usb usb function (corresponds to usb full speed) usb mini-host function supports up to 6 endpoints
document number: 002-04586 rev. *a page 4 of 122 MB96330 series contents product lineup ................................................................. 5 block diagram ................................................................. 7 pin assignments .............................................................. 9 pin function description ............................................... 11 pin circuit type .............................................................. 14 i/o circuit type ............................................................... 15 memory map .................................................................... 19 ramstart/end and external bus end addresses ... 20 user rom memory map for flash devices ................ 21 serial programming communication interface ........... 22 i/o map ............................................................................. 23 interrupt vector table .................................................... 63 handling devices ............................................................ 68 latch-up prevention ................................................... 68 unused pins handling ............. .............. .............. ....... 68 external clock usage ................................................. 68 unused sub clock signal ............................................ 69 notes on pll clock mode operation ......................... 69 power supply pins (vcc/vss) .. .............. ........... ....... 69 crystal oscillator and ceramic resonator circuit ......... 69 turn on sequence of power supply to a/d converter and analog inputs ............................... 69 pin handling when not using the a/d converter ........ 69 notes on power-on .. .................................................. 69 stabilization of power supply voltage ....... ............ ..... 70 serial communication ................................................ 70 electrical characteristics ............................................... 71 absolute maximum ratings ... .................................... 71 recommended operating conditions ....................... 74 dc characteristics ..................................................... 75 ac characteristics ..................................................... 82 usb characteristics ................................................ 103 analog digital converter .... ..................................... 106 alarm comparator ................................................... 110 low voltage detector characte ristics ...................... 112 flash memory program/erase characteristics ...... 114 example characteristics ......... ..................................... 115 package dimension mb96(f)33x lqfp 144p ............ 116 ordering information .................................................... 117 revision history ........................................................... 118 major changes .............................................................. 120 document history ......................................................... 121
document number: 002-04586 rev. *a page 5 of 122 MB96330 series 1. product lineup features mb96v300 mb96(f)33xy/r mb96(f)33xu product type evaluation sample flash product: mb96f33x mask rom product: mb9633x product options ys na low voltage reset persistently on / single clock devices rs low voltage reset can be disabled / single clock devices yw low voltage reset persistently on / dual clock devices rw low voltage reset can be disabled / dual clock devices us usb / low voltage reset can be disabled / single clock devices uw usb / low voltage reset can be disabled / dual clock devices flash/rom ram 288kb 24kb rom/flash memory emulation by external ram, 92kb internal ram mb96f336u * 1 544kb 32kb mb96f338y * 1 , mb96f338r * 1 mb96f338u * 1 package bga416 fpt-144p-m08 dma 16 channels 10 channels usart 10 channels 8 channels i 2 c 2 channels a/d converter 40 channels 40 channels 36 channels a/d converter reference voltage switch yes no 16-bit reload timer 6 channels + 1 channel (for ppg) 4 channels + 1 channel (for ppg) 16-bit free-running timer 4 channels 16-bit output compare 12 channels 16-bit input capture 10 channels 16-bit programmable pulse generator 20 channels can interface 5 channels 3 channels (1 channel for mb96f336u) usb no no 1 channel external interrupts 16 channels non-maskable interrupt 1 channel real time clock 1
document number: 002-04586 rev. *a page 6 of 122 MB96330 series *1: these devices are under development and specificati on is preliminary. these products under development may change its specification without notice. i/o ports 136 122 for part number with suffix ?w?, 124 for part number with suffix ?s? 118 for part number with suffix ?w?, 120 for part number with suffix ?s? alarm comparator 2 channels external bus interface yes chip select 6 signals clock output function 2 channels low voltage reset yes on-chip rc-oscillator yes features mb96v300 mb96(f)33xy/r mb96(f)33xu
document number: 002-04586 rev. *a page 7 of 8 MB96330 series 2. block diagram block diagram of mb96(f)33xy/r i 2 c 2 ch. sda0, sda1 scl0, scl1 boot rom peripheral bus bridge peripheral bus bridge 16fx core bus (clkb) 10-bit adc 40 ch. 16-bit ppg 20 ch. can interface 3 ch. real time clock ram voltage regulator wot av cc av ss avrh avrl an0 ... an39 adtg, adtg_r tx0 ... tx2, tx2_r rx0 ... rx2, rx2_r peripheral bus 1 (clkp1) peripheral bus 2 (clkp2) v cc v ss c ppg0 ... ppg19 ttg0 ... ttg15, ttg18 16fx cpu interrupt controller clock & mode controller flash memory a memory patch unit ad00 ... ad15 a0 ... a23 ale rdx wrlx/wrx, wrhx hrq hakx rdy eclk external bus interface lbx, ubx cs0 ... cs5, cs0_r ...cs5_r nmi, nmi_r *1: available only on devices with suffix ?w? dma controller 10ch ppg0_r ... ppg11_r, ppg16r ... ppg19_r ttg8_r ... ttg11_r, ttg16_r ... ttg19_r alarm comparator 2 ch. alarm0 alarm1 usart 8 ch. sin0...sin3, sin5, sin9 i/o timer 0 icu 0-3 ocu 0-3 external interrupt frck0 in0 ... in3 out0 ... out3 int0...int15 i/o timer 1 icu 4-7 ocu 4-7 frck1 in4 ... in7 out4 ... out7 i/o timer 3 ocu 10,11 out10_r, out11 int0_r...int15_r int3_r1, int5_r1 out6_r, out7_r 16-bit reload timer 4 ch. tin0 ... tin3 tot0 ... tot3 tin0_r, tin2_r tot0_r, tot2_r tin3_r tot3_r in4_r, in5_r i/o timer 2 icu 8,9 ocu 8,9 frck2_r in8, in9 out8, out9 ckot0, ckot0_r, ckot1, ckot1_r ckotx0, ckotx1, ckotx1_r x0, x1 x0a, x1a *1 rstx md0...md2 watchdog sin2_r, sin7_r ... sin9_r sot0...sot3, sot5, sot9 sot2_r, sot7_r ... sot9_r sck0...sck3, sck5 sck2_r, sck7_r ... sck9_r rlt6
document number: 002-04586 rev. *a page 8 of 8 MB96330 series block diagram of mb96(f)33xu i 2 c 2 ch. sda0, sda1 scl0, scl1 peripheral bus bridge peripheral bus bridge 16fx core bus (clkb) 10-bit adc 36 ch. 16-bit ppg 20 ch. can interface 3 ch. *2 real time clock ram voltage regulator wot av cc av ss avrh avrl an0 ... an35 adtg, adtg_r tx0 ... tx2, tx2_r *2 rx0 ... rx2, rx2_r *2 peripheral bus 1 (clkp1) peripheral bus 2 (clkp2) v cc v ss c ppg0 ... ppg19 ttg0 ... ttg15, ttg18 16fx cpu interrupt controller clock & mode controller flash memory a memory patch unit ad00 ... ad15 a0 ... a23 ale rdx wrlx/wrx, wrhx hrq hakx rdy eclk external bus interface lbx, ubx cs0 ... cs5, cs0_r ...cs5_r nmi, nmi_r *1: available only on devices with suffix ?w? dma controller 10ch ppg0_r ... ppg11_r, ppg16r ... ppg19_r ttg8_r ... ttg11_r, ttg16_r ... ttg19_r alarm comparator 2 ch. alarm0 alarm1 usart 8 ch. sin0...sin3, sin5, sin9 i/o timer 0 icu 0-3 ocu 0-3 external interrupt frck0 in0 ... in3 out0 ... out3 int0...int15 i/o timer 1 icu 4-7 ocu 4-7 frck1 in4 ... in7 out4 ... out7 i/o timer 3 ocu 10,11 out10_r, out11 int0_r...int15_r int3_r1, int5_r1 out6_r, out7_r 16-bit reload timer 4 ch. tin0 ... tin3 tot0 ... tot3 tin0_r, tin2_r tot0_r, tot2_r tin3_r tot3_r in4_r, in5_r i/o timer 2 icu 8,9 ocu 8,9 frck2_r in8, in9 out8, out9 ckot0, ckot0_r, ckot1, ckot1_r ckotx0, ckotx1, ckotx1_r x0, x1 x0a, x1a *1 rstx md0...md2 watchdog sin2_r, sin7_r ... sin9_r sot0...sot3, sot5, sot9 sot2_r, sot7_r ... sot9_r sck0...sck3, sck5 sck2_r, sck7_r ... sck9_r rlt6 peripheral bus 3 (clk3) udp udm usb hconx v cc3 boot rom peripheral bus bridge *2 : can1 and can2 not available on mb96f336u
document number: 002-04586 rev. *a page 9 of 122 MB96330 series 3. pin assignments pin assignment of m96f33xy/r (fpt-144p-m08) *1: devices with suffix w: x0a, x1a devices with suffix s: p04_0, p04_1 lqfp - 144 package code (mold) fpt-144p-m08 89 12345 7 6 101112131415161718192021222324252627282930 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 109 110 111 112 113 114 115 116 117 vss p00_1/ad01/int9/sot7_r/ttg9_r p00_2/ad02/int10/sin7_r/ttg10_r p00_3/ad03/int11/sck8_r/ttg11_r p00_4/ad04/int12/sot8_r/ppg8_r p00_5/ad05/int13/sin8_r/ppg9_r p00_6/ad06/int14/ppg10_r p00_7/ad07/int15/ppg11_r p01_0/ad08/tin1/ckot1/ttg16_r p01_1/ad09/tot1/ckotx1/ttg17_r p01_2/ad10/sin3/int11_r/ttg18_r p01_3/ad11/sot3/ttg19_r p01_4/ad12/sck3/ppg16_r p01_5/ad13/sin2_r/int7_r/ppg17_r p01_6/ad14/sot2_r/ppg18_r p01_7/ad15/sck2_r/ppg19_r p02_0/a16/ppg12/ckot1_r p02_1/a17/ppg13 p02_2/a18/ppg14/ckot0_r p02_3/a19/ppg15 p02_4/a20/in0/ttg0/ttg8 p02_5/a21/in1/ttg1/ttg9/adtg_r p02_6/a22/in2/ttg2/ttg10 p02_7/a23/in3/ttg3/ttg11 p03_0/ale/in4/ttg4/ttg12/tot0_r p03_1/rdx/in5/ttg5/ttg13/tot2_r p03_2/wr(l)x/int10_r/rx2 p03_3/wrhx/tx2 p03_4/hrq/out4 p03_5/hakx/out5 vss c p11_7/in5_r/a3 p12_0/rx2_r/int6_r/a4 p12_1/tx2_r/a5 p12_2/ppg0_r/a6 p12_3/ppg1_r/a7 p12_4/ppg2_r/a8 p12_5/ppg3_r/a9 p12_6/ppg4_r/a10 p12_7/ppg5_r/a11 p13_0/ppg6_r/a12 p13_1/ppg7_r/a13 p13_4/ppg16 p13_5 / ppg17 p13_6/ppg18/in8 p13_7/ppg19/in9 p04_2/in6/rx1/int9_r/ttg6/ttg14 p04_3/in7/tx1/ttg7/ttg15 p04_4/sda0/frck0/tin0_r p04_5/scl0/frck1/tin2_r p04_6/sda1 p04_7/scl1 p05_0/an8/alarm0/sin2/int3_r1 p05_1/an9/alarm1/sot2 p05_2/an10/sck2 p05_3/an11/tin3/wot p05_4/an12/tot3/int2_r p05_5/an13/int0_r/nmi_r p05_6/an14/int4_r vcc p15_7/an39 p15_6/an38 p15_5/an37 p15_4/an36 p15_2/an34 p15_1/an33 p14_6/an30 p15_3/an35 p14_5/an29 p14_4/an28 p14_3/an27 p14_2/an26 avrh avcc p07_7/an23/int7/sin9_r p07_4/an20/int4 p07_3/an19/int3 p07_2/an18/int2 p07_1/an17/int1 p07_0/an16/int0/nmi p06_7/an7/ppg7 p06_6/an6/ppg6 p06_5/an5/ppg5/cs5_r p06_4/an4/ppg4/cs4_r p06_3/an3/ppg3/cs3_r p06_2/an2/ppg2/cs2_r vss vcc p09_2/ppg10/cs5 p09_1/ppg9/lbx p09_0/ppg8/ubx p17_6/out11/ttg18/int3_r p17_4/sot9/out9 p17_3/sin9/out8 p10_4/sin5/int5_r1 p10_3/sot5 p10_2/sck5 p10_1/tx0 p10_0/rx0/int8_r p08_7/sck1 p08_6 / sot1 p08_5/sin1/int1_r p08_4/sck0/int15_r p08_3/sot0/tot2 p08_2/sin0/tin2/int14_r p08_1/tot0/int13_r/ckot0 p08_0/tin0/adtg/int12_r/ckotx0 rstx x1a/p04_1 * 1 x0a/p04_0 * 1 vss x1 x0 md2 md1 md0 vss 31 32 33 34 35 36 78 77 76 75 74 73 37 38 39 40 41 42 139 140 141 142 143 144 p05_7/an15/int5_r/out10_r p06_0/an0/ppg0/cs0_r p06_1/an1/ppg1/cs1_r p13_2/tin3_r/a14 p13_3/tot3_r/a15 vcc p07_5/an21/int5/sck9_r p07_6/an22/int6/sot9_r p14_1/an25 p14_0/an24 p14_7/an31 p15_0/an32 p09_3/ppg11/cs4/frck2_r p09_4/out0/cs3 p09_5/out1/cs2 p09_6/out2/cs1 p09_7/out3/cs0 p00_0/ad00/int8/sck7_r/ttg8_r p03_6/rdy/out6 p03_7/eclk/out7 p11_4/out6_r/a0 p11_5/out7_r/a1 p11_6/in4_r/a2 vcc (fpt-144p-m08) avrl avss
document number: 002-04586 rev. *a page 10 of 122 MB96330 series pin assignment of mb96f33xu (fpt-144p-m08) usb device lqfp - 144 package code (mold) fpt-144p-m08 89 12345 7 6 101112131415161718192021222324252627282930 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 109 110 111 112 113 114 115 116 117 vss p00_1/ad01/int9/sot7_r/ttg9_r p00_2/ad02/int10/sin7_r/ttg10_r p00_3/ad03/int11/sck8_r/ttg11_r p00_4/ad04/int12/sot8_r/ppg8_r p00_5/ad05/int13/sin8_r/ppg9_r p00_6/ad06/int14/ppg10_r p00_7/ad07/int15/ppg11_r p01_0/ad08/tin1/ckot1/ttg16_r p01_1/ad09/tot1/ckotx1/ttg17_r p01_2/ad10/sin3/int11_r/ttg18_r p01_3/ad11/sot3/ttg19_r p01_4/ad12/sck3/ppg16_r p01_5/ad13/sin2_r/int7_r/ppg17_r p01_6/ad14/sot2_r/ppg18_r p01_7/ad15/sck2_r/ppg19_r p02_0/a16/ppg12/ckot1_r p02_1/a17/ppg13 p02_2/a18/ppg14/ckot0_r p02_3/a19/ppg15 p02_4/a20/in0/ttg0/ttg8 p02_5/a21/in1/ttg1/ttg9/adtg_r p02_6/a22/in2/ttg2/ttg10 p02_7/a23/in3/ttg3/ttg11 p03_0/ale/in4/ttg4/ttg12/tot0_r p03_1/rdx/in5/ttg5/ttg13/tot2_r p03_2/wr(l)x/int10_r/rx2 *2 p03_3/wrhx/tx2 *2 p03_4/hrq/out4 p03_5/hakx/out5 vss c p11_7/in5_r/a3 p12_0/rx2_r/int6_r/a4 *2 p12_1/tx2_r/a5 *2 p12_2/ppg0_r/a6 p12_3/ppg1_r/a7 p12_4/ppg2_r/a8 p12_5/ppg3_r/a9 p12_6/ppg4_r/a10 p12_7/ppg5_r/a11 p13_0/ppg6_r/a12 p13_1/ppg7_r/a13 p13_4/ppg16 p13_5 / ppg17 p13_6/ppg18/in8 p13_7/ppg19/in9 p04_2/in6/rx1/int9_r/ttg6/ttg14 *2 p04_3/in7/tx1/ttg7/ttg15 *2 p04_4/sda0/frck0/tin0_r p04_5/scl0/frck1/tin2_r p04_6/sda1 p04_7/scl1 p05_0/an8/alarm0/sin2/int3_r1 p05_1/an9/alarm1/sot2 p05_2/an10/sck2 p05_3/an11/tin3/wot p05_4/an12/tot3/int2_r p05_5/an13/int0_r/nmi_r p05_6/an14/int4_r vcc udm udp vcc3 hconx p15_2/an34 p15_1/an33 p14_6/an30 p15_3/an35 p14_5/an29 p14_4/an28 p14_3/an27 p14_2/an26 avrh avcc p07_7/an23/int7/sin9_r p07_4/an20/int4 p07_3/an19/int3 p07_2/an18/int2 p07_1/an17/int1 p07_0/an16/int0/nmi p06_7/an7/ppg7 p06_6/an6/ppg6 p06_5/an5/ppg5/cs5_r p06_4/an4/ppg4/cs4_r p06_3/an3/ppg3/cs3_r p06_2/an2/ppg2/cs2_r vss vcc p09_2/ppg10/cs5 p09_1/ppg9/lbx p09_0/ppg8/ubx p17_6/out11/ttg18/int3_r p17_4/sot9/out9 p17_3/sin9/out8 p10_4/sin5/int5_r1 p10_3/sot5 p10_2/sck5 p10_1/tx0 p10_0/rx0/int8_r p08_7/sck1 p08_6 / sot1 p08_5/sin1/int1_r p08_4/sck0/int15_r p08_3/sot0/tot2 p08_2/sin0/tin2/int14_r p08_1/tot0/int13_r/ckot0 p08_0/tin0/adtg/int12_r/ckotx0 rstx x1a/(p04_1) *1 x0a/(p04_0) *1 vss x1 x0 md2 md1 md0 vss 31 32 33 34 35 36 78 77 76 75 74 73 37 38 39 40 41 42 139 140 141 142 143 144 p05_7/an15/int5_r/out10_r p06_0/an0/ppg0/cs0_r p06_1/an1/ppg1/cs1_r p13_2/tin3_r/a14 p13_3/tot3_r/a15 vcc p07_5/an21/int5/sck9_r p07_6/an22/int6/sot9_r p14_1/an25 p14_0/an24 p14_7/an31 p15_0/an32 p09_3/ppg11/cs4/frck2_r p09_4/out0/cs3 p09_5/out1/cs2 p09_6/out2/cs1 p09_7/out3/cs0 p00_0/ad00/int8/sck7_r/ttg8_r p03_6/rdy/out6 p03_7/eclk/out7 p11_4/out6_r/a0 p11_5/out7_r/a1 p11_6/in4_r/a2 vcc (fpt-144p-m08) avrl avss *1: devices with suffix w: x0a, x1a devices with suffix s: p04_0, p04_1 *2: tx1, rx1, tx2, rx2, tx2_r, rx2_r not available on mb96f336u
document number: 002-04586 rev. *a page 11 of 122 MB96330 series 4. pin function description pin function description (1 of 3) pin name feature description adn external bus external bus interface (n on multiplexed mode) data input/output. external bus interface (multiplexed mode) address output and data input/output adtg adc a/d converter trigger input adtg_r adc relocated a/d converter trigger input alarmn alarm comparator alarm comparator n input ale external bus external bus address latch enable output an external bus external bus non-multiplexed address output ann adc a/d converter channel n input av cc supply analog circuits power supply avrh adc a/d converter high reference voltage input avrl adc a/d converter low reference voltage input av ss supply analog circuits power supply c voltage regulator internally regulated power supply stabilization capacitor pin ckotn clock output function clock output function n output ckotn_r clock output function relocated clock output function n output ckotxn clock output function clock outp ut function n inverted output ckotxn_r clock output function relocated clo ck output function n inverted output eclk external bus external bus clock output csn external bus external bu s chip select n output csn_r external bus relocated exter nal bus chip select n output frckn free running timer free running timer n input frckn_r free running timer relocated free running timer n input hakx external bus external bus hold acknowledge hconx usb usb connection to host or hub hrq external bus external bus hold request inn icu input capture unit n input inn_r icu relocated input capture unit n input intn external interrupt external interrupt n input intn_r external interrupt relocated external interrupt n input lbx external bus external bus interface lower byte select strobe output
document number: 002-04586 rev. *a page 12 of 122 MB96330 series mdn core input pins for specifying the operating mode. nmi external interrupt non-maskable interrupt input nmi_r external interrupt relocated non-maskable interrupt input outn ocu output compare unit n waveform output outn_r ocu relocated output co mpare unit n waveform output pxx_n gpio general purpose io ppgn ppg programmable pulse generator n output ppgn_r ppg relocated programmabl e pulse generator n output rdx external bus external bus interface read strobe output rdy external bus external bus interfac e external wait state request input rstx core reset input rxn can can interface n rx input rxn_r can relocated can interface n rx input sckn usart usart n serial clock input/output sckn_r usart relocated usart n serial clock input/output scln i 2 ci 2 c interface n clock i/o input/output sdan i 2 ci 2 c interface n serial data i/o input/output sinn usart usart n serial data input sinn_r usart relocated usart n serial data input sotn usart usart n serial data output sotn_r usart relocated usart n serial data output tinn reload timer reload timer n event input tinn_r reload timer relocated reload timer n event input totn reload timer reload timer n output totn_r reload timer relocated reload timer n output ttgn ppg programmable pulse generator n trigger input ttgn_r ppg relocated programmable pulse generator n trigger input txn can can interface n tx output txn_r can relocated can interface n tx output ubx external bus external bus interface upper byte select strobe output udm usb usb minus pin function description (2 of 3) pin name feature description
document number: 002-04586 rev. *a page 13 of 122 MB96330 series udp usb usb plus v cc supply power supply v cc3 supply usb power supply v ss supply power supply wot rtc real timer clock output wrhx external bus external bus high byte write strobe output wrlx/wrx external bus external bus lo w byte / word write strobe output x0 clock oscillator input x0a clock subclock oscillator input (only for devices with suffix ?w?) x1 clock oscillator output x1a clock subclock oscillator output (only for devices with suffix ?w?) pin function description (3 of 3) pin name feature description
document number: 002-04586 rev. *a page 14 of 122 MB96330 series 5. pin circuit type *1: please refer to 6.?i/o circuit type? for deta ils on the i/o circuit types *2: devices with suffix ?w? *3: devices without suffix ?w? pin no. fpt-144p-m08 circuit type *1 mb96(f)33xy/r mb96(f)33xu (usb device) 1 supply 2f 3 to 21 h 22 to 25 n 26 to 35 i 36, 37 supply 38 to 43 i 44 supply 45 g 46 to 47 supply 48 to 67 i 68 i o 69 i supply (3.3v) 70, 71 i p 72, 73 supply 74 to 76 c 77, 78 a 79 supply 80, 81 b *2 80, 81 h *3 82 e 83 to 107 h 108, 109 supply 110 to 143 h 144 supply
document number: 002-04586 rev. *a page 15 of 122 MB96330 series 6. i/o circuit type type circuit remarks a high-speed oscillation circuit: ? programmable between oscillation mode (external crystal or resonator connected to x0/x1 pins) and fast external clock input (fci) mode (external clock connected to x0 pin) ? programmable feedback resistor = approx. 2 * 0.5 m ? . feedback resistor is grounded in the center when the oscillator is disabled or in fci mode b low-speed oscillation circuit: ? programmable feedback resistor = approx.20m ? (x1a: 19.5m ? , x0a: 0.5m ? ) feedback resistor is grounded in the center when the oscillator is disabled c ? mask rom and eva device: cmos hysteresis input pin ? flash device: cmos input pin e ? cmos hysteresis input pin ? pull-up resistor value: approx. 50 k ? x1 x0 r r mrfbe xout fci 0 1 fci or osc disable x1a x0a r r srfbe xout osc disable r hysteresis inputs r pull-up resistor hysteresis inputs
document number: 002-04586 rev. *a page 16 of 122 MB96330 series f ? power supply input protection circuit g ? a/d converter ref+ (avrh) power supply input pin with protection circuit ? flash devices do not have a protection circuit against vcc for pins avrh h ? cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) ? 2 different cmos hysteresis inputs with input shutdown function ? automotive input with in put shutdown function ? ttl input with input shutdown function ? programmable pull-up resistor: 50k ? approx. type circuit remarks ane avr ane pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown
document number: 002-04586 rev. *a page 17 of 122 MB96330 series i ? cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) ? 2 different cmos hysteresis inputs with input shutdown function ? automotive input with in put shutdown function ? ttl input with input shutdown function. ? programmable pull-up resistor: 50k ? approx. ? analog input n ? cmos level output (i ol = 3ma, i oh = -3ma) ? 2 different cmos hysteresis inputs with input shutdown function ? automotive input with in put shutdown function ? ttl input with input shutdown function ? programmable pull-up resistor: 50k ? approx. type circuit remarks r hysteresis input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown pull-up control pout nout automotive input ttl input analog input pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown
document number: 002-04586 rev. *a page 18 of 122 MB96330 series o hconx ? available only for device with suffix ?u? p usb io cell: udp and udm ? available only for device with suffix ?u? type circuit remarks pout (always disabled) pull-up control nout r hysteresis input automotive inputs ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown analog input differential d+ input d- input input d+ output direction d- output d- d+
document number: 002-04586 rev. *a page 19 of 122 MB96330 series 7. memory map mb96v300b mb96(f)33x ff:ffff h emulation rom user rom / external bus *4 de:0000 h external bus external bus 10:0000 h 0f:e000 h boot-rom boot-rom reserved reserved 0e:0000 h external ram 02:0000 h internal ram bank 1 reserved ramend1 *2 internal ram bank 1 ram availability de- pending on the device ramstart1 2 01:0000 h reserved rom/ram mirror rom/ram mirror 00:8000 h internal ram bank 0 internal ram bank 0 ramstart0 *2 reserved ramstart0 * external bus external bus end address *2 00:0c00 h external bus peripherals peripherals 00:0380 h 00:0180 h gpr *1 gpr *1 00:0100 h dma dma 00:00f0 h external bus external bus 00:0000 h peripheral peripheral *1: unused gpr banks can be used as ram area *2: for external bus end address and ramstart/end addr esses, please refer to the table on the next page. *3: for eva device, ramstart0 depends on t he configuration of the emulated device. *4: for details about user rom area, see the 9.?user rom memory map for flash devices? on the following pages. the external bus area and dma area are only availabl e if the device contains the corresponding resource. the available ram and rom area depends on the device.
document number: 002-04586 rev. *a page 20 of 122 MB96330 series 8. ramstart/end and ex ternal bus end addresses devices bank 0 ram size bank 1 ram size external bus end address ramstart0 ramstart1 ramend1 mb96f336 24kbyte - 00:11ff h 00:2240 h -- mb96f338, mb96338 28kbyte 4kb 00:11ff h 00:1240 h 01:8000 h 01:8fff h
document number: 002-04586 rev. *a page 21 of 122 MB96330 series 9. user rom memory map for flash devices mb96f338y mb96f338r mb96f336u mb96f338u alternative mode cpu address flash memory mode address flash size 288kbyte flash size 544kbyte ff:ffff h ff:0000 h 3f:ffff h 3f:0000 h s39 - 64k s39 - 64k fe:ffff h fe:0000 h 3e:ffff h 3e:0000 h s38 - 64k s38 - 64k flash a fd:ffff h fd:0000 h 3d:ffff h 3d:0000 h s37 - 64k s37 - 64k fc:ffff h fc:0000 h 3c:ffff h 3c:0000 h s36 - 64k s36 - 64k fb:ffff h fb:0000 h 3b:ffff h 3b:0000 h external bus s35 - 64k fa:ffff h fa:0000 h 3a:ffff h 3a:0000 h s34 - 64k f9:ffff h f9:0000 h 39:ffff h 39:0000 h s33 - 64k f8:ffff h f8:0000 h 38:ffff h 38:0000 h s32 - 64k f7:ffff h f7:0000 h 37:ffff h 37:0000 h external bus f6:ffff h f6:0000 h 36:ffff h 36:0000 h f5:ffff h f5:0000 h 35:ffff h 35:0000 h f4:ffff h f4:0000 h 34:ffff h 34:0000 h f3:ffff h f3:0000 h 33:ffff h 33:0000 h f2:ffff h f2:0000 h 32:ffff h 32:0000 h f1:ffff h f1:0000 h 31:ffff h 31:0000 h f0:ffff h f0:0000 h 30:ffff h 30:0000 h e0:ffff h e0:0000 h df:ffff h df:8000 h reserved reserved df:7fff h df:6000 h 1f:7fff h 1f:6000 h sa3 - 8k sa3 - 8k flash a df:5fff h df:4000 h 1f:5fff h 1f:4000 h sa2 - 8k sa2 - 8k df:3fff h df:2000 h 1f:3fff h 1f:2000 h sa1 - 8k sa1 - 8k df:1fff h df:0000 h 1f:1fff h 1f:0000 h sa0 - 8k *1 sa0 - 8k *1 de:ffff h de:0000 h reserved reserved *1: sector sa0 contains the rom confi guration block rcba at cpu address df:0000 h - df:007f h
document number: 002-04586 rev. *a page 22 of 122 MB96330 series 10. serial programming communication interface note: if a flash programmer and its software needs to use a hands haking pin, cypress suggests to the tool vendor to support at least port p00_1 on pin 110. if handshaking is used by the tool but p00_1 is not available in customer?s application, cypr ess suggests to the customer to check the tool manual or to contact the t ool vendor for alternative handshaking pins. usart pins for flash serial programming (md[2:0] = 010) mb96f33x pin number usart number normal function lqfp-144 85 usart0 sin0 86 sot0 87 sck0 88 usart1 sin1 89 sot1 90 sck1 26 usart2 sin2 27 sot2 28 sck2
document number: 002-04586 rev. *a page 23 of 122 MB96330 series 11. i/o map i/o map mb96(f)33x (1 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access 000000 h i/o port p00 - port data register pdr00 r/w 000001 h i/o port p01 - port data register pdr01 r/w 000002 h i/o port p02 - port data register pdr02 r/w 000003 h i/o port p03 - port data register pdr03 r/w 000004 h i/o port p04 - port data register pdr04 r/w 000005 h i/o port p05 - port data register pdr05 r/w 000006 h i/o port p06 - port data register pdr06 r/w 000007 h i/o port p07 - port data register pdr07 r/w 000008 h i/o port p08 - port data register pdr08 r/w 000009 h i/o port p09 - port data register pdr09 r/w 00000a h i/o port p10 - port data register pdr10 r/w 00000b h i/o port p11 - port data register pdr11 r/w 00000c h i/o port p12 - port data register pdr12 r/w 00000d h i/o port p13 - port data register pdr13 r/w 00000e h i/o port p14 - port data register pdr14 r/w 00000f h i/o port p15 - port data register pdr15 r/w 000010 h reserved - 000011 h i/o port p17 - port data register pdr17 r/w 000012 h - 000017 h reserved - 000018 h adc0 - control status register low adcsl adcs r/w 000019 h adc0 - control status register high adcsh r/w 00001a h adc0 - data register low adcrl adcr r 00001b h adc0 - data register high adcrh r 00001c h adc0 - setting register adsr r/w 00001d h adc0 - setting register r/w 00001e h adc0 - extended configuration register adecr r/w 00001f h reserved - 000020 h frt0 - data register of free-running timer tcdt0 r/w 000021 h frt0 - data register of free-running timer r/w
document number: 002-04586 rev. *a page 24 of 122 MB96330 series 000022 h frt0 - control status register of free-running timer low tccsl0 tccs0 r/w 000023 h frt0 - control status register of free-running timer high tccsh0 r/w 000024 h frt1 - data register of free-running timer tcdt1 r/w 000025 h frt1 - data register of free-running timer r/w 000026 h frt1 - control status register of free-running timer low tccsl1 tccs1 r/w 000027 h frt1 - control status register of free-running timer high tccsh1 r/w 000028 h ocu0 - output compare control status ocs0 r/w 000029 h ocu1 - output compare control status ocs1 r/w 00002a h ocu0 - compare register occp0 r/w 00002b h ocu0 - compare register r/w 00002c h ocu1 - compare register occp1 r/w 00002d h ocu1 - compare register r/w 00002e h ocu2 - output compare control status ocs2 r/w 00002f h ocu3 - output compare control status ocs3 r/w 000030 h ocu2 - compare register occp2 r/w 000031 h ocu2 - compare register r/w 000032 h ocu3 - compare register occp3 r/w 000033 h ocu3 - compare register r/w 000034 h ocu4 - output compare control status ocs4 r/w 000035 h ocu5 - output compare control status ocs5 r/w 000036 h ocu4 - compare register occp4 r/w 000037 h ocu4 - compare register r/w 000038 h ocu5 - compare register occp5 r/w 000039 h ocu5 - compare register r/w 00003a h ocu6 - output compare control status ocs6 r/w 00003b h ocu7 - output compare control status ocs7 r/w 00003c h ocu6 - compare register occp6 r/w 00003d h ocu6 - compare register r/w 00003e h ocu7 - compare register occp7 r/w 00003f h ocu7 - compare register r/w i/o map mb96(f)33x (2 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 25 of 122 MB96330 series 000040 h icu0/icu1 - control status register ics01 r/w 000041 h icu0/icu1 - edge register ice01 r/w 000042 h icu0 - capture register low ipcpl0 ipcp0 r 000043 h icu0 - capture register high ipcph0 r 000044 h icu1 - capture register low ipcpl1 ipcp1 r 000045 h icu1 - capture register high ipcph1 r 000046 h icu2/icu3 - control status register ics23 r/w 000047 h icu2/icu3 - edge register ice23 r/w 000048 h icu2 - capture register low ipcpl2 ipcp2 r 000049 h icu2 - capture register high ipcph2 r 00004a h icu3 - capture register low ipcpl3 ipcp3 r 00004b h icu3 - capture register high ipcph3 r 00004c h icu4/icu5 - control status register ics45 r/w 00004d h icu4/icu5 - edge register ice45 r/w 00004e h icu4 - capture register low ipcpl4 ipcp4 r 00004f h icu4 - capture register high ipcph4 r 000050 h icu5 - capture register low ipcpl5 ipcp5 r 000051 h icu5 - capture register high ipcph5 r 000052 h icu6/icu7 - control status register ics67 r/w 000053 h icu6/icu7 - edge register ice67 r/w 000054 h icu6 - capture register low ipcpl6 ipcp6 r 000055 h icu6 - capture register high ipcph6 r 000056 h icu7 - capture register low ipcpl7 ipcp7 r 000057 h icu7 - capture register high ipcph7 r 000058 h extint0 - external interrupt enable register enir0 r/w 000059 h extint0 - external interrupt interrupt request register eirr0 r/w 00005a h extint0 - external interrupt level select low elvrl0 elvr0 r/w 00005b h extint0 - external interrupt level select high elvrh0 r/w 00005c h extint1 - external interrupt enable register enir1 r/w 00005d h extint1 - external interrupt interrupt request register eirr1 r/w i/o map mb96(f)33x (3 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 26 of 122 MB96330 series 00005e h extint1 - external interrupt level select low elvrl1 elvr1 r/w 00005f h extint1 - external interrupt level select high elvrh1 r/w 000060 h rlt0 - timer control status register low tmcsrl0 tmcsr0 r/w 000061 h rlt0 - timer control status register high tmcsrh0 r/w 000062 h rlt0 - reload register - for writing tmrlr0 w 000062 h rlt0 - reload register - for reading tmr0 r 000063 h rlt0 - reload register - for writing w 000063 h rlt0 - reload register - for reading r 000064 h rlt1 - timer control status register low tmcsrl1 tmcsr1 r/w 000065 h rlt1 - timer control status register high tmcsrh1 r/w 000066 h rlt1 - reload register - for writing tmrlr1 w 000066 h rlt1 - reload register - for reading tmr1 r 000067 h rlt1 - reload register - for writing w 000067 h rlt1 - reload register - for reading r 000068 h rlt2 - timer control status register low tmcsrl2 tmcsr2 r/w 000069 h rlt2 - timer control status register high tmcsrh2 r/w 00006a h rlt2 - reload register - for writing tmrlr2 w 00006a h rlt2 - reload register - for reading tmr2 r 00006b h rlt2 - reload register - for writing w 00006b h rlt2 - reload register - for reading r 00006c h rlt3 - timer control status register low tmcsrl3 tmcsr3 r/w 00006d h rlt3 - timer control status register high tmcsrh3 r/w 00006e h rlt3 - reload register - for writing tmrlr3 w 00006e h rlt3 - reload register - for reading tmr3 r 00006f h rlt3 - reload register - for writing w 00006f h rlt3 - reload register - for reading r 000070 h rlt6 - timer control status register low (dedic. rlt for ppg) tmcsrl6 tmcsr6 r/w 000071 h rlt6 - timer control status register high (dedic. rlt for ppg) tmcsrh6 r/w 000072 h rlt6 - reload register (dedic. rlt for ppg) - for writing tmrlr6 w i/o map mb96(f)33x (4 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 27 of 122 MB96330 series 000072 h rlt6 - reload register (dedic. rlt for ppg) - for reading tmr6 r 000073 h rlt6 - reload register (dedic . rlt for ppg) - for writing w 000073 h rlt6 - reload register (dedic . rlt for ppg) - for reading r 000074 h ppg3-ppg0 - general control r egister 1 low gcn1l0 gcn10 r/w 000075 h ppg3-ppg0 - general control register 1 high gcn1h0 r/w 000076 h ppg3-ppg0 - general control r egister 2 low gcn2l0 gcn20 r/w 000077 h ppg3-ppg0 - general control register 2 high gcn2h0 r/w 000078 h ppg0 - timer register ptmr0 r 000079 h ppg0 - timer register r 00007a h ppg0 - period setting register pcsr0 w 00007b h ppg0 - period setting register w 00007c h ppg0 - duty cycle register pdut0 w 00007d h ppg0 - duty cycle register w 00007e h ppg0 - control status r egister low pcnl0 pcn0 r/w 00007f h ppg0 - control status register high pcnh0 r/w 000080 h ppg1 - timer register ptmr1 r 000081 h ppg1 - timer register r 000082 h ppg1 - period setting register pcsr1 w 000083 h ppg1 - period setting register w 000084 h ppg1 - duty cycle register pdut1 w 000085 h ppg1 - duty cycle register w 000086 h ppg1 - control status r egister low pcnl1 pcn1 r/w 000087 h ppg1 - control status register high pcnh1 r/w 000088 h ppg2 - timer register ptmr2 r 000089 h ppg2 - timer register r 00008a h ppg2 - period setting register pcsr2 w 00008b h ppg2 - period setting register w 00008c h ppg2 - duty cycle register pdut2 w 00008d h ppg2 - duty cycle register w 00008e h ppg2 - control status r egister low pcnl2 pcn2 r/w i/o map mb96(f)33x (5 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 28 of 122 MB96330 series 00008f h ppg2 - control status register high pcnh2 r/w 000090 h ppg3 - timer register ptmr3 r 000091 h ppg3 - timer register r 000092 h ppg3 - period setting register pcsr3 w 000093 h ppg3 - period setting register w 000094 h ppg3 - duty cycle register pdut3 w 000095 h ppg3 - duty cycle register w 000096 h ppg3 - control status r egister low pcnl3 pcn3 r/w 000097 h ppg3 - control status register high pcnh3 r/w 000098 h ppg7-ppg4 - general control r egister 1 low gcn1l1 gcn11 r/w 000099 h ppg7-ppg4 - general control register 1 high gcn1h1 r/w 00009a h ppg7-ppg4 - general control r egister 2 low gcn2l1 gcn21 r/w 00009b h ppg7-ppg4 - general control register 2 high gcn2h1 r/w 00009c h ppg4 - timer register ptmr4 r 00009d h ppg4 - timer register r 00009e h ppg4 - period setting register pcsr4 w 00009f h ppg4 - period setting register w 0000a0 h ppg4 - duty cycle register pdut4 w 0000a1 h ppg4 - duty cycle register w 0000a2 h ppg4 - control status r egister low pcnl4 pcn4 r/w 0000a3 h ppg4 - control status register high pcnh4 r/w 0000a4 h ppg5 - timer register ptmr5 r 0000a5 h ppg5 - timer register r 0000a6 h ppg5 - period setting register pcsr5 w 0000a7 h ppg5 - period setting register w 0000a8 h ppg5 - duty cycle register pdut5 w 0000a9 h ppg5 - duty cycle register w 0000aa h ppg5 - control status r egister low pcnl5 pcn5 r/w 0000ab h ppg5 - control status register high pcnh5 r/w 0000ac h i 2 c0 - bus status register ibsr0 r i/o map mb96(f)33x (6 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 29 of 122 MB96330 series 0000ad h i 2 c0 - bus control register ibcr0 r/w 0000ae h i 2 c0 - ten bit slave address register low itbal0 itba0 r/w 0000af h i 2 c0 - ten bit slave address register high itbah0 r/w 0000b0 h i 2 c0 - ten bit address mask r egister low itmkl0 itmk0 r/w 0000b1 h i 2 c0 - ten bit address ma sk register high itmkh0 r/w 0000b2 h i 2 c0 - seven bit slave address register isba0 r/w 0000b3 h i 2 c0 - seven bit address mask register ismk0 r/w 0000b4 h i 2 c0 - data register idar0 r/w 0000b5 h i 2 c0 - clock control register iccr0 r/w 0000b6 h i 2 c1 - bus status register ibsr1 r 0000b7 h i 2 c1 - bus control register ibcr1 r/w 0000b8 h i 2 c1 - ten bit slave address register low itbal1 itba1 r/w 0000b9 h i 2 c1 - ten bit slave address register high itbah1 r/w 0000ba h i 2 c1 - ten bit address mask r egister low itmkl1 itmk1 r/w 0000bb h i 2 c1 - ten bit address ma sk register high itmkh1 r/w 0000bc h i 2 c1 - seven bit slave address register isba1 r/w 0000bd h i 2 c1 - seven bit address mask register ismk1 r/w 0000be h i 2 c1 - data register idar1 r/w 0000bf h i 2 c1 - clock control register iccr1 r/w 0000c0 h usart0 - serial mode register smr0 r/w 0000c1 h usart0 - serial control register scr0 r/w 0000c2 h usart0 - tx register tdr0 w 0000c2 h usart0 - rx register rdr0 r 0000c3 h usart0 - serial status ssr0 r/w 0000c4 h usart0 - control/com. register eccr0 r/w 0000c5 h usart0 - ext. status register escr0 r/w 0000c6 h usart0 - baud rate generator register low bgrl0 bgr0 r/w 0000c7 h usart0 - baud rate genera tor register high bgrh0 r/w 0000c8 h usart0 - extended serial interrupt register esir0 r/w 0000c9 h reserved - i/o map mb96(f)33x (7 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 30 of 122 MB96330 series 0000ca h usart1 - serial mode register smr1 r/w 0000cb h usart1 - serial control register scr1 r/w 0000cc h usart1 - tx register tdr1 w 0000cc h usart1 - rx register rdr1 r 0000cd h usart1 - serial status ssr1 r/w 0000ce h usart1 - control/com. register eccr1 r/w 0000cf h usart1 - ext. status register escr1 r/w 0000d0 h usart1 - baud rate generator register low bgrl1 bgr1 r/w 0000d1 h usart1 - baud rate genera tor register high bgrh1 r/w 0000d2 h usart1 - extended serial interrupt register esir1 r/w 0000d3 h reserved - 0000d4 h usart2 - serial mode register smr2 r/w 0000d5 h usart2 - serial control register scr2 r/w 0000d6 h usart2 - tx register tdr2 w 0000d6 h usart2 - rx register rdr2 r 0000d7 h usart2 - serial status ssr2 r/w 0000d8 h usart2 - control/com. register eccr2 r/w 0000d9 h usart2 - ext. status register escr2 r/w 0000da h usart2 - baud rate generator register low bgrl2 bgr2 r/w 0000db h usart2 - baud rate genera tor register high bgrh2 r/w 0000dc h usart2 - extended serial interrupt register esir2 r/w 0000dd h reserved - 0000de h usart3 - serial mode register smr3 r/w 0000df h usart3 - serial control register scr3 r/w 0000e0 h usart3 - tx register tdr3 w 0000e0 h usart3 - rx register rdr3 r 0000e1 h usart3 - serial status ssr3 r/w 0000e2 h usart3 - control/com. register eccr3 r/w 0000e3 h usart3 - ext. status register escr3 r/w 0000e4 h usart3 - baud rate generator register low bgrl3 bgr3 r/w i/o map mb96(f)33x (8 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 31 of 122 MB96330 series 0000e5 h usart3 - baud rate genera tor register high bgrh3 r/w 0000e6 h usart3 - extended serial interrupt register esir3 r/w 0000e7 h - 0000ef h reserved - 0000f0 h -000 0ff h external bus area extbus0 r/w 000100 h dma0 - buffer address pointer low byte bapl0 r/w 000101 h dma0 - buffer address pointer middle byte bapm0 r/w 000102 h dma0 - buffer address pointer high byte baph0 r/w 000103 h dma0 - dma control register dmacs0 r/w 000104 h dma0 - i/o register address pointer low byte ioal0 ioa0 r/w 000105 h dma0 - i/o register address pointer high byte ioah0 r/w 000106 h dma0 - data counter low byte dctl0 dct0 r/w 000107 h dma0 - data counter high byte dcth0 r/w 000108 h dma1 - buffer address pointer low byte bapl1 r/w 000109 h dma1 - buffer address pointer middle byte bapm1 r/w 00010a h dma1 - buffer address pointer high byte baph1 r/w 00010b h dma1 - dma control register dmacs1 r/w 00010c h dma1 - i/o register address pointer low byte ioal1 ioa1 r/w 00010d h dma1 - i/o register address pointer high byte ioah1 r/w 00010e h dma1 - data counter low byte dctl1 dct1 r/w 00010f h dma1 - data counter high byte dcth1 r/w 000110 h dma2 - buffer address pointer low byte bapl2 r/w 000111 h dma2 - buffer address pointer middle byte bapm2 r/w 000112 h dma2 - buffer address pointer high byte baph2 r/w 000113 h dma2 - dma control register dmacs2 r/w 000114 h dma2 - i/o register address pointer low byte ioal2 ioa2 r/w 000115 h dma2 - i/o register address pointer high byte ioah2 r/w 000116 h dma2 - data counter low byte dctl2 dct2 r/w 000117 h dma2 - data counter high byte dcth2 r/w 000118 h dma3 - buffer address pointer low byte bapl3 r/w i/o map mb96(f)33x (9 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 32 of 122 MB96330 series 000119 h dma3 - buffer address pointer middle byte bapm3 r/w 00011a h dma3 - buffer address pointer high byte baph3 r/w 00011b h dma3 - dma control register dmacs3 r/w 00011c h dma3 - i/o register address pointer low byte ioal3 ioa3 r/w 00011d h dma3 - i/o register address pointer high byte ioah3 r/w 00011e h dma3 - data counter low byte dctl3 dct3 r/w 00011f h dma3 - data counter high byte dcth3 r/w 000120 h dma4 - buffer address pointer low byte bapl4 r/w 000121 h dma4 - buffer address pointer middle byte bapm4 r/w 000122 h dma4 - buffer address pointer high byte baph4 r/w 000123 h dma4 - dma control register dmacs4 r/w 000124 h dma4 - i/o register address pointer low byte ioal4 ioa4 r/w 000125 h dma4 - i/o register address pointer high byte ioah4 r/w 000126 h dma4 - data counter low byte dctl4 dct4 r/w 000127 h dma4 - data counter high byte dcth4 r/w 000128 h dma5 - buffer address pointer low byte bapl5 r/w 000129 h dma5 - buffer address pointer middle byte bapm5 r/w 00012a h dma5 - buffer address pointer high byte baph5 r/w 00012b h dma5 - dma control register dmacs5 r/w 00012c h dma5 - i/o register address pointer low byte ioal5 ioa5 r/w 00012d h dma5 - i/o register address pointer high byte ioah5 r/w 00012e h dma5 - data counter low byte dctl5 dct5 r/w 00012f h dma5 - data counter high byte dcth5 r/w 000130 h dma6 - buffer address pointer low byte bapl6 r/w 000131 h dma6 - buffer address pointer middle byte bapm6 r/w 000132 h dma6 - buffer address pointer high byte baph6 r/w 000133 h dma6 - dma control register dmacs6 r/w 000134 h dma6 - i/o register address pointer low byte ioal6 ioa6 r/w 000135 h dma6 - i/o register address pointer high byte ioah6 r/w 000136 h dma6 - data counter low byte dctl6 dct6 r/w i/o map mb96(f)33x (10 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 33 of 122 MB96330 series 000137 h dma6 - data counter high byte dcth6 r/w 000138 h dma7 - buffer address pointer low byte bapl7 r/w 000139 h dma7 - buffer address pointer middle byte bapm7 r/w 00013a h dma7 - buffer address pointer high byte baph7 r/w 00013b h dma7 - dma control register dmacs7 r/w 00013c h dma7 - i/o register address pointer low byte ioal7 ioa7 r/w 00013d h dma7 - i/o register address pointer high byte ioah7 r/w 00013e h dma7 - data counter low byte dctl7 dct7 r/w 00013f h dma7 - data counter high byte dcth7 r/w 000140 h dma8 - buffer address pointer low byte bapl8 r/w 000141 h dma8 - buffer address pointer middle byte bapm8 r/w 000142 h dma8 - buffer address pointer high byte baph8 r/w 000143 h dma8 - dma control register dmacs8 r/w 000144 h dma8 - i/o register address pointer low byte ioal8 ioa8 r/w 000145 h dma8 - i/o register address pointer high byte ioah8 r/w 000146 h dma8 - data counter low byte dctl8 dct8 r/w 000147 h dma8 - data counter high byte dcth8 r/w 000148 h dma9 - buffer address pointer low byte bapl9 r/w 000149 h dma9 - buffer address pointer middle byte bapm9 r/w 00014a h dma9 - buffer address pointer high byte baph9 r/w 00014b h dma9 - dma control register dmacs9 r/w 00014c h dma9 - i/o register address pointer low byte ioal9 ioa9 r/w 00014d h dma9 - i/o register address pointer high byte ioah9 r/w 00014e h dma9 - data counter low byte dctl9 dct9 r/w 00014f h dma9 - data counter high byte dcth9 r/w 000150 h - 00017f h reserved - 000180 h - 00037f h cpu - general purpose registers (ram access) gpr_ram r/w 000380 h dma0 - interrupt select disel0 r/w 000381 h dma1 - interrupt select disel1 r/w i/o map mb96(f)33x (11 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 34 of 122 MB96330 series 000382 h dma2 - interrupt select disel2 r/w 000383 h dma3 - interrupt select disel3 r/w 000384 h dma4 - interrupt select disel4 r/w 000385 h dma5 - interrupt select disel5 r/w 000386 h dma6 - interrupt select disel6 r/w 000387 h dma7 - interrupt select disel7 r/w 000388 h dma8 - interrupt select disel8 r/w 000389 h dma9 - interrupt select disel9 r/w 00038a h - 00038f h reserved - 000390 h dma - status register low byte dsrl dsr r/w 000391 h dma - status register high byte dsrh r/w 000392 h dma - stop status register low byte dssrl dssr r/w 000393 h dma - stop status register high byte dssrh r/w 000394 h dma - enable register low byte derl der r/w 000395 h dma - enable register high byte derh r/w 000396 h - 00039f h reserved - 0003a0 h interrupt level register ilr icr r/w 0003a1 h interrupt index register idx r/w 0003a2 h interrupt vector table base register low tbrl tbr r/w 0003a3 h interrupt vector table base register high tbrh r/w 0003a4 h delayed interrupt register dirr r/w 0003a5 h non maskable interrupt register nmi r/w 0003a6 h - 0003ab h reserved - 0003ac h edsu communication interrupt selection low edsu2l edsu2 r/w 0003ad h edsu communication interrupt selection high edsu2h r/w 0003ae h rom mirror contro l register romm r/w 0003af h edsu configuration register edsu r/w 0003b0 h memory patch control/status register ch 0/1 pfcs0 r/w 0003b1 h memory patch control/stat us register ch 0/1 r/w i/o map mb96(f)33x (12 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 35 of 122 MB96330 series 0003b2 h memory patch control/status register ch 2/3 pfcs1 r/w 0003b3 h memory patch control/stat us register ch 2/3 r/w 0003b4 h memory patch control/status register ch 4/5 pfcs2 r/w 0003b5 h memory patch control/stat us register ch 4/5 r/w 0003b6 h memory patch control/status register ch 6/7 pfcs3 r/w 0003b7 h memory patch control/stat us register ch 6/7 r/w 0003b8 h memory patch function - patch address 0 low pfal0 r/w 0003b9 h memory patch function - patch address 0 middle pfam0 r/w 0003ba h memory patch function - patch address 0 high pfah0 r/w 0003bb h memory patch function - patch address 1 low pfal1 r/w 0003bc h memory patch function - patch address 1 middle pfam1 r/w 0003bd h memory patch function - patch address 1 high pfah1 r/w 0003be h memory patch function - patch address 2 low pfal2 r/w 0003bf h memory patch function - patch address 2 middle pfam2 r/w 0003c0 h memory patch function - patch address 2 high pfah2 r/w 0003c1 h memory patch function - patch address 3 low pfal3 r/w 0003c2 h memory patch function - patch address 3 middle pfam3 r/w 0003c3 h memory patch function - patch address 3 high pfah3 r/w 0003c4 h memory patch function - patch address 4 low pfal4 r/w 0003c5 h memory patch function - patch address 4 middle pfam4 r/w 0003c6 h memory patch function - patch address 4 high pfah4 r/w 0003c7 h memory patch function - patch address 5 low pfal5 r/w 0003c8 h memory patch function - patch address 5 middle pfam5 r/w 0003c9 h memory patch function - patch address 5 high pfah5 r/w 0003ca h memory patch function - patch address 6 low pfal6 r/w 0003cb h memory patch function - patch address 6 middle pfam6 r/w 0003cc h memory patch function - patch address 6 high pfah6 r/w 0003cd h memory patch function - patch address 7 low pfal7 r/w 0003ce h memory patch function - patch address 7 middle pfam7 r/w 0003cf h memory patch function - patch address 7 high pfah7 r/w i/o map mb96(f)33x (13 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 36 of 122 MB96330 series 0003d0 h memory patch function - patch data 0 low pfdl0 pfd0 r/w 0003d1 h memory patch function - patch data 0 high pfdh0 r/w 0003d2 h memory patch function - patch data 1 low pfdl1 pfd1 r/w 0003d3 h memory patch function - patch data 1 high pfdh1 r/w 0003d4 h memory patch function - patch data 2 low pfdl2 pfd2 r/w 0003d5 h memory patch function - patch data 2 high pfdh2 r/w 0003d6 h memory patch function - patch data 3 low pfdl3 pfd3 r/w 0003d7 h memory patch function - patch data 3 high pfdh3 r/w 0003d8 h memory patch function - patch data 4 low pfdl4 pfd4 r/w 0003d9 h memory patch function - patch data 4 high pfdh4 r/w 0003da h memory patch function - patch data 5 low pfdl5 pfd5 r/w 0003db h memory patch function - patch data 5 high pfdh5 r/w 0003dc h memory patch function - patch data 6 low pfdl6 pfd6 r/w 0003dd h memory patch function - patch data 6 high pfdh6 r/w 0003de h memory patch function - patch data 7 low pfdl7 pfd7 r/w 0003df h memory patch function - patch data 7 high pfdh7 r/w 0003e0 h - 0003f0 h reserved - 0003f1 h memory control status register a mcsra r/w 0003f2 h memory timing configuration register a low mtcral mtcra r/w 0003f3 h memory timing configuration register a high mtcrah r/w 0003f4 h - 0003f8 h reserved - 0003f9 h flash memory write control register 1 fmwc1 r/w 0003fa h flash memory write control register 2 fmwc2 r/w 0003fb h flash memory write control register 3 fmwc3 r/w 0003fc h flash memory write control register 4 fmwc4 r/w 0003fd h flash memory write control register 5 fmwc5 r/w 0003fe h - 0003ff h reserved - 000400 h standby mode control register smcr r/w 000401 h clock select register cksr r/w i/o map mb96(f)33x (14 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 37 of 122 MB96330 series 000402 h clock stabilization select register ckssr r/w 000403 h clock monitor register ckmr r 000404 h clock frequency control register low ckfcrl ckfcr r/w 000405 h clock frequency control register high ckfcrh r/w 000406 h pll control register low pllcrl pllcr r/w 000407 h pll control register high pllcrh r/w 000408 h rc clock timer control register rctcr r/w 000409 h main clock timer cont rol regist er mctcr r/w 00040a h sub clock timer control register sctcr r/w 00040b h reset cause and clock status register with clear function rccsrc r 00040c h reset configuration register rcr r/w 00040d h reset cause and clock status register rccsr r 00040e h watch dog timer configuration register wdtc r/w 00040f h watch dog timer clear pattern register wdtcp w 000410 h - 000414 h reserved - 000415 h clock output activation register coar r/w 000416 h clock output configurat ion register 0 cocr0 r/w 000417 h clock output configurat ion register 1 cocr1 r/w 000418 h clock modulator control register cmcr r/w 000419 h reserved - 00041a h clock modulator parameter register low cmprl cmpr r/w 00041b h clock modulator paramete r register high cmprh r/w 00041c h - 00042b h reserved - 00042c h voltage regulator control register vrcr r/w 00042d h clock input and lvd control register cilcr r/w 00042e h - 00042f h reserved - 000430 h i/o port p00 - data direction register ddr00 r/w 000431 h i/o port p01 - data direction register ddr01 r/w 000432 h i/o port p02 - data direction register ddr02 r/w i/o map mb96(f)33x (15 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 38 of 122 MB96330 series 000433 h i/o port p03 - data direction register ddr03 r/w 000434 h i/o port p04 - data direction register ddr04 r/w 000435 h i/o port p05 - data direction register ddr05 r/w 000436 h i/o port p06 - data direction register ddr06 r/w 000437 h i/o port p07 - data direction register ddr07 r/w 000438 h i/o port p08 - data direction register ddr08 r/w 000439 h i/o port p09 - data direction register ddr09 r/w 00043a h i/o port p10 - data direction register ddr10 r/w 00043b h i/o port p11 - data direction register ddr11 r/w 00043c h i/o port p12 - data direction register ddr12 r/w 00043d h i/o port p13 - data direction register ddr13 r/w 00043e h i/o port p14 - data direction register ddr14 r/w 00043f h i/o port p15 - data direction register ddr15 r/w 000440 h reserved - 000441 h i/o port p17 - data direction register ddr17 r/w 000442 h - 000443 h reserved - 000444 h i/o port p00 - port input enable register pier00 r/w 000445 h i/o port p01 - port input enable register pier01 r/w 000446 h i/o port p02 - port input enable register pier02 r/w 000447 h i/o port p03 - port input enable register pier03 r/w 000448 h i/o port p04 - port input enable register pier04 r/w 000449 h i/o port p05 - port input enable register pier05 r/w 00044a h i/o port p06 - port input enable register pier06 r/w 00044b h i/o port p07 - port input enable register pier07 r/w 00044c h i/o port p08 - port input enable register pier08 r/w 00044d h i/o port p09 - port input enable register pier09 r/w 00044e h i/o port p10 - port input enable register pier10 r/w 00044f h i/o port p11 - port input enable register pier11 r/w 000450 h i/o port p12 - port input enable register pier12 r/w 000451 h i/o port p13 - port input enable register pier13 r/w i/o map mb96(f)33x (16 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 39 of 122 MB96330 series 000452 h i/o port p14 - port input enable register pier14 r/w 000453 h i/o port p15 - port input enable register pier15 r/w 000454 h reserved - 000455 h i/o port p17 - port input enable register pier17 r/w 000456 h - 000457 h reserved - 000458 h i/o port p00 - port input level register pilr00 r/w 000459 h i/o port p01 - port input level register pilr01 r/w 00045a h i/o port p02 - port input level register pilr02 r/w 00045b h i/o port p03 - port input level register pilr03 r/w 00045c h i/o port p04 - port input level register pilr04 r/w 00045d h i/o port p05 - port input level register pilr05 r/w 00045e h i/o port p06 - port input level register pilr06 r/w 00045f h i/o port p07 - port input level register pilr07 r/w 000460 h i/o port p08 - port input level register pilr08 r/w 000461 h i/o port p09 - port input level register pilr09 r/w 000462 h i/o port p10 - port input level register pilr10 r/w 000463 h i/o port p11 - port input level register pilr11 r/w 000464 h i/o port p12 - port input level register pilr12 r/w 000465 h i/o port p13 - port input level register pilr13 r/w 000466 h i/o port p14 - port input level register pilr14 r/w 000467 h i/o port p15 - port input level register pilr15 r/w 000468 h reserved - 000469 h i/o port p17 - port input level register pilr17 r/w 00046a h - 00046b h reserved - 00046c h i/o port p00 - extended port input level register epilr00 r/w 00046d h i/o port p01 - extended port input level register epilr01 r/w 00046e h i/o port p02 - extended port input level register epilr02 r/w 00046f h i/o port p03 - extended port input level register epilr03 r/w 000470 h i/o port p04 - extended port input level register epilr04 r/w i/o map mb96(f)33x (17 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 40 of 122 MB96330 series 000471 h i/o port p05 - extended port input level register epilr05 r/w 000472 h i/o port p06 - extended port input level register epilr06 r/w 000473 h i/o port p07 - extended port input level register epilr07 r/w 000474 h i/o port p08 - extended port input level register epilr08 r/w 000475 h i/o port p09 - extended port input level register epilr09 r/w 000476 h i/o port p10 - extended port input level register epilr10 r/w 000477 h i/o port p11 - extended port input level register epilr11 r/w 000478 h i/o port p12 - extended port input level register epilr12 r/w 000479 h i/o port p13 - extended port input level register epilr13 r/w 00047a h i/o port p14 - extended port input level register epilr14 r/w 00047b h i/o port p15 - extended port input level register epilr15 r/w 00047c h reserved - 00047d h i/o port p17 - extended port input level register epilr17 r/w 00047e h - 00047f h reserved - 000480 h i/o port p00 - port output drive register podr00 r/w 000481 h i/o port p01 - port output drive register podr01 r/w 000482 h i/o port p02 - port output drive register podr02 r/w 000483 h i/o port p03 - port output drive register podr03 r/w 000484 h i/o port p04 - port output drive register podr04 r/w 000485 h i/o port p05 - port output drive register podr05 r/w 000486 h i/o port p06 - port output drive register podr06 r/w 000487 h i/o port p07 - port output drive register podr07 r/w 000488 h i/o port p08 - port output drive register podr08 r/w 000489 h i/o port p09 - port output drive register podr09 r/w 00048a h i/o port p10 - port output drive register podr10 r/w 00048b h i/o port p11 - port output drive register podr11 r/w 00048c h i/o port p12 - port output drive register podr12 r/w 00048d h i/o port p13 - port output drive register podr13 r/w 00048e h i/o port p14 - port output drive register podr14 r/w 00048f h i/o port p15 - port output drive register podr15 r/w i/o map mb96(f)33x (18 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 41 of 122 MB96330 series 000490 h reserved - 000491 h i/o port p17 - port output drive register podr17 r/w 000492 h - 00049b h reserved - 00049c h i/o port p08 - port high drive register phdr08 r/w 00049d h i/o port p09 - port high drive register phdr09 r/w 00049e h i/o port p10 - port high drive register phdr10 r/w 00049f h - 0004a7 h reserved - 0004a8 h i/o port p00 - pull-up resistor control register pucr00 r/w 0004a9 h i/o port p01 - pull-up resistor control register pucr01 r/w 0004aa h i/o port p02 - pull-up resistor control register pucr02 r/w 0004ab h i/o port p03 - pull-up resistor control register pucr03 r/w 0004ac h i/o port p04 - pull-up resistor control register pucr04 r/w 0004ad h i/o port p05 - pull-up resistor control register pucr05 r/w 0004ae h i/o port p06 - pull-up resistor control register pucr06 r/w 0004af h i/o port p07 - pull-up resistor control register pucr07 r/w 0004b0 h i/o port p08 - pull-up resistor control register pucr08 r/w 0004b1 h i/o port p09 - pull-up resistor control register pucr09 r/w 0004b2 h i/o port p10 - pull-up resistor control register pucr10 r/w 0004b3 h i/o port p11 - pull-up resistor control register pucr11 r/w 0004b4 h i/o port p12 - pull-up resistor control register pucr12 r/w 0004b5 h i/o port p13 - pull-up resistor control register pucr13 r/w 0004b6 h i/o port p14 - pull-up resistor control register pucr14 r/w 0004b7 h i/o port p15 - pull-up resistor control register pucr15 r/w 0004b8 h reserved - 0004b9 h i/o port p17 - pull-up resistor control register pucr17 r/w 0004ba h - 0004bb h reserved - 0004bc h i/o port p00 - external pin state register epsr00 r 0004bd h i/o port p01 - external pin state register epsr01 r 0004be h i/o port p02 - external pin state register epsr02 r i/o map mb96(f)33x (19 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 42 of 122 MB96330 series 0004bf h i/o port p03 - external pin state register epsr03 r 0004c0 h i/o port p04 - external pin state register epsr04 r 0004c1 h i/o port p05 - external pin state register epsr05 r 0004c2 h i/o port p06 - external pin state register epsr06 r 0004c3 h i/o port p07 - external pin state register epsr07 r 0004c4 h i/o port p08 - external pin state register epsr08 r 0004c5 h i/o port p09 - external pin state register epsr09 r 0004c6 h i/o port p10 - external pin state register epsr10 r 0004c7 h i/o port p11 - external pin state register epsr11 r 0004c8 h i/o port p12 - external pin state register epsr12 r 0004c9 h i/o port p13 - external pin state register epsr13 r 0004ca h i/o port p14 - external pin state register epsr14 r 0004cb h i/o port p15 - external pin state register epsr15 r 0004cc h reserved - 0004cd h i/o port p17 - external pin state register epsr17 r 0004ce h - 0004cf h reserved - 0004d0 h adc analog input enable register 0 ader0 r/w 0004d1 h adc analog input enable register 1 ader1 r/w 0004d2 h adc analog input enable register 2 ader2 r/w 0004d3 h adc analog input enable register 3 ader3 r/w 0004d4 h adc analog input enable register 4 ader4 r/w 0004d5 h reserved - 0004d6 h peripheral resource relocation register 0 prrr0 r/w 0004d7 h peripheral resource relocation register 1 prrr1 r/w 0004d8 h peripheral resource relocation register 2 prrr2 r/w 0004d9 h peripheral resource relocation register 3 prrr3 r/w 0004da h peripheral resource relocation register 4 prrr4 r/w 0004db h peripheral resource relocation register 5 prrr5 r/w 0004dc h peripheral resource relocation register 6 prrr6 r/w 0004dd h peripheral resource relocation register 7 prrr7 r/w i/o map mb96(f)33x (20 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 43 of 122 MB96330 series 0004de h peripheral resource relocation register 8 prrr8 r/w 0004df h peripheral resource relocation register 9 prrr9 r/w 0004e0 h rtc - sub second register l wtbrl0 wtbr0 r/w 0004e1 h rtc - sub second register m wtbrh0 r/w 0004e2 h rtc - sub-second register h wtbr1 r/w 0004e3 h rtc - second register wtsr r/w 0004e4 h rtc - minutes wtmr r/w 0004e5 h rtc - hour wthr r/w 0004e6 h rtc - timer control extended register wtcer r/w 0004e7 h rtc - clock select register wtcksr r/w 0004e8 h rtc - timer control register low wtcrl wtcr r/w 0004e9 h rtc - timer control register high wtcrh r/w 0004ea h cal - calibration unit control register cucr r/w 0004eb h reserved - 0004ec h cal - duration timer data register low cutdl cutd r/w 0004ed h cal - duration timer data register high cutdh r/w 0004ee h cal - calibration timer register 2 low cutr2l cutr2 r 0004ef h cal - calibration timer register 2 high cutr2h r 0004f0 h cal - calibration timer register 1 low cutr1l cutr1 r 0004f1 h cal - calibration timer register 1 high cutr1h r 0004f2 h - 0004f9 h reserved - 0004fa h rlt - timer input select (for cascading) tmisr r/w 0004fb h - 0004ff h reserved - 000500 h frt2 - data register of free-running timer tcdt2 r/w 000501 h frt2 - data register of free-running timer r/w 000502 h frt2 - control status register of free-running timer low tccsl2 tccs2 r/w 000503 h frt2 - control status register of free-running timer high tccsh2 r/w 000504 h frt3 - data register of free-running timer tcdt3 r/w 000505 h frt3 - data register of free-running timer r/w i/o map mb96(f)33x (21 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 44 of 122 MB96330 series 000506 h frt3 - control status register of free-running timer low tccsl3 tccs3 r/w 000507 h frt3 - control status register of free-running timer high tccsh3 r/w 000508 h ocu8 - output compare control status ocs8 r/w 000509 h ocu9 - output compare control status ocs9 r/w 00050a h ocu8 - compare register occp8 r/w 00050b h ocu8 - compare register r/w 00050c h ocu9 - compare register occp9 r/w 00050d h ocu9 - compare register r/w 00050e h ocu10 - output compare control status ocs10 r/w 00050f h ocu11 - output compare control status ocs11 r/w 000510 h ocu10 - compare register occp10 r/w 000511 h ocu10 - compare register r/w 000512 h ocu11 - compare register occp11 r/w 000513 h ocu11 - compare register r/w 000514 h icu8/icu9 - control status register ics89 r/w 000515 h icu8/icu9 - edge register ice89 r/w 000516 h icu8 - capture register low ipcpl8 ipcp8 r 000517 h icu8 - capture register high ipcph8 r 000518 h icu9 - capture register low ipcpl9 ipcp9 r 000519 h icu9 - capture register high ipcph9 r 00051a h - 000529 h reserved - 00052a h usart5 - serial mode register smr5 r/w 00052b h usart5 - serial control register scr5 r/w 00052c h usart5 - rx register tdr5 w 00052c h usart5 - tx register rdr5 r 00052d h usart5 - serial status ssr5 r/w 00052e h usart5 - control/com. register eccr5 r/w 00052f h usart5 - ext. status register escr5 r/w 000530 h usart5 - baud rate generator register low bgrl5 bgr5 r/w 000531 h usart5 - baud rate genera tor register high bgrh5 r/w i/o map mb96(f)33x (22 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 45 of 122 MB96330 series 000532 h usart5 - extended serial interrupt register esir5 r/w 000533 h - 00053d h reserved - 00053e h usart7 - serial mode register smr7 r/w 00053f h usart7 - serial control register scr7 r/w 000540 h usart7 - serial tx register tdr7 w 000540 h usart7 - serial rx register rdr7 r 000541 h usart7 - serial status register ssr7 r/w 000542 h usart7 - ext. control/ com. register eccr7 r/w 000543 h usart7 - ext. status com. register escr7 r/w 000544 h usart7 - baud rate generator register low bgrl7 bgr7 r/w 000545 h usart7 - baud rate genera tor register high bgrh7 r/w 000546 h usart7 - extended serial interrupt register esir7 r/w 000547 h reserved - 000548 h usart8 - serial mode register smr8 r/w 000549 h usart8 - serial control register scr8 r/w 00054a h usart8 - serial tx register tdr8 w 00054a h usart8 - serial rx register rdr8 r 00054b h usart8 - serial status register ssr8 r/w 00054c h usart8 - ext. control/ com. register eccr8 r/w 00054d h usart8 - ext. status com. register escr8 r/w 00054e h usart8 - baud rate generator register low bgrl8 bgr8 r/w 00054f h usart8 - baud rate genera tor register high bgrh8 r/w 000550 h usart8 - extended serial interrupt register esir8 r/w 000551 h reserved - 000552 h usart9 - serial mode register smr9 r/w 000553 h usart9 - serial control register scr9 r/w 000554 h usart9 - serial tx register tdr9 w 000554 h usart9 - serial rx register rdr9 r 000555 h usart9 - serial status register ssr9 r/w 000556 h usart9 - ext. control/ com. register eccr9 r/w i/o map mb96(f)33x (23 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 46 of 122 MB96330 series 000557 h usart9 - ext. status com. register escr9 r/w 000558 h usart9 - baud rate generator register low bgrl9 bgr9 r/w 000559 h usart9 - baud rate genera tor register high bgrh9 r/w 00055a h usart9 - extended serial interrupt register esir9 r/w 00055b h - 00055f h reserved - 000560 h alarm0 - control status register acsr0 r/w 000561 h alarm0 - extended control status register aecsr0 r/w 000562 h alarm1 - control status register acsr1 r/w 000563 h alarm1 - extended control status register aecsr1 r/w 000564 h ppg6 - timer register ptmr6 r 000565 h ppg6 - timer register r 000566 h ppg6 - period setting register pcsr6 w 000567 h ppg6 - period setting register w 000568 h ppg6 - duty cycle register pdut6 w 000569 h ppg6 - duty cycle register w 00056a h ppg6 - control status r egister low pcnl6 pcn6 r/w 00056b h ppg6 - control status register high pcnh6 r/w 00056c h ppg7 - timer register ptmr7 r 00056d h ppg7 - timer register r 00056e h ppg7 - period setting register pcsr7 w 00056f h ppg7 - period setting register w 000570 h ppg7 - duty cycle register pdut7 w 000571 h ppg7 - duty cycle register w 000572 h ppg7 - control status r egister low pcnl7 pcn7 r/w 000573 h ppg7 - control status register high pcnh7 r/w 000574 h ppg11-ppg8 - general control register 1 low gcn1l2 gcn12 r/w 000575 h ppg11-ppg8 - general control register 1 high gcn1h2 r/w 000576 h ppg11-ppg8 - general control register 2 low gcn2l2 gcn22 r/w 000577 h ppg11-ppg8 - general control register 2 high gcn2h2 r/w 000578 h ppg8 - timer register ptmr8 r i/o map mb96(f)33x (24 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 47 of 122 MB96330 series 000579 h ppg8 - timer register r 00057a h ppg8 - period setting register pcsr8 w 00057b h ppg8 - period setting register w 00057c h ppg8 - duty cycle register pdut8 w 00057d h ppg8 - duty cycle register w 00057e h ppg8 - control status r egister low pcnl8 pcn8 r/w 00057f h ppg8 - control status register high pcnh8 r/w 000580 h ppg9 - timer register ptmr9 r 000581 h ppg9 - timer register r 000582 h ppg9 - period setting register pcsr9 w 000583 h ppg9 - period setting register w 000584 h ppg9 - duty cycle register pdut9 w 000585 h ppg9 - duty cycle register w 000586 h ppg9 - control status r egister low pcnl9 pcn9 r/w 000587 h ppg9 - control status register high pcnh9 r/w 000588 h ppg10 - timer register ptmr10 r 000589 h ppg10 - timer register r 00058a h ppg10 - period setting register pcsr10 w 00058b h ppg10 - period setting register w 00058c h ppg10 - duty cycle register pdut10 w 00058d h ppg10 - duty cycle register w 00058e h ppg10 - control status register low pcnl10 pcn10 r/w 00058f h ppg10 - control status register high pcnh10 r/w 000590 h ppg11 - timer register ptmr11 r 000591 h ppg11 - timer register r 000592 h ppg11 - period setting register pcsr11 w 000593 h ppg11 - period setting register w 000594 h ppg11 - duty cycle register pdut11 w 000595 h ppg11 - duty cycle register w 000596 h ppg11 - control status register low pcnl11 pcn11 r/w i/o map mb96(f)33x (25 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 48 of 122 MB96330 series 000597 h ppg11 - control status register high pcnh11 r/w 000598 h ppg15-ppg12 - general control register 1 low gcn1l3 gcn13 r/w 000599 h ppg15-ppg12 - general control register 1 high gcn1h3 r/w 00059a h ppg15-ppg12 - general control register 2 low gcn2l3 gcn23 r/w 00059b h ppg15-ppg12 - general control register 2 high gcn2h3 r/w 00059c h ppg12 - timer register ptmr12 r 00059d h ppg12 - timer register r 00059e h ppg12 - period setting register pcsr12 w 00059f h ppg12 - period setting register w 0005a0 h ppg12 - duty cycle register pdut12 w 0005a1 h ppg12 - duty cycle register w 0005a2 h ppg12 - control status register low pcnl12 pcn12 r/w 0005a3 h ppg12 - control status register high pcnh12 r/w 0005a4 h ppg13 - timer register ptmr13 r 0005a5 h ppg13 - timer register r 0005a6 h ppg13 - period setting register pcsr13 w 0005a7 h ppg13 - period setting register w 0005a8 h ppg13 - duty cycle register pdut13 w 0005a9 h ppg13 - duty cycle register w 0005aa h ppg13 - control status register low pcnl13 pcn13 r/w 0005ab h ppg13 - control status register high pcnh13 r/w 0005ac h ppg14 - timer register ptmr14 r 0005ad h ppg14 - timer register r 0005ae h ppg14 - period setting register pcsr14 w 0005af h ppg14 - period setting register w 0005b0 h ppg14 - duty cycle register pdut14 w 0005b1 h ppg14 - duty cycle register w 0005b2 h ppg14 - control status register low pcnl14 pcn14 r/w 0005b3 h ppg14 - control status register high pcnh14 r/w 0005b4 h ppg15 - timer register ptmr15 r i/o map mb96(f)33x (26 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 49 of 122 MB96330 series 0005b5 h ppg15 - timer register r 0005b6 h ppg15 - period setting register pcsr15 w 0005b7 h ppg15 - period setting register w 0005b8 h ppg15 - duty cycle register pdut15 w 0005b9 h ppg15 - duty cycle register w 0005ba h ppg15 - control status register low pcnl15 pcn15 r/w 0005bb h ppg15 - control status register high pcnh15 r/w 0005bc h ppg19-ppg16 - general control register 1 low gcn1l4 gcn14 r/w 0005bd h ppg19-ppg16 - general control register 1 high gcn1h4 r/w 0005be h ppg19-ppg16 - general control register 2 low gcn2l4 gcn24 r/w 0005bf h ppg19-ppg16 - general control register 2 high gcn2h4 r/w 0005c0 h ppg16 - timer register ptmr16 r 0005c1 h ppg16 - timer register r 0005c2 h ppg16 - period setting register pcsr16 w 0005c3 h ppg16 - period setting register w 0005c4 h ppg16 - duty cycle register pdut16 w 0005c5 h ppg16 - duty cycle register w 0005c6 h ppg16 - control status register low pcnl16 pcn16 r/w 0005c7 h ppg16 - control status register high pcnh16 r/w 0005c8 h ppg17 - timer register ptmr17 r 0005c9 h ppg17 - timer register r 0005ca h ppg17 - period setting register pcsr17 w 0005cb h ppg17 - period setting register w 0005cc h ppg17 - duty cycle register pdut17 w 0005cd h ppg17 - duty cycle register w 0005ce h ppg17 - control status register low pcnl17 pcn17 r/w 0005cf h ppg17 - control status register high pcnh17 r/w 0005d0 h ppg18 - timer register ptmr18 r 0005d1 h ppg18 - timer register r 0005d2 h ppg18 - period setting register pcsr18 w i/o map mb96(f)33x (27 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 50 of 122 MB96330 series 0005d3 h ppg18 - period setting register w 0005d4 h ppg18 - duty cycle register pdut18 w 0005d5 h ppg18 - duty cycle register w 0005d6 h ppg18 - control status register low pcnl18 pcn18 r/w 0005d7 h ppg18 - control status register high pcnh18 r/w 0005d8 h ppg19 - timer register ptmr19 r 0005d9 h ppg19 - timer register r 0005da h ppg19 - period setting register pcsr19 w 0005db h ppg19 - period setting register w 0005dc h ppg19 - duty cycle register pdut19 w 0005dd h ppg19 - duty cycle register w 0005de h ppg19 - control status register low pcnl19 pcn19 r/w 0005df h ppg19 - control status register high pcnh19 r/w 0005e0 h - 00065f h reserved - 000660 h peripheral resource relocation register 10 prrr10 r/w 000661 h peripheral resource relocation register 11 prrr11 r/w 000662 h peripheral resource relocation register 12 prrr12 r/w 000663 h peripheral resource relocation register 13 prrr13 w 000664 h - 00069f h reserved - 0006a0 h usb - host control register low hcntl0 hcnt0 r/w 0006a1 h usb - host control register high hcnth0 r/w 0006a2 h usb - host interrupt register hirq0 r/w 0006a3 h usb - host error status register herr0 r/w 0006a4 h usb - host state status register hstate0 r/w 0006a5 h usb - host sof int. frame compare register hfcomp0 r/w 0006a6 h usb - host retry timer setting register low hrtimerl0 r/w 0006a7 h usb - host retry timer settin g register middle hrtimerm0 r/w 0006a8 h usb - host retry timer setting register high hrtimerh0 r/w 0006a9 h usb - host address register hadr0 r/w i/o map mb96(f)33x (28 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 51 of 122 MB96330 series 0006aa h usb - host eof setting r egister low heofl0 heof0 r/w 0006ab h usb - host eof setting register high heofh0 r/w 0006ac h usb - host frame register low hframel0 hframe0 r/w 0006ad h usb - host frame register high hframeh0 r/w 0006ae h usb - host token end point register htoken0 r/w 0006af h reserved - 0006b0 h usb - udc control register udcc0 r/w 0006b1 h reserved - 0006b2 h usb - ep0 control register low ep0cl0 ep0c0 r/w 0006b3 h usb - ep0 control register high ep0ch0 r/w 0006b4 h usb - ep1 control register low ep1cl0 ep1c0 r/w 0006b5 h usb - ep1 control register high - non public ep1ch0 r/w 0006b6 h usb - ep2 control register low ep2cl0 ep2c0 r/w 0006b7 h usb - ep2 control register high ep2ch0 r/w 0006b8 h usb - ep3 control register low ep3cl0 ep3c0 r/w 0006b9 h usb - ep3 control register high ep3ch0 r/w 0006ba h usb - ep4 control register low ep4cl0 ep4c0 r/w 0006bb h usb - ep4 control register high ep4ch0 r/w 0006bc h usb - ep5 control register low ep5cl0 ep5c0 r/w 0006bd h usb - ep5 control register high ep5ch0 r/w 0006be h usb - timer stamp register low tmspl0 tmsp0 r/w 0006bf h usb - timer stamp register high tmsph0 r/w 0006c0 h usb - udc status register udcs0 r/w 0006c1 h usb - udc interrupt enable register udcie0 r/w 0006c2 h usb - ep0i status register low ep0isl0 ep0is0 w 0006c3 h usb - ep0i status register high ep0ish0 r/w 0006c4 h usb - ep0o status register low ep0osl0 ep0os0 r/w 0006c5 h usb - ep0o status register high ep0osh0 r/w 0006c6 h usb - ep1 status register low ep1sl0 ep1s0 r/w 0006c7 h usb - ep1 status register high ep1sh0 r/w i/o map mb96(f)33x (29 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 52 of 122 MB96330 series 0006c8 h usb - ep2 status register low ep2sl0 ep2s0 r/w 0006c9 h usb - ep2 status register high ep2sh0 r/w 0006ca h usb - ep3 status register low ep3sl0 ep3s0 r/w 0006cb h usb - ep3 status register high ep3sh0 r/w 0006cc h usb - ep4 status register low ep4sl0 ep4s0 r/w 0006cd h usb - ep4 status register high ep4sh0 r/w 0006ce h usb - ep5 status register low ep5sl0 ep5s0 r/w 0006cf h usb - ep5 status register high ep5sh0 r/w 0006d0 h usb - ep0 data register low ep0dtl0 ep0dt0 r/w 0006d1 h usb - ep0 data register high ep0dth0 r/w 0006d2 h usb - ep1 data register low ep1dtl0 ep1dt0 r/w 0006d3 h usb - ep1 data register high ep1dth0 r/w 0006d4 h usb - ep2 data register low ep2dtl0 ep2dt0 r/w 0006d5 h usb - ep2 data register high ep2dth0 r/w 0006d6 h usb - ep3 data register low ep3dtl0 ep3dt0 r/w 0006d7 h usb - ep3 data register high ep3dth0 r/w 0006d8 h usb - ep4 data register low ep4dtl0 ep4dt0 r/w 0006d9 h usb - ep4 data register high ep4dth0 r/w 0006da h usb - ep5 data register low ep5dtl0 ep5dt0 r/w 0006db h usb - ep5 data register high ep5dth0 r/w 0006dc h - 0006df h reserved - 0006e0 h external bus - area configuration register 0 low eacl0 eac0 r/w 0006e1 h external bus - area configuration register 0 high each0 r/w 0006e2 h external bus - area configuration register 1 low eacl1 eac1 r/w 0006e3 h external bus - area configuration register 1 high each1 r/w 0006e4 h external bus - area configuration register 2 low eacl2 eac2 r/w 0006e5 h external bus - area configuration register 2 high each2 r/w 0006e6 h external bus - area configuration register 3 low eacl3 eac3 r/w 0006e7 h external bus - area configuration register 3 high each3 r/w 0006e8 h external bus - area configuration register 4 low eacl4 eac4 r/w i/o map mb96(f)33x (30 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 53 of 122 MB96330 series 0006e9 h external bus - area configuration register 4 high each4 r/w 0006ea h external bus - area configuration register 5 low eacl5 eac5 r/w 0006eb h external bus - area configuration register 5 high each5 r/w 0006ec h external bus - area select register 2 eas2 r/w 0006ed h external bus - area select register 3 eas3 r/w 0006ee h external bus - area select register 4 eas4 r/w 0006ef h external bus - area select register 5 eas5 r/w 0006f0 h external bus - mode register ebm r/w 0006f1 h external bus - clock and function register ebcf r/w 0006f2 h external bus - address outpu t enable register 0 ebae0 r/w 0006f3 h external bus - address outpu t enable register 1 ebae1 r/w 0006f4 h external bus - address outpu t enable register 2 ebae2 r/w 0006f5 h external bus - control signal register ebcs r/w 0006f6 h - 0006ff h reserved - 000700 h can0 - control register low ctrlrl0 ctrlr0 r/w 000701 h can0 - control register high (reserved) ctrlrh0 r 000702 h can0 - status register low statrl0 statr0 r/w 000703 h can0 - status register high (reserved) statrh0 r 000704 h can0 - error counter low (transmit) errcntl0 errcnt0 r 000705 h can0 - error counter high (receive) errcnth0 r 000706 h can0 - bit timing register low btrl0 btr0 r/w 000707 h can0 - bit timing register high btrh0 r/w 000708 h can0 - interrupt register low intrl0 intr0 r 000709 h can0 - interrupt register high intrh0 r 00070a h can0 - test register low testrl0 testr0 r/w 00070b h can0 - test register high (reserved) testrh0 r 00070c h can0 - brp extension regi ster low brperl0 brper0 r/w 00070d h can0 - brp extension regi ster high (reserved) brperh0 r 00070e h - 00070f h reserved - i/o map mb96(f)33x (31 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 54 of 122 MB96330 series 000710 h can0 - if1 command request register low if1creql0 if1creq0 r/w 000711 h can0 - if1 command request register high if1creqh0 r/w 000712 h can0 - if1 command mask register low if1cmskl0 if1cmsk0 r/w 000713 h can0 - if1 command mask register high (reserved) if1cmskh0 r 000714 h can0 - if1 mask 1 register low if1msk1l0 if1msk10 r/w 000715 h can0 - if1 mask 1 register high if1msk1h0 r/w 000716 h can0 - if1 mask 2 register low if1msk2l0 if1msk20 r/w 000717 h can0 - if1 mask 2 register high if1msk2h0 r/w 000718 h can0 - if1 arbitration 1 register low if1arb1l0 if1arb10 r/w 000719 h can0 - if1 arbitration 1 register high if1arb1h0 r/w 00071a h can0 - if1 arbitration 2 register low if1arb2l0 if1arb20 r/w 00071b h can0 - if1 arbitration 2 register high if1arb2h0 r/w 00071c h can0 - if1 message control register low if1mctrl0 if1mctr0 r/w 00071d h can0 - if1 message control register high if1mctrh0 r/w 00071e h can0 - if1 data a1 low if1dta1l0 if1dta10 r/w 00071f h can0 - if1 data a1 high if1dta1h0 r/w 000720 h can0 - if1 data a2 low if1dta2l0 if1dta20 r/w 000721 h can0 - if1 data a2 high if1dta2h0 r/w 000722 h can0 - if1 data b1 low if1dtb1l0 if1dtb10 r/w 000723 h can0 - if1 data b1 high if1dtb1h0 r/w 000724 h can0 - if1 data b2 low if1dtb2l0 if1dtb20 r/w 000725 h can0 - if1 data b2 high if1dtb2h0 r/w 000726 h - 00073f h reserved - 000740 h can0 - if2 command request register low if2creql0 if2creq0 r/w 000741 h can0 - if2 command request register high if2creqh0 r/w 000742 h can0 - if2 command mask register low if2cmskl0 if2cmsk0 r/w 000743 h can0 - if2 command mask register high (reserved) if2cmskh0 r 000744 h can0 - if2 mask 1 register low if2msk1l0 if2msk10 r/w 000745 h can0 - if2 mask 1 register high if2msk1h0 r/w 000746 h can0 - if2 mask 2 register low if2msk2l0 if2msk20 r/w i/o map mb96(f)33x (32 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 55 of 122 MB96330 series 000747 h can0 - if2 mask 2 register high if2msk2h0 r/w 000748 h can0 - if2 arbitration 1 register low if2arb1l0 if2arb10 r/w 000749 h can0 - if2 arbitration 1 register high if2arb1h0 r/w 00074a h can0 - if2 arbitration 2 register low if2arb2l0 if2arb20 r/w 00074b h can0 - if2 arbitration 2 register high if2arb2h0 r/w 00074c h can0 - if2 message control register low if2mctrl0 if2mctr0 r/w 00074d h can0 - if2 message control register high if2mctrh0 r/w 00074e h can0 - if2 data a1 low if2dta1l0 if2dta10 r/w 00074f h can0 - if2 data a1 high if2dta1h0 r/w 000750 h can0 - if2 data a2 low if2dta2l0 if2dta20 r/w 000751 h can0 - if2 data a2 high if2dta2h0 r/w 000752 h can0 - if2 data b1 low if2dtb1l0 if2dtb10 r/w 000753 h can0 - if2 data b1 high if2dtb1h0 r/w 000754 h can0 - if2 data b2 low if2dtb2l0 if2dtb20 r/w 000755 h can0 - if2 data b2 high if2dtb2h0 r/w 000756 h - 00077f h reserved - 000780 h can0 - transmission request 1 register low treqr1l0 treqr10 r 000781 h can0 - transmission request 1 register high treqr1h0 r 000782 h can0 - transmission request 2 register low treqr2l0 treqr20 r 000783 h can0 - transmission request 2 register high treqr2h0 r 000784 h - 00078f h reserved - 000790 h can0 - new data 1 register low newdt1l0 newdt10 r 000791 h can0 - new data 1 register high newdt1h0 r 000792 h can0 - new data 2 register low newdt2l0 newdt20 r 000793 h can0 - new data 2 register high newdt2h0 r 000794 h - 00079f h reserved - 0007a0 h can0 - interrupt pending 1 register low intpnd1l0 intpnd10 r 0007a1 h can0 - interrupt pending 1 register high intpnd1h0 r 0007a2 h can0 - interrupt pending 2 register low intpnd2l0 intpnd20 r i/o map mb96(f)33x (33 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 56 of 122 MB96330 series 0007a3 h can0 - interrupt pending 2 register high intpnd2h0 r 0007a4 h - 0007af h reserved - 0007b0 h can0 - message valid 1 register low msgval1l0 msgval10 r 0007b1 h can0 - message valid 1 register high msgval1h0 r 0007b2 h can0 - message valid 2 register low msgval2l0 msgval20 r 0007b3 h can0 - message valid 2 register high msgval2h0 r 0007b4 h - 0007cd h reserved - 0007ce h can0 - output enable register coer0 r/w 0007cf h - 0007ff h reserved - 000800 h can1 - control register low ctrlrl1 ctrlr1 r/w 000801 h can1 - control register high (reserved) ctrlrh1 r 000802 h can1 - status register low statrl1 statr1 r/w 000803 h can1 - status register high (reserved) statrh1 r 000804 h can1 - error counter low (transmit) errcntl1 errcnt1 r 000805 h can1 - error counter high (receive) errcnth1 r 000806 h can1 - bit timing register low btrl1 btr1 r/w 000807 h can1 - bit timing register high btrh1 r/w 000808 h can1 - interrupt register low intrl1 intr1 r 000809 h can1 - interrupt register high intrh1 r 00080a h can1 - test register low testrl1 testr1 r/w 00080b h can1 - test register high (reserved) testrh1 r 00080c h can1 - brp extension regi ster low brperl1 brper1 r/w 00080d h can1 - brp extension regi ster high (reserved) brperh1 r 00080e h - 00080f h reserved - 000810 h can1 - if1 command request register low if1creql1 if1creq1 r/w 000811 h can1 - if1 command request register high if1creqh1 r/w 000812 h can1 - if1 command mask register low if1cmskl1 if1cmsk1 r/w 000813 h can1 - if1 command mask register high (reserved) if1cmskh1 r i/o map mb96(f)33x (34 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 57 of 122 MB96330 series 000814 h can1 - if1 mask 1 register low if1msk1l1 if1msk11 r/w 000815 h can1 - if1 mask 1 register high if1msk1h1 r/w 000816 h can1 - if1 mask 2 register low if1msk2l1 if1msk21 r/w 000817 h can1 - if1 mask 2 register high if1msk2h1 r/w 000818 h can1 - if1 arbitration 1 register low if1arb1l1 if1arb11 r/w 000819 h can1 - if1 arbitration 1 register high if1arb1h1 r/w 00081a h can1 - if1 arbitration 2 register low if1arb2l1 if1arb21 r/w 00081b h can1 - if1 arbitration 2 register high if1arb2h1 r/w 00081c h can1 - if1 message control register low if1mctrl1 if1mctr1 r/w 00081d h can1 - if1 message control register high if1mctrh1 r/w 00081e h can1 - if1 data a1 low if1dta1l1 if1dta11 r/w 00081f h can1 - if1 data a1 high if1dta1h1 r/w 000820 h can1 - if1 data a2 low if1dta2l1 if1dta21 r/w 000821 h can1 - if1 data a2 high if1dta2h1 r/w 000822 h can1 - if1 data b1 low if1dtb1l1 if1dtb11 r/w 000823 h can1 - if1 data b1 high if1dtb1h1 r/w 000824 h can1 - if1 data b2 low if1dtb2l1 if1dtb21 r/w 000825 h can1 - if1 data b2 high if1dtb2h1 r/w 000826 h - 00083f h reserved - 000840 h can1 - if2 command request register low if2creql1 if2creq1 r/w 000841 h can1 - if2 command request register high if2creqh1 r/w 000842 h can1 - if2 command mask register low if2cmskl1 if2cmsk1 r/w 000843 h can1 - if2 command mask register high (reserved) if2cmskh1 r 000844 h can1 - if2 mask 1 register low if2msk1l1 if2msk11 r/w 000845 h can1 - if2 mask 1 register high if2msk1h1 r/w 000846 h can1 - if2 mask 2 register low if2msk2l1 if2msk21 r/w 000847 h can1 - if2 mask 2 register high if2msk2h1 r/w 000848 h can1 - if2 arbitration 1 register low if2arb1l1 if2arb11 r/w 000849 h can1 - if2 arbitration 1 register high if2arb1h1 r/w 00084a h can1 - if2 arbitration 2 register low if2arb2l1 if2arb21 r/w i/o map mb96(f)33x (35 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 58 of 122 MB96330 series 00084b h can1 - if2 arbitration 2 register high if2arb2h1 r/w 00084c h can1 - if2 message control register low if2mctrl1 if2mctr1 r/w 00084d h can1 - if2 message control register high if2mctrh1 r/w 00084e h can1 - if2 data a1 low if2dta1l1 if2dta11 r/w 00084f h can1 - if2 data a1 high if2dta1h1 r/w 000850 h can1 - if2 data a2 low if2dta2l1 if2dta21 r/w 000851 h can1 - if2 data a2 high if2dta2h1 r/w 000852 h can1 - if2 data b1 low if2dtb1l1 if2dtb11 r/w 000853 h can1 - if2 data b1 high if2dtb1h1 r/w 000854 h can1 - if2 data b2 low if2dtb2l1 if2dtb21 r/w 000855 h can1 - if2 data b2 high if2dtb2h1 r/w 000856 h - 00087f h reserved - 000880 h can1 - transmission request 1 register low treqr1l1 treqr11 r 000881 h can1 - transmission request 1 register high treqr1h1 r 000882 h can1 - transmission request 2 register low treqr2l1 treqr21 r 000883 h can1 - transmission request 2 register high treqr2h1 r 000884 h - 00088f h reserved - 000890 h can1 - new data 1 register low newdt1l1 newdt11 r 000891 h can1 - new data 1 register high newdt1h1 r 000892 h can1 - new data 2 register low newdt2l1 newdt21 r 000893 h can1 - new data 2 register high newdt2h1 r 000894 h - 00089f h reserved - 0008a0 h can1 - interrupt pending 1 register low intpnd1l1 intpnd11 r 0008a1 h can1 - interrupt pending 1 register high intpnd1h1 r 0008a2 h can1 - interrupt pending 2 register low intpnd2l1 intpnd21 r 0008a3 h can1 - interrupt pending 2 register high intpnd2h1 r 0008a4 h - 0008af h reserved - 0008b0 h can1 - message valid 1 register low msgval1l1 msgval11 r i/o map mb96(f)33x (36 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 59 of 122 MB96330 series 0008b1 h can1 - message valid 1 register high msgval1h1 r 0008b2 h can1 - message valid 2 register low msgval2l1 msgval21 r 0008b3 h can1 - message valid 2 register high msgval2h1 r 0008b4 h - 0008cd h reserved - 0008ce h can1 - output enable register coer1 r/w 0008cf h - 0008ff h reserved - 000900 h can2 - control register low ctrlrl2 ctrlr2 r/w 000901 h can2 - control register high (reserved) ctrlrh2 r 000902 h can2 - status register low statrl2 statr2 r/w 000903 h can2 - status register high (reserved) statrh2 r 000904 h can2 - error counter low (transmit) errcntl2 errcnt2 r 000905 h can2 - error counter high (receive) errcnth2 r 000906 h can2 - bit timing register low btrl2 btr2 r/w 000907 h can2 - bit timing register high btrh2 r/w 000908 h can2 - interrupt register low intrl2 intr2 r 000909 h can2 - interrupt register high intrh2 r 00090a h can2 - test register low testrl2 testr2 r/w 00090b h can2 - test register high (reserved) testrh2 r 00090c h can2 - brp extension regi ster low brperl2 brper2 r/w 00090d h can2 - brp extension regi ster high (reserved) brperh2 r 00090e h - 00090f h reserved - 000910 h can2 - if1 command request register low if1creql2 if1creq2 r/w 000911 h can2 - if1 command request register high if1creqh2 r/w 000912 h can2 - if1 command mask register low if1cmskl2 if1cmsk2 r/w 000913 h can2 - if1 command mask register high (reserved) if1cmskh2 r 000914 h can2 - if1 mask 1 register low if1msk1l2 if1msk12 r/w 000915 h can2 - if1 mask 1 register high if1msk1h2 r/w 000916 h can2 - if1 mask 2 register low if1msk2l2 if1msk22 r/w 000917 h can2 - if1 mask 2 register high if1msk2h2 r/w i/o map mb96(f)33x (37 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 60 of 122 MB96330 series 000918 h can2 - if1 arbitration 1 register low if1arb1l2 if1arb12 r/w 000919 h can2 - if1 arbitration 1 register high if1arb1h2 r/w 00091a h can2 - if1 arbitration 2 register low if1arb2l2 if1arb22 r/w 00091b h can2 - if1 arbitration 2 register high if1arb2h2 r/w 00091c h can2 - if1 message control register low if1mctrl2 if1mctr2 r/w 00091d h can2 - if1 message control register high if1mctrh2 r/w 00091e h can2 - if1 data a1 low if1dta1l2 if1dta12 r/w 00091f h can2 - if1 data a1 high if1dta1h2 r/w 000920 h can2 - if1 data a2 low if1dta2l2 if1dta22 r/w 000921 h can2 - if1 data a2 high if1dta2h2 r/w 000922 h can2 - if1 data b1 low if1dtb1l2 if1dtb12 r/w 000923 h can2 - if1 data b1 high if1dtb1h2 r/w 000924 h can2 - if1 data b2 low if1dtb2l2 if1dtb22 r/w 000925 h can2 - if1 data b2 high if1dtb2h2 r/w 000926 h - 00093f h reserved - 000940 h can2 - if2 command request register low if2creql2 if2creq2 r/w 000941 h can2 - if2 command request register high if2creqh2 r/w 000942 h can2 - if2 command mask register low if2cmskl2 if2cmsk2 r/w 000943 h can2 - if2 command mask register high (reserved) if2cmskh2 r 000944 h can2 - if2 mask 1 register low if2msk1l2 if2msk12 r/w 000945 h can2 - if2 mask 1 register high if2msk1h2 r/w 000946 h can2 - if2 mask 2 register low if2msk2l2 if2msk22 r/w 000947 h can2 - if2 mask 2 register high if2msk2h2 r/w 000948 h can2 - if2 arbitration 1 register low if2arb1l2 if2arb12 r/w 000949 h can2 - if2 arbitration 1 register high if2arb1h2 r/w 00094a h can2 - if2 arbitration 2 register low if2arb2l2 if2arb22 r/w 00094b h can2 - if2 arbitration 2 register high if2arb2h2 r/w 00094c h can2 - if2 message control register low if2mctrl2 if2mctr2 r/w 00094d h can2 - if2 message control register high if2mctrh2 r/w 00094e h can2 - if2 data a1 low if2dta1l2 if2dta12 r/w i/o map mb96(f)33x (38 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 61 of 122 MB96330 series 00094f h can2 - if2 data a1 high if2dta1h2 r/w 000950 h can2 - if2 data a2 low if2dta2l2 if2dta22 r/w 000951 h can2 - if2 data a2 high if2dta2h2 r/w 000952 h can2 - if2 data b1 low if2dtb1l2 if2dtb12 r/w 000953 h can2 - if2 data b1 high if2dtb1h2 r/w 000954 h can2 - if2 data b2 low if2dtb2l2 if2dtb22 r/w 000955 h can2 - if2 data b2 high if2dtb2h2 r/w 000956 h - 00097f h reserved - 000980 h can2 - transmission request 1 register low treqr1l2 treqr12 r 000981 h can2 - transmission request 1 register high treqr1h2 r 000982 h can2 - transmission request 2 register low treqr2l2 treqr22 r 000983 h can2 - transmission request 2 register high treqr2h2 r 000984 h - 00098f h reserved - 000990 h can2 - new data 1 register low newdt1l2 newdt12 r 000991 h can2 - new data 1 register high newdt1h2 r 000992 h can2 - new data 2 register low newdt2l2 newdt22 r 000993 h can2 - new data 2 register high newdt2h2 r 000994 h - 00099f h reserved - 0009a0 h can2 - interrupt pending 1 register low intpnd1l2 intpnd12 r 0009a1 h can2 - interrupt pending 1 register high intpnd1h2 r 0009a2 h can2 - interrupt pending 2 register low intpnd2l2 intpnd22 r 0009a3 h can2 - interrupt pending 2 register high intpnd2h2 r 0009a4 h - 0009af h reserved - 0009b0 h can2 - message valid 1 register low msgval1l2 msgval12 r 0009b1 h can2 - message valid 1 register high msgval1h2 r 0009b2 h can2 - message valid 2 register low msgval2l2 msgval22 r 0009b3 h can2 - message valid 2 register high msgval2h2 r i/o map mb96(f)33x (39 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 62 of 122 MB96330 series note: any write access to rese rved addresses in the i/o map should not be perfor med. a read access to a reserved address resu lts in reading ?x?. registers of resources which are described in this table, but wh ich are not supported by the device, should also be handled as ?reserved?. 0009b4 h - 0009cd h reserved - 0009ce h can2 - output enable register coer2 r/w 0009cf h - 000bff h reserved - i/o map mb96(f)33x (40 of 40) address register abbreviation 8-bit access abbreviation 16-bit access access
document number: 002-04586 rev. *a page 63 of 122 MB96330 series 12. interrupt vector table interrupt vector table mb96(f)33x (1 of 5) vector number offset in vector table vector name cleared by dma index in icr to program description 03fc h callv0 no - 13f8 h callv1 no - 23f4 h callv2 no - 33f0 h callv3 no - 43ec h callv4 no - 53e8 h callv5 no - 63e4 h callv6 no - 73e0 h callv7 no - 83dc h reset no - 93d8 h int9 no - 10 3d4 h exception no - 11 3d0 h nmi no - non-maskable interrupt 12 3cc h dly no 12 delayed interrupt 13 3c8 h rc_timer no 13 rc timer 14 3c4 h mc_timer no 14 main clock timer 15 3c0 h sc_timer no 15 sub clock timer 16 3bc h pll_unlock no 16 reserved 17 3b8 h extint0 yes 17 external interrupt 0 18 3b4 h extint1 yes 18 external interrupt 1 19 3b0 h extint2 yes 19 external interrupt 2 20 3ac h extint3 yes 20 external interrupt 3 21 3a8 h extint4 yes 21 external interrupt 4 22 3a4 h extint5 yes 22 external interrupt 5 23 3a0 h extint6 yes 23 external interrupt 6 24 39c h extint7 yes 24 external interrupt 7 25 398 h extint8 yes 25 external interrupt 8 26 394 h extint9 yes 26 external interrupt 9
document number: 002-04586 rev. *a page 64 of 122 MB96330 series 27 390 h extint10 yes 27 external interrupt 10 28 38c h extint11 yes 28 external interrupt 11 29 388 h extint12 yes 29 external interrupt 12 30 384 h extint13 yes 30 external interrupt 13 31 380 h extint14 yes 31 external interrupt 14 32 37c h extint15 yes 32 external interrupt 15 33 378 h can0 no 33 can controller 0 34 374 h can1 no 34 can controller 1 35 370 h can2 no 35 can controller 2 36 36c h ppg0 yes 36 programmable pulse generator 0 37 368 h ppg1 yes 37 programmable pulse generator 1 38 364 h ppg2 yes 38 programmable pulse generator 2 39 360 h ppg3 yes 39 programmable pulse generator 3 40 35c h ppg4 yes 40 programmable pulse generator 4 41 358 h ppg5 yes 41 programmable pulse generator 5 42 354 h ppg6 yes 42 programmable pulse generator 6 43 350 h ppg7 yes 43 programmable pulse generator 7 44 34c h ppg8 yes 44 programmable pulse generator 8 45 348 h ppg9 yes 45 programmable pulse generator 9 46 344 h ppg10 yes 46 programmable pulse generator 10 47 340 h ppg11 yes 47 programmable pulse generator 11 48 33c h ppg12 yes 48 programmable pulse generator 12 49 338 h ppg13 yes 49 programmable pulse generator 13 50 334 h ppg14 yes 50 programmable pulse generator 14 51 330 h ppg15 yes 51 programmable pulse generator 15 52 32c h ppg16 yes 52 programmable pulse generator 16 53 328 h ppg17 yes 53 programmable pulse generator 17 interrupt vector table mb96(f)33x (2 of 5) vector number offset in vector table vector name cleared by dma index in icr to program description
document number: 002-04586 rev. *a page 65 of 122 MB96330 series 54 324 h ppg18 yes 54 programmable pulse generator 18 55 320 h ppg19 yes 55 programmable pulse generator 19 56 31c h rlt0 yes 56 reload timer 0 57 318 h rlt1 yes 57 reload timer 1 58 314 h rlt2 yes 58 reload timer 2 59 310 h rlt3 yes 59 reload timer 3 60 30c h ppgrlt yes 60 reload timer 6 - dedicated for ppg 61 308 h icu0 yes 61 input capture unit 0 62 304 h icu1 yes 62 input capture unit 1 63 300 h icu2 yes 63 input capture unit 2 64 2fc h icu3 yes 64 input capture unit 3 65 2f8 h icu4 yes 65 input capture unit 4 66 2f4 h icu5 yes 66 input capture unit 5 67 2f0 h icu6 yes 67 input capture unit 6 68 2ec h icu7 yes 68 input capture unit 7 69 2e8 h icu8 yes 69 input capture unit 8 70 2e4 h icu9 yes 70 input capture unit 9 71 2e0 h ocu0 yes 71 output compare unit 0 72 2dc h ocu1 yes 72 output compare unit 1 73 2d8 h ocu2 yes 73 output compare unit 2 74 2d4 h ocu3 yes 74 output compare unit 3 75 2d0 h ocu4 yes 75 output compare unit 4 76 2cc h ocu5 yes 76 output compare unit 5 77 2c8 h ocu6 yes 77 output compare unit 6 78 2c4 h ocu7 yes 78 output compare unit 7 79 2c0 h ocu8 yes 79 output compare unit 8 80 2bc h ocu9 yes 80 output compare unit 9 interrupt vector table mb96(f)33x (3 of 5) vector number offset in vector table vector name cleared by dma index in icr to program description
document number: 002-04586 rev. *a page 66 of 122 MB96330 series 81 2b8 h ocu10 yes 81 output compare unit 10 82 2b4 h ocu11 yes 82 output compare unit 11 83 2b0 h frt0 yes 83 free running timer 0 84 2ac h frt1 yes 84 free running timer 1 85 2a8 h frt2 yes 85 free running timer 2 86 2a4 h frt3 yes 86 free running timer 3 87 2a0 h rtc0 no 87 real timer clock 88 29c h cal0 no 88 clock calibration unit 89 298 h iic0 yes 89 i 2 c interface 90 294 h iic1 yes 90 i 2 c interface 91 290 h adc0 yes 91 a/d converter 92 28c h alarm0 no 92 alarm comparator 0 93 288 h alarm1 no 93 alarm comparator 1 94 284 h linr0 yes 94 lin usart 0 rx 95 280 h lint0 yes 95 lin usart 0 tx 96 27c h linr1 yes 96 lin usart 1 rx 97 278 h lint1 yes 97 lin usart 1 tx 98 274 h linr2 yes 98 lin usart 2 rx 99 270 h lint2 yes 99 lin usart 2 tx 100 26c h linr3 yes 100 lin usart 3 rx 101 268 h lint3 yes 101 lin usart 3 tx 102 264 h linr5 yes 102 lin usart 5 rx 103 260 h lint5 yes 103 lin usart 5 tx 104 25c h linr7 yes 104 lin usart 7 rx 105 258 h lint7 yes 105 lin usart 7 tx 106 254 h linr8 yes 106 lin usart 8 rx 107 250 h lint8 yes 107 lin usart 8 tx interrupt vector table mb96(f)33x (4 of 5) vector number offset in vector table vector name cleared by dma index in icr to program description
document number: 002-04586 rev. *a page 67 of 122 MB96330 series 108 24c h linr9 yes 108 lin usart 9 rx 109 248 h lint9 yes 109 lin usart 9 tx 110 244 h flash_a no 110 main flash memory interrupt (only flash devices) 111 240 h reserved - - reserved 112 23c h usb_ep0in0 yes 112 usb end point 0 in 113 238 h usb_ep0out0 yes 113 usb end point 0 out 114 234 h usb_ep10 yes 114 usb end point 1 115 230 h usb_ep20 yes 115 usb end point 2 116 22c h usb_ep30 yes 116 usb end point 3 117 228 h usb_ep40 yes 117 usb end point 4 118 224 h usb_ep50 yes 118 usb end point 5 119 220 h usb_f10 no 119 usb function flags 1 (susp sof brst wkup conf) 120 21c h usb_f20 no 120 usb function flags 2 (spk) 121 218 h usb_h10 no 121 usb minihost 1 (dirq cnnirq urirq rwkirq) 122 214 h usb_h20 no 122 usb minihost 2 (sofirq cmpirq) interrupt vector table mb96(f)33x (5 of 5) vector number offset in vector table vector name cleared by dma index in icr to program description
document number: 002-04586 rev. *a page 68 of 122 MB96330 series 13. handling devices special care is required for the following when handling the device: ? latch-up prevention ? unused pins handling ? external clock usage ? unused sub clock signal ? notes on pll clock mode operation ? power supply pins (v cc /v ss ) ? crystal oscillator circuit ? turn on sequence of power supply to a/d converter and analog inputs ? pin handling when not using the a/d converter ? notes on energization ? stabilization of power supply voltage 13.1 latch-up prevention cmos ic chips may suffer latch-up under the following conditions: ? a voltage higher than v cc or lower than v ss is applied to an input or output pin. ? a voltage higher than the rated voltage is applied between v cc pins and v ss pins. ?the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current dramat ically, causing thermal damages to the device. for the same reason, extra care is required to not let the analog power-supply voltage (av cc , avrh) exceed the digital power-supply voltage. 13.2 unused pins handling unused input pins can be left open when the input is disabled (corresponding bit of port inpu t enable register pier = 0). leaving unused input pins open when the input is enabled may resu lt in misbehavior and possible permanent damage of the device. they must therefore be pulled up or pulled down through resistors. to prevent latch-up, those resistors should be more than 2 k ? . unused bidirectional pins can be set either to the output state and be then left open, or to t he input state with either input disabled or external pull-up/pull-down resistor as described above. 13.3 external clock usage the permitted frequency range of an external clock depends on the oscillator type and configuration. see ac characteristics for detailed modes and frequency limits. single and opposite phas e external clocks must be connected as follows: 1. single phase external clock ? when using a single phase external clock, x0 pin must be driven and x1 pin left open. x0 x1
document number: 002-04586 rev. *a page 69 of 122 MB96330 series 2. opposite phase external clock ? when using an opposite phase external clock, x1 (x1a) must be supplied with a clock signal which has the opposite phase to the x0 (x0a) pins. 13.4 unused sub clock signal if the pins x0a and x1a are not connected to an oscillator, a pull- down resistor must be connected on the x0a pin and the x1a p in must be left open. 13.5 notes on pll clock mode operation if the pll clock mode is selected and no exter nal oscillator is operating or no exter nal clock is supplied, the microcontroller attempts to work with the free oscillating pll. performanc e of this operation, however, cannot be guaranteed. 13.6 power supply pins (v cc /v ss ) it is required that all v cc -level as well as all v ss -level power supply pins are at the same potential. if there is more than one v cc or v ss level, the device may operate incorrectly or be damaged even within the guaranteed operating range. v cc and v ss must be connected to the device from the power supply with lowest possible impedance. as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 ? f between v cc and v ss as close as possible to v cc and v ss pins. 13.7 crystal oscillator and ceramic resonator circuit noise at x0, x1 pins or x0a, x1a pins might cause abnormal oper ation. it is required to provide bypass capacitors with shortest possible distance to x0, x1 pins and x0a, x1a pins, crystal o scillator (or ceramic resonator) and ground lines, and, to the utm ost effort, that the lines of oscillation circui t do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art wo rk surrounding x0, x1 pins and x0a, x1a pins with a ground ar ea for stabilizing the operation. it is highly recommended to evalua te the quartz/mcu or re sonator/mcu system at the quartz or resonator manufacturer, especially when using low-q resonator s at higher frequencies. 13.8 turn on sequence of power supply to a/d converter and analog inputs it is required to turn the a/d converter power supply (av cc , avrh, avrl) and analog inputs (ann) on after turning the digital power supply (v cc ) on. it is also required to turn the digital power off after turnin g the a/d converter supply and analog inputs off. in this case, t he voltage must not exceed avrh or av cc (turning the analog and digital power supplies simultaneously on or off is acceptable). 13.9 pin handling when not using the a/d converter it is required to connect the unused pins of the a/d converter as av cc = v cc , av ss = avrh = avrl = v ss . 13.10 notes on power-on to prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be sl ower than 50 ? s from 0.2 v to 2.7 v. x0 x1
document number: 002-04586 rev. *a page 70 of 122 MB96330 series 13.11 stabilization of power supply voltage if the power supply voltage varies acutely even within the operat ion safety range of the vcc power supply voltage, a malfunctio n may occur. the vcc power supply voltage must therefore be stabiliz ed. as stabilization guidelines, the power supply voltage must be stabilized in such a way that vcc ripple fluc tuations (peak to peak value) in the co mmercial frequencies (50 to 60 hz) fall wit hin 10% of the standard vcc power supply voltage and the transient fluctuation rate becomes 0.1v/ ? s or less in instantaneous fluctuation for power supply switching. 13.12 serial communication there is a possibility to receive wrong data due to noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider receiving of wrong data when designing the system. for example apply a checksum and retransmit the data if an error occurs.
document number: 002-04586 rev. *a page 71 of 122 MB96330 series 14. electrical characteristics 14.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc = av cc *1 usb power supply voltage v cc3 v ss - 0.3 v ss + 4.0 v usb device only ad converter voltage references avrh, avrl v ss - 0.3 v ss + 6.0 v av cc ?? avrh, av cc ?? avrl, avrh ? ?? avrl, avrl ?? av ss input voltage v i v ss - 0.3 v ss + 6.0 v v i ?? v cc + 0.3v *2 usb input voltage v iusb v ss - 0.5 v ss + 4.0 v v iusb ?? v cc3 + 0.5 (usb pins udp, udm) output voltage v o v ss - 0.3 v ss + 6.0 v v o ?? v cc + 0.3v *2 usb output voltage v ousb v ss - 0.5 v ss + 4.0 v v ousb ?? v cc3 + 0.5 (usb pins udp, udm) maximum clamp current i clamp -4.0 +4.0 ma applicable to general purpose i/o pins *3 total maximum clamp current ? |i clamp | -40ma applicable to general purpose i/o pins *3 ?l? level maximum output current i ol1 - 15 ma normal outputs with driving strength set to 5ma i olusb - 36 ma usb pins udp, udm ?l? level average output current i olav1 - 5 ma normal outputs with driving strength set to 5ma i olavusb - 15 ma usb pins udp, udm ?l? level maximum overall output current ? i ol1 - 100 ma normal outputs ?l? level average overall output current ? i olav1 - 50 ma normal outputs ?h? level maximum output current i oh1 - -15 ma normal outputs with driving strength set to 5ma i ohusb - -36 ma usb pins udp, udm ?h? level average output current i ohav1 - -5 ma normal outputs with driving strength set to 5ma i ohavusb - -15 ma usb pins udp, udm ?h? level maximum overall output current ? i oh1 - -100 ma normal outputs ?h? level average overall output current ? i ohav1 - -50 ma normal outputs
document number: 002-04586 rev. *a page 72 of 122 MB96330 series *1: av cc and v cc must be set to the same voltage. it is required that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc neither when the power is switched on. *2: v i and v o should not exceed v cc + 0.3 v. v i should also not exceed the specified ratings. however if the maximum current to/from a input is limited by some means with external components, the i clamp rating supersedes the v i rating. input/output voltages of standard ports depend on v cc. * 3: ? applicable to all general purpose i/o pins (pnn_m) ? use within recommended operating conditions. ? use at dc voltage (current) ? the +b signal should always be applied a limiting resistance placed between the +b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the microcontrol ler pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potentia l at the vcc pin, and this may affect other devices. ? note that if a +b signal is input when the microcontroller power supply is off (not fixed at 0 v), the power supply is provide d from the pins, so that incomplete operation may result. ? note that if the +b input is applied during power-on, the power supply is provid ed from the pins and the resulting supply volt age may not be sufficient to operate the power reset (except devi ces with persistent low voltage re set in internal vector mode). ? sample recommended circuits : permitted power dissipat ion (flash devices) *4 p d - 370 *5 mw t a =105 o c - 740 *5 mw t a =85 o c - 460 *5 mw t a =125 o c, no flash program/erase, mb96(f)338y/r only *6 - 550 *5 mw t a =120 o c, no flash program/erase, mb96(f)338y/r only *6 operating ambient temperature t a 0+70 o c mb96v300b -40 +105 mb96(f)33x -40 +125 mb96(f)338y/r *6 storage temperature t stg -55 +150 o c parameter symbol rating unit remarks min max p-ch n-ch v cc r protective diode limiting resistance +b input (0v to 16v)
document number: 002-04586 rev. *a page 73 of 122 MB96330 series *4: the maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductanc e of the package on the pcb. the actual power dissipation depends on the customer application and can be calculated as follows: p d = p io + p int p io = ? (v ol * i ol + v oh * i oh ) (io load power dissipation, sum is performed on all io ports) p int = v cc * (i cc + i a ) (internal power dissipation) i cc is the total core current consumption into v cc as described in the ?dc characteristi cs? and depends on the selected operation mode and clock frequency and the usage of functi ons like flash programming or the clock modulator. i a is the analog current consumption into av cc . *5: worst case value for a package mounted on single layer pcb at specified t a without air flow. *6: please contact cypress for reliability limit ations when using under these conditions. warning: semiconductor devices can be permanently da maged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings.
document number: 002-04586 rev. *a page 74 of 122 MB96330 series 14.2 recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics ar e warranted when the device is operated within these ranges. always use semiconductor devi ces within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditi ons, or combinations not re presented on the data sheet. users considering application outside the listed condition s are advised to contact t heir cypress representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc 3.0 - 5.5 v usb power supply voltage v cc3 3.0 3.3 3.6 v usb device only smoothing capacitor at c pin c s 4.7 - 10 ? f use a low inductance capacitor (for example x7r ceramic capacitor)
document number: 002-04586 rev. *a page 75 of 122 MB96330 series 14.3 dc characteristics (t a = -40c to 125c, v cc = av cc = 3.0v to 5.5v, v cc3 = 3.0v to 3.6v, v ss = av ss = 0v) parameter symbol pin condition value unit remarks min typ max input h voltage v ih port inputs pnn_m cmos hysteresis 0.8/0.2 input selected 0.8 v cc - v cc + 0.3 v cmos hysteresis 0.7/0.3 input selected 0.7 v cc - v cc + 0.3 v v cc ?? 4.5v 0.74 v cc - v cc + 0.3 v v cc < 4.5v automotive hysteresis input selected 0.8 v cc - v cc + 0.3 v ttl input selected 2.0 - v cc + 0.3 v v ihusb udp, udm - 2.0 - v cc3 + 0.3 v usb pins v ihx0f x0 external clock in ?fast clock input mode? 0.8 v cc - v cc + 0.3 v v ihx0s x0,x1, x0a,x1a external clock in ?oscillation mode? 2.5 - v cc + 0.3 v v ihr rstx - 0.8 v cc - v cc + 0.3 v cmos hysteresis input v ihm md2-md0 - v cc - 0.3 - v cc + 0.3 v
document number: 002-04586 rev. *a page 76 of 122 MB96330 series input l voltage v il port inputs pnn_m cmos hysteresis 0.8/0.2 input selected v ss - 0.3 - 0.2 v cc v cmos hysteresis 0.7/0.3 input selected v ss - 0.3 - 0.3 v cc v automotive hysteresis input selected v ss - 0.3 - 0.5 v cc v v cc ?? 4.5v v ss - 0.3 - 0.46 v cc v cc < 4.5v ttl input selected v ss - 0.3 -0.8v v ilusb udp, udm - v ss - 0.3 - 0.8 v usb pins v ilx0f x0 external clock in ?fast clock input mode? v ss - 0.3 - 0.2 v cc v v ilx0s x0,x1, x0a,x1a external clock in ?oscillation mode? v ss - 0.3 -0.4v v ilr rstx - v ss - 0.3 - 0.2 v cc v cmos hysteresis input v ilm md2-md0 - v ss - 0.3 - v ss + 0.3 v output h voltage v oh2 normal out- puts 4.5v ?? v cc ? 5.5v i oh = -2ma v cc - 0.5 --v driving strength set to 2ma 3.0v ?? v cc ? 4.5v i oh = -1.6ma v oh5 normal out- puts 4.5v ?? v cc ? 5.5v i oh = -5ma v cc - 0.5 --v driving strength set to 5ma 3.0v ?? v cc ? 4.5v i oh = -3ma v oh3 3ma outputs 4.5v ?? v cc ? 5.5v i oh = -3ma v cc - 0.5 --v 3.0v ?? v cc ? 4.5v i oh = -2ma v ohusb udp, udm 3.0v ?? v cc3 ? 3.6v i oh = -20ma v cc3 - 0.4 - - v usb pins (t a = -40c to 125c, v cc = av cc = 3.0v to 5.5v, v cc3 = 3.0v to 3.6v, v ss = av ss = 0v) parameter symbol pin condition value unit remarks min typ max
document number: 002-04586 rev. *a page 77 of 122 MB96330 series output l voltage v ol2 normal outputs 4.5v ?? v cc ? 5.5v i ol = +2ma --0.4v driving strength set to 2ma 3.0v ?? v cc ? 4.5v i ol = +1.6ma v ol5 normal outputs 4.5v ?? v cc ? 5.5v i ol = +5ma --0.4v driving strength set to 5ma 3.0v ?? v cc ? 4.5v i ol = +3ma v ol3 3ma outputs 3.0v ?? v cc ? 5.5v i ol = +3ma --0.4v v olusb udp, udm 3.0v ?? v cc3 ? 3.6v i ol = +20ma - - 0.4 v usb pins input leak current i il pnn_m (except usb pins) v ss < v i < v cc av ss , avrl < v i < av cc , avrh -1 - +1 ? a single port pin usb input leak cur- rent udp, udm v ss < v i < v cc3 -5 - +5 ? a usb pins pull-up resistance r up pnn_m, rstx v cc ? 3.3v ? 10 ? 40 100 160 k ? v cc ? 5.0v ? 10 ? 25 50 100 k ? (t a = -40c to 125c, v cc = av cc = 3.0v to 5.5v, v cc3 = 3.0v to 3.6v, v ss = av ss = 0v) parameter symbol pin condition value unit remarks min typ max
document number: 002-04586 rev. *a page 78 of 122 MB96330 series (t a = -40c to 125c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v ) parameter symbol condition (at t a ) value remarks typ max unit power supply current in run modes* i ccpll pll run mode with clks1/2 = 48mhz, clkb = clkp1/2 = 24mhz, clkp3 = 48mhz +25c 39 47 ma clkrc and clksc stopped. core voltage at 1.9v 0 flash/rom wait states +125c 40 50 pll run mode with clks1/2 = clkb = clkp1/3 = 48mhz, clkp2 = 24mhz +25c 45 57 ma clkrc and clksc stopped. core voltage at 1.9v 2 flash/rom wait states +125c 46 60 pll run mode with clks1/2 = 96mhz, clkb = clkp1/3 = 48mhz, clkp2 = 24mhz +25c 56 68 ma clkrc and clksc stopped. core voltage at 1.9v 1 flash/rom wait state +125c 57 71 i ccmain main run mode with clks1/2 = clkb = clkp1/2/3 = 4mhz +25c 5 6 ma clkpll, clksc and clkrc stopped 1 flash/rom wait state +125c 5.6 9 i ccrch rc run mode with clks1/2 = clkb = clkp1/2/3 = 2mhz +25c 2.9 4 ma clkmc, clkpll and clksc stopped 1 flash/rom wait state +125c 3.5 6.5 i ccrcl rc run mode with clks1/2 = clkb = clkp1/2/3 = 100khz, smcr:lpms = 0 +25c 0.4 0.6 ma clkmc, clkpll and clksc stopped. voltage regulator in high power mode 1 flash/rom wait state +125c 0.9 3.5 rc run mode with clks1/2 = clkb = clkp1/2/3 = 100khz, smcr:lpms = 1 +25c 0.15 0.25 ma clkmc, clkpll and clksc stopped. voltage regulator in low power mode, no flash programming/erasing allowed. 1 flash/rom wait state +125c 0.65 3.2 i ccsub sub run mode with clks1/2 = clkb = clkp1/2/3 = 32khz +25c 0.1 0.2 ma clkmc, clkpll and clkrc stopped, no flash programming/erasing allowed. 1 flash/rom wait state +125c 0.6 3
document number: 002-04586 rev. *a page 79 of 122 MB96330 series power supply current in sleep modes* i ccspll pll sleep mode with clks1/2 = 48mhz, clkp1/2 = 24mhz clkp3 = 48mhz +25c 12.5 15 ma clkrc and clksc stopped. core voltage at 1.9v +125c 13.3 17.5 pll sleep mode with clks1/2 = clkp1/3 = 48mhz, clkp2 = 24mhz +25c 17 20 ma clkrc and clksc stopped. core voltage at 1.9v +125c 17.8 22.5 pll sleep mode with clks1/2 = 96mhz, clkp1/3 = 48mhz, clkp2 = 24mhz +25c 19 22 ma clkrc and clksc stopped. core voltage at 1.9v +125c 19.8 24.5 i ccsmain main sleep mode with clks1/2 = clkp1/2/3 = 4mhz +25c 1.9 2.3 ma clkpll, clksc and clkrc stopped +125c 2.4 5 i ccsrch rc sleep mode with clks1/2 = clkp1/2/3 = 2mhz +25c 0.9 1.4 ma clkmc, clkpll and clksc stopped +125c 1.5 4.1 i ccsrcl rc sleep mode with clks1/2 = clkp1/2/3 = 100khz, smcr:lpmss = 0 +25c 0.3 0.5 ma clkmc, clkpll and clksc stopped. voltage regulator in high power mode +125c 0.8 3.4 rc sleep mode with clks1/2 = clkp1/2/3 = 100khz, smcr:lpmss = 1 +25c 0.06 0.15 ma clkmc, clkpll and clksc stopped. voltage regulator in low power mode +125c 0.56 3 i ccssub sub sleep mode with clks1/2 = clkp1/2/3 = 32khz +25c 0.04 0.12 ma clkmc, clkpll and clkrc stopped +125c 0.54 2.9 (t a = -40c to 125c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v ) parameter symbol condition (at t a ) value remarks typ max unit
document number: 002-04586 rev. *a page 80 of 122 MB96330 series power supply current in timer modes* i cctpll pll timer mode with clkmc = 4mhz, clkpll = 48mhz +25c 1.6 2 ma clkrc and clksc stopped. core voltage at 1.9v +125c 2.1 4.8 i cctmain main timer mode with clkmc = 4mhz, smcr:lpmss = 0 +25c 0.35 0.5 ma clkpll, clkrc and clksc stopped. voltage regulator in high power mode +125c 0.85 3.3 main timer mode with clkmc = 4mhz, smcr:lpmss = 1 +25c 0.1 0.15 ma clkpll, clkrc and clksc stopped. voltage regulator in low power mode +125c 0.6 2.9 i cctrch rc timer mode with clkrc = 2mhz, smcr:lpmss = 0 +25c 0.35 0.5 ma clkmc, clkpll and clksc stopped. voltage regulator in high power mode +125c 0.85 3.3 rc timer mode with clkrc = 2mhz, smcr:lpmss = 1 +25c 0.1 0.15 ma clkmc, clkpll and clksc stopped. voltage regulator in low power mode +125c 0.6 2.9 i cctrcl rc timer mode with clkrc = 100khz, smcr:lpmss = 0 +25c 0.3 0.45 ma clkmc, clkpll and clksc stopped. voltage regulator in high power mode +125c 0.8 3.2 rc timer mode with clkrc = 100khz, smcr:lpmss = 1 +25c 0.05 0.1 ma clkmc, clkpll and clksc stopped. voltage regulator in low power mode +125c 0.55 2.8 i cctsub sub timer mode with clksc = 32khz +25c 0.03 0.1 ma clkmc, clkpll and clkrc stopped +125c 0.53 2.8 (t a = -40c to 125c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v ) parameter symbol condition (at t a ) value remarks typ max unit
document number: 002-04586 rev. *a page 81 of 122 MB96330 series stop mode i cch vrcr:lpmb[2:0] = 110 b +25c 0.02 0.08 ma core voltage at 1.8v +125c 0.52 2.8 vrcr:lpmb[2:0] = 000 b +25c 0.015 0.06 ma core voltage at 1.2v +125c 0.4 2.3 power supply current for active low voltage detector i cclvd low voltage detector en- abled (rcr:lvde = 1) +25c 90 140 ? a this current must be added to all power supply currents above +125c 100 150 clock modulator current i ccclomo clock modulator enabled (cmcr:pdx = 1) -34.5ma must be added to all current above flash write/erase cur- rent i ccflash current for one flash mod- ule -1540ma must be added to all current above input capaci- tance c in --515pf other than c, av cc , av ss , avrh, avrl, v cc , v ss *: the power supply current is measured with a 4mhz external cl ock connected to the main oscillator and a 32khz external clock connected to the sub oscillator. see chapter ?standby mode and voltage regulator control circuit? of the hardware manual for further details about voltage regulator control. (t a = -40c to 125c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v ) parameter symbol condition (at t a ) value remarks typ max unit
document number: 002-04586 rev. *a page 82 of 122 MB96330 series 14.4 ac characteristics source clock timing (t a = -40c to 125c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3 - 16 mhz when using a crystal oscillator, pll off 0-16mhz when using an opposite phase external clock, pll off 3.5 - 16 mhz when using a crystal oscillator or opposite phase external clock, pll on clock frequency f fci x0 0-56mhz when using a single phase external clock in ?fast clock input mode?, pll off 3.5 - 56 mhz when using a single phase external clock in ?fast clock input mode?. pll on clock frequency f cl x0a, x1a 32 32.768 100 khz when using an oscillation circuit 0 - 100 khz when using an opposite phase external clock x0a 0 - 50 khz when using a single phase external clock clock frequency f cr - 50 100 200 khz when using slow frequency of rc oscillator 1 2 4 mhz when using fast frequency of rc oscillator pll clock frequency f clkvco - 64 - 200 mhz permitted vco output frequency of pll (clkvco) pll phase jitter t pskew --- ? 5 ns for clkmc (pll input clock) ??? mhz input clock pulse width p wh , p wl x0,x1 8 - - ns duty ratio is about 30% to 70% input clock pulse width p whl , p wll x0a,x1a 5 - - ? s x0 t cyl p wh p wl v il v ih x0a t cyll p whl p wll v il v ih
document number: 002-04586 rev. *a page 83 of 122 MB96330 series internal clock timing (t a = -40c to 125c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol core voltage settings unit remarks 1.8v 1.9v min max min max internal system clock frequency (clks1 and clks2) f clks1 , f clks2 0 92 0 96 mhz others than below 0 90 0 96 mhz mb96f33x internal cpu clock frequency (clkb), internal peripheral clock frequency (clkp1) f clkb , f clkp1 0 52 0 56 mhz others than below 0 43.5 0 48 mhz mb96f33x internal peripheral clock frequency (clkp2) f clkp2 028032mhz internal peripheral clock frequency (clock clkp3) f clkp3 0 43.5 0 48 mhz mb96f33x warning: for usb usage, it is important to change the voltage regulator setting to output 1.9v. please refer to the chapter standby mode and voltage regulator control circuit of the hardware manual to perform such setting.
document number: 002-04586 rev. *a page 84 of 122 MB96330 series external reset timing (t a = -40c to 125c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max reset input time t rstl rstx 500 - - ns 0.2 v cc rstx t rstl 0.2 v cc
document number: 002-04586 rev. *a page 85 of 122 MB96330 series power on reset timing (t a = -40c to 125c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max power on rise time t r vcc 0.05 - 30 ms power off time t off vcc 1 - - ms 0.2 v t r 2.7v t off 0.2 v 0.2 v if the power supply is changed too rapidly, a power-on reset may occur. we recommend a smooth startup by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. 3 v v cc v cc rising edge of 50 mv/ms maximum is allowed
document number: 002-04586 rev. *a page 86 of 122 MB96330 series external input timing note : relocated resource input s have same characteristics (t a = -40c to 125c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin condition value unit used pin input function min max input pulse width t inh t inl intn(_r) ? 200 ? ns external interrupt nmi(_r) nmi pnn_m 2*t clkp1 + 200 (t clkp1 =1/f clkp1 ) ?ns general purpose io tinn(_r) reload timer ttgn(_r) ppg trigger input adtg(_r) ad converter trigger frckn(_r) free running timer external clock inn(_r) input capture v il v ih t inh v il v ih t inl external pin input
document number: 002-04586 rev. *a page 87 of 122 MB96330 series external bus timing note: the values given below are for an i/o driving strength io drive = 5ma. if io drive is 2ma, all the maximum output timing described in the different tables must then be increased by 10ns. basic timing (t a ? ? 40c to ? 125c, v cc ? 5.0 v ? 10 ? , v ss ? 0.0 v, io drive = 5ma, c l = 50pf ) parameter symbol pin condition value unit remarks min max eclk t cyc eclk ? 25 ? ns t chcl t cyc /2-5 t cyc /2+5 t clch t cyc /2-5 t cyc /2+5 eclk ? ubx/ lbx / csn time t chcbh csn, ubx, lbx, eclk ? -20 20 ns t chcbl -20 20 t clcbh -20 20 t clcbl -20 20 eclk ale time t chlh ale, eclk ? -10 10 ns t chll -10 10 t cllh -10 10 t clll -10 10 eclk ? address valid time (non-multiplexed) t chav a[23:0], eclk ebm:nms=1 -15 15 ns t clav -15 15 eclk ? address valid time (multiplexed) t chav a[23:16], eclk ebm:nms=0 -15 15 ns t clav -15 15 t cladv ad[15:0], eclk ebm:nms=0 -15 15 ns t chadv -15 15 eclk rdx /wrx time t chrwh rdx, wrx, wrlx,wrhx, eclk ? -10 10 ns t chrwl -10 10 t clrwh -10 10 t clrwl -10 10
document number: 002-04586 rev. *a page 88 of 122 MB96330 series (t a ? ? 40c to ? 125c, v cc ? 3.0 to 4.5v, v ss ? 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin condition value unit remarks min max eclk t cyc eclk ? 30 ? ns t chcl t cyc /2-8 t cyc /2+8 t clch t cyc /2-8 t cyc /2+8 eclk ? ubx/ lbx / csn time t chcbh csn, ubx, lbx, eclk ? -25 25 ns t chcbl -25 25 t clcbh -25 25 t clcbl -25 25 eclk ale time t chlh ale, eclk ? -15 15 ns t chll -15 15 t cllh -15 15 t clll -15 15 eclk ? address valid time (non-multiplexed) t chav a[23:0], eclk ebm:nms=1 -20 20 ns t clav -20 20 eclk ? address valid time (multiplexed) t chav a[23:16], eclk ebm:nms=0 -20 20 ns t clav -20 20 t cladv ad[15:0], eclk ebm:nms=0 -20 20 ns t chadv -20 20 eclk rdx /wrx time t chrwh rdx, wrx, wrlx, wrhx, eclk ? -15 15 ns t chrwl -15 15 t clrwh -15 15 t clrwl -15 15
document number: 002-04586 rev. *a page 89 of 122 MB96330 series eclk t cyc csn ale a[23:0] 0.2*vcc t chcl t chav t chcbl t chcbh lbx ubx t cllh t chll t chlh t clll t cladv ad[15:0] address t clav t chadv t clcbh t clcbl t chrwh t clrwh t clrwl t chrwl rdx wrx (wrlx, wrhx) 0.8*vcc t clch refer to the hardware manual for detailed timing charts
document number: 002-04586 rev. *a page 90 of 122 MB96330 series bus timing (read) (t a ? ? 40c to ? 125c, v cc ? 5.0 v ? 10 ? , v ss ? 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max ale pulse width (multiplexed) t lhll ale eacl:sts=0 and eacl:ace=0 t cyc /2 ? 5? ns ebm:nms = 0 eacl:sts=1 t cyc ? 5? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 5? valid address ? ale ? time (multiplexed) t avll ale, a[23:16], eacl:sts=0 and eacl:ace=0 t cyc ? 15 ? ns eacl:sts=1 and eacl:ace=0 3t cyc /2 ? 15 ? eacl:sts=0 and eacl:ace=1 2t cyc ? 15 ? eacl:sts=1 and eacl:ace=1 5t cyc /2 ? 15 ? t advll ale,ad[15:0] eacl:sts=0 and eacl:ace=0 t cyc /2 ? 15 ? ns eacl:sts=1 and eacl:ace=0 t cyc ? 15 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 15 ? eacl:sts=1 and eacl:ace=1 2t cyc ? 15 ? ale ? ? address valid time (multiplexed) t llax ale, ad[15:0] eacl:sts=0 t cyc /2 ? 15 ? ns eacl:sts=1 -15 ? valid address ? rdx ? time (non-multiplexed) t avrl rdx, a[23:0] ebm:nms= 1 t cyc /2 ? 15 ? ns valid address ? rdx ? time (multiplexed) t avrl rdx, a[23:16] eacl:ace=0 ebm:nms=0 3t cyc /2 ? 15 ? ns eacl:ace=1 ebm:nms=0 5t cyc /2 ? 15 ? t advrl rdx, ad[15:0] eacl:ace=0 ebm:nms=0 t cyc ? 15 ? ns eacl:ace=1 ebm:nms=0 2t cyc ? 15 ? valid address ? valid data input (non-multiplexed) t avdv a[23:0], ad[15:0] ebm:nms= 1 ? 2t cyc ? 55 ns w/o cycle extension
document number: 002-04586 rev. *a page 91 of 122 MB96330 series valid address ? valid data input (multiplexed) t avdv a[23:16], ad[15:0] eacl:ace=0 ebm:nms=0 ?3t cyc ? 55 ns w/o cycle extension eacl:ace=1 ebm:nms=0 ?4t cyc ? 55 t ad- vdv ad[15:0] eacl:ace=0 ebm:nms=0 ?5t cyc /2 ? 55 ns w/o cycle extension eacl:ace=1 ebm:nms=0 ?7t cyc /2 ? 55 rdx pulse width t rlrh rdx ? 3 t cyc /2 ? 5? ns w/o cycle extension rdx ? ? valid data input t rldv rdx, ad[15:0] ? ? 3 t cyc /2 ? 50 ns w/o cycle extension rdx ? ? data hold time t rhdx rdx, ad[15:0] ? 0 ? ns address valid ? data hold time t axdx a[23:0], ad[15:0] ? 0 ? ns rdx ? ? ale ? time t rhlh rdx, ale eacl:sts=1 and eacl:ace=1 3t cyc /2 ? 10 ? ns other ecl:sts, eacl:ace setting t cyc /2 ? 10 ? valid address ? eclk ? time t avch a[23:0], eclk ? t cyc ? 15 ? ns t ad- vch ad[15:0], eclk t cyc /2 ? 15 ? rdx ? ? eclk ? time t rlch rdx, eclk ? t cyc /2 ? 10 ? ns ale ? ? rdx ? time t llrl ale, rdx eacl:sts=0 t cyc /2 ? 10 ? ns eacl:sts=1 ? 10 ? eclk ? ? valid data input t chdv ad[15:0], eclk ? ? t cyc ? 50 ns (t a ? ? 40c to ? 125c, v cc ? 5.0 v ? 10 ? , v ss ? 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max
document number: 002-04586 rev. *a page 92 of 122 MB96330 series (t a ? ? 40c to ? 125c, v cc ? 3.0 to 4.5v, v ss ? 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max ale pulse width (multiplexed) t lhll ale eacl:sts=0 and eacl:ace=0 t cyc /2 ? 8? ns ebm:nms = 0 eacl:sts=1 t cyc ? 8? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 8? valid address ? ale ? time (multiplexed) t avll ale, a[23:16], eacl:sts=0 and eacl:ace=0 t cyc ? 20 ? ns eacl:sts=1 and eacl:ace=0 3t cyc /2 ? 20 ? eacl:sts=0 and eacl:ace=1 2t cyc ? 20 ? eacl:sts=1 and eacl:ace=1 5t cyc /2 ? 20 ? t advll ale, ad[15:0] eacl:sts=0 and eacl:ace=0 t cyc /2 ? 20 ? ns eacl:sts=1 and eacl:ace=0 t cyc ? 20 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 20 ? eacl:sts=1 and eacl:ace=1 2t cyc ? 20 ? ale ? ? address valid time (multiplexed) t llax ale, ad[15:0] eacl:sts=0 t cyc /2 ? 20 ? ns eacl:sts=1 -20 ? valid address ? rdx ? time (non-multiplexed) t avrl rdx, a[23:0] ebm:nms= 1 t cyc /2 ? 20 ? ns valid address ? rdx ? time (multiplexed) t avrl rdx, a[23:16] eacl:ace=0 ebm:nms=0 3t cyc /2 ? 20 ? ns eacl:ace=1 ebm:nms=0 5t cyc /2 ? 20 ? t advrl rdx, ad[15:0] eacl:ace=0 ebm:nms=0 t cyc ? 20 ? ns eacl:ace=1 ebm:nms=0 2t cyc ? 20 ? valid address ? valid data input (non-multiplexed) t avdv a[23:0], ad[15:0] ebm:nms= 1 ? 2t cyc ? 60 ns w/o cycle extension
document number: 002-04586 rev. *a page 93 of 122 MB96330 series valid address ? valid data input (multiplexed) t avdv a[23:16], ad[15:0] eacl:ace=0 ebm:nms=0 ?3t cyc ? 60 ns w/o cycle extension eacl:ace=1 ebm:nms=0 ?4t cyc ? 60 t ad- vdv ad[15:0] eacl:ace=0 ebm:nms=0 ?5t cyc /2 ? 60 ns w/o cycle extension eacl:ace=1 ebm:nms=0 ?7t cyc /2 ? 60 rdx pulse width t rlrh rdx ? 3t cyc /2 ? 8? ns w/o cycle extension rdx ? ? valid data input t rldv rdx, ad[15:0] ? ? 3t cyc /2 ? 55 ns w/o cycle extension rdx ? ? data hold time t rhdx rdx, ad[15:0] ? 0 ? ns address valid ? data hold time t axdx a[23:0] ? 0 ? ns rdx ? ? ale ? time t rhlh rdx, ale eacl:sts=1 and eacl:ace=1 3t cyc /2 ? 15 ? ns other ecl:sts, eacl:ace setting t cyc /2 ? 15 ? valid address ? eclk ? time t avch a[23:0], eclk ? t cyc ? 20 ? ns t ad- vch ad[15:0], eclk t cyc /2 ? 20 ? rdx ? ? eclk ? time t rlch rdx, eclk ? t cyc /2 ? 15 ? ns ale ? ? rdx ? time t llrl ale, rdx eacl:sts=0 t cyc /2 ? 15 ? ns eacl:sts=1 ? 15 ? eclk ? ? valid data input t chdv ad[15:0], eclk ? ? t cyc ? 55 ns (t a ? ? 40c to ? 125c, v cc ? 3.0 to 4.5v, v ss ? 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max
document number: 002-04586 rev. *a page 94 of 122 MB96330 series . a[23:0] ad[15:0] address v il v ih v ih v il read data t rhdx t rldv t advdv eclk t advch 0.8*vcc t rlch ale t lhll t rhlh 0.2*v cc t llax t advll rdx t llrl t rlrh t advrl t avch t avll t avdv t avrl t chdv t axdx refer to the hardware manual for detailed timing charts
document number: 002-04586 rev. *a page 95 of 122 MB96330 series bus timing (write) (t a ? ? 40c to ? 125c, v cc ? 5.0 v ? 10 ? , v ss ? 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin condition value unit remarks min max valid address ? wrx ? time (non-multiplexed) t avwl wrx, wrlx, wrhx, a[23:0] eacl:sts=0 ebm:nms=1 t cyc /2 ? 15 ? ns eacl:sts=1 ebm:nms=1 t cyc ? 15 ? valid address ? wrx ? time (multiplexed) t avwl wrx, wrlx, wrhx, a[23:16] eacl:ace=0 ebm:nms=0 3t cyc /2 ? 15 ? ns eacl:ace=1 ebm:nms=0 5t cyc /2 ? 15 ? t advwl wrx, wrlx, wrhx, ad[15:0] eacl:ace=0 ebm:nms=0 t cyc ? 15 ? ns eacl:ace=1 ebm:nms=0 2t cyc ? 15 ? wrx pulse width t wlwh wrx, wrxl, wrhx ?t cyc ? 5?ns w/o cycle extension valid data output ? wrx ? time t dvwh wrx, wrlx, wrhx, ad[15:0] ?t cyc ? 20 ? ns w/o cycle extension wrx ? ? data hold time t whdx wrx, wrlx, wrhx, ad[15:0] ?t cyc /2 ? 15 ? ns wrx ? ? address valid time (non-multiplexed) t whax wrx, wrlx, wrhx, a[23:0] eacl:sts=1 ebm:nms=1 ? 15 ? ns eacl:sts=0 ebm:nms=1 t cyc /2 ? 15 ? ns wrx ? ? address valid time (multiplexed) t whax wrx, wrlx, wrhx, a[23:16] ebm:nms=0 t cyc /2 ? 15 ? ns wrx ? ? ale ? time (multiplexed) t whlh wrx, wrlx, wrhx, ale ebm:ace=1 and eacl:sts=1 2t cyc ? 10 ? ns ebm:nms=0 other ebm:ace and eacl:sts setting t cyc ? 10 ? wrx ? ? eclk ? time t wlch wrx, wrlx, wrhx, eclk ?t cyc /2 ? 10 ? ns csn ? wrx time (non-multiplexed) t cslwl wrx, wrlx, wrhx, csn eacl:sts=0 ebm:nms=1 ?t cyc /2 ? 15 ns eacl:sts=1 ebm:nms=1 ?t cyc ? 15 csn ? wrx time (multiplexed) t cslwl wrx, wrlx, wrhx, csn eacl:ace=0 ebm:nms=0 ?3t cyc /2 ? 15 ns eacl:ace=1 ebm:nms=0 ?5t cyc /2 ? 15
document number: 002-04586 rev. *a page 96 of 122 MB96330 series wrx ? csn time (non-multiplexed) t whcsh wrx, wrlx, wrhx, csn eacl:sts=1 ebm:nms=1 ? 15 ? ns eacl:sts=0 ebm:nms=1 t cyc /2 ? 15 ? ns wrx ? csn time (multiplexed) t whcsh wrx, wrlx, wrhx, csn ebm:nms=0 t cyc /2 ? 15 ? ns (t a ? ? 40c to ? 125c, v cc ? 3.0 to 4.5v, v ss ? 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin condition value unit remarks min max valid address ? wrx ? time (non-multiplexed) t avwl wrx, wrlx, wrhx, a[23:0] eacl:sts=0 ebm:nms=1 t cyc /2 ? 20 ? ns eacl:sts=1 ebm:nms=1 t cyc ? 20 ? valid address ? wrx ? time (multiplexed) t avwl wrx, wrlx, wrhx, a[23:16] eacl:ace=0 ebm:nms=0 3t cyc /2 ? 20 ? ns eacl:ace=1 ebm:nms=0 5t cyc /2 ? 20 ? t advwl wrx, wrlx, wrhx, ad[15:0] eacl:ace=0 ebm:nms=0 t cyc ? 20 ? ns eacl:ace=1 ebm:nms=0 2t cyc ? 20 ? wrx pulse width t wlwh wrx, wrxl, wrhx ?t cyc ? 8?ns w/o cycle extension valid data output ? wrx ? time t dvwh wrx, wrlx, wrhx, ad[15:0] ?t cyc ? 25 ? ns w/o cycle extension wrx ? ? data hold time t whdx wrx, wrlx, wrhx, ad[15:0] ?t cyc /2 ? 20 ? ns wrx ? ? address valid time (non-multiplexed) t whax wrx, wrlx, wrhx, a[23:0] eacl:sts=1 ebm:nms=1 ? 20 ? ns eacl:sts=0 ebm:nms=1 t cyc /2 ? 20 ? ns wrx ? ? address valid time (multiplexed) t whax wrx, wrlx, wrhx, a[23:16] ebm:nms=0 t cyc /2 ? 20 ? ns wrx ? ? ale ? time (multiplexed) t whlh wrx, wrlx, wrhx, ale ebm:ace=1 and eacl:sts=1 2t cyc ? 15 ? ns ebm:nms=0 other ebm:ace and eacl:sts setting t cyc ? 15 ? wrx ? ? eclk ? time t wlch wrx, wrlx, wrhx, eclk ?t cyc /2 ? 15 ? ns (t a ? ? 40c to ? 125c, v cc ? 5.0 v ? 10 ? , v ss ? 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin condition value unit remarks min max
document number: 002-04586 rev. *a page 97 of 122 MB96330 series csn ? wrx time (non-multiplexed) t cslwl wrx, wrlx, wrhx, csn eacl:sts=0 ebm:nms=1 ?t cyc /2 ? 20 ns eacl:sts=1 ebm:nms=1 ?t cyc ? 20 csn ? wrx time (multiplexed) t cslwl wrx, wrlx, wrhx, csn eacl:ace=0 ebm:nms=0 ?3t cyc /2 ? 20 ns eacl:ace=1 ebm:nms=0 ?5t cyc /2 ? 20 wrx ? csn time (non-multiplexed) t whcsh wrx, wrlx, wrhx, csn eacl:sts=1 ebm:nms=1 ? 20 ? ns eacl:sts=0 ebm:nms=1 t cyc /2 ? 20 ? ns wrx ? csn time (multiplexed) t whcsh wrx, wrlx, wrhx, csn ebm:nms=0 t cyc /2 ? 20 ? ns (t a ? ? 40c to ? 125c, v cc ? 3.0 to 4.5v, v ss ? 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin condition value unit remarks min max eclk t wlch 0.8*v cc ale t whlh wrx (wrlx, wrhx) t wlwh t advwl a[23:0] t whax ad[15:0] address write data t dvwh t whdx csn t whcsh t avwl t cslwl 0.2*v cc refer to the hardware manual for detailed timing charts
document number: 002-04586 rev. *a page 98 of 122 MB96330 series . ready input timing note : if the rdy setup time is insufficient, use the auto-ready function. (t a ? ? 40c to ? 125c, v cc ? 5.0 v ? 10 ? , v ss ? 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin test condition rated value units remarks min max rdy setup time t ryhs rdy ? 35 ? ns rdy hold time t ryhh rdy 0 ? ns (t a ? ? 40c to ? 125c, v cc ? 3.0 to 4.5v, v ss ? 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin test condition rated value units remarks min max rdy setup time t ryhs rdy ? 45 ? ns rdy hold time t ryhh rdy 0 ? ns eclk rdy when wait is not used. v ih v ih t ryhh rdy when wait is used. t ryhs v il 0.8*v cc refer to the hardware manual for detailed timing charts
document number: 002-04586 rev. *a page 99 of 122 MB96330 series hold timing (t a ? ? 40c to ? 125c, v cc ? 5.0 v ? 10 ? , v ss ? 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin condition value units remarks min max pin floating ? hakx ? time t xhal hakx ? t cyc ? 20 t cyc + 20 ns hakx ? time ? pin valid time t hahv hakx t cyc ? 20 t cyc + 20 ns (t a ? ? 40c to ? 125c, v cc ? 3.0 to 4.5v, v ss ? 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin condition value units remarks min max pin floating ? hakx ? time t xhal hakx ? t cyc ? 25 t cyc + 25 ns hakx ? time ? pin valid time t hahv hakx t cyc ? 25 t cyc + 25 ns hakx each pin high-z t hahv t xhal 0.8*v cc 0.2*v cc 0.8*v cc 0.2*v cc refer to the hardware manual for detailed timing charts
document number: 002-04586 rev. *a page 100 of 122 MB96330 series usart timing warning: the values given below are for an i/o driving strength io drive = 5ma. if io drive is 2ma, all the maximum output timing described in the different tables must then be increased by 10ns. notes: ? ac characteristic in clk synchronized mode. ?c l is the load capacity value of pins when testing. ? depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. these parameters are shown in ?mb96300 super series hardware manual? ?t clkp1 is the cycle time of the periphe ral clock 1 (clkp1), unit : ns *1: parameter n depends on t scyci and can be calculated as follows: ?if t scyci = 2*k*t clkp1 , then n = k, where k is an integer > 2 ?if t scyci = (2*k+1)*t clkp1 , then n = k+1, where k is an integer > 1 examples: (t a = -40c to 125c, v cc = 3.0v to 5.5v, v ss = av ss = 0v, io drive = 5ma, c l = 50pf) parameter symbol pin condition v cc = av cc = 4.5v to 5.5v v cc = av cc = 3.0v to 4.5v unit min max min max serial clock cycle time t scyci sckn internal shift clock mode 4 t clkp1 ?4 t clkp1 ?ns sck sot delay time t slovi sckn, sotn -20 ? 20 -30 ? 30 ns sot sck delay time t ovshi sckn, sotn n*t clkp1 - 20 *1 ? n*t clkp1 - 30 *1 ?ns valid sin sck t ivshi sckn, sinn t clkp1 + 45 ? t clkp1 + 55 ?ns sck valid sin hold time t shixi sckn, sinn 0? 0 ?ns serial clock ?l? pulse width t slshe sckn external shift clock mode t clkp1 + 10 ? t clkp1 + 10 ?ns serial clock ?h? pulse width t shsle sckn t clkp1 + 10 ? t clkp1 + 10 ?ns sck sot delay time t slove sckn, sotn ? 2 t clkp1 + 45 ? 2 t clkp1 + 55 ns valid sin sck t ivshe sckn, sinn t clkp1 /2 + 10 ? t clkp1 /2 + 10 ?ns sck valid sin hold time t shixe sckn, sinn t clkp1 + 10 ? t clkp1 + 10 ?ns sck fall time t fe sckn ? 20 ? 20 ns sck rise time t re sckn ? 20 ? 20 ns t scyci n 4*t clkp1 2 5*t clkp1, 6*t clkp1 3 7*t clkp1, 8*t clkp1 4 ... ...
document number: 002-04586 rev. *a page 101 of 122 MB96330 series internal shift clock mode sot t slovi sin v il v ih t ivshi v il v ih t shixi t ovshi sck for escr:sces = 0 0.8*v cc t scyci sck for escr:sces = 1 0.8*v cc 0.8*v cc 0.2*v cc 0.2*v cc 0.2*v cc 0.8*v cc 0.2*v cc external shift clock mode t fe v il v il v il v il sot t slove sin v il v ih t ivshe v il v ih t shixe v ih t re v ih t slshe v il v ih t shsle v ih v ih sck for escr:sces = 0 sck for escr:sces = 1 0.8*v cc 0.2*v cc
document number: 002-04586 rev. *a page 102 of 122 MB96330 series i 2 c timing *1 : r,c : pull-up resistor and load capacitor of the scl and sda lines. *2 : the maximum t hddat have only to be met if the device does not stretch the ?l? width (t low ) of the scl signal. *3 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat 250 ns must then be met. *4 : for use at over 100 khz, set the peripheral clock 1 to at least 6 mhz. (t a = -40c to 125c, v cc = av cc = 3.0v to 5.5v,v ss = av ss =0v) parameter symbol condition standard-mode fast-mode* 4 unit min max min max scl clock frequency f scl r ? 1.7 k ? , c ? 50 pf* 1 0 100 0 400 khz hold time (repeated) start condition sda scl t hdsta 4.0 ? 0.6 ? ? s ?l? width of the scl clock t low 4.7 ? 1.3 ? ? s ?h? width of the scl clock t high 4.0 ? 0.6 ? ? s set-up time for a repeated start condition scl sda t susta 4.7 ? 0.6 ? ? s data hold time scl sda t hddat 0 3.45* 2 00.9* 3 ? s data set-up time sda scl t sudat 250 ? 100 ? ns set-up time for stop condition scl sda t susto 4.0 ? 0.6 ? ? s bus free time between a stop and start condi- tion t bus 4.7 ? 1.3 ? ? s sda scl t low t sudat t hdsta t bus t hdsta t hddat t high t susta t susto
document number: 002-04586 rev. *a page 103 of 122 MB96330 series 14.5 usb characteristics (t a = -40c to 105c, v cc = av cc = 3.0v to 5.5v,v ss = av ss = 0v, v cc3 = 3.0v to 3.6v, usb pins udp and udm) *1 : the switching threshold voltage of single-end-receiver of usb i/o buffer is set as within v il (max) ? 0.8 [v], v ih (min) ? 2.0 [v] (ttl input standard). there are some hystereses to lower noise sensitivity. (continued) parameter symbol conditions value unit remarks min max input characteristics input high level voltage v ih ?2.0v cc ? 0.3 v *1 input low level voltage v il ?v ss ? 0.3 0.8 v *1 differential input sensitivity v di ?0.2?v*2 differential common mode input voltage v cm ?0.82.5v*2 output characteristics output high level voltage v oh external pull-down resistance ? 15 k ? 2.8 3.6 v *3 output low level voltage v ol external pull-up resistance ? 1.5 k ? 0.0 0.3 v *3 crossover voltage v crs ?1.32.0v*4 rise time t fr ? 4 20 ns *5 fall time t ff ? 4 20 ns *5 rise/fall time matching t rfm ? 90 111.11 ? *5 output impedance z drv ?2844 ? including rs ? 27 ? input capacitance transceiver edge rate control capacitance c edge ? ? 75 pf *6 series resistance r s ?2530 ? recommended value:27 ?
document number: 002-04586 rev. *a page 104 of 122 MB96330 series (continued) * 2 : use differential-receiver to receive usb differential data signal. differential-receiver has 200 [mv] of diff erential input sensitivity when the different ial data input is within 0.8 [v] to 2.5 [v] to the local ground reference level. above voltage range is the common mode input voltage range. *3 : the output drive capability of the driver is below 0.3 [v] at low-state (v ol ) (to 3.6 [v] and 1.5 k ? load), and 2.8 [v] or above (to the v ss and 1.5 k ? load). *4 : the cross voltage of the exte rnal differential output signal (d ? /d ? ) of usb i/o buffer is within 1.3 [v] to 2.0 [v]. * 5 : regarding t fr ,t ff , t rfm they indicate rise time (trise) and fall time (tfall) of the differential data signal . they are defined by the time between 10 ? to 90 ? of the output signal voltage. for full-speed buffer, t fr /t ff ratio is regulated as within ? 10 ? to minimize rfi emission . (continued) 1.0 [v] 0.2 [v] 0.8 [v] 2.5 [v] minimum differential input sensitivity [v] common mode input voltage [v] d+ d- max 2.0 [v] min 1.3 [v] v crs standard range 90% 90% 10% 10% v cr s udp udm t fr t ff rise time fall time
document number: 002-04586 rev. *a page 105 of 122 MB96330 series (continued) * 6 : the place to connect transceiver edge rate control capacitance c edge for this usb i/o, it is recommended to use c edge control capacitor. for usb max standard as 75 pf, please control the edge char acteristic of output waveform by connecting 30 to 50 [pf] (recommended value : 47 [pf] : = 50[pf]) to d ? and d ? lines when implementing on the board . r s = 27 r s = 27 c edge + d - d 3- s tate c edge driver output impedance 3 ? to 19 ? rs serial resist ance value 25 ? to 30 ? please apply 27 ? of serial resistance va lue as a recommended value.
document number: 002-04586 rev. *a page 106 of 122 MB96330 series 14.6 analog digital converter note: the accuracy gets worse as |avrh - avrl| becomes smaller. (t a = -40 c to +125 c, 3.0 v ?? avrh - avrl, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max resolution - - - - 10 bit total error - - -3 - +3 lsb nonlinearity error - - -2.5 - +2.5 lsb differential nonlinearity error - - -1.9 - +1.9 lsb zero reading voltage v ot ann avrl - 1.5 lsb avrl+ 0.5 lsb avrl + 2.5 lsb v full scale reading voltage v fst ann avrh - 3.5 lsb avrh - 1.5 lsb avrh + 0.5 lsb v compare time - - 1.0 - 16,500 ? s 4.5v ??? v cc ? 5.5v 2.0 - - ? s 3.0v ??? v cc ? 4.5v sampling time - - 0.5 - - ? s 4.5v ??? v cc ? 5.5v 1.2 - - ? s 3.0v ??? v cc ? 4.5v analog port input current i ain ann -3 - +3 ? a av ss , avrl < v i < av cc , avrh analog port input current i ain ann -1 - +1 ? a t a ? 25 c, av ss , avrl < v i < av cc , avrh -3 - +3 ? a t a ? 125 c, av ss , avrl < v i < av cc , avrh analog input voltage range v ain ann avrl - avrh v reference voltage range avrh avrh 0.75 avcc - avcc v avrl avrl av ss - 0.25 av cc v power supply current i a avcc - 2.5 5 ma a/d converter active i ah avcc - - 5 ? a a/d converter not operated reference voltage current i r avrh/avrl - 0.7 1 ma a/d converter active i rh avrh/avrl - - 5 ? a a/d converter not operated offset between input channels -ann--4lsb
document number: 002-04586 rev. *a page 107 of 122 MB96330 series definition of a/d converter terms resolution: analog variation that is recognized by an a/d converter. total error: difference between the actual value and the ideal value. the to tal error includes zero transition error, full-scale transition error and nonlinearity error. nonlinearity error: deviation between a line across zero-transition line (? 00 0000 0000? <--> ?00 0000 0001?) and full-scale transition line (?11 1111 1110? <--> ?11 1111 1111?) and actual conversion characteristics. differential nonlinearity error: deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. zero reading voltage: input voltage which results in the minimum conversion value. full scale reading voltage: input voltage which results in the maximum conversion value. 3ff 3fe 3fd 004 003 002 001 avrl avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} actual conversion characteristics (actually-measured value) actual conversion characteristics ideal characteristics digital output analog input total error of digital output ?n? ? v nt ? {1 lsb (n ? 1) ? 0.5 lsb} 1 lsb [lsb] 1 lsb ? (ideal value) avrh ? avrl 1024 [v] v ot (ideal value) ? avrl ? 0.5 lsb [v] v fst (ideal value) ? avrh ? 1.5 lsb [v] v nt : a voltage at which digital output transitions from (n ? 1) to n. total error n: a/d converter digital output value
document number: 002-04586 rev. *a page 108 of 122 MB96330 series notes on a/d converter section ? about the external impedance of the analog input and the sampling time of the a/d converter (with sample and hold circuit): if the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and h old capacitor is insufficient, adversely affecting a/d conversion precision. 3ff 3fe 3fd 004 003 002 001 avrl avrh avrl avrh n + 1 n n ? 1 n ? 2 v ot ( actual measurement value ) {1 lsb (n ? 1) + v ot } actual conversion characteristics v fst (actual measurement value) v nt (actual measurement value) actual conversion characteristics ideal characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output digital output analog input analog input v nt (actual measurement value) v (n + 1) t (actual measurement value) nonlinearity error differe ntial nonlinearity error differential nonlinearity error of digital output n ? 1 lsb ? analog input circuit model: comparator sampling switch r c analog input reference value: ? c = 8.5 pf (max) nonlinearity error of digital output n ? v nt ? {1 lsb (n ? 1) ? v ot } 1 lsb [lsb] v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] n : a/d converter digital output value v ot : voltage at which digital output transits from ?000 h ? to ?001 h .? v fst : voltage at which digital output transits from ?3fe h ? to ?3ff h .?
document number: 002-04586 rev. *a page 109 of 122 MB96330 series to satisfy the a/d conversion precision standard, the relationsh ip between the external impedance and minimum sampling time mus t be considered and then either the resistor value and operating fr equency must be adjusted or the external impedance must be decreased so that the sampling time (t samp ) is longer than the minimum value. usually, this value is set to 7 ??? where ??? = rc. if the external input resistance (r ext ) connected to the analog input is included, the sampling time is expressed as follows: t samp [min] = 7 (r ext + 2.6k ? ) c for 4.5 ?? av cc ?? 5.5 t samp [min] = 7 (r ext + 12.1k ? ) c for 3.0 ?? av cc ?? 4.5 if the sampling time cannot be sufficient, connect a capacitor of about 0.1 ? f to the analog input pin. about the error the accuracy gets worse as |avrh - avrl| becomes smaller.
document number: 002-04586 rev. *a page 110 of 122 MB96330 series 14.7 alarm comparator (t a = -40 c to +125 c, v cc = av cc = 3.0v - 5.5v, v ss = av ss = 0v ) parameter symbol pin value unit remarks min typ max power supply current i a5almf av cc -2545 ? a alarm comparator enabled in fast mode (one channel) i a5alms -713 ? a alarm comparator enabled in slow mode (one channel) i a5almh --5 ? a alarm comparator disabled alarm pin input current i alin alarm0, alarm1 -1 - +1 ? a t a = 25 c -3 - +3 ? a t a = 125 c alarm pin input voltage range v alin 0- av cc v external low threshold high->low transition v evtl(h->l) 0.36 * av cc -0.25 0.36 * av cc -0.1 -v intref = 0 external low threshold low->high transition v evtl(l->h) - 0.36 * av cc +0.1 0.36 * av cc +0.25 v external high threshold high->low transition v evth(h->l) 0.78 * av cc -0.25 0.78 * av cc -0.1 -v external high threshold low->high transition v evth(l->h) 0.78 * av cc +0.1 0.78 * av cc +0.25 v internal low threshold high->low transition v ivtl(h->l) 0.9 1.1 - v intref = 1 internal low threshold low->high transition v ivtl(l->h) - 1.3 1.55 v internal high threshold high->low transition v ivth(h->l) 2.2 2.4 - v internal high threshold low->high transition v ivth(l->h) - 2.6 2.85 v switching hysteresis v hys 50 - 300 mv comparison time t compf -0.11 ? s cmd = 1 (fast) t comps -110 ? s cmd = 0 (slow) slow/fast mode transition time t cmd - 100 500 ? s threshold levels specified above are not guaranteed within this time
document number: 002-04586 rev. *a page 111 of 122 MB96330 series comparator output v xvtx(l->h) v hys v alin h l v xvtx(h->l)
document number: 002-04586 rev. *a page 112 of 122 MB96330 series 14.8 low voltage detector characteristics cilcr:lvl[3:0] are the low voltage detector level select bits of the cilcr register. levels 10 to 15 are not used in this device. for correct detection, the slope of the voltage level must satisfy . faster variations are regarded as noise and may not be detected. the functional operation of the mcu is guaranteed down to the mi nimum low voltage detection level of vcc = 2.7v. the electrical characteristics however are only valid in the specified range (usually down to 3.0v). (t a = -40 c to +125 c, v cc = av cc = 3.0v - 5.5v, v ss = av ss = 0v) parameter symbol value unit remarks min max stabilization time t lvdstab 60 75 ? s level 0 v dl0 2.7 2.9 v cilcr:lvl[3:0]=?0000? level 1 v dl1 2.9 3.1 v cilcr:lvl[3:0]=?0001? level 2 v dl2 3.1 3.3 v cilcr:lvl[3:0]=?0010? level 3 v dl3 3.5 3.75 v cilcr:lvl[3:0]=?0011? level 4 v dl4 3.6 3.85 v cilcr:lvl[3:0]=?0100? level 5 v dl5 3.7 3.95 v cilcr:lvl[3:0]=?0101? level 6 v dl6 3.8 4.05 v cilcr:lvl[3:0]=?0110? level 7 v dl7 3.9 4.15 v cilcr:lvl[3:0]=?0111? level 8 v dl8 4.0 4.25 v cilcr:lvl[3:0]=?1000? level 9 v dl9 4.1 4.35 v cilcr:lvl[3:0]=?1001? level 10 v dl10 not used level 11 v dl11 not used level 12 v dl12 not used level 13 v dl13 not used level 14 v dl14 not used level 15 v dl15 not used dt dv v 0.004 s
document number: 002-04586 rev. *a page 113 of 122 MB96330 series low voltage detector operation in the following figure, the occurrence of a low voltage condition is illustrated. for a detailed description of the reset and startup behavior, please refer to the corresponding hardware manual chapter. voltage [v] time [s] v cc v dlx, min v dlx, max dv dt low voltage reset assertion normal operation power reset extension time
document number: 002-04586 rev. *a page 114 of 122 MB96330 series 14.9 flash memory program/erase characteristics *1: this value was converted from the results of evaluating the re liability of the technology (usi ng arrhenius equation to conve rt high temperature measurements in to normalized value at 85 o c) (t a = -40c to 105c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter value unit remarks min typ max sector erase time - 0.9 3.6 s without erasure pre-programming time chip erase time - n*0.9 n*3.6 s without erasure pre-programming time (n is the number of flash sector of the device) word (16-bit width) programming time - 23 370 us without overhead ti me for submitting write command program/erase cycle 10 000 - - cycle flash data retention time 20 - - year *1
document number: 002-04586 rev. *a page 115 of 122 MB96330 series 15. example characteristics to be prepared
document number: 002-04586 rev. *a page 116 of 122 MB96330 series 16. package dimensi on mb96(f)33x lqfp 144p 144-pin pla s tic lqfp lead pitch 0.50 mm package width package length 20.0 20.0 mm lead s hape g u llwing s ealing method pla s tic mold mo u nting height 1.70 mm max weight 1.20g code (reference) p-lfqfp144-20 20-0.50 144-pin pla s tic lqfp (fpt-144p-m08) (fpt-144p-m08) c 2003 fujit s u limited f144019 s -c-4-6 detail s of "a" part 0.25(.010) ( s tand off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.008) 0.500.20 1.50 +0.20 ?0.10 +.008 ?.004 .059 0 ? ~8 ? 0.50(.020) "a" 0.08(.003) 0.1450.055 (.006.002) lead no. 1 36 index 37 72 73 108 109 144 0.220.05 (.009.002) m 0.08(.003) 20.000.10(.787.004) s q 22.000.20(.866.008) s q (mo u nting height) * dimen s ion s in mm (inche s ). note: the val u e s in parenthe s e s are reference val u e s . ?2003-2008 fujit s u microelectronic s limited f144019 s -c-4-7 note 1) * :val u e s do not incl u de re s in protr us ion. re s in protr us ion i s +0.25(.010)max(each s ide). note 2) pin s width and pin s thickne ss incl u de plating thickne ss . note 3) pin s width do not incl u de tie bar c u tting remainder.
document number: 002-04586 rev. *a page 117 of 122 MB96330 series 17. ordering information *1: these devices are under development and specification is pr eliminary. these products under development may change its specification without notice. part number flash/rom subclock persistent low voltage reset package remarks mb96f336usa pmc-gse2 *1 flash a (288kb) no no 144 pin plastic lqfp (fpt-144p-m08) with usb mb96f336uwa pmc-gse2 *1 yes mb96f338ysa pmc-gse2 *1 flash a (544kb) no yes 144 pin plastic lqfp (fpt-144p-m08) mb96f338rsa pmc-gse2 *1 no mb96f338ywa pmc-gse2 *1 yes yes mb96f338rwa pmc-gse2 *1 no mb96f338usa pmc-gse2 *1 flash a (544kb) no no 144 pin plastic lqfp (fpt-144p-m08) with usb mb96f338uwa pmc-gse2 *1 yes mb96v300brb-es (for evaluation) emulated by ext. ram yes no 416 pin plastic bga (bga-416p-m02)
document number: 002-04586 rev. *a page 118 of 120 MB96330 series 18. revision history revision date modification prelim 0.1 2007-05-23 creation prelim 0.2 2007-08-14 - information about mb96f338u (with usb function) is added - dma 8ch --> 16ch - adc reference switch is removed prelim 0.3 2007-09-11 - circuit type of device with ?u? suffix is added - circuit type diagram: ttl input cell type was changed from nor to nand - io map, irq table are updated - parallel programing flash memory control signals is updated - dc/ac spec of usb i/o is added prelim 0.4 2007-09-24 - block diagram for mb96f338u was corrected: usb pb1 -> pb3 - irq table was modified: vector number 111 was inserted (reserved) - pin assignment was corrected: not used resource name was removed prelim 0.5 2007-11-02 - internal max freq 56mhz --> 48mhz - dma 12ch --> 10ch - fpt-144p-m12 package was removed prelim 1 2007-12-20 update of the block diagram to include usb block. update dc characteristics to include all usb pins characteristics. iomap regenerated. memory maps and flash configuration reworked. typos corrected across the document. renaming of the flash banks. prelim 2 2008-02-07 ?features: - removed adc reference switch - changed usb description ? lineup: - option description added - part number names corrected - flash b removed - rlt6 added ? block diagrams: - flash b removed - out5_r -> out6_r - tx2_r, rx2_r added - sin2_r, sot2_r, sck2_r and sot9 added - not existing ttgx, ttgx_r and ppgx_r pins deleted - rlt6 added ? pin function description: relocated clock output and can pins added ? i/o circuit types updated ? memory maps replaced by new standard maps ? parallel flash programming pinning removed ? iomap regenerated (naming style c hanged, all reserved registers added) ? dc current limits updated with new setting and corrected frequencies ? external bus timings: missing cond itions added and readability improved ? alarm comparator spec update d (transition voltages defined) ? ordering information updated ? typos and formatting corrected
document number: 002-04586 rev. *a page 119 of 120 MB96330 series prelim 3 2008-11-24 ? format adjusted to official fujitsu microelectronics datasheet standard (mainly style changes and official notes and disclaimer added) ? note about devices under development modified ? i/o map: note added about reserved addresses ? serial programming interface: note about handshaking pins improved ? specified ad converter channel offset to 4lsb ? package code of mb96v300 corrected in ordering information ? added voltage condition to pull-up resistance spec ? rom devices removed from lineup, memory map and ordering information ? ordering information: column ?flash/rom added? ? official package dimension drawing with additional notes added ? empty pages removed ? adjusted run and sleep mode specifications according to evaluation results ? absolute maximum ratings: v iusb and v ousb corrected, permitted power dissipation spec added ? dc characteristics: output h/l voltage for usb pins: specified for load of 20ma ? usb characteristics: updated according to mb91660 series ? alarm comparator: power supply current max values increased, comparison time reduced, mode transition time newly added ? handling devices: notes added about serial communication and about using ceramic resona- tors. ? feature list and ac characteri stics: 16mhz maximum frequency is valid for crystal oscillators. for resonators, maximum frequency depends on q-factor ? ac characteristics: pll phase skew spec added, clkvco min=64mhz ? new family member mb96f336u added ? vol3 spec improved: spec valid for 3ma load for full vcc range revision date modification
document number: 002-04586 rev. *a page 120 of 120 MB96330 series 19. major changes spansion publication number: ds07-13805-1e note: please see ?document history? about later revised information. page section change results 108 electrical characteristics 5. analog digital converter changed the item for ?zero reading voltage? and ?full scale reading voltage?.
document number: 002-04586 rev. *a page 121 of 122 MB96330 series document history document title: MB96330 series f 2 mc-16fx 16-bit proprietary microcontroller document number: 002-04586 revision ecn orig. of change submission date description of change ** ? akih 05/23/2007 migrated to cypress and assigned document number 002-04586. no change to document contents or format. *a 5245336 akih 05/13/2016 updated to cypress template
document number: 002-04586 rev. *a revised may 13, 2016 page 122 of 122 MB96330 series ? cypress semiconductor corporation, 2007-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desi gn, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a crit ical component is any compo nent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez-usb, f-ram, and traveo are trademarks or registered trad emarks of cypress in the united states and other countries. for a more complete list of cypre ss trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | projects | video | blogs | training | components technical support cypress.com/support

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