silego technology, inc. rev 1.09 SLG46531_ds_109 revised october 21, 2016 greenpak programmable mixed -signal matrix with asynchronous state machine SLG46531 block diagram features ? logic & mixed signal circuits ? highly versatile macro cells ? read back protection (read lock) ? 1.8 v (5%) to 5 v (10%) supply ? operating temperature range: -40c to 85c ? rohs compliant / halogen-free ? 20-pin stqfn: 2 x 3 x 0.55 mm, 0.4 mm pitch applications ? personal computers and servers ? pc peripherals ? consumer electronics ? data communications equipment ? handheld and portable electronics pin configuration gpio gpio gpio gpio gpio gpio 2 3 414 15 16 17 gpi vdd 1 stqfn-20 (top view) gpio gpio 5 6 gpio gpio 12 13 gpio 7 gnd 11 sda/gpio scl/gpio 8 9 gpio 10 gpio gpio 18 19 gpio 20 3-bit lut3_2 or dff5 pin 6 gpio programmable delay rc oscillator pin 7 gpio pin 1 vdd pin 2 gpi pin3 gpio pin 4 gpio pin 5 gpio pin 20 gpio pin 19 gpio pin 18 gpio pin 8 scl or gpio pin 9 sda or gpio pin 10 gpio pin 12 gpio pin 11 gnd pin 17 gpio pin 16 gpio pin 15 gpio pin 14 gpio pin 13 gpio acmp0 acmp1 acmp2 acmp 3 additional logic functions combination function macrocells 2-bit lut2_0 or dff0 2-bit lut2_2 or dff2 2-bit lut2_1 or dff1 2-bit lut2_3 or pgen 3-bit lut3_1 or dff4 3bit lut3_0 or dff3 3-bit lut3_4 or dff7 3-bit lut3_3 or dff6 filter_1 with edge detect por i 2 c serial communication asm 8 states 3-bit lut3_5 or cnt/dly2 3-bit lut3_6 or cnt/dly3 3-bit lut3_7 or cnt/dly4 3-bit lut3_8 or cnt/dly5 3-bit lut3_9 or cnt/dly6 4-bit lut4_0 or cnt/dly0 4-bit lut4_1 or cnt/dly1 3-bit lut3_10 or pipe de- fil- ter_0with edge detect 8 byte ram + otp memory vref crystal oscillator 25m oscillator
SLG46531_ds_109 page 1 of 169 SLG46531 1.0 overview the SLG46531 provides a small, low power component for commonly used mixed-signal functions. the user creates their circuit design by programming the one time non-volatile memory (nvm) to configure the interconnect logic, the i/o pins and the macro cells of the SLG46531. this highly versatile device allows a wi de variety of mixed-signal functions to be designed within a ve ry small, low power single integrat ed circuit. the macro cells in the device include the following: ? four analog comparators (acmp) ? two voltage references (vref) ? seventeen combination function macrocells ? three selectable dff/latch or 2-bit luts ? one selectable continuous dff/latch or 3-bit lut ? four selectable dff/latch or 3-bit luts ? one selectable pipe delay or 3-bit lut ? one selectable programmable pattern generator or 2-bit lut ? five 8-bit delays/co unters or 3-bit luts ? two 16-bit delays/co unters or 4-bit luts ? asynchronous state machine ? eight states ? flexible input logic from state transitions ? serial communications ?i 2 c protocol compliant ? pipe delay C 16 sta ge/3 output (part of c ombination function m acrocell) ? programmable delay ? additional logic functions C 2 deg litch filters with edge dete ctors ? two oscillators (osc) ? configurable 25 khz/2 mhz ? 25 mhz rc oscillator ? crystal oscillator ? power-on-reset (por) ? eight byte ram + otp user memory ? ram memory space that is readable and writeable via i 2 c ? user defined initial valu es transferred from otp
SLG46531_ds_109 page 2 of 169 SLG46531 2.0 pin description 2.1 functional pin description pin # pin name function 1 vdd power supply 2 gpi general purpose input 3 gpio general purpose i/o with oe 4 gpio general purpose i/o 5 gpio general purpose i/o with oe 6 gpio general purpose i/o o r analog comparator 0 (+) 7 gpio general purpose i/o with oe or external vref (acmp0 in-) 8 scl/gpio general purpose i/o scl or gpiod (nmos open drain only ) 9 sda/gpio general purpose i/o sda or gpiod (nmos open drain only ) 10 gpio general purpose i/o with oe or analog comparator 1 (+) 11 gnd ground 12 gpio general purpose i/o o r external vre f (acmp1 in-) 13 gpio general purpose i/o with oe or analog comparator 2 (+) 14 gpio general purpose i/o with oe or external vref (acmp2 in-) 15 gpio general purpose i/o o r analog comparator 3 (+) 16 gpio general pu rpose i/o with oe 17 gpio general purpose i/o 18 gpio general purpose i/o wit h oe and vref output (vref1) 19 gpio general purpose i/o wit h oe and vref output (vref0) 20 gpio general purpose i/o or external clock input
SLG46531_ds_109 page 3 of 169 SLG46531 3.0 user programmability the SLG46531 is a user programmable device with one-time-programmable (otp) memory elements that are able to construct combinatorial logic elements. three of the i/o pins provide a c onnection for the bit patterns into the otp on board memory. a programming development kit allows the user the ability to crea te initial devices. once the design is finalized, the programmi ng code (.gpx file) is forwarded to silego to integrate into a pro duction process. figure 1. steps to create a cu stom silego greenpak device 3 u r g x f w ' h i l q l w l r q & |