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S70FL01GS 1 gbit (128 mbyte) 3.0v spi flash cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-98295 rev. *m revised june 23, 2017 features ? cmos 3.0v core ? serial peripheral interf ace (spi) with multi-i/o ? spi clock polarity and phase modes 0 and 3 ? double data rate (ddr) option ? extended addressing: 32-bit address ? serial command set and footprint compatible with s25fl-a, s25fl-k, and s25fl-p spi families ? multi i/o command set and footprint compatible with s25fl-p spi family ? read commands ? normal, fast, dual, quad, fast ddr, dual ddr, quad ddr ? autoboot ? power up or reset and execute a normal or quad read command automat ically at a preselected address ? common flash interface (cfi) data for configuration information ? programming (1.5 mbytes/s) ? 512-byte page programming buffer ? quad-input page programming (qpp) for slow clock systems ? erase (0.5 mbytes/s) ? uniform 256-kbyte sectors ? cycling endurance ? 100,000 program-erase cycles, minimum ? data retention ? 20 year data retention, minimum security features ? one time program (otp) array of 2048 bytes ? block protection ? status register bits to control protection against program or erase of a contiguous range of sectors. ? hardware and software control options ? advanced sector protection (asp) ? individual sector protection controlled by boot code or password ? cypress ? 65 nm mirrorbit ? technology with eclipse ? architecture ? core supply voltage: 2.7v to 3.6v ? i/o supply voltage: 1.65v to 3.6v ? temperature range / grade: ? industrial ( ? 40 c to +85 c) ? industrial plus ( ? 40 c to +105 c) ? automotive, aec-q100 grade 3 ( ? 40 c to +85 c) ? automotive, aec-q100 grade 2 ( ? 40 c to +105 c) ? automotive, aec-q100 grade 1 ( ? 40 c to +125 c) ? packages (all pb-free) ? 16-lead soic (300 mils) ? bga-24, 8 ? 6 mm ?5 ? 5 ball (zsa024) footprint general description this document contains information for the S70FL01GS device, which is a dual die stack of two s25fl512s die. for detailed specifications, refer to the discr ete die datasheet provided in the affected documents/related documents table. affected documents/related documents document title publication number s25fl512s 512 mbit (64 mbyte) 3.0v spi flash memory datasheet 001-98284
document number: 001-98295 rev. *m page 2 of 19 S70FL01GS contents 1. block diagram .............................................................. 3 2. connection diagrams .................................................. 4 3. input/output summary ................................................ 5 4. device operations ....................................................... 6 4.1 programming ................................................................. 6 4.2 simultaneous die operation .......................................... 6 4.3 sequential reads........................................................... 6 4.4 sector/bulk erase .......................................................... 6 4.5 status registers............................................................. 6 4.6 configuration register ................................................... 6 4.7 bank address register .................................................. 6 4.8 security and ddr registers ..... .............. .............. ......... 6 4.9 block protection ............................................................. 6 5. read identifi cation (rdid) ........................................... 7 6. reset# ......................................................................... 7 7. versatile i/o power supply (v io ) ................................. 7 8. dc characteristics ....................................................... 8 9. ac test conditions ...................................................... 9 10. sdr ac characteristics ............................................. 10 10.1 ddr ac characteristics ............................................... 11 10.2 capacitance characteristics . ........... ........... ........... ....... 11 11. ordering information .................................................. 12 11.1 valid combinations ? standard................................... 13 11.2 valid combinations ? automotive grade / aec-q100 .................................................................... 13 12. other resources ......................................................... 14 12.1 cypress flash memory road map ................................ 14 12.2 links to software .......................................................... 14 12.3 links to application notes.. ........................................... 14 13. physical diagram ........................................................ 15 13.1 soic 16 lead, 300-mil body width ............... ............... 15 13.2 24-ball bga 8 x 6 mm (zsa024 ) .................................. 16 14. revision history .......................................................... 17 sales, solutions, and legal information .......................... 19 worldwide sales and design supp ort ............ ........... .... 19 products ........................................................................ 19 psoc? solutions .......................................................... 19 cypress developer community ..................................... 19 technical support ................... ...................................... 19
document number: 001-98295 rev. *m page 3 of 19 S70FL01GS 1. block diagram si/io0 si/io0 wp#/io2 wp#/io2 so/io1 hold#/io3 hold#/io3 vss vss sck sck cs#1 cs# vcc vcc si/io0 wp#/io2 hold#/io3 vss sck cs#2 cs# vcc so/io1 so/io1 fl512s flash memory fl512s flash memory
document number: 001-98295 rev. *m page 4 of 19 S70FL01GS 2. connection diagrams figure 1. 16-pin plastic small outline package (so) figure 2. 24-ball bga, 5 x 5 ball footprint (zsa024), top view note: 1. v io is not supported in the S70FL01GS device and is rfu. refer to section 7. for more details. 1 2 3 4 16 15 14 13 hold#/io3 vcc reset# dnu nc vio/rfu si/io0 sck 5 6 7 8 12 11 10 9 wp#/io2 vss dnu dnu dnu cs2# cs1# so/io1 3 25 4 1 cs2# dnu rfu reset# b d e a c vss sck rfu vcc dnu rfu cs1# rfu wp#/io2 dnu si/io0 so/io1 dnu hold#/io3 dnu dnu dnu dnu vio/rfu dnu
document number: 001-98295 rev. *m page 5 of 19 S70FL01GS 3. input/output summary table 2. signal list signal name type description reset# input hardware reset: low = device resets and returns to standby state, ready to receive a command. the signal has an internal pull-up resistor and may be left unconnected in the host system if not used. sck input serial clock. cs1# input chip select. fl512s #1. cs2# input chip select. fl512s #2. si / io0 i/o serial input for single bit data commands or io0 for dual or quad commands. so / io1 i/o serial output for single bit data commands. io1 for dual or quad commands. wp# / io2 i/o write protect when not in quad mode. io2 in quad mode. the signal has an internal pull-up resistor and may be left unconnected in th e host system if not used for quad commands. hold# / io3 i/o hold (pause) serial transfer in single bit or dual data commands. io3 in quad-i/o mode. the signal has an internal pull-up resistor and may be left unconnected in the host system if not used for quad commands. v cc supply core power supply. v io supply versatile i/o power supply. note: v io is not supported in the S70FL01GS device. refer to section 7. for more details. v ss supply ground. nc unused not connected. no device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a printed circuit board (pcb). however, any signal connected to an nc must not have voltage levels higher than v cc . rfu reserved reserved for future use. no device internal signal is currently connected to the package connector but there is pot ential future use of the connector for a signal. it is recommended to not use rfu connectors for pcb routing channels so that the pcb may take advantage of future enhanced features in comp atible footprint devices. dnu reserved do not use. a device internal signal may be connected to the package connector. the connection may be used by cypress for test or ot her purposes and is not intended for connection to any host system signal. any dnu signal related function will be inactive when the signal is at v il . the signal has an internal pu ll-down resistor and may be left unconnected in the host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to this connection.
document number: 001-98295 rev. *m page 6 of 19 S70FL01GS 4. device operations 4.1 programming each flash die must be programmed independentl y due to the nature of the dual die stack. 4.2 simultaneous die operation the user may only access one flash die of the dual di e stack at a time via its respective chip select. 4.3 sequential reads sequential reads are not supported across the end of the first fl ash die to the beginning of the second. if the user desires to sequentially read across the two die, dat a must be read out of the first die via cs 1# and then read out of the second die via c s2#. 4.4 sector/bulk erase a sector erase command must be issued for sectors in each flas h die separately. full device bulk erase via a single command is not supported due to the nature of the dual die stack. a bulk erase command must be issued for each die. 4.5 status registers each flash die of the dual die stack is ma naged by its own status regist ers. reads and updates to th e status registers must be managed separately. it is recommended that status register control bit settings of each die are kept identical to maintain consistency when switching between die. 4.6 configuration register each flash die of the dual die stack is ma naged by its own configuration register. updat es to the configuration register contro l bits must be managed separately. it is recommended that configuration register control bit settings of each die are kept identical t o maintain consistency when switching between die. 4.7 bank address register it is recommended that the bank address register bit settings of each die are kept identical to maintain consistency when switc hing between die. 4.8 security and ddr registers it is recommended that the bit settings for asp register, password register, ppb lock register, ppb access register, dyb access register, and ddr data learning register in each die are kept identical to maintain consistency when switching between die. 4.9 block protection each flash die of the dual die stack will maintain its own block protection. updates to the tbprot and bpnv bits of each die mu st be managed separately. by default, each die is configured to be pr otected starting at the top (hig hest address) of each array, but no address range is protected. it is recommended that the block pr otection settings of each die are kept identical to maintain consistency when switching between die. in addition, any update to the freeze bit must be managed separately for each die. if t he freeze bit is set to a logic 1, it cannot be cleared to a lo gic 0 until a power-on-reset is ex ecuted on each die that has the f reeze bit set to 1.
document number: 001-98295 rev. *m page 7 of 19 S70FL01GS 5. read identification (rdid) the read identification (rdid) command outputs the one-byte manufacturer identification, followed by the two-byte device identification and the bytes for the common flash interface (cfi) tables. each die of the fl01gs dual die stack will have ident ical identification data as the fl512s die, with the exception of the cfi data at byte 27h, as shown in table 3 . 6. reset# note that the hardware reset# input (pin 3 on the 16-pin so package and ball a4 on the 5x5 bga package) is bonded out and active for the S70FL01GS device. for applications that do not re quire use of the reset# pin, it is recommended to not use reset# for pcb routing channels that would cause the reset# si gnal to be asserted low (v il ). doing so will cause the device to reset to standby state. the reset# signal has an internal pull- up resistor and may be left uncon nected in the host system if no t used. 7. versatile i/o power supply (v io ) note that the versatile i/o (v io ) power supply (pin 14 on the 16-pin so packa ge and ball e4 on the 5x5 bga package) is not supported, and pin 14 and ball e4 are rfu (reserved for future use) in the standard configurat ion of the S70FL01GS device. contact your local sales office to confirm availability with the v io feature enabled. table 3. product group cfi device geometry definition byte data description 27h 1bh device size = 2 n byte
document number: 001-98295 rev. *m page 8 of 19 S70FL01GS 8. dc characteristics this section summarizes the dc ch aracteristics of the device. notes: 1. typical values are at t ai = 25c and v cc = 3v. 2. output switching current is not included. 3. bulk erase current is for both die erasing simultaneously. table 4. dc characteristics symbol parameter test conditions min typ (1) max unit v il input low voltage ? -0.5 ? 0.2 x v cc v v ih input high voltage ? 0.7 x v cc ? v cc + 0.4 v v ol output low voltage i ol = 1.6 ma, v cc = v cc min ?? 0.15 x v cc v v oh output high voltage i oh = ?0.1 ma 0.85 x v cc ? v i li input leakage current v cc = v cc max, v in = v ih or v il ? ? 4 a i lo output leakage current v cc = v cc max, v in = v ih or v il ? ? 4 a i cc1 active power supply current (read) serial sdr @ 50 mhz serial sdr @ 133 mhz quad sdr @ 80 mhz quad sdr @ 104 mhz quad ddr @ 66 mhz quad ddr @ 80 mhz outputs unconnected during read data return (2) ? ? 18 36 50 61 75 90 ma i cc2 active power supply current (page program) cs# = v cc ? ? 100 ma i cc3 active power supply current (wrr) cs# = v cc ? ? 100 ma i cc4 active power supply current (se) cs# = v cc ? ? 100 ma i cc5 active power supply current (be) (3) cs# = v cc ? ? 200 ma i sb (industrial) standby current reset#, cs# = v cc ; si, sck = v cc or v ss , industrial temp ? 140 200 a i sb (industrial plus) standby current reset#, cs# = v cc ; si, sck = v cc or v ss , industrial plus temp ? 140 600 a
document number: 001-98295 rev. *m page 9 of 19 S70FL01GS 9. ac test conditions figure 3. input, output, and timing reference levels figure 4. test setup notes: 1. output high-z is defined as the point where data is no longer driven. 2. input slew rate: 1.5 v/ns. 3. ac characteristics tables assume clock and da ta signals have the same slew rate (slope). 4. ddr operation. table 5. ac measurement conditions symbol parameter min max unit c l load capacitance 30 15 (4) pf input rise and fall times 2.4 ns input pulse voltage 0.2 x v cc to 0.8 v cc v input timing ref voltage 0.5 v cc v output timing ref voltage 0.5 v cc v v cc + 0.4v 0.7 x v cc 0.2 x v cc - 0.5v timing reference level 0.5 x v cc 0.85 x v cc 0.15 x v cc input levels output levels device under test c l
document number: 001-98295 rev. *m page 10 of 19 S70FL01GS 10. sdr ac characteristics notes: 1. only applicable as a constraint for wrr instruction when srwd is set to a 1. 2. full v cc range (2.7 - 3.6v) and cl = 30 pf. 3. regulated v cc range (3.0 - 3.6v) and cl = 30 pf. 4. regulated v cc range (3.0 - 3.6v) and cl = 15 pf. 5. 10% duty cycle is supported for frequencies ? 50 mhz. 6. maximum value only applies during program/erase suspend/resume commands. 7. when switching between die, a minimum time of t cs must be kept between the rising edge of one chip select and the falling edge of the other for operations and data to be valid. table 6. sdr ac characteristics (single die package, v cc = 2.7v to 3.6v) symbol parameter min typ max unit f sck, r sck clock frequency for read and 4read instructions dc ? 50 mhz f sck, c sck clock frequency for single commands (4) dc ? 133 mhz f sck, c sck clock frequency for the following dual and quad commands: dor, 4dor, qor, 4qor, dior, 4dior, qior, 4qior dc ? 104 mhz f sck, qpp sck clock frequency for the qpp, 4qpp commands dc ? 80 mhz p sck sck clock period 1/ f sck ? ? t wh , t ch clock high time (5) 45% p sck ? ? ns t wl , t cl clock low time (5) 45% p sck ? ? ns t crt , t clch clock rise time (slew rate) 0.1 ? ? v/ns t cft , t chcl clock fall time (slew rate) 0.1 ? ? v/ns t cs (7) cs# high time (read instructions) cs# high time (program/erase) 10 50 ? ? ns t css cs# active setup time (relative to sck) 3 ? ? ns t csh cs# active hold time (relative to sck) 3 ? 3000 (6) ns t su data in setup time 1.5 ? ? ns t hd data in hold time 2 ? ? ns t v clock low to output valid ? ? 8.0 (2) 7.65 (3) 6.5 (4) ns t ho output hold time 2 ? ? ns t dis output disable time 0 ? 8 ns t wps wp# setup time 20 (1) ? ? ns t wph wp# hold time 100 (1) ? ? ns t hlch hold# active setup time (relative to sck) 3 ? ? ns t chhh hold# active hold time (relative to sck) 3 ? ? ns t hhch hold# non-active setup ti me (relative to sck) 3 ? ? ns t chhl hold# non-active hold time (relative to sck) 3 ? ? ns t hz hold# enable to output invalid ? ? 8 ns t lz hold# disable to output valid ? ? 8 ns
document number: 001-98295 rev. *m page 11 of 19 S70FL01GS 10.1 ddr ac characteristics notes: 1. regulated v cc range (3.0 - 3.6v) and cl =15 pf. 2. maximum value only applies during program/erase suspend/resume commands. 10.2 capacitance characteristics note: 1. for more information on capacitance, please consult the ibis models. table 7. ddr ac characteristics 66 mhz and 80 mhz operation symbol parameter 66 mhz 80 mhz unit min typ max min typ max f sck, r sck clock frequency for ddr read instruction dc ? 66 dc ? 80 mhz p sck, r sck clock period for ddr read instruction 15 ? ? 12.5 ? ? ns t wh , t ch clock high time 45% p sck ? ? 45% p sck ? ? ns t wl , t cl clock low time 45% p sck ? ? 45% p sck ? ? ns t cs cs# high time (read instructions) 10 ? ? 10 ? ? ns t css cs# active setup time (relative to sck) 3 ? ? 3 ? ? ns t csh cs# active hold time (relative to sck) 3 ? ? 3 ? ? ns t su io in setup time 2 ? 3000 (2) 1.5 ? 3000 (2) ns t hd io in hold time 2 ? ? 1.5 ? ? ns t v clock low to output valid 0 ? 6.5 (1) ? ? 6.5 (1) ns t ho output hold time 1.5 ? ? 1.5 ? ? ns t dis output disable time ? ? 8 ? ? 8 ns t lz clock to output low impedance 0 ? 8 0 ? 8 ns t io_skew first io to last io data valid time ? ? 600 ? ? 600 ps table 8. capacitance parameter test conditions min max unit c in input capacitance (applies to sck, cs#1, cs#2, reset#) 1 mhz ? 16 pf c out output capacitance (applies to all i/o) 1 mhz ? 16 pf
document number: 001-98295 rev. *m page 12 of 19 S70FL01GS 11. ordering information the ordering part number is formed by a valid combination of the following: notes: 1. ehplc = enhanced high performance latency code table. 2. uniform 256-kb sectors = all sectors are uniform 256-kb with a 512b programming buffer. s70fl 01g s ag m f i 0 1 1 packing type (note 1) 0 = tray 1 = tube 3 = 13? tape and reel model number (sector type) 1 = uniform 256-kb sectors model number (latency type, package details, reset# support) 0 = ehplc, so footprint c = ehplc, 5 x 5 ball bga footprint with reset# temperature range / grade i = industrial (-40c to + 85c) v = industrial plus (-40c to +105c) a = automotive, aec-q100 grade 3 (-40c to +85c) b = automotive, aec-q100 grade 2 (-40c to +105c) m = automotive, aec-q100 grade 1(-40c to +125c) package materials f = lead (pb)-free h = low-halogen, lead (pb)-free package type b = 24-ball bga 8 x 6 mm package, 1.00 mm pitch m = 16-pin so package speed ag = 133 mhz dp = 66 mhz ddr ds = 80 mhz ddr device technology s = 65 nm mirrorbit process technology density 01g = 1 gbit device family s70fl cypress stacked memory 3.0v-only, serial peripheral interface (spi) flash memory
document number: 001-98295 rev. *m page 13 of 19 S70FL01GS 11.1 valid combinations ? standard table 9 lists the valid combinations configurations pla nned to be supported in volume for this device. note: 1. package marking omits the leading ?s70? and package type. 11.2 valid combinations ? automotive grade / aec-q100 table 10 lists configurations that are automotive grade / aec-q100 qu alified and are planned to be available in volume. the table will be updated as new combinations are released. consult your loca l sales representative to conf irm availability of specific combinations and to check on newly released combinations. production part approval process (ppap) suppor t is only provided for aec-q100 grade products. products to be used in end-use applications that requir e iso/ts-16949 compliance must be aec-q100 grade products in combination with ppap. non?aec-q100 grade products are no t manufactured or documented in full compliance with iso/ts-16949 requirements. aec-q100 grade products are also offered without ppap suppor t for end-use applications that do not require iso/ts-16949 compliance. note: 1. package marking omits the leading ?s70? and package type. table 9. S70FL01GS valid combinations ? standard S70FL01GS valid combinations package marking (1) base ordering part number speed option package and temperature model number packing type S70FL01GS ag mfi, mfv 01 0, 1, 3 fl01gs + a + (temp) + f + (model number) dp fl01gs + d + (temp) + f + (model number) ds fl01gs + s + (temp) + f + (model number) ag bhi, bhv c1 0, 3 fl01gs + a + (temp) + h + (model number) dp fl01gs + d + (temp) + h + (model number) ds fl01gs + s + (temp) + h + (model number) table 10. S70FL01GS valid combinations ? automotive grade / aec-q100 S70FL01GS valid combinations package marking (1) base ordering part number speed option package and temperature model number packing type S70FL01GS ag mfa, mfb, mfm 01 0, 1, 3 fl01gs + a + (temp) + f + (model number) ds fl01gs + s + (temp) + f + (model number) ag bha, bhb, bhm c1 0, 3 fl01gs + a + (temp) + h + (model number) ds fl01gs + s + (temp) + h + (model number)
document number: 001-98295 rev. *m page 14 of 19 S70FL01GS 12. other resources 12.1 cypress flash memory roadmap www.cypress.com/product-roadmaps /cypress-flash-memory-roadmap 12.2 links to software www.cypress.com/software-and-d rivers-cypress-flash-memory 12.3 links to application notes www.cypress.com/appnotes
document number: 001-98295 rev. *m page 15 of 19 S70FL01GS 13. physical diagram 13.1 soic 16 lead, 300-mil body width sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date 0.33 c 0.25 m d ca-b 0.20 c a-b 0.10 c 0.10 c 0.10 c d 2x 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. 1. all dimensions are in millimeters. notes: d and e1 dimensions are determined at datum h. flash, but inclusive of any mismatch between the top and bottom of exclusive of mold flash, tie bar burrs, gate burrs and interlead 4. the package top may be smaller than the package bottom. dimensions 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified 7. the dimensions apply to the flat section of the lead between 0.10 to maximum material condition. the dambar cannot be located on the 8. dimension "b" does not include dambar protrusion. allowable dambar lower radius of the lead foot. identifier must be located within the index area indicated. 9. this chamfer feature is optional. if it is not present, then a pin 1 10. lead coplanarity shall be within 0.10 mm as measured from the h 0 d l2 n e a1 b c e e1 a 0.75 10.30 bsc 1.27 bsc 0.30 10.30 bsc 0.33 0 0.25 16 0.20 7.50 bsc 0.10 0.31 8 0.51 2.65 2.35 a2 2.05 2.55 b1 0.27 0.48 0.30 0.20 c1 l1 0.40 l 1.27 1.40 ref 0.25 bsc 0 5 15 0 0 1 2 - dimensions symbol min. nom. max. - - - - - - - - - - - - mold flash, protrusions or gate burrs shall not exceed 0.15 mm per d and e1 are determined at the outmost extremes of the plastic body 0.25 mm from the lead tip. protrusion shall be 0.10 mm total in excess of the "b" dimension at the plastic body. package length. seating plane. so3016 kota besy 24-oct-16 24-oct-16 *a 002-15547 package outline, 16 lead soic 12 to fit 10.30x7.50x2.65 mm so3016/sl3016/ss3016 sl3016 ss3016
document number: 001-98295 rev. *m page 16 of 19 S70FL01GS 13.2 24-ball bga 8 x 6 mm (zsa024) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date metallized mark indentation or other means. a1 corner to be identified by chamfer, laser or ink mark, n is the number of populated solder ball positions for matrix size when there is an even number of solder balls in the outer row, when there is an odd number of solder balls in the outer row, the position of the center solder ball in the outer row. "sd" and "se" are measured with respect to datums a and b and define symbol "me" is the ball matrix size in the "e" direction. symbol "md" is the ball matrix size in the "d" direction. e represents the solder ball grid pitch. dimension "b" is measured at the maximum ball diameter in a plane ball position designation per jep95, section 3, spp-020. dimensioning and tolerancing methods per asme y14.5m-1994. "+" indicates the theoretical center of depopulated balls. 8. 9. 7 all dimensions are in millimeters. parallel to datum c. 5. 6 4. 3. 1. 2. notes: 0.35 ed ee me md b n 1.00 bsc 0.00 1.00 bsc 5 5 0.40 24 min. 0.20 d1 e1 d e symbol a1 a 8.00 bsc 4.00 bsc 6.00 bsc 4.00 bsc nom. 0.45 1.20 max. dimensions -- - - se sd 0.00 "sd" = ed/2 and "se" = ee/2. "sd" or "se" = 0. md x me. zsa024 kota syli 5-jul-16 5-jul-16 ** 002-15078 8.0x6.0x1.2 mm zsa024 package outline, 24 ball fbga 12 to fit
document number: 001-98295 rev. *m page 17 of 19 S70FL01GS 14. revision history document title: S70FL01GS, 1 gbit (128 mbyte) 3.0v spi flash document number: 001-98295 rev. ecn no. orig. of change submission date description of change ** ? bwha 11/06/2012 initial release *a ? bwha 04/25/2013 global: datasheet designation updated from advance information to preliminary dc characteristics: dc characteristics table: changed max value of ili, ilo, icc1, and isb *b ? bwha 05/16/2013 soic 16 physical diagram: updated package nomenclature from s03016 to sl3016 *c ? bwha 08/22/2013 valid combinations: valid combinations table: added mfv dc characteristics: dc characterist ics table: added isb (automotive) *d ? bwha 11/08/2013 global: datasheet designation updated from preliminary to full production *e ? bwha 03/19/2014 features: packages (all pb-free): added bga-24, 8 x 6 mm connections diagrams: added figure: 24-ball bga, 5 x 5 ball footprint (fab024), to p vi e w ordering information: added options to: model number, package materials, package type, and speed valid combinations: added option to S70FL01GS valid combinations table sdr ac characteristics: sdr ac char acteristics (single die package, vcc = 2.7v to 3.6v) table: updated tv min ddr ac characteristics:updated ddr ac characteristics 66 mhz operation table capacitance characteristics: capacit ance table: updated max values and removed note *f ? bwha 11/07/2014 valid combinations: added dp speed option for bga 5x5 package *g ? bwha 04/21/2015 valid combinations: added bhv option *h 4871631 bwha 08/24/2015 updated to cypress template. changed automotive temperature range to industrial plus temperature range in features and section 4. *i 5123878 bwha 02/03/2016 updated general description . *j 5536564 bwha 12/02/2016 updated features on page 1: added extended and automotive grade temperatures. updated ddr ac characteristics 66 mhz and 80 mhz operation on page 11 table: corrected t ho min value, t csh and t su max value. ordering information on page 12 : added extended and automotive grade. added other resources on page 14 . *k 5612027 ecao 01/17/2017 added i cc1 value for quad ddr @ 80 mhz in table 4, dc characteristics on page 8 updated i cc5 value in table 4, dc characteristics on page 8 updated ddr ac characteristics 66 mhz and 80 mhz operation on page 11 removed extended (-40c to +125c) temperature option in ordering infor- mation updated physical diagram : updated package name and drawing from sl3016 to ss3016. updated package name and drawing from fab024 to zsa024.
document number: 001-98295 rev. *m page 18 of 19 S70FL01GS *l 5669602 ecao 04/05/2017 updated figure 2, 24-ball bga, 5 x 5 ball footprint (zsa024), top view on page 4 . removed ss3016 from section 13.1, soic 16 lead, 300-mil body width on page 15 . removed cs# from table 2, signal list on page 5 . updated t su in table 6, sdr ac characteristics (single die package, v cc = 2.7v to 3.6v) on page 10 . updated cypress logo. updated sales page. *m 5783913 ecao 06/23/2017 changed otp total space in security features . updated i sb values in table 4 . document title: S70FL01GS, 1 gbit (128 mbyte) 3.0v spi flash document number: 001-98295 rev. ecn no. orig. of change submission date description of change
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