document number: 91080 www.vishay.com s09-0046-rev. a, 19-jan-09 1 power mosfet irf9610, sihf9610 vishay siliconix features ? dynamic dv/dt rating ? p-channel ? fast switching ? ease of paralleling ? simple drive requirements ? lead (pb)-free available description the power mosfets technology is the key to vishay?s advanced line of power mosfet transistors. the efficient geometry and unique processing of the power mosfets design achieve very low on-state resistance combined with high transconductance and extreme device ruggedness. the to-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 w. the low thermal resistance and low package cost of the to-220 contribute to its wide acceptance throughout the industry. notes a. repetitive rating; pulse width limited by maximum junction temperature (see fig. 5). b. not applicable. c. i sd - 1.8 a, di/dt 70 a/s, v dd v ds , t j 150 c. d. 1.6 mm from case. product summary v ds (v) - 200 r ds(on) ( )v gs = - 10 v 3.0 q g (max.) (nc) 11 q gs (nc) 7.0 q gd (nc) 4.0 configuration single s g d p-channel mosfet to-220 g d s a v aila b le rohs* compliant ordering information package to-220 lead (pb)-free irf9610pbf sihf9610-e3 snpb irf9610 sihf9610 absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds - 200 v gate-source voltage v gs 20 continuous drain current v gs at - 10 v t c = 25 i d - 1.8 a t c = 100 - 1.0 pulsed drain current a i dm - 7.0 linear derating factor 0.16 w/c maximum power dissipation t c = 25 c p d 20 w inductive current, clamp i lm - 7.0 a peak diode recovery dv/dt c dv/dt - 5.0 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d mounting torque 6-32 or m3 screw 10 lbf in 1.1 n m * pb containing terminations are not rohs compliant, exemptions may apply
www.vishay.com document number: 91080 2 s09-0046-rev. a, 19-jan-09 irf9610, sihf9610 vishay siliconix notes a. repetitive rating; pulse width limited by maximum junction temper ature (see fig. 5). b. pulse width 300 s; duty cycle 2 %. thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -62 c/w case-to-sink, flat, greased surface r thcs 0.50 - maximum junction-to-case (drain) r thjc -6.4 specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = - 250 a - 200 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = - 1 ma - - 0.23 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 2.0 - - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = - 200 v, v gs = 0 v - - - 100 a v ds = - 160 v, v gs = 0 v, t j = 125 c - - - 500 drain-source on-state resistance r ds(on) v gs = - 10 v i d = -0.90 a b -- 3.0 forward transconductance g fs v ds = - 50 v, i d = - 0.90 a b 0.90 - - s dynamic input capacitance c iss v gs = 0 v, v ds = - 25 v, f = 1.0 mhz, see fig. 10 - 170 - pf output capacitance c oss -50- reverse transfer capacitance c rss -15- total gate charge q g v gs = - 10 v i d = - 3.5 a, v ds = - 160 v, see fig. 11 and 18 b --11 nc gate-source charge q gs --7.0 gate-drain charge q gd --4.0 turn-on delay time t d(on) v dd = - 100 v, i d = - 0.90 a, r g = 50 , r d = 110 , see fig. 17 b -8.0- ns rise time t r -15- turn-off delay time t d(off) -10- fall time t f -8.0- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact -4.5- nh internal source inductance l s -7.5- drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the integral reverse p - n junction diode --- 1.8 a pulsed diode forward current a i sm --- 7.0 body diode voltage v sd t j = 25 c, i s = - 1.8 a, v gs = 0 v b --- 5.8v body diode reverse recovery time t rr t j = 25 c, i f = - 1.8 a, di/dt = 100 a/s b - 240 360 ns body diode reverse recovery charge q rr -1.72.6c forward turn-on time t on intrinsic turn-on time is neglig ible (turn-on is dominated by l s and l d ) d s g s d g
document number: 91080 www.vishay.com s09-0046-rev. a, 19-jan-09 3 irf9610, sihf9610 vishay siliconix typical characteristics 25 c, unless otherwise noted fig. 1 - typical output characteristics fig. 2 - typical transfer characteristics fig. 3 - typical saturation characteristics fig. 4 - maximum safe operating area fig. 5 - maximum effective transient thermal impedance, junction-to-case vs. pulse duration 910 8 0_01 v ds , drain-to-so u rce v oltage ( v ) i d , drain c u rrent (a) - 10 - 2.40 - 4 v - 6 v - 5 v v gs = - 10, - 9, - 8 , - 7 v - 1.92 - 1.44 - 0.96 - 0.4 8 0.00 0 - 20 - 30 - 40 - 50 8 0 s p u lse test v gs , gate-to-so u rce v oltage ( v ) i d , drain c u rrent (a) 8 0 s p u lse test v ds > i d(on) x r ds(on) max. 910 8 0_02 - 2 - 2.40 - 1.92 - 1.44 - 0.96 - 0.4 8 0.00 0 - 4 - 6 - 8 - 10 t j = - 55 c t j = 25 c t j = 125 c 8 0 s p u lse test i d , drain c u rrent (a) v ds , drain-to-so u rce v oltage ( v ) 910 8 0_03 - 4 v - 6 v - 5 v v gs = - 10, - 9, - 8 v - 7 v - 2 - 2.40 - 1.92 - 1.44 - 0.96 - 0.4 8 0.00 0 - 4 - 6 - 8 - 10 100 s 1 ms 10 ms operation in this area limited b y r ds(on) n egati v e v ds , drain-to-so u rce v oltage ( v ) n egati v e i d , drain c u rrent (a) t c = 25 c t j = 150 c single p u lse 10 2 2 5 0.1 1 2 5 10 2 5 25 110 25 10 2 10 3 25 910 8 0_04 2.0 1.0 0.1 10 -5 10 -4 10 -3 10 -2 0.1 1.0 10 p dm t 1 t 2 t 1 , s qu are w a v e p u lse d u ration (s) z thjc (t)/r thjc , n ormalized effecti v e transient n otes: 1. d u ty factor, d = t 1 /t 2 2. per unit base = r thjc = 6.4 c/ w 3. t jm - t c = p dm z thjc (t) 0.2 0.05 0.02 0.01 910 8 0_05 0.1 d = 0.5 0.5 0.2 0.05 0.02 0.01 25 25 25 25 25 25 thermal impedence (per unit) single p u lse (transient thermal impedence)
www.vishay.com document number: 91080 4 s09-0046-rev. a, 19-jan-09 irf9610, sihf9610 vishay siliconix fig. 6 - typical transconductance vs. drain current fig. 7 - typical source-drain diode forward voltage fig. 8 - breakdown voltage vs. temperature fig. 9 - normalized on-resistance vs. temperature fig. 10 - typical capacitance vs. drain-to-source voltage fig. 11 - typical gate charge vs. gate-to-source voltage 2.0 g fs ,transcond u ctance (s) i d , drain c u rrent (a) - 0.4 8 - 0.96 - 1.44 - 1.92 - 2.40 0 t j = 25 c t j = - 55 c 910 8 0_06 t j = 125 c 8 0 s p u lse test v ds > i d(on) x r ds(on) max. 1.6 1.2 0. 8 0.4 0.0 t j = 25 c t j = 150 c - 10.0 v sd , so u rce-to-drain v oltage ( v ) i d , drain c u rrent (a) - 2.0 - 6. 8 - 5.6 - 4.4 - 3.2 910 8 0_07 - 0.1 - 0.2 - 0.5 - 1.0 - 2.0 - 5.0 - 8 .0 910 8 0_0 8 t j , j u nction temperat u re (c) b v dss , drain-to-so u rce breakdo w n 1.25 v oltage ( n ormalized) 1.15 0.75 0. 8 5 0.95 1.05 - 40 160 120 8 0 40 0 910 8 0_09 t j , j u nction temperat u re (c) r ds(on) , drain-to-so u rce on resistance 2.5 ( n ormalized) 2.0 0.0 0.5 1.0 1.5 - 40 160 120 8 0 40 0 i d = - 0.6 a v gs = - 10 v 910 8 0_10 v ds , drain-to-so u rce v oltage ( v ) c, capacitance (pf) 500 0 100 200 300 400 0 - 50 - 40 - 30 - 20 - 10 c iss c rss c oss v gs = 0 v , f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gs , c gd c gs + c gd c gs + c gd q g , total gate charge (nc) n egati v e v gs , gate-to-so u rce v oltage ( v ) 20 16 12 8 0 4 02 8 6 4 v ds = - 40 v v ds = - 60 v for test circ u it see fig u re 1 8 v ds = - 100 v 910 8 0_11 i d = - 1. 8 a
document number: 91080 www.vishay.com s09-0046-rev. a, 19-jan-09 5 irf9610, sihf9610 vishay siliconix fig. 12 - typical on-resistance vs. drain current fig. 13 - maximum drain current vs. case temperature fig. 14 - power vs. temperature derating curve fig. 15 - clamped inductive test circult fig. 16 - clamped inductive waveforms 910 8 0_12 i d , drain c u rrent (a) r ds(on) , drain-to-so u rce 7 r ds(on) meas u red w ith c u rrent p u lse of 2.0 s d u ration. initial t j = 25 c. (heating effect of 2.0 s p u lse is minimal.) 6 0 1 2 3 4 5 0 - 7 - 6 - 1 - 2 - 3 - 4 - 5 on resistance ( ) v gs = - 10 v v gs = - 20 v 150 n egati v e i d , drain c u rrent (a) t c , case temperat u re (c) 0.0 0.4 0. 8 1.2 1.6 2.0 25 910 8 0_13 125 100 75 50 t c , case temperat u re (c) p d , po w er dissipation ( w ) 20 15 10 0 5 0 20 100 8 0 60 40 910 8 0_14 140 120 0.05 d.u.t. l v ds + - v dd v gs = - 10 v v ary t p to o b tain re qu ired i l t p v dd = 0.5 v ds e c = 0.75 v ds e c i l v dd v ds t p e c i l
www.vishay.com document number: 91080 6 s09-0046-rev. a, 19-jan-09 irf9610, sihf9610 vishay siliconix fig. 17a - switching time test circuit fig. 17b - switching time waveforms fig. 18a - basic gate charge waveform fig. 18b - gate charge test circuit p u lse w idth 1 s d u ty factor 0.1 % r d v gs r g d.u.t. - 10 v + - v ds v dd v gs 10 % 90 % v ds t d(on) t r t d(off) t f q gs q gd q g v g charge 15 v d.u.t. - 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v c u rrent reg u lator c u rrent sampling resistors same type as d.u.t. + -
document number: 91080 www.vishay.com s09-0046-rev. a, 19-jan-09 7 irf9610, sihf9610 vishay siliconix fig. 19 - for p-channel vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91080 . p. w . period di/dt diode reco v ery d v /dt ripple 5 % body diode for w ard drop re-applied v oltage re v erse reco v ery c u rrent body diode for w ard c u rrent v gs = - 10 v * v dd i sd dri v er gate dri v e d.u.t. i sd w a v eform d.u.t. v ds w a v eform ind u ctor c u rrent d = p. w . period + - - - - + + + * v gs = - 5 v for logic le v el and - 3 v dri v e de v ices peak diode recovery dv/dt test circuit v dd ? d v /dt controlled b y r g ? i sd controlled b y d u ty factor "d" ? d.u.t. - de v ice u nder test d.u.t. circ u it layo u t considerations ? lo w stray ind u ctance ? gro u nd plane ? lo w leakage ind u ctance c u rrent transformer r g compliment n -channel of d.u.t. for dri v er
package information www.vishay.com vishay siliconix revison: 14-dec-15 1 document number: 66542 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 to-220-1 note ? m* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for hvm m * 3 2 1 l l(1) d h(1) q ? p a f j(1) b(1) e(1) e e b c dim. millimeters inches min. max. min. max. a 4.24 4.65 0.167 0.183 b 0.69 1.02 0.027 0.040 b(1) 1.14 1.78 0.045 0.070 c 0.36 0.61 0.014 0.024 d 14.33 15.85 0.564 0.624 e 9.96 10.52 0.392 0.414 e 2.41 2.67 0.095 0.105 e(1) 4.88 5.28 0.192 0.208 f 1.14 1.40 0.045 0.055 h(1) 6.10 6.71 0.240 0.264 j(1) 2.41 2.92 0.095 0.115 l 13.36 14.40 0.526 0.567 l(1) 3.33 4.04 0.131 0.159 ? p 3.53 3.94 0.139 0.155 q 2.54 3.00 0.100 0.118 ecn: x15-0364-rev. c, 14-dec-15 dwg: 6031 package picture a s e xian
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