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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00646 rev. *m revised april 27, 2017 S25FL128P 128-mbit, 3.0 v flash memory this product is not recommended for new and current designs . for new and current designs, s25fl128s supersedes S25FL128P. this is the factory-recommended migration path. please refer to the s25fl128s data sheet for specifications and ordering information. distinctive characteristics architectural advantages ? single power supply operation ? full voltage range: 2.7v to 3.6v read and program operations ? memory architecture ? 128mb uniform 256 kb sector product ? 128mb uniform 64 kb sector product ? program ? page program (up to 256 bytes) in 1.5 ms (typical) ? faster program time in accelerated programming mode (8.5 v?9.5 v on #wp/acc) in 1.2 ms (typical) ? erase ? 2 s typical 256 kb sector erase time ? 0.5 s typical 64 kb sector erase time ? 128 s typical bulk erase time ? sector erase (se) command (d8h) for 256 kb sectors; (20h or d8h) for 64kb sectors ? bulk erase command (c7h) for 256 kb sectors; (60h or c7h) for 64kb sectors ? cycling endurance ? 100,000 cycles per sector typical ? data retention ? 20 years typical ? device id ? rdid (9fh), read_id (90h) and res (abh) commands to read manufacturer and device id information ? res command one-byte electronic signature for backward compatibility ? process technology ? manufactured on 0.09 m mirrorbit ? process technology ? package option ? industry standard pinouts ? 16-pin so package (300 mils) ? 8-contact wson package (6 x 8 mm) performance characteristics ? speed ? 104 mhz clock rate (maximum) ? power saving standby mode ? standby mode 200 a (max) ? deep power down mode 3 a (typical) memory protection features ? memory protection ? wp#/acc pin works in conjunction with status register bits to protect specified memory areas ? 256 kb uniform sector product: status register block protection bits (bp2, bp1, bp0) in status register configure parts of memory as read-only. ? 64kb uniform sector product: status register block protecti on bits (bp3, bp2, bp1, bp0) in status register configure parts of memory as read-only software features ? spi bus compatible serial interface hardware features ? x8 parallel programming mode (for 16-pin so package only) general description the S25FL128P is a 3.0 volt (2.7v to 3.6v), single-power-supply flash memory device. the device consists of 64 sectors of 256 kb memory, or 256 sectors of 64 kb memory. the device accepts data written to si (serial input) and out puts data on so (serial output). the devices are designed to be programmed in-system with the standard system 3.0 volt v cc supply. the memory can be programmed 1 to 256 bytes at a time, usin g the page program command. the device supports sector erase and bulk erase commands. each device requires only a 3.0 volt power supply (2.7v to 3.6v) for both read and write fu nctions. internally generated and regulated voltages are provided for the program operations. this device requires a high voltage supply to wp#/acc pin for the accelerated programming mode.
document number: 002-00646 rev. *m page 3 of 45 S25FL128P contents distinctive characteristics .................................................. 2 general description ............................................................. 2 1. block diagram .............................................................. 4 2. connection diagrams .................................................. 5 3. input/output descriptions ........................................... 6 4. logic symbol ............................................................... 6 5. ordering information ................................................... 7 5.1 valid combinations ........................................................ 7 6. spi modes ..................................................................... 8 7. device operations ....................................................... 9 7.1 byte or page programming............................................ 9 7.2 sector erase / bulk erase.............................................. 9 7.3 monitoring write operations using the status register 9 7.4 active power and standby power modes...................... 9 7.5 status register .............................................................. 9 7.6 data protection modes .................................................. 9 7.7 hold mode (hold#) .................................................... 11 8. sector address table ................................................ 11 9. parallel mode (for 16-pin so package only) ............ 15 10. accelerated programming operation ...................... 15 11. command definitions ................................................ 16 11.1 read data bytes (read: 03h) . .............. .............. ....... 16 11.2 read data bytes at higher speed (fast_read: 0bh) 17 11.3 read identification (rdid: 9f h)........... .............. .......... 18 11.4 read manufacturer and device id (read_id: 90h) 19 11.5 write enable (wren: 06h) .......................................... 20 11.6 write disable (wrdi: 04h)........................................... 21 11.7 read status register (rdsr: 05h) ............................. 21 11.8 write status register (wrsr: 01h)............................. 24 11.9 page program (pp: 02h).............................................. 25 11.10sector erase (se: 20h, d8h) .......... ........... ........... ....... 26 11.11bulk erase (be: c7h, 60h) .......................................... 27 11.12deep power down (dp: b9h) ...................................... 28 11.13release from deep power down }(res: abh) ................................................................. 29 11.14release from deep power down and read electronic signature (res: abh) ........................ 29 11.15command definiti ons .................................................. 31 12. program acceleration via wp#/acc pin .................. 32 13. power-up and power-down ....................................... 33 14. initial delivery state ................................................... 35 15. absolute maximum ratings ...................................... 35 16. operating ranges ...................................................... 36 17. dc characteristics ..................................................... 36 18. test conditions ........................................................... 37 19. ac characteristics ...................................................... 38 19.1 capacitance ............ .............. ........... ........... ........... ....... 39 20. physical dimensions .................................................. 41 20.1 so3 016 wide ? 16-pin plastic small outline package (300-mil body width) .....................................41 20.2 wnf008 ? wson 8-contact (6 x 8 mm) no-lead package ........................................................................42 21. revision history .......................................................... 43
document number: 002-00646 rev. *m page 4 of 45 S25FL128P 1. block diagram sram ps logic array - l array - r rd data path io x d e c cs# sck si so/po[7-0] gnd hold# wp#/acc v cc
document number: 002-00646 rev. *m page 5 of 45 S25FL128P 2. connection diagrams figure 2.1 16-pin plastic small outline package (so) figure 2.2 8-pin wson package (6 x 8 mm) note: there is an exposed central pad on the under side of the wson package. this should no t be connected to any voltage or signal lin e on the pcb. connecting the central pad to gnd (v ss ) is possible, provided pcb routing ensures 0m v difference between voltage at the wson gnd (v ss ) lead and the central exposed pad. 1 2 3 4 16 15 14 13 hold# vcc nc po2 po5 po6 si sck 5 6 7 8 12 11 10 9 wp#/acc gnd po3 po4 po1 po0 cs# so/po7 1 2 3 4 5 6 7 8 cs# v cc so hold# sck si gnd wson wp#/acc
document number: 002-00646 rev. *m page 6 of 45 S25FL128P 3. input/output descriptions 4. logic symbol signal name i/o description so (signal data output) output transfers data seri ally out of the device on the falling edge of sck. po[7?0] (parallel data input/output) input/output transfers parallel data into the device on the rising edge of sck or out of the device on the falling edge of sck. si (serial data input) input transfers data serially into the device . device latches commands, addresses, and program data on si on the rising edge of sck. sck (serial clock) input provides serial interface timing. latches commands, addresses, and data on si on rising edge of sck. triggers output on so after the falling edge of sck. cs# (chip select) input places device in active power mode when driven low. deselects device and places so at high impedance when high. after power-up, device requires a falling edge on cs# before any command is written. device is in standby mode when a program, erase, or write status register operation is not in progress. hold# (hold) input pauses any serial communication with the device without deselecting it. when driven low, so is at high impedance, and all input at si and sck are ignored. requires that cs# also be driven low. wp#/acc (write protect/accelerated programming) input when driven low, prevents any program or erase command from altering the data in the protected memory area specified by status regi ster bits (bp bits). if the system asserts v hh on this pin, accelerated programming operation is provided. v cc input supply voltage gnd input ground cs# so wp#/acc gnd si sck hold# v cc po[7-0] (for 16-pin so package)
document number: 002-00646 rev. *m page 7 of 45 S25FL128P 5. ordering information this product is not recommended for new and current designs. for new and current designs, s25fl128s supersedes S25FL128P. this is the factory-recommended migratio n path. please refer to the s25fl128s dat a sheet for specifications and ordering information. the ordering part number is formed by a valid combination of the following: table 5.1 S25FL128P valid combinations table note package marking omits leading ?s25? and speed, package, and model number form. 5.1 valid combinations table 5.1 lists the valid combinations configurations pl anned to be supported in volume for this device. s25fl 128 p 0x m f i 00 1 packing type 0 = tray 1 = tube 3 = 13? tape and reel model number (additiona l ordering options) 00 = uniform 64 kb sector product 01 = uniform 256 kb sector product temperature range i = industrial (?40c to + 85c) package materials f = lead (pb)-free package type m = 16-pin so package n = 8-pin wson package speed 0x = 104 mhz device technology p = 0.09 m mirrorbit ? process technology density 128= 128 mbit device family s25fl cypress memory 3.0 volt-only, serial peripheral interface (spi) flash memory S25FL128P valid combinations package marking (see note) base ordering part number speed option package & temperature model number packing type S25FL128P 0x mfi, nfi 00 0, 1, 3 fl128p + i + f 01 fl128p + i + fl
document number: 002-00646 rev. *m page 8 of 45 S25FL128P 6. spi modes a microcontroller can use either of its two spi m odes to control cypress spi flash memory devices: ? cpol = 0, cpha = 0 (mode 0) ? cpol = 1, cpha = 1 (mode 3) input data is latched in on the rising e dge of sck, and output data is available fr om the falling edge of sck for both modes. when the bus master is in stan dby mode, sck is as shown in figure 6.2 for each of the two modes: ? sck remains at 0 for (cpol = 0, cpha = 0 mode 0) ? sck remains at 1 for (cpol = 1, cpha = 1 mode 3) figure 6.1 bus master and memory devices on the spi bus note the write protect/accelerated programming (wp#/acc) and hold (hol d#) signals should be driven high (logic level 1) or low (logi c level 0) as appropriate. figure 6.2 spi modes supported spi interface with (cpol, cpha) = (0, 0) or (1, 1) bus master cs3 cs2 cs1 spi memory device spi memory device spi memory device cs# hold# cs# hold# cs# wp#/acc wp#/acc wp#/acc hold# sck so si sck so si sck so si so si sck msb msb sck sck si so cpha cpol 00 11 cs# mode 0 mode 3
document number: 002-00646 rev. *m page 9 of 45 S25FL128P 7. device operations all cypress spi devices (s25fl-p) accept a nd output data in bytes (8 bits at a time). 7.1 byte or page programming programming data requires two commands: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of four bytes plus data. the page program sequence accept s from 1 byte up to 256 consecut ive bytes of data (which is t he size of one page) to be programmed in one operation. programming means that bits can either be left at the current state (1 or 0), or programmed from 1 to 0. changing bits from 0 to 1 requires an er ase operation. before this can be applied, the bytes of the mem ory need to be first erased to all 1?s (ffh) before any programming. 7.2 sector erase / bulk erase the sector erase (se) and bulk erase (be) co mmands set all the bits in a sector or the entire memory array to 1. while bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (se) or array-wide (be) level. th e memory array needs to be first erased to all 1's (ffh) before any programming. 7.3 monitoring write operations using the status register the host system can determine when a write status register, program, or erase operation is complete by monitoring the write in progress (wip) bit in the status register. the read from st atus register command provides the state of the wip bit. 7.4 active power and standby power modes the device is enabled and in the active power mode when chip se lect (cs#) is low. when cs# is high, the device is disabled, but may still be in the active power mode until all program, erase, and write status register operatio ns have completed. the device then goes into the standby power mode, and power consumption drops to i sb . the deep power down (dp) command provides additional data protection against inadvertent signals. after wr iting the dp command, the device ignores any further program or erase commands, and reduces its power consumption to i dp . 7.5 status register the status register contains the status and control bits that can be read or set by specific commands (see table table 11.6, command definitions on page 31 ): ? write in progress (wip): indicates whether the device is performing a write status register, program or erase operation. ? write enable latch (wel): indicates the status of th e internal write enable latch. ? block protect (bp2, bp1, bp0 for uniform 256 kb sector pr oduct: bp3, bp2, bp1, bp0 for uniform 64 kb sector product): non-volatile bits that define memory area to be software-protected against program and erase commands. ? status register write disable (srwd): places the device in the hardware protected mode when this bit is set to 1 and the wp#/acc input is driven low. in this mode, the non-volatile bits of the stat us register (srwd, bp3, bp2, bp1, bp0) become read-only bits.
document number: 002-00646 rev. *m page 10 of 45 S25FL128P 7.6 data protection modes cypress spi flash memory devices provi de the following data protection methods: ? the write enable (wren) command: must be written prior to any command that modifies data. the wren command sets the write enable latch (wel) bit. the wel bit resets (disables writes) on power-up or after the device completes the following commands : ? page program (pp) ? sector erase (se) ? bulk erase (be) ? write disable (wrdi) ? write status register (wrsr) ? software protected mode (spm): the block protect (bp2, bp1, bp0 for unifo rm 256 kb sector product: bp3, bp2, bp1, bp0 for uniform 64 kb sector product) bits define the section of the memory array that can be read but not programmed or erased. table 7.1 shows the sizes and address ranges of protected areas that are defined by status register bits bp2:bp0 for uniform 256 kb sector product, bp3:bp0 for uniform 64 kb sector product). ? hardware protected mode (hpm): the write protect (wp#/acc) input and the status register write disable (srwd) bit together provide write protection. ? clock pulse count: the device verifies that all program, erase, and wr ite status register commands consist of a clock pulse count that is a multiple of eight before executing them. table 7.1 S25FL128P protected area size s (uniform 256 kb sector) status register block protect bits memory array protected portion of total memory area bp2 bp1 bp0 protected address range protected sectors unprotected address range unprotected sectors 0 0 0 none (0) 000000h-ffffffh (64) sa63:sa0 0 0 0 1 fc0000h-ffffffh (1) sa63 000000h-fbffffh (32) sa62:sa0 1/64 010f800 00h-ffffffh (2) sa63:sa62 000000h-f7ffffh (16) sa61:sa0 1/32 011f000 00h-ffffffh (4) sa63:sa60 000000h-efffffh (8) sa59:sa0 1/16 1 0 0 e00000h-ffffffh (8) sa63:sa56 000000h-dfffffh (4) sa55:sa0 1/8 1 0 1 c00000h-ffffffh (16) sa63:sa48 000000h-bfffffh (2) sa47:sa0 1/4 1 1 0 800000h-ffffffh (32) sa63:sa32 000000h-7fffffh (1) sa31:sa0 1/2 1 1 1 000000h-ffffffh (64) sa63:sa0 none (0) all table 7.2 S25FL128P protected area sizes (uniform 64 kb sector) status register block protect bits memory array protected portion of total memory area bp3 bp2 bp1 bp0 protected address range protected sectors unprotected address range unprotected sectors 0 0 0 0 none (0) 000000h-ffffffh (256) sa255:sa0 0 0 0 0 1 fe0000h-ffffffh (2) sa255:sa254 000000h-fdffffh (128) sa253:sa0 1/128 0 0 1 0 fc0000h-ffffffh (4) sa255:sa252 000000h-fbffffh (64) sa251:sa0 1/64 0 0 1 1 f80000h-ffffffh (8) sa255:sa248 000000h-f7ffffh (32) sa247:sa0 1/32 0 1 0 0 f00000h-ffffffh (16) sa255:sa240 000000h-efffffh (16) sa239:sa0 1/16 0 1 0 1 e00000h-ffffffh (32) sa255:sa224 000000h-dfffffh (8) sa223:sa0 1/8 0 1 1 0 c00000h-ffffffh (64) sa255:sa192 000000h-bfffffh (4) sa191:sa0 1/4 0 1 1 1 800000h-ffffffh (128) sa255:sa128 000000h-7fffffh (2) sa127:sa0 1/2 1 0 0 0 000000h-ffffffh (256) sa255:sa0 none (0) all 1 0 0 1 000000h-ffffffh (256) sa255:sa0 none (0) all
document number: 002-00646 rev. *m page 11 of 45 S25FL128P 7.7 hold mode (hold#) the hold input (hold#) stops any serial communication with the dev ice, but does not terminate any write status register, progra m or erase operation that is currently in progress. the hold mode starts on the falling e dge of hold# if sck is also low (see figure 7.1 on page 11 , standard use). if the falling edge of hold# does not occur while sck is low, the hold mode begi ns after the next falling edge of sck (non-standard use). the hold mode ends on the rising edge of ho ld# signal (standard use) if sck is also low. if the rising edge of hold# does not occur while sck is low, the hold mode ends on th e next falling edge of clk (non-standard use) see figure 7.1 . the so output is high impedance, and the si and sck inputs are ignored (don?t care) for the duration of the hold mode. cs# must remain low for the entire duration of the hold mode to ensure that the device internal logic remains unchanged. if cs# goes high while the device is in the hold mode, the internal logi c is reset. to prevent the device from reverting to the hold m ode when device communication is resumed, hold# mu st be held high, followed by driving cs# low. figure 7.1 hold mode operation 8. sector address table table 8.1 shows the size of the memory array, sectors, and pages. the device uses pages to cache the program data before the data is programmed into the memory array. each page or byte ca n be individually programmed (bits are changed from 1 to 0). the data is erased (bits are changed from 0 to 1) on a se ctor- or device-wide basis using the se or be commands. table 8.2 shows the starting and ending address for each sector. the complete set of sectors comprises the memory array of the flash device. 1 0 1 0 000000h-ffffffh (256) sa255:sa0 none (0) all 1 0 1 1 000000h-ffffffh (256) sa255:sa0 none (0) all 1 1 0 0 000000h-ffffffh (256) sa255:sa0 none (0) all 1 1 0 1 000000h-ffffffh (256) sa255:sa0 none (0) all 1 1 1 0 000000h-ffffffh (256) sa255:sa0 none (0) all 1 1 1 1 000000h-ffffffh (256) sa255:sa0 none (0) all table 8.1 S25FL128P device organization each device has each sector has each page has 16,777,216 262144 (256 kb sector) 65536 (64 kb sector) 256 bytes 65,536 1024 (256 kb sector) 256 (64 kb sector) ? pages 64 (256 kb sector) 256 (64 kb sector) ? ? sectors table 7.2 S25FL128P protected area sizes (uniform 64 kb sector) (continued) sck hold# hold condition (standard use) hold condition (non-standard use)
document number: 002-00646 rev. *m page 12 of 45 S25FL128P table 8.2 S25FL128P sector address table (uniform 256 kb sector) sector address range sector address range 63 fc0000h ffffffh 31 7c0000h 7fffffh 62 f80000h fbffffh 30 780000h 7bffffh 61 f40000h f7ffffh 29 740000h 77ffffh 60 f00000h f3ffffh 28 700000h 73ffffh 59 ec0000h efffffh 27 6c0000h 6fffffh 58 e80000h ebffffh 26 680000h 6bffffh 57 e40000h e7ffffh 25 640000h 67ffffh 56 e00000h e3ffffh 24 600000h 63ffffh 55 dc0000h dfffffh 23 5c0000h 5fffffh 54 d80000h dbffffh 22 580000h 5bffffh 53 d40000h d7ffffh 21 540000h 57ffffh 52 d00000h d3ffffh 20 500000h 53ffffh 51 cc0000h cfffffh 19 4c0000h 4fffffh 50 c80000h cbffffh 18 480000h 4bffffh 49 c40000h c7ffffh 17 440000h 47ffffh 48 c00000h c3ffffh 16 400000h 43ffffh 47 bc0000h bfffffh 15 3c0000h 3fffffh 46 b80000h bbffffh 14 380000h 3bffffh 45 b40000h b7ffffh 13 340000h 37ffffh 44 b00000h b3ffffh 12 300000h 33ffffh 43 ac0000h afffffh 11 2c0000h 2fffffh 42 a80000h abffffh 10 280000h 2bffffh 41 a40000h a7ffffh 9 240000h 27ffffh 40 a00000h a3ffffh 8 200000h 23ffffh 39 9c0000h 9fffffh 7 1c0000h 1fffffh 38 980000h 9bffffh 6 180000h 1bffffh 37 940000h 97ffffh 5 140000h 17ffffh 36 900000h 93ffffh 4 100000h 13ffffh 35 8c0000h 8fffffh 3 0c0000h 0fffffh 34 880000h 8bffffh 2 080000h 0bffffh 33 840000h 87ffffh 1 040000h 07ffffh 32 800000h 83ffffh 0 000000h 03ffffh
document number: 002-00646 rev. *m page 13 of 45 S25FL128P table 8.3 S25FL128P sector address table (uniform 64 kb sector) sector address range sector address range sector address range 255 ff0000h ffffffh 207 cf0000h cfffffh 159 9f0000h 9fffffh 254 fe0000h feffffh 206 ce0000h ceffffh 158 9e0000h 9effffh 253 fd0000h fdffffh 205 cd0000h cdffffh 157 9d0000h 9dffffh 252 fc0000h fcffffh 204 cc0000h ccffffh 156 9c0000h 9cffffh 251 fb0000h fbffffh 203 cb0000h cbffffh 155 9b0000h 9bffffh 250 fa0000h faffffh 202 ca0000h caffffh 154 9a0000h 9affffh 249 f90000h f9ffffh 201 c90000h c9ffffh 153 990000h 99ffffh 248 f80000h f8ffffh 200 c80000h c8ffffh 152 980000h 98ffffh 247 f70000h f7ffffh 199 c70000h c7ffffh 151 970000h 97ffffh 246 f60000h f6ffffh 198 c60000h c6ffffh 150 960000h 96ffffh 245 f50000h f5ffffh 197 c50000h c5ffffh 149 950000h 95ffffh 244 f40000h f4ffffh 196 c40000h c4ffffh 148 940000h 94ffffh 243 f30000h f3ffffh 195 c30000h c3ffffh 147 930000h 93ffffh 242 f20000h f2ffffh 194 c20000h c2ffffh 146 920000h 92ffffh 241 f10000h f1ffffh 193 c10000h c1ffffh 145 910000h 91ffffh 240 f00000h f0ffffh 192 c00000h c0ffffh 144 900000h 90ffffh 239 ef0000h efffffh 191 bf0000h bfffffh 143 8f0000h 8fffffh 238 ee0000h eeffffh 190 be0000h beffffh 142 8e0000h 8effffh 237 ed0000h edffffh 189 bd0000h bdffffh 141 8d0000h 8dffffh 236 ec0000h ecffffh 188 bc0000h bcffffh 140 8c0000h 8cffffh 235 eb0000h ebffffh 187 bb0000h bbffffh 139 8b0000h 8bffffh 234 ea0000h eaffffh 186 ba0000h baffffh 138 8a0000h 8affffh 233 e90000h e9ffffh 185 b90000h b9ffffh 137 890000h 89ffffh 232 e80000h e8ffffh 184 b80000h b8ffffh 136 880000h 88ffffh 231 e70000h e7ffffh 183 b70000h b7ffffh 135 870000h 87ffffh 230 e60000h e6ffffh 182 b60000h b6ffffh 134 860000h 86ffffh 229 e50000h e5ffffh 181 b50000h b5ffffh 133 850000h 85ffffh 228 e40000h e4ffffh 180 b40000h b4ffffh 132 840000h 84ffffh 227 e30000h e3ffffh 179 b30000h b3ffffh 131 830000h 83ffffh 226 e20000h e2ffffh 178 b20000h b2ffffh 130 820000h 82ffffh 225 e10000h e1ffffh 177 b10000h b1ffffh 129 810000h 81ffffh 224 e00000h e0ffffh 176 b00000h b0ffffh 128 800000h 80ffffh 223 df0000h dfffffh 175 af0000h afffffh 127 7f0000h 7fffffh 222 de0000h deffffh 174 ae0000h aeffffh 126 7e0000h 7effffh 221 dd0000h ddffffh 173 ad0000h adffffh 125 7d0000h 7dffffh 220 dc0000h dcffffh 172 ac0000h acffffh 124 7c0000h 7cffffh 219 db0000h dbffffh 171 ab0000h abffffh 123 7b0000h 7bffffh 218 da0000h daffffh 170 aa0000h aaffffh 122 7a0000h 7affffh 217 d90000h d9ffffh 169 a90000h a9ffffh 121 790000h 79ffffh 216 d80000h d8ffffh 168 a80000h a8ffffh 120 780000h 78ffffh 215 d70000h d7ffffh 167 a70000h a7ffffh 119 770000h 77ffffh 214 d60000h d6ffffh 166 a60000h a6ffffh 118 760000h 76ffffh 213 d50000h d5ffffh 165 a50000h a5ffffh 117 750000h 75ffffh 212 d40000h d4ffffh 164 a40000h a4ffffh 116 740000h 74ffffh 211 d30000h d3ffffh 163 a30000h a3ffffh 115 730000h 73ffffh 210 d20000h d2ffffh 162 a20000h a2ffffh 114 720000h 72ffffh
document number: 002-00646 rev. *m page 14 of 45 S25FL128P 209 d10000h d1ffffh 161 a10000h a1ffffh 113 710000h 71ffffh 208 d00000h d0ffffh 160 a00000h a0ffffh 112 700000h 70ffffh 111 6f0000h 6fffffh 71 470000h 47ffffh 31 1f0000h 1fffffh 110 6e0000h 6effffh 70 460000h 46ffffh 30 1e0000h 1effffh 109 6d0000h 6dffffh 69 450000h 45ffffh 29 1d0000h 1dffffh 108 6c0000h 6cffffh 68 440000h 44ffffh 28 1c0000h 1cffffh 107 6b0000h 6bffffh 67 430000h 43ffffh 27 1b0000h 1bffffh 106 6a0000h 6affffh 66 420000h 42ffffh 26 1a0000h 1affffh 105 690000h 69ffffh 65 410000h 41ffffh 25 190000h 19ffffh 104 680000h 68ffffh 64 400000h 40ffffh 24 180000h 18ffffh 103 670000h 67ffffh 63 3f0000h 3fffffh 23 170000h 17ffffh 102 660000h 66ffffh 62 3e0000h 3effffh 22 160000h 16ffffh 101 650000h 65ffffh 61 3d0000h 3dffffh 21 150000h 15ffffh 100 640000h 64ffffh 60 3c0000h 3cffffh 20 140000h 14ffffh 99 630000h 63ffffh 59 3b0000h 3bffffh 19 130000h 13ffffh 98 620000h 62ffffh 58 3a0000h 3affffh 18 120000h 12ffffh 97 610000h 61ffffh 57 390000h 39ffffh 17 110000h 11ffffh 96 600000h 60ffffh 56 380000h 38ffffh 16 100000h 10ffffh 95 5f0000h 5fffffh 55 370000h 37ffffh 15 0f0000h 0fffffh 94 5e0000h 5effffh 54 360000h 36ffffh 14 0e0000h 0effffh 93 5d0000h 5dffffh 53 350000h 35ffffh 13 0d0000h 0dffffh 92 5c0000h 5cffffh 52 340000h 34ffffh 12 0c0000h 0cffffh 91 5b0000h 5bffffh 51 330000h 33ffffh 11 0b0000h 0bffffh 90 5a0000h 5affffh 50 320000h 32ffffh 10 0a0000h 0affffh 89 590000h 59ffffh 49 310000h 31ffffh 9 090000h 09ffffh 88 580000h 58ffffh 48 300000h 30ffffh 8 080000h 08ffffh 87 570000h 57ffffh 47 2f0000h 2fffffh 7 070000h 07ffffh 86 560000h 56ffffh 46 2e0000h 2effffh 6 060000h 06ffffh 85 550000h 55ffffh 45 2d0000h 2dffffh 5 050000h 05ffffh 84 540000h 54ffffh 44 2c0000h 2cffffh 4 040000h 04ffffh 83 530000h 53ffffh 43 2b0000h 2bffffh 3 030000h 03ffffh 82 520000h 52ffffh 42 2a0000h 2affffh 2 020000h 02ffffh 81 510000h 51ffffh 41 290000h 29ffffh 1 010000h 01ffffh 80 500000h 50ffffh 40 280000h 28ffffh 0 000000h 00ffffh 79 4f0000h 4fffffh 39 270000h 27ffffh 78 4e0000h 4effffh 38 260000h 26ffffh 77 4d0000h 4dffffh 37 250000h 25ffffh 76 4c0000h 4cffffh 36 240000h 24ffffh 75 4b0000h 4bffffh 35 230000h 23ffffh 74 4a0000h 4affffh 34 220000h 22ffffh 73 490000h 49ffffh 33 210000h 21ffffh 72 480000h 48ffffh 32 200000h 20ffffh table 8.3 S25FL128P sector address table (uniform 64 kb sector) (continued) sector address range sector address range sector address range
document number: 002-00646 rev. *m page 15 of 45 S25FL128P 9. parallel mode (for 16-pin so package only) the parallel mode provides 8 bits of input/ output to increase factory production thr oughput at the customer manufacturing facil ities. this function is recommended for increasing production throughput. entering parallel mode requires issuing the enter parallel m ode command (55h). after writing the parallel mode entry command and pulling cs# high, the available commands are read, write enable (wren), write disable (wrdi), page program (pp), sector erase (se), bulk er ase (be), write status register (wrsr), read status register (rdsr), release from deep power down/rel ease from deep power down and read electronic signature (res), deep power down (dp), read identification (rdid) and read id (read_id). the flash memory will remain in parallel mode until either the parallel mode exit command (45h) is issued, or until a power-dow n / power-up sequence has been completed, after which the flash memory will exit parallel mode automatically and switch back to ser ial mode (no power-down will be necessary to switch back to serial mode if the parallel mode exit command is issued). in parallel mode, the maximum sck clock frequency is limited to 6 mhz for read data bytes and 10 mhz for other operations. po[6-0] can be left unconnected if the parallel mode functions are not needed. fast-read command is not applicable in parallel mode. 10. accelerated programming operation the device offers accelerated program operat ions through the acc function. this functi on is primarily intended to allow faster manufacturing throughput at the fa ctory. if the system asserts v hh on this pin, the device uses the higher voltage on the pin to reduce the time required fo r program operations. removing v hh from the wp#/acc pin returns the device to normal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated pr ogramming, or device damage may result. in addition, the wp#/acc pin must not be left floating or unconnec ted; inconsistent behavior of the device may result.
document number: 002-00646 rev. *m page 16 of 45 S25FL128P 11. command definitions the host system must shift all commands, addresses, and data in and out of the device, beginni ng with the most significant bit. on the first rising edge of sck after cs# is driven low, the device accepts the one-byte command on si (all commands are one byte long), most significant bit first. each successive bit is latched on the rising edge of sck. table 11.6 on page 31 lists the complete set of commands. every command sequence begins with a one-byte command code . the command may be followed by address, data, both, or nothing, depending on the command. cs# must be driven high af ter the last bit of the command sequence has been written. the read data bytes (read), read status register (rds r), read data bytes at higher speed (fast_read) and read identification (rdid) command s equences are followed by a data out put sequence on so. cs# can be driven high after any bit of the sequence is output to terminate the operation. the page program (pp), sector erase (se), bulk erase (be), wr ite status register (wrsr), wr ite enable (wren), or write disable (wrdi) commands require that cs# be driven high at a byte boundary, otherwis e the command is not executed. since a byte is composed of eight bits, cs# must therefore be driven high when th e number of clock pulses af ter cs# is driven low is an exact multiple of eight. the device ignores any attempt to access the memory array du ring a write status register, program, or erase operation, and continues the operation uninterrupted. 11.1 read data bytes (read: 03h) 11.1.1 serial mode the read data bytes (read-serial mode) command read s data from the memory array at the frequency (f sck ) presented at the sck input, with a maximum speed of 40 mhz. the host system must first select the device by driving cs# low. the read command is then written to si, followed by a 3-byte address (a23-a0). each bit is latched on the rising edge of sck. the memory array d ata, at that address, are output se rially on so at a frequency f sck , on the falling edge of sck. figure 11.1 and table 11.6 detail the read command sequence. the first byte specified can be at any location. the device automatically increments to the next higher address after each byte of data is output. the entire memory array can therefore be read with a single read command. when the highest address is re ached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. the read command is terminated by driving cs# high at any ti me during data output. the device rejects any read command issued while it is executing a program, eras e, or write status register operation, and continues the operation uninterrupted. figure 11.1 read data bytes (read) command sequence command 24-bit address hi-z msb msb data out 1 data out 2 0 31 32 33 34 35 36 37 38 39 30 29 28 10 9 8 7 6 5 4 3 2 1 7 6 5 23 22 21 4 3 2 1 0 3 2 10 7 so si sck cs# mode 3 mode 0
document number: 002-00646 rev. *m page 17 of 45 S25FL128P 11.1.2 parallel mode in parallel mode, the maximum sc k clock frequency is 6 mhz. the device requires a single clock cycle instead of eight clock cycl es to access the next data byte. the memory array output will be the sa me as in the serial mode. the only difference is that a byt e of data is output per clock cycle in stead of a single bit. this me ans that 256 bytes of data can be copied into t he 256 byte wide page write buffer in 256 clock cycles instead of in 2,048 clock cycles. figure 11.2 parallel read instruction sequence notes 1. 1st byte = ?03h?. 2. 2nd byte = address 1, msb first (bits 23 through 16). 3. 3rd byte = address 2, msb first (bits 15 through 8). 4. 4th byte = address 3, msb first (bits 7 through 0). 5. from the 5th byte, so will output the array data. 6. in parallel mode, the maximum clock frequency (fsck) is 6 mhz. 7. for parallel mode operation, the device requires an enter parallel mode command (55h) before the read command. an exit parall el mode (45h) command or a power-down / power-up sequence is required to exit the parallel mode. 11.2 read data bytes at higher speed (fast_read: 0bh) the fast_read command reads data from the memory array at the frequency (f sck ) presented at the sck input, with a maximum speed of 104 mhz. the host system must first select the device by driving cs# low. the fast_read command is then written to si, followed by a 3-byte address (a23-a0) and a dummy byte. each bit is latched on the rising edge of sck. the memory array dat a, at that address, are output se rially on so at a frequency f sck , on the falling edge of sck. the fast_read command sequence is shown in figure 11.3 and table 11.6 . the first byte specified can be at any location. the device automatically increments to the next higher address after each byte of data is output. the entire memory array can there fore be read with a single fast_read command. when the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. the fast_read command is terminated by driving cs# high at any time during data output. the device rejects any fast_read command issued while it is executing a program, erase, or wr ite status register operation, and continues the operation uninterrupted. note that the fast_read command is not valid in parallel mode. figure 11.3 read data bytes at higher speed (fast_read) command sequence cs# sck si po[7-0] high impedance data out instruction 24-bit address cs# sck si so command 24-bit address dummy byte hi-z data out 1 data out 2 msb msb 01 2 34 56 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 23 22 21 3 2 1 0 7 654 3 2 1 0 7 6 5 4 3 210 7 mode 3 mode 0
document number: 002-00646 rev. *m page 18 of 45 S25FL128P 11.3 read identification (rdid: 9fh) 11.3.1 serial mode the read identification (rdid) instruction opcode allows the 8-bit manufacturer identification to be read, follow by two bytes of device identification. the manufacturer identification is assigned by jedec. the device identificat ion is assigned by the devic e manufacturer. any read identification (rdid) instruction opcode issued while a program, erase, or write cycle is in progress is not decoded a nd has no effect on execution of the program, erase, or write cycle that is in progress. the device is first selected by driving the cs# chip select i nput pin to the logic low state. after this, the rdid 8-bit instru ction opcode is shifted in onto the si serial input pin. after the last bit of the rdid instructio n opcode is shifted into the device, a byt e of manufacturer identification, tw o bytes of device identification and two bytes of extended device identification will be shifted sequentially out of the so serial output pin. each bit is shif ted out during the falling edge of the sck serial clock signal. t he maximum clock frequency for the rdid (9fh) command is at 40 mhz (normal read). the read identification (rdid) in struction sequence is terminated by driving the cs# chip select input pin to the logic high st ate anytime during data output. after issuing any read id instructio n opcodes (90h, 9fh, abh), driving the cs# chip select input pi n to the logic high state will automatically send the device into t he standby mode. driving the cs# chip select input pin to the log ic low state again will automatically send the device out of the standby mode and into the active mode. figure 11.4 read identification command sequence and data out sequence 11.3.2 parallel mode in parallel mode, the maximum sck clock frequency is 10 mhz. th e device requires a single clock cycle instead of eight clock cycles to access the ne xt data byte. the method of memory content output will be the same compared to the serial mode. the only difference is that a byte of data is outp ut per clock cycle instead of a single bit. in this case, the manufacturer identificat ion will be output during the first byte cycl e and the device identifi cation during the se cond and third byte cycles out of the po7-po0 ser ial output pins. to read id in parallel mode requires a parallel mode entry command (55h) to be i ssued before the rdid command. once in the parallel mode, the flash memory will not exit paralle l mode until a parallel mode exit (45h) command is given to th e flash device, or upon power down/power up sequence. figure 11.5 parallel read_id command sequence and data out sequence cs# sck si so high impedance manufacturer / device identification extended device identification msb msb instruction 012345678910 28 23 22 21 15 14 13 3210 3210 29 30 31 32 33 34 44 45 46 47 cs# sck si po[7-0] high impedance instruction manufacturer/device identification 012 3456789101112 byte 0 byte 1 byte 2 byte 3 byte 4
document number: 002-00646 rev. *m page 19 of 45 S25FL128P 11.4 read manufacturer a nd device id (read_id: 90h) 11.4.1 serial mode the read_id (90h) instruction identifies the device manufacturer id and the device id. the instruction is initiated by driving the cs# pin low and shifting in (via the si in put pin) the instruction code ?90h? follow ed by a 24-bit address of xxxxx0h. (x: high or low) following this, the manufacturer id and the device id are shifted out on so output pin st arting after the falling edge of the sck serial clock input signal. the ma nufacturer id and the device id are always shifted out on the so output pin with the msb first , as shown in figure 11.6 . if the 24-bit address is set to xxxxx1h, then the device id is read out first follo wed by the manufacturer id. note that the upper 23 bits of the address do not have to be 0?s and can be don?t cares. once the device is in read_id mode, th e manufacturer id and device id output data toggles between address 000000h and 000001h until terminated by a low to high transition on the cs# input pin. after the first 24-bit a ddress is provided, the user must wait 16 clock cycles for both the ma nufacturer id and device id to be output on the so output pin. the maxi mum clock frequency for the read_id (90h) command is at 104mhz (fast read). parallel mode the maxi mum clock frequency is 10 mhz. the manufacturer id & device id is outpu t continuously until terminated by a low to high transition on cs# chip select input pi n. after issuing read_id instruction, driving the cs# chip select input pin to the logic high state will automatically send the de vice into the standby mode. driving the cs# chip select input pin to the logic low state again will automatically send the device out of the standby mode and into the active mode. figure 11.6 serial read_id instruction sequence table 11.1 manufacturer & device id entification, rdid (9fh) device manufacturer identification device identi fication extended device identification byte 0 byte 1 byte 2 byte 3 byte 4 uniform 256 kb sector 01h 20h 18h 03h 00h uniform 64 kb sector 01h 20h 18h 03h 01h cs# sck si so high impedance 24-bit address high impedance instruction 90h 01234567 23 22 21 20 19 18 17 16 8 9 10 11 12 13 14 15 15 14 13 12 11 10 9 8 16 17 18 19 20 21 22 23 cs# sck si so high impedance manufacturer id device id 24-bit address msb msb 76543210 7654321076543210 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
document number: 002-00646 rev. *m page 20 of 45 S25FL128P 11.4.2 parallel mode the maximum clock frequency allowed on the sck input pin in pa rallel mode is 10 mhz. the parallel mode entry command (55h) must be issued before writing the read_id co mmand. once in the parallel mode, the fl ash memory will not exit parallel mode unti l a parallel mode exit (45h) command is given to the flash device, or upon power-down/power-up sequence. figure 11.7 parallel read_id instruction sequence 11.5 write enable (wren: 06h) the write enable (wren) command (see figure 11.8 ) sets the write enable latch (wel) bit to a 1, which enables the device to accept a write status register, program, or erase command. the wel bit must be set pr ior to every page program (pp), erase (se or be) and write status register (wrsr) command. the host system must first drive cs# low, wr ite the wren command, and then drive cs# high. figure 11.8 write enable (wren) command sequence table 11.2 read_id command and data description address data manufacturer identification 00000h 01h device identification (memory capacity) 00001h 17h 1 31 20 0 instruction 2 dummy bytes 15 13 14 1 32 0 high impedance msb 90h manufacture id device id 7 28 29 20 31 32 3 add (1) byte 1 byte 2 1 32 0 7654 3 24 25 26 2 22 0 21 2 3 34 3 cs# sck si po[7-0] 456789 cs# sck si so/po[7-0] hi-z command 01 23 4 5 67 mode 3 mode 0
document number: 002-00646 rev. *m page 21 of 45 S25FL128P 11.6 write disable (wrdi: 04h) the write disable (wrdi) command (see figure 11.9 ) resets the write enable latch (wel) bi t to a 0, which disables the device from accepting a write status register, program, or erase comma nd. the host system must first drive cs# low, write the wrdi command, and then drive cs# high. any of following conditions resets the wel bit: ? power-up ? write disable (wrdi) command completion ? write status register (wrsr) command completion ? page program (pp) command completion ? sector erase (se) command completion ? bulk erase (be) command completion figure 11.9 write disable (wrdi) command sequence 11.7 read status register (rdsr: 05h) 11.7.1 serial mode the read status register (rdsr) command out puts the state of the st atus register bits. table 11.3 shows the status register bits and their functions. the rdsr command may be written at any time, even while a program, erase, or write status regi ster operation is in progress. the host system should check the write in progress (wip) bit be fore sending a new command to the device if an operation is already in progress. figure 11.10 shows the rdsr command sequence, which also s hows that it is possible to read the status register continuously unt il cs# is driven high. table 11.3 S25FL128P status register (uniform 256 kb sector) bit status register bit bit function description 7 srwd status register write disable 1 = protects when wp#/acc is low 0 = no protection, even when wp#/acc is low 6 don?t care ? ? 5 0 ? not used 4bp2 block protect 000?111 = protects upper half of address range in 7 sizes. 3bp1 2bp0 0 1 2 34 5 6 7 command cs# hi-z sck si so/po[7-0] mode 3 mode 0
document number: 002-00646 rev. *m page 22 of 45 S25FL128P figure 11.10 read status register (rdsr) command sequence 1 wel write enable latch 1 = device accepts write status register, program, or erase commands 0 = ignores write status register, program, or erase commands 0 wip write in progress 1 = device busy. a write status register, program, or erase operation is in progress 0 = ready. device is in standby mode and can accept commands. table 11.4 S25FL128P status register (uniform 64 kb sector) bit status register bit bit function description 7 srwd status register write disable 1 = protects when wp#/acc is low 0 = no protection, even when wp#/acc is low 6 don?t care ? ? 5bp3 block protect 0000?1111= protects upper half of address range in 8 sizes. 4bp2 3bp1 2bp0 1 wel write enable latch 1 = device accepts write status register, program, or erase commands 0 = ignores write status register, program, or erase commands 0 wip write in progress 1 = device busy. a write status register, program, or erase operation is in progress 0 = ready. device is in standby mode and can accept commands. table 11.3 S25FL128P status register (uniform 256 kb sector) (continued) command hi-z msb msb status register out status register out 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 7 6 5 4 3 2 10 7 6 5 4 3 2 1 0 7 so si sck cs# mode 3 mode 0
document number: 002-00646 rev. *m page 23 of 45 S25FL128P 11.7.2 parallel mode when the device is in parall el mode, the maximum sck clock frequency is 10 mhz. the device re quires a single clock cycle instea d of eight clock cycles to access th e next data byte. the method of memory content output will be the same compared to outside of parallel mode. the only difference is that a byte of data is output per clock cycle in stead of a single bi t. the status registe r contents can be read out on the po[7-0] serial output pins continuously by applying multiples of clock cycles. figure 11.11 parallel read status register (rdsr) instruction sequence notes 1. instruction byte = 05h. 2. under parallel mode, the fastest access clock frequency (fsck) will be changed to a maximum of 10mhz (sck pin clock frequency ). 3. to read status register in parallel mode requires a parallel mode entry command (55h) to be issued before the rdsr command. o nce in the parallel mode, the flash memory will not exit the parallel mode until a parallel mode exit (45h) command is given to the flash device, or upon power dow n / power up sequence. 11.7.3 status register bit descriptions the following describes the status and cont rol bits of the status register, and applies to both serial and parallel modes. write in progress (wip) bit: indicates whether the device is busy performing a write status regi ster, program, or erase operation. this bit is read-only, and is controlled internally by the device . if wip is 1, one of these operat ions is in progress; if wip is 0, no such operation is in progress. write enable latch (wel) bit: determines whether the device will accept and exec ute a write status regist er, program, or erase command. when set to 1, the device accepts t hese commands; when set to 0, the device rejects the commands. this bit is set to 1 by writing the wren command, and set to 0 by the wrdi command, and is also automatically reset to 0 after the completion of a write status register, program, or erase operation. wel cannot be directly set by the wrsr command. block protect (bp2, bp1, bp0) bits for uniform 256kb secto r product: (bp3, bp2, bp1, bp0) for uniform 64kb sector product: define the portion of the memory area that will be protected against any changes to the stored data. the write status register (wrsr) command controls these bits , which are non-volatile. when one or more of these bits is set to 1, the correspond ing memory area (see table 7.1 on page 10 ) is protected against page program (pp) and sector erase (se) commands. if the hardware protected mode is enabled, bp2:bp0 (or bp3:bp0) cannot be changed. the bulk erase (b e) command is executed only if all block protect bits are 0. status register writ e disable (srwd) bit: provides data protection when used toget her with the write protect (wp#/acc) signal. when srwd is set to 1 and wp#/acc is driv en low, the device enters the hardware pr otected mode. the non-v olatile bits of the status register (srwd, bp2, bp1, bp0) be come read-only bits and the device ignor es any write status register (wrsr) command. command hi-z status register out 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 mode 3 mode 0 byte 1 byte 2 byte n sck si cs# po[7-0]
document number: 002-00646 rev. *m page 24 of 45 S25FL128P 11.8 write status register (wrsr: 01h) the write status register (wrsr) command changes the bits in the status register . a write enable (wren) command, which itself sets the write enable latch (wel) in the status register, is required prior to writing the wrsr command. table 11.3, S25FL128P status register (uniform 256 kb sector) on page 21 shows the status register bits and their functions. the host system must drive cs# low, write the wr sr command, and the appropriate data byte on si ( figure 11.12 ). the wrsr command cannot change the state of the write enabl e latch (bit 1). the wren command must be used for that purpose. bit 0 is a status bit controlled internally by the flas h device. bits 6 and 5 are always read as 0 and have no user significance. the wrsr command also controls the value of the status re gister write disable (srwd) bit. the srwd bit and wp#/acc together place the device in the hardware protected mode (hpm). the device ignores all wrsr commands once it enters the hardware protected mode (hpm). table 11.5 shows that wp#/acc must be driven low and the srwd bit must be 1 for this to occur. figure 11.12 write status register (wrsr) command sequence figure 11.13 parallel write status register (wrsr) command sequence notes 1. instruction byte = 01h 2. in parallel mode, the maximum access clock fr equency (fsck) is 10 mhz (sck pin clock frequency). 3. writing to the status register in parallel mode requires a parallel mode entry command (55h) to be issued before the wrsr com mand. once in the parallel mode, the flash memory will not exit the parallel mode until a parallel mo de exit (45h) command is given to the flash device, or upon pow er-down or power-up sequence. note as defined by the values in the block protect (bp2, bp1, bp0) bits of the status register, as shown in table 7.1 on page 10 . table 11.5 protection modes wp#/acc signal srwd bit mode write protection of the status register protected area (see note) unprotected area (see note) 11 software protected (spm) status register is writable (if the wren command has set the wel bit). the values in the srwd, bp2, bp1 and bp0 (or bp3, bp2, bp1 and bp0) bits can be changed. protected against program and erase commands ready to accept page program and sector erase commands 10 00 01 hardware protected (hpm) status register is hardware write protected. the values in the srwd, bp2, bp1 and bp0 (or bp3, bp2, bp1 and bp0) bits cannot be changed. protected against program and erase commands ready to accept page program and sector erase commands hi-z msb command status register in cs# sck si so 0 12 3 4 5 6 7 76543210 8 9 10 11 12 13 14 15 mode 0 mode 3 hi-z command status register in cs# sck si po[7-0] 0 12 3 4 5 6 7 byte 1 8 9 10 11 12 13 14 15 mode 0 mode 3
document number: 002-00646 rev. *m page 25 of 45 S25FL128P table 11.5 shows that neither wp#/acc or srwd bit by themselves can enable hpm. the device can enter hpm either by setting the srwd bit after driving wp#/acc low, or by driving wp#/acc low after setting the srwd bit. however, the device disables hpm only when wp#/acc is driven high. note that hpm only protects against changes to the status re gister. since bp2:bp0 (or bp3:bp0) cannot be changed in hpm, the size of the protected area of the memory array cannot be changed. note that hpm provides no protection to the memory array area outside that specified by block protect bits (software protected mode, or spm). if wp#/acc is permanently tied high, hpm can never be activated, and only the spm (block protect bi ts of the status register) c an be used. 11.9 page program (pp: 02h) 11.9.1 serial mode the page program (pp) command changes specified bytes in the memory array (from 1 to 0 only ). a wren command is required prior to writing the pp command. the host system must drive cs# low, and th en write the pp command, three address bytes, and at least one data byte on si. cs# must be driven low for the entire duration of th e pp sequence. the command sequence is shown in figure 11.14 and table 11.6 . the device programs only the last 256 data bytes sent to the devi ce. if the number of data bytes exceeds this limit, the bytes sent before the last 256 bytes are discarded, and the device begins pr ogramming the last 256 bytes sent at the starting address of t he specified page. this may result in data being programmed into di fferent addresses within the same page than expected. if fewer than 256 data bytes are sent to device, they ar e correctly programmed at the requested addresses. the host system must drive cs# high after the device has latched the 8th bi t of the data byte, other wise the device does not ex ecute the pp command. the pp operation begins as soon as cs# is driven high. the device inte rnally controls the timing of the operati on, which requires a period of t pp . the status register may be read to check the value of the write in progress (wip) bit while the pp operation is in progress. the wip bit is 1 during the pp operation, and is 0 when the operation is completed. the device intern ally resets the write enable latch to 0 before the operation completes (the exact timing is not specified). the device does not execute a page program ( pp) command that specifies a page that is protected by the block protect bits (see table 7.1 on page 10 ). figure 11.14 page program (pp) command sequence 0 34 33 32 31 30 29 28 10 9 8 7 6 5 4 3 2 1 35 36 37 38 39 46 45 44 43 42 41 40 47 48 49 50 51 52 53 54 55 2073 2072 2076 2075 2074 2079 2078 2077 23 22 21 3 21 07 6 5 43 2 1 0 data byte 1 24-bit address command data byte 2 data byte 3 data byte 256 msb msb msb msb msb sck si sck si 7 65 4 3 2 1 0 76 54 321 0 7 6 5 43210 cs# cs# mode 0 mode 3
document number: 002-00646 rev. *m page 26 of 45 S25FL128P 11.9.2 parallel mode in parallel mode, the maximum sck clock frequency is 10 mhz. the device requires a single clock cycle instead of eight clock cycles to access the next data by te. the memory content input met hod is the same as serial mode . the only difference is that a byte of data is input per clock cycle in stead of a single bit. this m eans that 256 bytes of data can be copied into t he 256 byte wid e page write buffer in 256 clock cycles instead of in 2,048 clock cycles. figure 11.15 parallel page program (pp) instruction sequence notes 1. 1st byte = ?02h?. 2. 2nd byte = address 1, msb first (bits 23 through 16). 3. 3rd byte = address 2, msb first (bits 15 through 8). 4. 4th byte = address 3, msb first (bits 7 through 0). 5. 5th byte = first write data byte. 6. in parallel mode, the fastest access clock frequency (fsck) is 10 mhz (sck pin clock frequency). 7. programming in parallel mode requires an ?parallel mode entry? command (55h) before the program command. once in the parallel mode, the flash memory will not exit parallel mode until an ?exit parallel mode? (45h) command is given to the flash device, or upon power down / power up sequ ence completion. 11.10 sector erase (se: 20h, d8h) the sector erase (se) command sets all bits at all addresses with in a specified sector to a logic 1. a wren command is required prior to writing the se command. the host system must drive cs# low, and then write the se command plus three address bytes on si. any address within the sector (see table 7.1 on page 10 ) is a valid address for the se command. cs# must be driven low for the entire duration of the se sequence. the command sequence is shown in figure 11.16 and table 11.6 . the host system must drive cs# high after the device has latched the 24th bit of the address input, otherwise the device does n ot execute the command. the se operation begins as soon as cs# is driven high. the device internally controls the timing of the operation, which requires a period of t se . the status register may be read to check the value of the write in progress (wip) bit while the se operation is in progress. the wip bit is 1 during the se operation, and is 0 when the operation is completed. the device internally resets the write enable latch to 0 before the operation completes (the ex act timing is not specified). the device does not execute an se command that specifies a sector that is prot ected by the block protect bits (see table 7.1 on page 10 ). figure 11.16 sector erase (se) command sequence cs# 1 3 101112131415 2 0 instruction (02h) address byte 1 address byte 2 address byte 3 23 22 21 17 high-z msb 90h byte 1 byte 2 byte n 16 23 24 31 32 33 sck si po[7-0] 4 20 19 18 16 8 0 56789 15 7 n hi-z cs# sck si so/po[7-0] msb command 24-bit address 01 2 3 4 5 6 7 8 9 10 28 29 30 31 23 22 21 3 2 1 0 hi-z mode 0 mode 3
document number: 002-00646 rev. *m page 27 of 45 S25FL128P 11.11 bulk erase (be: c7h, 60h) the bulk erase (be) command sets all the bi ts within the entire memory array to logic 1s. a wren command is required prior to writing the be command. for 64 kb sector devices, the bulk erase command may be written as either c7h or 60h. for 256 kb sector devices, only the c7h command is valid. the host system must drive cs# low, and then write the be command on si. cs# must be driven low for the entire duration of the be sequence. the command sequence is shown in figure 11.17 and table 11.6 . the host system must drive cs# high after the device has latched the 8th bit of the be command, otherwise the device does not execute the command. the be operation begins as soon as cs# is driven high. the device internally controls the timing of the operation, which requires a period of t be . the status register may be read to check the value of the write in progress (wip) bit while the be operation is in progress. the wip bit is 1 during the be operation, and is 0 when the operation is completed. the device internally resets the write enable latch to 0 before the operation completes (the ex act timing is not specified). the device only executes a be command if all blo ck protect bits (bp2:bp0 or bp3:bp0) are 0 (see table 7.1 on page 10 ). otherwise, the device ignores the command. figure 11.17 bulk erase (be) command sequence 01 2 4 56 7 command cs# sck si 3 so/po[7-0] hi-z mode 0 mode 3
document number: 002-00646 rev. *m page 28 of 45 S25FL128P 11.12 deep power down (dp: b9h) the deep power down (dp) command provides the lowest power co nsumption mode of the device. it is intended for periods when the device is not in active use, and ignores all commands except for the release from de ep power down (res) command. the dp mode therefore provides the maximum data protection against unintended write operations. the standard standby mode, which the device goes into automatically when cs# is high (and all operat ions in progress are complete), should generally be used for the lowest power consumption when the quickest return to device activity is required. the host system must drive cs# low, and th en write the dp command on si. cs# must be driven low for the entire duration of the dp sequence. the command sequence is shown in figure 11.18 and table 11.6 . the host system must drive cs# high after the device has latche d the 8th bit of the dp command , otherwise the device does not execute the command. after a delay of t dp, the device enters the dp mode and current reduces from i sb to i dp (see table 17.1 on page 36 ). once the device has entered the dp mode, all commands are ignored except the res command (which releases the device from the dp mode). the res command also provides the electronic si gnature of the device to be outp ut on so, if desired (see sections 11.13 and 11.14 ) . dp mode automatically terminates when power is removed, and the device always powers up in the standard standby mode. the device rejects any dp command issued while it is executing a pr ogram, erase, or write status re gister operation, and continues the operation uninterrupted. figure 11.18 deep power down (dp) command sequence cs# sck si so/po[7-0] standby mode deep power-down mode command 0 1 234 56 7 t dp hi-z mode 0 mode 3
document number: 002-00646 rev. *m page 29 of 45 S25FL128P 11.13 release from deep power down (res: abh) the device requires the release from deep power down (res) co mmand to exit the deep power down mode. when the device is in the deep power down mode, all commands except res are ignored. the host system must drive cs# low and wr ite the res command to si. cs# must be driven low for the entire duration of the sequence. the command sequence is shown in figure 11.19 and table 11.6 . the host system must drive cs# high t res(max) after the 8-bit res command byte. the dev ice transitions from dp mode to the standby mode after a delay of t res (see table 19.1 on page 38 ). in the standby mode, the devic e can execute any read or write command. figure 11.19 release from deep power down (res) command sequence 11.14 release from deep power down an d read electronic signature (res: abh) 11.14.1 serial mode this command reads the old-style electronic sign ature from the so seri al output pin. see figure 11.20 and table 11.6 for the command sequence and signature value. please note that the electronic signa ture only consists of the device id portion of the 1 6- bit jedec id that is read by the read i dentifier (rdid) instruction. the old styl e electronic signature is supported for backwa rd compatibility, and should not be used for ne w software designs, which should instea d use the jedec 16-bit electronic signature by issuing the read identifier (rdid) command. the device is first selected by driving the cs# chip select inpu t pin to the logic low state. the res command is shifted in fol lowed by three dummy bytes onto the si serial input pi n. after the last bit of the three dummy bytes is shifted into the device, a byte of electronic signature will be shifted out of the so serial output pin. each bit is shifted out during the falling edge of the sc k serial clock signal. the maximum clock frequency for the res (abh) command is at 104 mhz. the electronic signature can be read repeatedly by applying multiples of eight clock cycles. the res instruction sequence is terminated by driving the cs# chip select input pin to the logic high state anytime during data output. after issuing any read id commands (90h, 9fh, abh), driv ing the cs# chip select input pin to the logic high state will automatically send the device into the standby mode. driving th e cs# chip select input pin to the logic low state again will automatically send the device out of t he standby mode and into the active mode. cs# sck si so/po[7-0] 0 1 23 4 5 6 7 command deep power-down mode t res standby mode mode 0 hi-z mode 3
document number: 002-00646 rev. *m page 30 of 45 S25FL128P figure 11.20 serial release from deep power down and read electronic signature (res) command sequence 11.14.2 parallel mode when the device is in parallel mode, the maximum sck clock frequen cy is 10 mhz. the device requir es a single clock cycle instea d of eight clock cycles to access th e next data byte. the method of memory content output will be the same compared to outside of parallel mode. the only difference is that a byte of data is output per clock cycle in stead of a single bit. in this case, the electronic signature will be output onto the p0[7?0] parallel output pins. figure 11.21 parallel release from deep power down and read electronic signature (res) command sequence notes 1. in parallel mode, the maximum access clock fr equency (fsck) is 10 mhz (sck pin clock frequency). 2. to release the device from deep power down and read electroni c id in parallel mode, a parallel mode enter command (55h) must be issued before the res command. the device will not exit parallel mode until a parallel mode exit command (45h) is written, or upon power-down or powe r-up sequence. 3. byte 1 will output the electronic signature. cs# sck si so 3 dummy bytes hi-z msb deep power-down mode standby mode 0 1 2 34567 8 9 10 28 29 30 31 32 33 34 35 36 37 38 electronic id out command t res 23 22 21 3 2 10 7 65 4 32 1 0 msb cs# sck si po[7-0] 3 dummy bytes electronic id hi-z deep power-down mode standby mode 0 1 2 3 4567 8 9 10 28 29 30 31 32 33 34 35 36 37 38 command t res 23 22 21 3 2 10 msb byte 1
document number: 002-00646 rev. *m page 31 of 45 S25FL128P 11.15 command definitions note for 64 kb sector devices, either command is valid and performs the same function. table 11.6 command definitions operation command description one-byte command code address bytes dummy byte data bytes read read read data bytes 03h (0000 0011) 3 0 1 to ? fast_read read data bytes at higher speed 0bh (0000 1011) 3 1 1 to ? rdid read identification 9fh (1001 1111) 0 0 1 to 3 read_id read manufacturer id and device id 90h (1001 0000) 3 0 1 to ? write control wren write enable 06h (0000 0110) 0 0 0 wrdi write disable 04h (0000 0100) 0 0 0 erase se 64 kb sector erase (see note) 20h (0010 0000) or d8h (1101 1000) 30 0 256 kb sector erase d8h (1101 1000) 3 0 0 be bulk (chip) erase, uniform 64 kb sector product (see note) c7h (1100 0111) or 60h (0110 0000) 00 0 bulk (chip) erase, uniform 256 kb sector product c7h (1100 0111) 0 0 0 program pp page program 02h (0000 0010) 3 0 1 to 256 status register rdsr read from status register 05h (0000 0101) 0 0 1 to ? wrsr write to status register 01h (0000 0001) 0 0 1 parallel mode entry enter x8 parallel mode 55h (0101 0101) 0 0 0 exit exit x8 parallel mode 45h (0100 0101) 0 0 0 power saving dp deep power down b9h (1011 1001) 0 0 0 res release from deep power down abh (1010 1011) 0 0 0 release from deep power down and read electronic signature abh (1010 1011) 0 3 1 to ?
document number: 002-00646 rev. *m page 32 of 45 S25FL128P 12. program acceleration via wp#/acc pin the program acceleration function requires applying v hh to the wp#/acc input, and then waiting a period of t wc . minimum t vhh rise and fall times is required for wp#/acc to change to v hh from v il or v ih . removing v hh from the wp#/acc pin returns the device to normal operation after a period of t wc . figure 12.1 acc program acceleration timing requirements note only read status register (rdsr) and page prog ram (pp) operations are allow when acc is at (v hh ). table 12.1 acc program acceleration specifications parameter description min. max. unit v hh acc pin voltage high 8.5 9.5 v t vhh acc voltage rise and fall time 250 ns t wc acc at v hh and v il or v ih to first command 5ns acc t vhh v hh v il or v ih v il or v ih t vhh t wc t wc command ok command ok
document number: 002-00646 rev. *m page 33 of 45 S25FL128P 13. power-up and power-down during power-up and power-down, certain conditions must be observed. cs# must follow the voltage applied on v cc , and must not be driven low to select the device until v cc reaches the allowable values as follows (see figure 13.1 and table 13.1 ): ? at power-up, v cc (min.) plus a period of t pu ? at power-down, v ss a pull-up resistor on chip select (cs#) typically meets proper power-up and power-down requirements. no write status register, program, or erase command should be sent to the device until v cc rises to the v cc minimum, plus a delay of t pu . at power-up, the device is in standby mode (not d eep power down mode) and the wel bit is reset (0). each device in the host system should have the v cc rail decoupled by a suitable capacitor cl ose to the package pins (this capacitor is generally of the order of 0.1 f), as a precaution to stabilizing the v cc feed. when v cc drops from the operating voltage to below the minimum v cc threshold at power-down, all operations are disabled and the device does not respond to any commands. no te that data corruption may result if a power-down occurs while a write register, program, or erase operation is in progress. figure 13.1 power-up timing diagram figure 13.2 power-down and voltage drop v cc v cc (max) v cc (min) full device access t pu time vcc v cc (max) v cc (min) v cc (cut-off) v cc (low) t pd t pu device access allowed no device access allowed time
document number: 002-00646 rev. *m page 34 of 45 S25FL128P table 13.1 power-up / power-down voltage and timing symbol parameter min max unit v cc(min) v cc (minimum operation voltage) 2.7 v v cc (cut-off) v cc (cut off where re-initialization is needed) 2.4 v v cc (low) v cc (low voltage for initialization to occur at read/standby) v cc (low voltage for initialization to occur at embedded) 0.2 2.3 v t pu v cc (min) to device operation 300 s t pd v cc (low duration time) 1.0 s
document number: 002-00646 rev. *m page 35 of 45 S25FL128P 14. initial delivery state the device is delivered with all bits set to 1 (each byte contains ffh) upon initial factory shipment. the status register cont ains 00h (all status register bits are 0). 15. absolute maximum ratings do not stress the device beyond the ratings listed in this sectio n, or serious, permanent damage to the device may result. thes e are stress ratings only and device oper ation at these or any other conditions beyond those indicated in this section and in the operating ranges section of this document is not implied. device operation for extended periods at the limits listed in this section may affect device reliability. notes 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input at i/o pins may overshoot v ss to ?2.0v for periods of up to 20 ns. see figure 15.2 . maximum dc voltage on output and i/o pins is 3.6 v. duri ng voltage transitions output pins may overshoot to v cc + 2.0v for periods up to 20 ns. see figure 15.2 . 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 3. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. ex posure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 15.1 maximum negative overshoot waveform figure 15.2 maximum positive overshoot waveform table 15.1 absolute maximum ratings description rating ambient storage temperature ?65c to +150c voltage with respect to ground: all inputs and i/os ?0.5v to v cc +0.5v 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
document number: 002-00646 rev. *m page 36 of 45 S25FL128P 16. operating ranges note operating ranges define those limits between wh ich functionality of the device is guaranteed. 17. dc characteristics this section summarizes the dc characteristics of the device. de signers should check that the operating conditions in their cir cuit match the measurement conditions specif ied in the test specifications in table 18.1 on page 37 , when relying on the quoted parameters. note typical values are at t a = 25 c and 3.0 v. table 16.1 operating ranges description rating ambient operating temperature (t a ) industrial ?40c to +85c positive power supply voltage range 2.7v to 3.6 v table 17.1 dc characteristics (cmos compatible) parameter description test conditions (see note) min typ. max unit v cc supply voltage 2.7 3.6 v i cc1 active read current sck = 0.1 v cc /0.9v cc 104 mhz (serial) 22 ma sck = 0.1 v cc /0.9v cc 40 mhz (serial: fast read mode) 10 ma 3 mhz (parallel mode) 10 ma i cc2 active page program current cs# = v cc 26 ma i cc3 active wrsr current cs# = v cc 26 ma i cc4 active sector erase current cs# = v cc 26 ma i cc5 active bulk erase current cs# = v cc 26 ma i sb standby current v in = gnd or v cc , cs# = v cc 200 a i dp deep power down current v in = gnd or v cc , cs# = v cc 320a i li input leakage current v in = gnd or v cc , v cc = v cc max 2 a i lo output leakage current v in = gnd to v cc , v cc = v cc max 2 a v il input low voltage ?0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage i ol = 1.6 ma, v cc = v cc min 0.4 v v oh output high voltage i oh = ?0.1 ma v cc ? 0.6 v
document number: 002-00646 rev. *m page 37 of 45 S25FL128P 18. test conditions figure 18.1 ac measurements i/o waveform table 18.1 test specifications symbol parameter min max unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltage 0.2 v cc to 0.8 v cc v input timing reference voltage 0.3 v cc to 0.7 v cc v output timing reference voltage 0.5 v cc v 0.8 v cc 0.2 v cc 0.7 v cc 0.3 v cc input levels input and output 0.5 v cc
document number: 002-00646 rev. *m page 38 of 45 S25FL128P 19. ac characteristics notes 1. typical program and erase times assume the following conditions: 25c, v cc = 3.0 v; 10,000 cycles; checkerboard data pattern 2. under worst-case conditions of 90 c; v cc = 2.7v; 100,000 cycles 3. not 100% tested. 4. fast_read is not valid in parallel mode. 5. only applicable as a constraint for wr sr command when srwd is set to a ?1?. 6. for ?00? data pattern at 25c. table 19.1 ac characteristics symbol parameter min typ(notes) max(notes) unit f sck sck clock frequency read, rdid command d.c. 40 (serial) 6 (parallel) mhz f sck sck clock frequency for: fast_read, read_id, pp, se, be, dp, res, wren, wrdi, rdsr, wrsr (note 4) d.c. 104 (serial) 10 (parallel) mhz t crt clock rise time (slew rate) 0.1 (serial) 0.25 (parallel) v/ns t cft clock fall time (slew rate) 0.1 (serial) 0.25 (parallel) v/ns t wh sck high time 4.5 (serial) 50 (parallel) ns t wl sck low time 4.5 (serial) 50 (parallel) ns t cs cs# high time 50 (serial) 20 (parallel) ns t css cs# setup time (note 3) 3ns t csh cs# hold time (note 3) 3ns t hd hold# setup time (relative to sck) (note 3) 3ns t cd hold# non-active hold time (relative to sck) (note 3) 3ns t hc hold# non-active setup time (relative to sck) 3 ns t ch hold# hold time (relative to sck) 3 ns t v output valid 0 8 (serial) 20 (parallel) ns t ho output hold time 2 ns t hd:dat data in hold time 2 (serial) 10 (parallel) ns t su:dat data in setup time 3 (serial) 10 (parallel) ns t r input rise time 5ns t f input fall time 5ns t lz hold# to output low z (note 3) 8 (serial) 20 (parallel) ns t hz hold# to output high z (note 3) 8 (serial) 20 (parallel) ns t dis output disable time (note 3) 8 (serial) 20 (parallel) ns t wps write protect setup time (notes 3 , 5 )20ns t wph write protect hold time (notes 3 , 5 ) 100 ns t w write status register time 100 ms t dp cs# high to deep power down mode 3s t res release dp mode 30 s t pp page programming time 1.2 (note 1) 3 (note 2) ms t ep page programming time (wp#/acc = 9 v) 1.02 (note 6) 2.4 (note 2) ms t se sector erase time (64 kb) 0.5 (note 1) 3 (note 2) sec t se sector erase time (256 kb) 2 (note 1) 12 (note 2) sec t be bulk erase time 128 (note 1) 768 (note 2) sec
document number: 002-00646 rev. *m page 39 of 45 S25FL128P 19.1 capacitance figure 19.1 spi mode 0 (0,0) input timing figure 19.2 spi mode 0 (0,0) output timing symbol parameter test conditions min typ max unit c in input capacitance (applies to sck, po7-po0, si, cs#) v out = 0v 9.0 12.0 pf c out output capacitance (applies to po7-po0, so) v in = 0v 12.0 16.0 pf cs# sck si so t csh t css t csh t css t crt t cft msb in lsb in hi-z t su:dat t hd:dat t cs cs# sck so lsb out t wh t wl t dis t v t ho t v t ho
document number: 002-00646 rev. *m page 40 of 45 S25FL128P figure 19.3 hold# timing figure 19.4 write protect setup and hold timing during wrsr when srwd=1 t ch t hz t cd t hd t hc t lz cs# sck so si hold# wp#/acc cs# sck si so hi-z t wps t wph
document number: 002-00646 rev. *m page 41 of 45 S25FL128P 20. physical dimensions 20.1 so3 016 wide ? 16-pin plastic small outline package (300-mil body width)
document number: 002-00646 rev. *m page 42 of 45 S25FL128P 20.2 wnf008 ? wson 8-contact (6 x 8 mm) no-lead package g1015 \ 16-038.30 \ 07.21.11 notes: 1. dimensioning and tolerancing conforms to asme y14.5m - 1994. 2. all dimensions are in millmeters. 3. n is the total number of terminals. 4 dimension ?b? applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension ?b? should nt be measured in that radius area. 5 nd refer to the number of terminals on d side. 6. max. package warpage is 0.05mm. 7. maximum allowable burrs is 0.076mm in all directions. 8 pin #1 id on top will be laser marked. 9 bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. 10 a maximum 0.15mm pull back (l1) may be present. symbol min nom max note e 1.27 bsc. n 8 3 nd 4 5 l 0.45 0.50 0.55 b 0.35 0.40 0.45 4 d2 4.70 4.80 4.90 e2 5.70 5.80 5.90 d 6.00 bsc e 8.00 bsc a 0.70 0.75 0.80 a1 0.00 0.02 0.05 k 0.20 min. l1 0.00 --- 0.15 10 package wnf008
document number: 002-00646 rev. *m page 43 of 45 S25FL128P 21. revision history spansion publication number: S25FL128P_00 section description revision 01 (january 12, 2007) initial release revision 02 (march 13, 2007) distinctive characteristics changed standby mode current S25FL128P sector address table (uniform 64 kb sector) corrected addresses for sectors 0 and 32 parallel mode (for 16-pin so package only) added last sentence in section read status register (rdsr: 05h) separated status re gister bit descriptions in to an additional subsection page program (pp: 02h) modified parallel page program (pp) instruction s equence figure to match format of other parallel mode figures command definitions changed code for bulk erase (be) 256 kb product in table read manufacturer and device id (read_id: 90h) corrected si and clk in parallel read_id instruction sequence figure absolute maximum ratings added overshoot and undershoot information dc characteristics changed maxi mum specifications for i cc1 (parallel mode), i sb , and i dp revision 03 (april 24, 2007) ordering information changed valid combinations table revision 04 (july 2, 2007) device operations added a sentence to byte or page programming parallel mode (for 16-pin so package only) added a sentence revision 05 (november 4, 2008) ordering information added tray package type option ac characteristics added note 6 modified page programming time revision 06 (december 8, 2008) global the data sheet went from a ?prelim inary? designation to full production. revision 07 (may 26, 2009) table: power-up timing ch aracteristics modified table figure: power-down and voltage drop added figure revision 08 (september 8, 2009) ac characteristics changed t cs cs# high time minimum (serial) from 100 to 50 ns revision 09 (december 8, 2011) connection diagrams added note to wson package power-up / power-down voltage and timing table updated the t pu (max) value ac characteristics table updated the value of t ep physical dimensions updated the package outli ne drawing for packages so3 016 and wnf008 revision 10 (may 16, 2012) global added text for recommending fl128s as migration device revision 11 (september 21, 2012) ac characteristics table changed output hold time (t ho ) to 2 ns (min) revision 12 (january 29, 2013) ac characteristics added capacitance table.
document number: 002-00646 rev. *m page 44 of 45 S25FL128P document history page document title: S25FL128P, 128-mbit, 3.0 v flash memory document number: 002-00646 rev. ecn no. orig. of change submission date description of change ** ? bwha 01/12/2007 initial release *a ? bwha 03/13/2007 distinctive characteristics: changed standby mode current S25FL128P sector address table (uniform 64 kb sector): corrected addresses for sectors 0 and 32 parallel mode (for 16-pin so package only): added last sentence in section read status register (rdsr: 05h): sepa rated status register bit descriptions into an additional subsection page program (pp: 02h): modified para llel page program (pp) instruction sequence figure to match format of other parallel mode figures command definitions: changed code for bulk erase (be) 256 kb product in table read manufacturer and device id (read_id: 90h): corrected si and clk in parallel read_id instruction sequence figure absolute maximum ratings: added overshoot and undershoot information dc characteristics: changed ma ximum specifications for i cc1 (parallel mode), i sb , and i dp *b ? bwha 04/24/2007 ordering information: changed valid combinations table *c ? bwha 07/02/2007 device operations: added a sentenc e to byte or page programming parallel mode (for 16-pin so package only): added a sentence *d ? bwha 11/04/2008 ordering information: added tray package type option ac characteristics: added note 6. modified page programming time. *e ? bwha 12/08/2008 global: the data sheet went from a ?preliminary? designation to full production. *f ? bwha 05/26/2009 table: power-up timing characteristics: modified table figure: power-down and voltage drop: added figure *g ? bwha 09/08/2009 ac characteristics: changed t cs cs# high time minimum (serial) from 100 to 50 ns *h ? bwha 12/08/2011 connection diagrams: added note to wson package power-up / power-down voltage and timing table: updated the t pu (max) value ac characteristics table: updated the value of t ep physical dimensions: updated the package outline drawing for packages so3 016 and wnf008 *i ? bwha 05/16/2012 global: added text for reco mmending fl128s as migration device *j ? bwha 09/21/2012 ac characteristics tabl e: changed output hold time (t ho ) to 2 ns (min) *k ? bwha 01/29/2013 ac characteristi cs: added capacitance table. *l 4904072 bwha 09/18/2015 updated to cypress template. *m 5716345 hara 04/27/2017 updated logo and copyright.
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