View PT7C4337ZEE_8920047.PDF datasheet online --- IC-ON-LINE

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||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||| real - time clock module (i 2 c bus) 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 1 p t7c4337 features ? using external 32.768khz quartz crystal for pt7c4337 ? supports i 2 c - bus's high speed mode (400 khz) ? includes time (h our /m inute /s econd ) and calendar (y ear /m onth /d ate /d ay ) counter functions (bcd code) ? programmable square wave output signal ? two time - of - day alarms ? oscillator stop flag ? operating range: 1.8v to 5.5v ? timekeeping range : 1. 2 v to 1.8 v description the pt7c4337 serial real - time clock is a low - power clock/calendar with two programmable time - of - day alarms and a programmable square - wave out put. address and data are transferred serially via a 2 - wire, bidirectional bus. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer th an 31 days, including corrections for leap year. the clock operates in either the 24 - hour or 12 - hour format with am/pm indicator. the device is fully accessible through the serial interface while vcc is between 1.8v and 5.5v. i 2 c operation is not guarantee d below 1.8v. timekeeping operation is maintained with vcc as low as 1.2v. table 1 shows the basic functions of pt7c4337. more details are shown in section: overview of functions. table 1. basic functions of pt7c4337 item function pt7c4337 1 oscillator source crystal(32.768khz) e xternal crystal oscillator enable/disable ? oscillator fail detect ? 2 time time display 12 - hour ? 24 - hour ? century bit - time count chain enable/disable ? 3 interrupt alarm interrupt output ? 2 4 programm able square wave output (hz) 1, 4.096k, 8.192k, 32.768k 5 communication 2 - wire i 2 c bus ?
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 2 pt7c4337 real - time clock m odule (i 2 c bus) pin assignment pin description p in n o . pin type description 1 x1 i oscillator circuit input. together with x1, 32.768khz crystal is connected between them. or external clock input. 2 x2 o oscillator circuit output. together with x1, 32.768khz crystal is connected between them. when 32.768khz external input, x2 must be float. 6 scl i serial clock input. scl is used to synchronize d ata movement on the i 2 c serial interface. 5 sda i/o serial data input/output. sda is the input/output pin for the 2 - wire serial interface. the sda pin is open - drain output and requires an external pull - up resistor. 3 inta o interrupt output. when enable d, inta is asserted low when the time matches the values set in the alarm registers. this pin is an open - drain output and requires an external pull up resistor. 7 sqw/i ntb o square - wave/interrupt output. programmable square - wave or interrupt output sign al. it is an open - drain output and requires an external pull up resistor. 8 vcc p power. primary po wer for pt7c43 3 7. 4 gnd p ground. / nc no connect. these pins are not connected internally, but must be grounded for proper operation. maximum rati ng s storage temperature ................................ ............................ - 6 5 to + 1 50 ambient temperature with power applied ........................... - 40 to +85 supply voltag e to ground potential ( v cc to gnd) ............... - 0.3 v to + 6.5 v dc input (all other inputs except vcc & gnd) ................................ ...... - 0.3v to ( vcc +0.3v ) dc output voltage (sda, /inta, /intb pins) ................................ ........ - 0.3 v to + 6.5 v dc out put current (fout) ................................ ............... - 0.3v to ( vcc +0.3v ) power dissipation ................................ ............. 320 mw (depend on package) note: stresses greater than those list ed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. x 2 i n t a g n d v c c s q w / i n t b s c l 6 7 8 1 2 3 x 1 4 5 s d a p t 7 c 4 3 3 7 d i p - 8 s o i c - 8 m s o p 8
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 3 pt7c4337 real - time clock m odule (i 2 c bus) operating mode the amount of current consumed by the pt7c43 37 is determined, in part, by the i 2 c interface and oscillator operation. the following table shows the relatio nship between the operating mode and the corresponding i cc parameter. operating mode v cc power i 2 c interface active 1.8v v cc 5.5v cc active (i cca ) i 2 c interface inactive 1.8v v cc 5.5v cc standby (i ccs ) i 2 c interface inactive 1.2v v cc 1.8v cctosc ) i 2 c interface inactive, oscillator disabled 1.2v v cc 1.8v cctddr ) reco mmended operating conditions part no. sym . description min type max unit pt7c4337 v cc v cc supply voltage 1.8 3.3 5.5 v v cc t 1.2 - 1.8 v osc oscillator start up voltage 1. 2 - 5.5 v ih input high level scl, sda 0.7v cc - v cc +0.3 inta, sqw/intb - - 5.5 v il input low level - 0.3 - 0.3v cc t a operating temperature - 40 - 85 oc dc electrical characteristics unless otherwise specified, v cc = 1.8~5.5v, t a = - 40 c to +85 c sym. item pin condition min typ max unit v cc supply voltage v cc full op eration 1.8 - 5.5 v v cc t timekeeping (note 5) 1.2 - 1.8 v osc oscillator voltage v cc 1. 2 - 5.5 v v il 1 low - level input voltage scl - 0.3 - 0.3v cc v v ih 1 high - level input voltage scl 0.7v cc - v cc +0.3 v il 2 low - level input voltage x1 - 0.53 - v v ih 2 high - level input voltage x1 - 0.53 - i o l low - level output current sda, /inta, /intb v ol = 0.4v 3 - - ma i il input leakage current scl - 1 - 1 ? oz output current when off sda, /inta, /intb - 1 - 1 ?
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|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 7 pt7c4337 real - time clock m odule (i 2 c bus) function block o scillator circuit pt7c43 37 the pt7c4337 uses an external 32.768 khz crystal. table2 specifi es several crystal parameters for the external crystal. the block diagram shows a functional schematic of the oscillator circuit. the startup time is usually less than 1 second when using a crystal with the specified characteristics. table2 crystal specif ications parameter symbol min typ max unit nominal frequency f o - 32.768 - khz series resistance esr - - 70 k ? l - 6/12.5 - pf note: the crystal, traces, and crystal input pins should be isolated from rf generating signals. c lock acc uracy the accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. crystal frequency drift caused by temperature shifts creates additional error. external circuit noise coupled into the oscillator circuit can result in the clo ck running fast. figure 1 shows a typical pc board layout for isolating the crystal and oscillator from noise. time counter ( sec,min,hour,day,date,month,year ) interrupt control square wave output control comparator 1 alarm 2 register (min, hour, day/date) comparator 2 alarm 1 register (sec, min, hour, day/date) shift register address decoder address register inta sqw/intb scl sda pt7c4337 osc x1 x2 c g c d 32.768 khz control register counter chain i /o interface (i 2 c)
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 8 pt7c4337 real - time clock m odule (i 2 c bus) function description overview of functions clock function cpu can read or write data including the year (last two digits), month, date, day, hour, minute, and second. any (two - digit) year that is a multiple of 4 is treated as a leap year and calculated automaticall y as such until the year 2100. alarm function this device has two alarm system (alarm 1 and alarm 2) that outputs interrupt signals from inta or intb to cpu when the date, day of the week, hour, minute or second correspond to the setting. each of them may output interrupt signal separately at a specified time. the alarm is be selectable between on and off for matching alarm or repeating alarm. programmable square wave output a square wave output enable bit controls square wave output at pin 7. frequencies are selectable: 1, 4.096k, 8.192k, 32.768k hz. interface with cpu data is read and written via the i 2 c bus interface using two signal lines: scl (clock) and sda (data). since the output of the i/o pin sda is open drain, a pull - up resistor should be used on the circuit board if the cpu output i/o is also open drain. the scl's maximum clock frequency is 400 khz, which supports the i 2 c bus's high - speed mode. oscillator fail detect when oscillator fail, pt7c4337 osf bit will be set. oscillator enable/disabl e oscillator and time count chain can be enabled or disabled at the same time by /etime bit. registers allocation of registers addr. (hex) *1 function register definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 seconds (00 - 59) 0 s40 s20 s1 0 s8 s4 s2 s1 01 minutes (00 - 59) 0 m40 m20 m10 m8 m4 m2 m1 02 hours (00 - 23 / 01 - 12) 0 12, /24 h20 or p , /a h10 h8 h4 h2 h1 03 days of the week (01 - 07) 0 0 0 0 0 w4 w2 w1 04 dates (01 - 31) 0 0 d20 d10 d8 d4 d2 d1 05 months (01 - 12) century 0 0 mo10 mo8 mo4 mo2 mo1 06 years (00 - 99) y80 y40 y20 y10 y8 y4 y2 y1 07 alarm 1: seconds a1m1 *2 s40 s20 s10 s8 s4 s2 s1
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 9 pt7c4337 real - time clock m odule (i 2 c bus) 08 alarm 1: minutes a1m2 *2 m40 m20 m10 m8 m4 m2 m1 09 alarm 1: hours a1m3 *2 12, /24 h20 or p , /a h10 h8 h4 h2 h1 0a alarm 1: day, date a1 m4 *2 day, /date 0, d20 0, d10 0, d8 w4, d4 w2, d2 w1, d1 0b alarm 2: minutes a2m2 *3 m40 m20 m10 m8 m4 m2 m1 0c alarm 2: hours a2m3 *3 12, /24 h20 or p , /a h10 h8 h4 h2 h1 0d alarm 2: day, date a2m4 *3 day, /date 0, d20 0, d10 0, d8 w4, d4 w2, d2 w1, d1 0e control /etime *4 0 0 rs2 *5 rs1 *5 intcn *6 a2ie *7 a1ie *7 0f status osf *9 0 0 0 0 0 a2f *8 a1f *8 caution points: *1. pt7c4337 uses 8 bits for address. for excess 0fh address, pt7c4337 will not respond (no acknowledge signal was given). *2. alarm 1 mas k bits. select alarm repeated rate when an alarm occurs. *3. alarm 2 mask bits. select alarm repeated rate when an alarm occurs. *4. oscillator and time count chain enable/disable bit. *5. square wave output frequency select. *6. interrupt output p in select bit. *7. alarm 1 and alarm 2 enable bits. *8. alarm 1 and alarm 2 flag bits. *9. oscillator stop flag. *10. all bits marked with " 0 " are read - only bits. their value when read is always "0". control and status register addr. (hex) descri ption d7 d6 d5 d4 d3 d2 d1 d0 0e control /etime 0 0 rs2 rs1 intcn a2ie a1ie (default) 0 0 0 1 1 0 0 0 0f status osf 0 0 0 0 0 a2f a1f (default) 1 0 0 0 0 0 undefined undefined oscillator related bits ? /etime enable oscillator and time count chain b it. /etime data description read / write 0 enable oscillator and time count chain. default 1 disable oscillator and time count chain. ? osf oscillator stop flag. a logic 1 in this bit indicates that the oscillator either is stopped or was stopped for so me period of time and may be used to judge the validity of the clock and calendar data. this bit is set to logic 1 anytime that the oscillator stops. the following are examples of conditions that can cause the osf bit to be set: 1) the first time power is a pplied. 2) the voltage present on vcc is insufficient to support oscillation. 3) the /etime bit is turned off. 4) external influences on the crystal (e.g., noise, leakage, etc.). this bit remains at logic 1 until written to logic 0.
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 10 pt7c4337 real - time clock m odule (i 2 c bus) square wave frequency selec tion bits ? rs2, rs1 square wave rate select. these bits control the frequency of the square - wave output when the square wave has been enabled. rs2, rs1 data sqw output freq. (hz) read / write 00 1 01 4.096k 10 8.192k 11 32.768k default interrupt related bits ? intcn interrupt output pin select bit. this bit controls the relationship between the two alarms and the interrupt output pins. intcn data description read / write 1 a match between the timekeeping registers and the alarm 1 registers activates the inta pin (if the alarm 1 is enabled) and a match between the timekeeping registers and the alarm 2 registers activates the sqw/intb pin (if the alarm 2 is enabled). 0 a match between the timekeeping registers and either alarm 1 or alarm 2 r egisters activates the inta pin (if the alarms are enabled). in this configuration, a square wave is output on the sqw/intb pin. default ? a1ie alarm 1 interrupt enable. a1ie data description read / write 0 the a1f bit does not initiate the inta signa l. default 1 permits the alarm 1 flag (a1f) bit in the status register to assert inta. ? a1f alarm 1 flag. a1f data description read / write 0 the time do not match the alarm 1 registers. default read 1 indicates that the time matched the alarm 1 r egisters. if the a1ie bit is also logic 1, the inta pin goes low. a1f is cleared when written to logic 0. attempting to write to logic 1 leaves the value unchanged. ? a2ie alarm 2 interrupt enable. a2ie data description read / write 0 the a2f bit doe s not initiate an interrupt signal. default 1 permits the alarm 2 flag (a2f) bit in the status register to assert inta (when intcn = 0) or to assert sqw/intb (when intcn = 1).
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 11 pt7c4337 real - time clock m odule (i 2 c bus) ? a2f alarm 2 flag. a1f data description read / write 0 the time do no t match the alarm 2 registers. default read 1 indicates that the time matched the alarm 1 registers. this flag can be used to generate an interrupt on either inta or sqw/intb depending on the status of the intcn bit. if the intcn = 0 and a2f = 1 (and a2ie = 1), the inta pin goes low. if the intcn = 1 and a2f = 1 (and a2ie = 1), the sqw/intb pin goes low. a2f is cleared when written to logic 0. attempting to write to logic 1 leaves the value unchanged. time counter time digit display (in bcd code): ? second digits: range from 00 to 59 and carried to minute digits when incremented from 59 to 00. ? minute digits: range from 00 to 59 and carried to hour digits when incremented from 59 to 00. ? hour digits: see description on the /12, 24 bit. carried to day an d day - of - the - week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 00 seconds 0 s40 s20 s10 s8 s4 s2 s1 (default) 0 undefined undefined undefined undefined undefined undefined undefined 01 min utes 0 m40 m20 m10 m8 m4 m2 m1 (default) 0 undefined undefined undefined undefined undefined undefined undefined 02 hours 0 12, /24 h20 or p,/a h10 h8 h4 h2 h1 (default) 0 undefined undefined undefined undefined undefined undefined undefined note: an y registered imaginary time should be replaced with correct time, otherwise it will cause the clock counter malfunction. ? 12, /24 bit this bit is used to select between 12 - hour clock system and 24 - hour clock system. 12, /24 data description read / write 0 24 - hour system 1 12 - hour system
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 12 pt7c4337 real - time clock m odule (i 2 c bus) this bit is used to select between 12 - hour clock operation and 24 - hour clock operation. 12, /24 description hours register 0 24 - hour time display 1 12 - hour time display * be sure to select between 12 - hour and 24 - hour clock operation before writing the time data. days of the week counter the day counter is a divide - by - 7 counter that counts from 01 to 07 and up 07 before starting again from 01. values that correspond to the day of week are user define d but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illogical time and date entries result in undefined operation. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 03 day s of the week 0 0 0 0 0 w4 w2 w1 (default) 0 0 0 0 0 undefined undefined undefined calendar counter the data format is bcd format. ? day digits: range from 1 to 31 (for january, march, may, july, august, october and december). range from 1 to 30 (for april, june, september and november ). range from 1 to 29 (for february in leap years). range from 1 to 28 (for february in ordinary years). carried to month digits when cycled to 1. ? month digits: range from 1 to 12 and carried to year digits when cycled to 1. ? year digits: range from 00 to 99 and 00, 04, 08, , 92 and 96 are counted as leap years. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 04 dates 0 0 d20 d10 d8 d4 d2 d1 (default) 0 0 undefined undefined undefined undefined undefined undefined 05 months century *1 0 0 m10 m8 m4 m2 m1 (default) und efined 0 0 undefined undefined undefined undefined undefined 06 years y80 y40 y20 y10 y8 y4 y2 y1 (default) undefined undefined undefined undefined undefined undefined undefined undefined *1 : the century bit is toggled when the years register overflows from 99 to 00. 24 - hour clock 12 - hour clock 24 - hour clock 12 - hour clock 00 52 ( am 12 ) 12 72 ( pm 12 ) 01 41 ( am 01 ) 13 61 ( pm 01 ) 02 42 ( am 02 ) 14 62 ( pm 02 ) 03 43 ( am 03 ) 15 63 ( pm 03 ) 04 44 ( am 04 ) 16 64 ( pm 04 ) 05 45 ( am 05 ) 17 65 ( pm 05 ) 06 46 ( am 06 ) 18 66 ( pm 06 ) 07 47 ( am 07 ) 19 67 ( pm 07 ) 08 48 ( am 08 ) 20 68 ( pm 08 ) 09 49 ( am 09 ) 21 69 ( pm 09 ) 10 50 ( am 10 ) 22 70 ( pm 10 ) 11 51 ( am 11 ) 23 71 ( pm 11 )
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 13 pt7c4337 real - time clock m odule (i 2 c bus) alarm register ? alarm 1, alarm 2 register addr. description d7 d6 d5 d4 d3 d2 d1 d0 07 alarm 1: seconds a1m1 *1 s40 s20 s10 s8 s4 s2 s1 (default) undefined undefined undefined undefined undefined undefined undefined undefined 08 ala rm 1: minutes a1m2 *1 m40 m20 m10 m8 m4 m2 m1 (default) undefined undefined undefined undefined undefined undefined undefined undefined 09 alarm 1: hours a1m3 *1 12, /24 h20 or p,/a h10 h8 h4 h2 h1 (default) undefined undefined undefined undefined unde fined undefined undefined undefined 0a alarm 1: day, date a1m4 *1 day, /date *1 0, d20 0, d10 0, d8 w4, d4 w2, d2 w1, d1 (default) undefined undefined undefined undefined undefined undefined undefined undefined 0b alarm 2: minutes a2m2 *2 m40 m20 m10 m8 m4 m2 m1 (default) undefined undefined undefined undefined undefined undefined undefined undefined 0c alarm 2: hours a2m3 *2 12, /24 h20 or p,/a h10 h8 h4 h2 h1 (default) undefined undefined undefined undefined undefined undefined undefined undefined 0d alarm 2: day, date a2m4 *2 day, /date *2 0, d20 0, d10 0, d8 w4, d4 w2, d2 w1, d1 (default) undefined undefined undefined undefined undefined undefined undefined undefined *1 note: alarm mask bit, using to select alarm 1 alarm rate. *2 note: alarm mas k bit, using to select alarm 2 alarm rate.
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 14 pt7c4337 real - time clock m odule (i 2 c bus) alarm function related register addr. (hex) function register definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 seconds 0 s40 s20 s10 s8 s4 s2 s1 01 minutes 0 m40 m20 m10 m8 m4 m2 m1 02 hours 0 12, /24 h20 or a , /p h10 h8 h4 h2 h1 03 days of the week 0 0 0 0 0 w4 w2 w1 04 dates 0 0 d20 d10 d8 d4 d2 d1 07 alarm 1: seconds a1m1 s40 s20 s10 s8 s4 s2 s1 08 alarm 1: minutes a1m2 m40 m20 m10 m8 m4 m2 m1 09 alarm 1: hours a1m3 12, /24 h20 or a , /p h10 h8 h4 h2 h1 0a alarm 1: day, date a1m4 day, /date 0, d20 0, d10 0, d8 w4, d4 w2, d2 w1, d1 0b alarm 2: minutes a2m2 m40 m20 m10 m8 m4 m2 m1 0c alarm 2: hours a2m3 12, /24 h20 or a , /p h10 h8 h4 h2 h1 0d alarm 2: day, date a2m4 day, /date 0, d20 0, d10 0, d8 w4, d4 w2, d2 w1, d1 0e control /etime 0 0 rs2 rs1 intcn a2ie a1ie 0f status osf 0 0 0 0 0 a2f a1f note: alarm function does not support different hour system adopted in time and alarm register. the pt7c433 7 contains two time - of - day/date alarms. the alarms can be programmed (by the intcn bit of the control register) to operate in two different modes - each alarm can drive its own separate interrupt output or both alarms can drive a common interrupt output. b it 7 of each of the time - of - day/date alarm registers are mask bits. when all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h ~ 04h match the values stored in the time - of - day/date alarm reg isters. the alarms can also be programmed to repeat every second, minute, hour, day, or date. table 2 and table 3 shows the possible settings. the day, /date bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 ~ 5 of that register reflects the day of the week or the date of the month. if the bit is written to logic 0, the alarm is the result of a match w ith date of the month. if the bit is written to logic 1, the alarm is the result of a match with day of the week . when the pt7c4337 register values match alarm register settings, the corresponding alarm flag (a1f or a2f) bit is set to logi c 1. if the corresponding alarm interrupt enable (a1ie or a2ie) is also set to logic 1, the alarm condition activates one of the interrupt output (inta or sqw/intb) signals. the match is tested on the once - per - second update of the time and date registers.
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 15 pt7c4337 real - time clock m odule (i 2 c bus) table 1. alarm 1 mask bits day, /date alarm 1 register mask bits alarm rate a1m4 a1m3 a1m2 a1m1 ? ? ? ? table 2. alarm 2 mask bits day, /date alarm 2 register mask bits alarm rate a2m4 a2m3 a2m2 ? ? ?
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 16 pt7c4337 real - time clock m odule (i 2 c bus) i 2 c bus interface overview of i 2 c - bus the i 2 c bus supports bi - directional communications via two signal lines: the s da (data) line and scl (clock) line. a combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on. both the scl and sda signals are held at high level whenever communicati ons are not being performed. the starting and stopping of communications is controlled at the rising edge or falling edge of sda while scl is at high level. during data transfers, data changes that occur on the sda line are performed while the scl line is at low level, and on the receiving side the data is captured while the scl line is at high level. in either case, the data is transferred via the scl line at a rate of o ne bit per clock pulse. the i 2 c bus device does not include a chip select pin such as i s found in ordinary logic devices. instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when i ts slave address matches the slave address in the received data. system conf iguration all ports connected to the i 2 c bus must be either open drain or open collector ports in order to enable and connections to multiple devices. scl and sda are both connected to the vdd line via a pull - up resistance. consequently, scl and sda are b oth held at high level when the bus is released (when communication is not being performed). fig 1. system configuration master mcu slave rtc other peripheral device v cc sda scl note: when there is only one master, the mcu is ready for driving scl to "h" and r p of scl may not required. r p r p
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 17 pt7c4337 real - time clock m odule (i 2 c bus) starting and stopping i 2 c bus communications fig 2 . starting and stopping on i 2 c bus 1) start condition, repeated start condition, and stop condition a ) start condition sda level changes from high to low while scl is at high level b ) stop condition sda level changes from low to high while scl is at high level c ) repeated start condit ion (restart condition) in some cases, the start condition occurs between a previous start condition and the next stop condition, in which case the second start condition is distinguished as a restart condition. since the required status is the same as for the start condition, the sda level changes from high to low while scl is at high level. 2) data transfers and acknowledge responses during i 2 c - bus communication a) data transfers data transfers are performed in 8 - bit (1 byte) units once the start conditi on has occurred. there is no limit on the amount (bytes) of data that are transferred between the start condition and stop condition. the address auto increment function operates during both write and read operations. updating of data on the transmitter (transmitting side)'s sda line is performed while the scl line is at low level. the receiver (receiving side) captures data while the scl line is at high level. *note with caution that if the sda data is changed while the scl line is at high level, it will be treated as a start, restart, or stop condition. b) data acknowledge response (ack signal) when transferring data, the receiver generates a confirmation response (ack signal, low active) each time an 8 - bit data segment is received. if there is no ack signal from the receiver, it indicates that normal communication has not been established. (this does not include instances where the master device intentionally does not generate an ack signal.) immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the scl line, the transmitter releases the sda line and the receiver sets the sda line to low (= acknowledge) level.
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 18 pt7c4337 real - time clock m odule (i 2 c bus) after transmitting the ack signal, if the master remains the receiver for trans fer of the next byte, the sda is released at the falling edge of the clock corresponding to the 9th bit of data on the scl line. data transfer resumes when the master becomes the transmitter. when the master is the receiver, if the master does not send an ack signal in response to the last byte sent from the slave, that indicates to the transmitter that data transfer has ended. at that point, the transmitter continues to release the sda and aw aits a stop condition from the master. slave address the i 2 c b us device does not include a chip select pin such as is found in ordinary logic devices. instead of using a chip select pin, slave addresses are allocated to each device. all communications begin with transmitting the [start condition] + [slave address (+ r/w specification)]. the receiving device responds to this communication only when the specified slave address it has received matches its own slave address. slave addresses have a fixed length of 7 bits. see table for the details. an r/w bit is added to each 7 - bit slave address during 8 - bit transfers. table operation transfer data slave address r / w bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read d1 h 1 1 0 1 0 0 0 1 (= read) write d0 h 0 (= write) i 2 c buss basic transfer forma t scl from master 1 2 8 9 sda from transmitter (sending side) sda from receiver (receiving side) release sda low active ack signal s start indication p stop indication sr restart indication a rtc acknowledge a master acknowledge
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 19 pt7c4337 real - time clock m odule (i 2 c bus) 1) write via i 2 c bus 2) read via i 2 c bus a) standard read b) simplified read note: 1. the above steps are an example of transfers of one or two bytes only. there is no limit to the number of bytes transferred during actual communications. 2. 49h, 4ah are used as test mode address. customer should not use the addresses. slave address (7 bits) 1 1 0 1 0 0 0 0 write addr. setting slave address + write specification address specifies the write start address. a bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit a p write data s a a c k a c k a c k start stop slave address (7 bits) 1 1 0 1 0 0 0 0 write slave address + write specification address specifies the read start address. addr. setting a s slave address (7 bits) 1 1 0 1 0 0 0 1 read slave address + read specification data read (1) data is read from the specified start address and address auto increment. a bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit /a p sr 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit bit data read (2) address auto increment to set the address for the next data to be read. a c k n o a c k a a c k a c k a c k a start stop restart data read (2) address register auto increment to set the address for the next data to be read. data read (1) data is read from the address pointed by the internal address register and address auto increment. slave address (7 bits) 1 1 0 1 0 0 0 1 read a bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit /a p s 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit bit a c k n o a c k a c k a stop start slave address + read specification
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 20 pt7c4337 real - time clock m odule (i 2 c bus) mechanical information we ( lead free and green soic - 8 ) min max a 1.350 1.750 a1 0.100 0.250 a2 1.350 1.550 b 0.330 0.510 c 0.170 0.250 d 4.700 5.100 e 3.800 4.000 e1 5.800 6.200 e l 0.400 1.270 0 8 symbol dimensions in millimeters 1.27 bsc note: 1) controlling dimensions in millimeters. 2) ref: jedec ms-012e/aa
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 21 pt7c4337 real - time clock m odule (i 2 c bus) ue( lead free and green msop - 8) min max a 0.82 1.10 a1 0.02 0.15 a2 0.75 0.95 b 0.25 0.38 c 0.09 0.23 d 2.90 3.10 e 2.90 3.10 e1 4.75 5.05 e l 0.40 0.80 0 6 symbol dimensions in millimeters 0.65 bsc note: 1) controlling dimensions in millimeters. 2) ref: jedec mo-187e/ba
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 22 pt7c4337 real - time clock m odule (i 2 c bus) le (lead free and green 8 - pin tssop ) symbol min max a 1.20 a1 0.02 0.15 a2 0.80 1.00 b 0.19 0.30 c 0.09 0.20 d 2.90 3.10 e 4.30 4.50 e1 6.25 6.55 e l 0.50 0.70 1 7 pkg. dimensions(mm) 0.65 bsc note: 1) controlling dimensions in millimeters.
|||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2013 - 06 - 0002 pt0205 - 9 0 6 / 18 /1 3 23 pt7c4337 real - time clock m odule (i 2 c bus) z e e (lead free and green 8 - pin t dfn) ordering information part number package code package pt7c4337w e w lead free and green 8 - pin soic pt7c4337 ue u lead free and green 8 - pin msop pt7c4337 zee ze lead free and green 8 - pin tdfn pt7c4337le l lead free and green 8 - pin tssop notes: ? e = pb - free or pb - free and green ? adding x suffix = tape /r eel pericom semic onductor corporation ? 1 - 800 - 435 - 2336 ? www.pericom.com pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. pericom does not assume any responsibility for use of any circuitry described other than the circu itry embodied in pericom product. the company makes no representations that circuitry described herein is free from patent infring ement or other rights, of pericom . symbol min. max a 0.700 0.800 a1 0.000 0.500 a3 d 1.924 2.076 e 2.924 3.076 d1 1.400 1.600 e1 1.400 1.600 k b 0.200 0.300 e l 0.224 0.376 pkg. dimensions(mm) 0.203ref 0.200min 0.500typ note: ref: jedec mo-229

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