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general description the max16935/max16939 are 3.5a current-mode step-down converters with integrated high-side and low- side mosfets designed to operate with an external schottky diode for better efficiency. the low-side mosfet enables fixed-frequency forced-pwm (fpwm) operation under light-load applications. the devices operate with input voltages from 3.5v to 36v, while using only 28 f a quiescent current at no load. the switching frequency is resistor programmable from 220khz to 2.2mhz and can be synchronized to an external clock. the devices? output voltage is available as 3.3v/5v fixed or adjustable from 1v to 10v. the wide input voltage range along with its ability to operate at 98% duty cycle during undervoltage transients make the devices ideal for automotive and industrial applications. under light-load applications, the fsync logic input allows the devices to either operate in skip mode for reduced current consumption or fixed-frequency fpwm mode to eliminate frequency variation to minimize emi. fixed-frequency fpwm mode is extremely use - ful for power supplies designed for rf transceivers where tight emission control is necessary. protection features include cycle-by-cycle current limit and thermal shutdown with automatic recovery. additional features include a power-good monitor to ease power-supply sequencing and a 180 n out-of-phase clock output relative to the internal oscillator at syncout to create cascaded power supplies with multiple devices. the max16935/max16939 operate over the -40 n c to +125 n c automotive temperature range and are available in 16-pin (5mm x 5mm) tqfn-ep and 16-pin tssop-ep packages. applications point-of-load applications distributed dc power systems navigation and radio head units beneits and features integration and high-switching frequency saves space ? integrated 3.5a high-side switch ? low-bom-count current-mode control architecture ? fixed output voltage with 2% accuracy or externally resistor adjustable (1v to 10v) ? 220khz to 2.2mhz switching frequency with three operation modes (skip mode, forced fixed-frequency operation, and external frequency synchronization) ? automatic lx slew-rate adjustment for optimum eficiency across operating frequency range 180 out-of-phase clock output at syncout enables cascaded power supplies for increased power output spread-spectrum frequency modulation reduces emi emissions wide input voltage range supports automotive applications ? 3.5v to 36v input voltage range (42v tolerant) ? enable input compatible from 3.3v logic level to 42v robust performance supports wide range of automotive applications ? -40c to +125c automotive temperature range ? thermal-shutdown protection ? aec-q100 qualiied power-good output allows power-supply sequencing tight overvoltage protection provides smaller overshoot voltages (max16939) 19-6868; rev 10; 4/16 ordering information/selector guide and typical application circuit appear at end of data sheet. max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current evaluation kit available downloaded from: http:///
sup, supsw, en to pgnd ................................... -0.3v to +42v lx (note 1) ............................................................ -0.3v to +42v sup to supsw ..................................................... -0.3v to +0.3v bias to agnd ......................................................... -0.3v to +6v syncout, fosc, comp, fsync, pgood, fb to agnd ........................ -0.3v to (v bias + 0.3v) out to pgnd ........................................................ -0.3v to +12v bst to lx (note 1) .................................................. -0.3v to +6v agnd to pgnd ................................................... -0.3v to + 0.3v lx continuous rms current ................................................ 3.5a output short-circuit duration .................................... continuous continuous power dissipation (t a = +70 n c)* tqfn (derate 28.6mw/ n c above +70 n c)...............2285.7mw tssop (derate 26.1mw/ n c above +70 n c).............2088.8mw operating temperature range .................... -40 n c to +125 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratings note 1: self-protected against transient voltages exceeding these limits for 50ns under normal operation and loads up to the maxi - mum rated output current. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. *as per jedec51 standard (multilayer board). tqfn junction-to-ambient thermal resistance ( b ja ) .......... 35 n c/w junction-to-case thermal resistance ( b jc ) .............. 2.7 n c/w tssop junction-to-ambient thermal resistance ( b ja ) ....... 38.3 n c/w junction-to-case thermal resistance ( b jc ) ................. 3 n c/w package thermal characteristics (note 2) electrical characteristics (v sup = v supsw = 14v, v en = 14v, l1 = 2.2 f h, c in = 4.7 f f, c out = 22 f f, c bias = 1 f f, c bst = 0.1 f f, r fosc = 12k i , t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) www.maximintegrated.com maxim integrated 2 max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current parameter symbol conditions min typ max units supply voltage v sup, v supsw 3.5 36 v load dump event supply voltage v sup_ld t ld < 1s 42 v supply current i sup_standby standby mode, no load, v out = 5v, v fsync = 0v 28 40 f a standby mode, no load, v out = 3.3v, v fsync = 0v 22 35 shutdown supply current i shdn v en = 0v 5 10 f a bias regulator voltage v bias v sup = v supsw = 6v to 42v, i bias = 0 to 10ma 4.7 5 5.4 v bias undervoltage lockout v uvbias v bias rising 2.95 3.15 3.40 v bias undervoltage lockout hysteresis 450 650 mv thermal shutdown threshold +175 n c thermal shutdown threshold hysteresis 15 n c downloaded from: http:///
electrical characteristics (continued) (v sup = v supsw = 14v, v en = 14v, l1 = 2.2 f h, c in = 4.7 f f, c out = 22 f f, c bias = 1 f f, c bst = 0.1 f f, r fosc = 12k i , t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) www.maximintegrated.com maxim integrated 3 max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current parameter symbol conditions min typ max units output voltage (out)fpwm mode output voltage v out_5v v fb = v bias, 6v < v supsw < 36v, fixed-frequency mode (notes 3, 4) 4.9 5 5.1 v v out_3.3v 3.234 3.3 3.366 skip mode output voltag v out_skip_5v no load, v fb = v bias, skip mode (note 5) 4.9 5 5.15 v v out_skip_3.3v 3.234 3.3 3.4 load regulation v fb = v bias , 300ma < i load < 3.5a 0.5 % line regulation v fb = v bias , 6v < v supsw < 36v (note 4) 0.02 %/v bst input current i bst_on high-side mosfet on, v bst - v lx = 5v 1 1.5 2 ma i bst_off high-side mosfet off, v bst - v lx = 5v, t a = +25 c 5 f a lx current limit i lx peak inductor current 4.2 5.2 6.2 a lx rise time r fosc = 12k w 4 ns skip mode current threshold i skip_th t a = +25 c max16935 150 300 400 ma max16939 200 400 500 spread spectrum spread spectrum enabled f osc q 6% high-side switch on-resistance r on_h i lx = 1a, v bias = 5v 100 220 m i high-side switch leakage current high-side mosfet off, v sup = 36v, v lx = 0v, t a = +25 n c 1 3 f a low-side switch on-resistance r on_l i lx = 0.2a, v bias = 5v 1.5 3 i low-side switch leakage current v lx = 36v, t a = +25 n c 1 f a transconductance amplifier (comp)fb input current i fb 20 100 na fb regulation voltage v fb fb connected to an external resistor divider, 6v < v supsw < 36v (note 6) 0.99 1.0 1.015 v fb line regulation d v line 6v < v supsw < 36v 0.02 %/v transconductance (from fb to comp) g m v fb = 1v, v bias = 5v 700 f s minimum on-time t on_min (note 5) 80 ns maximum duty cycle dc max 98 % oscillator frequencyoscillator frequency r fosc = 73.2k i 340 400 460 khz r fosc = 12k i 2.0 2.2 2.4 mhz downloaded from: http:///
note 3: device not in dropout condition. note 4: filter circuit required, see the typical application circuit . note 5: guaranteed by design; not production tested. note 6: fb regulation voltage is 1%, 1.01v (max), for -40c < t a < +105c. note 7: contact the factory for sync frequency outside the specified range. electrical characteristics (continued) (v sup = v supsw = 14v, v en = 14v, l1 = 2.2 f h, c in = 4.7 f f, c out = 22 f f, c bias = 1 f f, c bst = 0.1 f f, r fosc = 12k i , t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) www.maximintegrated.com maxim integrated 4 max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current parameter symbol conditions min typ max units external clock input (fsync)external input clock acquisition time t fsync 1 cycles external input clock frequency r fosc = 12k i (note 7) 1.8 2.6 mhz external input clock high threshold v fsync_hi v fsync rising 1.4 v external input clock low threshold v fsync_lo v fsync falling 0.4 v soft-start time t ss 5.6 8 12 ms enable input (en)enable input high threshold v en_hi 2.4 v enable input low threshold v en_lo 0.6 enable threshold voltage hysteresis v en_hys 0.2 v enable input current i en t a = +25 n c 0.1 1 f a power good (pgood)pgood switching level v th_rising v fb rising, v pgood = high 93 95 97 %v fb v th_falling v fb falling, v pgood = low 90 92 94 pgood debounce time 10 25 50 f s pgood output low voltage i sink = 5ma 0.4 v pgood leakage current v out in regulation, t a = +25 n c 1 f a syncout low voltage i sink = 5ma 0.4 v syncout leakage current t a = +25 n c 1 f a fsync leakage current t a = +25 n c 1 f a overvoltage protectionovervoltage protection threshold v out rising (monitored at fb pin) max16935 107 % max16939 105 v out falling (monitored at fb pin) max16935 105 max16939 102 downloaded from: http:///
typical operating characteristics (v sup = v supsw = 14v, v en = 14v, v out = 5v, v fysnc = 0v, r fosc = 12k i , t a = +25 n c, unless otherwise noted.) maxim integrated 5 www.maximintegrated.com max16935/max16939 36v, 3.5a, 2.2mhz step-down converter with 28a quiescent current supply current vs. supply voltage toc09 supply voltage (v) supply current (a) 26 16 15 20 25 30 35 40 45 5010 63 6 5v/2.2mhzskip mode switching frequency vs. r fosc toc08 r fosc (k ) switching frequency (mhz) 102 72 42 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 0 12 132 f sw vs. temperature toc07 temperature (c) f sw (mhz) 110 95 -25 -10 5 35 50 65 20 80 2.04 2.08 2.12 2.16 2.20 2.24 2.28 2.00 -40 125 v in = 14v, pwm mode v out = 5v 425 427 429 431 433 435 437 439 441 443 445 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 f sw (khz) i load (a) f sw vs. load current v in = 14v, pwm mode v out = 3.3v v out = 5v toc06 2.10 2.12 2.14 2.16 2.18 2.20 2.22 2.24 2.26 2.28 2.30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 f sw (mhz) i load (a) f sw vs. load current v in = 14v, pwm mode v out = 3.3v v out = 5v toc05 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v out (v) i load (a) v out load regulation v out = 5v, v in = 14v pwm mode 400khz 2.2mhz toc04 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v out (v) i load (a) v out load regulation v out = 5v, v in = 14v skip mode 400khz 2.2mhz toc03 0 10 20 30 40 50 60 70 80 90 100 0.0000 0.0010 0.1000 10.0000 efficiency (%) load current (a) efficiency vs. load current f sw = 400khz, v in = 14v skip mode pwm mode 3.3v 3.3v 5v 5v toc02 0 10 20 30 40 50 60 70 80 90 100 0.0000 0.0010 0.1000 10.0000 efficiency (%) load current (a) efficiency vs. load current f sw = 2.2mhz, v in = 14v skip mode pwm mode 3.3v 3.3v 5v 5v toc01 downloaded from: http:///
typical operating characteristics (continued) (v sup = v supsw = 14v, v en = 14v, v out = 5v, v fysnc = 0v, r fosc = 12k i , t a = +25 n c, unless otherwise noted.) maxim integrated 6 www.maximintegrated.com max16935/max16939 36v, 3.5a, 2.2mhz step-down converter with 28a quiescent current dips and drops test toc18 v in v out v lx v pgood 5v/2.2mhz 10ms 10v/div0v 0v 5v/div10v/div 0v 0v 5v/div sync function toc17 v lx v fsync 200ns 5v/div 2v/div 10v/div 0v 5v/div 0v 2a/div 0v toc15 v in v out slow v in ramp behavior i load v pgood 5v/div 0v 10v/div 0v 5v/div 0v 1a/div 0v toc14 v in v out full - load startup behavior i load v pgood 5v/div 0v v out vs. v in toc13 v in (v) v out (v) 30 24 18 12 4.97 4.99 5.01 5.03 5.054.95 63 6 5v/400khzpwm mode i load = 0a v out vs. v in toc12 v in (v) v out (v) 36 30 24 18 12 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.084.90 64 2 5v/2.2mhzpwm mode i load = 0a v bias vs. temperature toc11 temperature (c) v bias (v) 110 95 65 80 -10 5 20 35 50 -25 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.024.90 -40 125 i load = 0a v in = 14v, pwm mode shdn current vs. supply voltage toc10 supply voltage (v) supply current (a) 30 24 18 12 1 2 3 4 5 6 7 8 9 10 0 63 6 5v/2.2mhzskip mode downloaded from: http:///
typical operating characteristics (continued) (v sup = v supsw = 14v, v en = 14v, v out = 5v, v fysnc = 0v, r fosc = 12k i , t a = +25 n c, unless otherwise noted.) maxim integrated 7 www.maximintegrated.com max16935/max16939 36v, 3.5a, 2.2mhz step-down converter with 28a quiescent current cold crank toc19 v in v out v pgood 400ms 2v/div 0v 2v/div2v/div 200mv/ div 2a/ div 0a toc21 v out (ac_coupled) load current load transient (pwm mode) load dump toc20 v in v out 100ms 10v/div 0v 0v 5v/div short circuit in pwm mode toc22 v out inductor current 10ms 2v/div 0v 0v 5v/div 2a/div 0a v pgood downloaded from: http:///
pin descriptions pin conigurations www.maximintegrated.com maxim integrated 8 max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current pin name function tqfn tssop 16 1 syncout open-drain clock output. syncout outputs 180 n out-of-phase signal relative to the internal oscillator. connect to out with a resistor between 100 i and 1k w for 2mhz operation. for low frequency operation, use a resistor between 1k w and 10k w . 1 2 fsync synchronization input. the device synchronizes to an external signal applied to fsync. connect fsync to agnd to enable skip mode operation. connect to bias or to an external clock to enable fixed-frequency forced pwm mode operation. 2 3 fosc resistor-programmable switching frequency setting control input. connect a resistor from fosc to agnd to set the switching frequency. 3 4 out switching regulator output. out also provides power to the internal circuitry when the output voltage of the converter is set between 3v to 5v during standby mode. 4 5 fb feedback input. connect an external resistive divider from out to fb and agnd to set the output voltage. connect to bias to set the output voltage to 5v. 5 6 comp error amplifier output. connect an rc network from comp to agnd for stable operation. see the compensation network section for more information. 6 7 bias linear regulator output. bias powers up the internal circuitry. bypass with a 1 f f capacitor to ground. 7 8 agnd analog ground 8 9 bst high-side driver supply. connect a 0.1 f f capacitor between lx and bst for proper operation. 9 10 en sup voltage compatible enable input. drive en low to disable the device. drive en high to enable the device. + tssop 13 4 lx out 14 3 lx fosc 15 2 pgnd fsync 16 1 top view pgood syncout 10 7 en bias 11 6 sup comp 98 bst agnd 12 5 supsw fb ep max16935max16939 + ep 1516 14 13 65 7 fosc fb 8 fsync supswen lx 12 pgnd 4 12 11 9 syncout bstagnd bias comp out sup 3 10 lx tqfn pgood max16935max16939 downloaded from: http:///
pin name function tqfn tssop 10 11 sup voltage supply input. sup powers up the internal linear regulator. bypass sup to pgnd with a 4.7 f f ceramic capacitor. it is recommended to add a placeholder for an rc filter to reduce noise on the internal logic supply (see the typical application circuit ) 11 12 supsw internal high-side switch supply input. supsw provides power to the internal switch. bypass supsw to pgnd with 0.1 f f and 4.7 f f ceramic capacitors. 12, 13 13, 14 lx inductor switching node. connect a schottky diode between lx and agnd. 14 15 pgnd power ground 15 16 pgood open-drain, active-low power-good output. pgood asserts when v out is above 95% regulation point. pgood goes low when v out is below 92% regulation point. ? ? ep exposed pad. connect ep to a large-area contiguous copper ground plane for effective power dissipation. do not use as the only ic ground connection. ep must be connected to pgnd. detailed description the max16935/max16939 are 3.5a current-mode step-down converters with integrated high-side and low-side mosfets designed to operate with an external schottky diode for better efficiency. the low-side mosfet enables fixed-frequency forced-pwm (fpwm) operation under light-load applications. the devices operate with input voltages from 3.5v to 36v, while using only 28 f a quiescent current at no load. the switching frequency is resistor programmable from 220khz to 2.2mhz and can be synchronized to an external clock. the output voltage is available as 3.3v/5v fixed or adjustable from 1v to 10v. the wide input voltage range along with its ability to operate at 98% duty cycle during undervoltage transients make the devices ideal for automotive and industrial applications. under light-load applications, the fsync logic input allows the devices to either operate in skip mode for reduced current consumption or fixed-frequency fpwm mode to eliminate frequency variation to minimize emi. fixed frequency fpwm mode is extremely useful for power supplies designed for rf transceivers where tight emission control is necessary. protection features include cycle-by-cycle current limit, overvoltage protection, and thermal shutdown with auto - matic recovery. additional features include a power- good monitor to ease power-supply sequencing and a 180 n out-of-phase clock output relative to the internal oscillator at syncout to create cascaded power supplies with multiple devices. wide input voltage range the devices include two separate supply inputs (sup and supsw) specified for a wide 3.5v to 36v input voltage range. v sup provides power to the device and v supsw provides power to the internal switch. when the device is operating with a 3.5v input supply, conditions such as cold crank can cause the voltage at sup and supsw to drop below the programmed output voltage. under such conditions, the device operate in a high duty-cycle mode to facilitate minimum dropout from input to output. in applications where the input voltage exceeds 25v, output is 5v, operating frequency is 1.8mhz and the ic is selected to be in fpwm mode by either forcing the fsync pin high, or using an external clock, pulse skipping is observed on the lx pin. this happens due to insufficient minimum on time. under certain load conditions (typically < 1a), a filter circuit from lx to gnd is required to maintain the output voltage within the expected data sheet limits. a typical filter value of r filter = 1 i , c filter = 220pf (see the typical application circuit ) is sufficient to filter out the noise and maintain the output voltage within data sheet limits. this extra filter on the lx pin of the ic has no impact on efficiency. linear regulator output (bias) the devices include a 5v linear regulator (bias) that provides power to the internal circuit blocks. connect a 1 f f ceramic capacitor from bias to agnd. pin descriptions (continued) www.maximintegrated.com maxim integrated 9 max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current downloaded from: http:///
power-good output (pgood)the devices feature an open-drain power-good output, pgood. pgood asserts when v out rises above 95% of its regulation voltage. pgood deasserts when v out drops below 92% of its regulation voltage. connect pgood to bias with a 10k i resistor. overvoltage protection (ovp)if the output voltage reaches the ovp threshold, the high-side switch is forced off and the low-side switch is forced on until negative-current limit is reached. after negative-current limit is reached, both the high-side and low-side switches are turned off. the max16939 offers a lower voltage threshold for applications requiring tighter limits of protection. synchronization input (fsync)fsync is a logic-level input useful for operating mode selection and frequency control. connecting fsync to bias or to an external clock enables fixed-frequency fpwm operation. connecting fsync to agnd enables skip mode operation. the external clock frequency at fsync can be higher or lower than the internal clock by 20%. ensure the duty cycle of the external clock used has a minimum pulse width of 100ns. the devices synchronize to the external clock within one cycle. when the external clock signal at fsync is absent for more than two clock cycles, the devices revert back to the internal clock. figure 1. internal block diagram www.maximintegrated.com maxim integrated 10 max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current fbsw out comp pgood en fb soft start slope comp fbok eamp hsd lsd aon logic cs ref hvldo switch over pwm sup bias bst supswlx pgnd syncout bias fsync fosc agnd osc max16935max16939 downloaded from: http:///
system enable (en) an enable control input (en) activates the device from its low-power shutdown mode. en is compatible with inputs from automotive battery level down to 3.5v. the high voltage compatibility allows en to be connected to sup, key/kl30, or the inhibit pin (inh) of a can transceiver. en turns on the internal regulator. once v bias is above the internal lockout threshold, v uvl = 3.15v (typ), the controller activates and the output voltage ramps up within 8ms. a logic-low at en shuts down the device. during shutdown, the internal linear regulator and gate drivers turn off. shutdown is the lowest power state and reduces the quiescent current to 5 f a (typ). drive en high to bring the device out of shutdown.spread-spectrum option the devices have an internal spread-spectrum option to optimize emi performance. this is factory set and the s-version of the device should be ordered. for spread- spectrum-enabled devices, the operating frequency is varied 6% centered on the oscillator frequency (f osc ). the modulation signal is a triangular wave with a period of 110s at 2.2mhz. therefore, f osc will ramp down 6% and back to 2.2mhz in 110s and also ramp up 6% and back to 2.2mhz in 110s. the cycle repeats. for operations at f osc values other than 2.2mhz, the modulation signal scales proportionally (e.g., at 400khz, the 110s modulation period increases to 110s x 2.2mhz/400khz = 605s). the internal spread spectrum is disabled if the device is synced to an external clock. however, the device does not filter the input clock and passes any modulation (including spread-spectrum) present on the driving external clock to the syncout pin. automatic slew-rate control on lx the devices have automatic slew-rate adjustment that optimizes the rise times on the internal hsfet gate drive to minimize emi. the device detects the internal clock frequency and adjusts the slew rate accordingly. when the user selects the external frequency setting resistor r fosc such that the frequency is > 1.1mhz, the hsfet is turned on in 4ns (typ). when the frequency is < 1.1mhz the hsfet is turned on in 8ns (typ). this slew-rate control optimizes the rise time on lx node externally to minimize emi while maintaining good efficiency. internal oscillator (fosc)the switching frequency (f sw ) is set by a resistor (r fosc ) connected from fosc to agnd. see figure 3 to select the correct r fosc value for the desired switching fre - quency. for example, a 400khz switching frequency is set with r fosc = 73.2k i . higher frequencies allow designs with lower inductor values and less output capacitance. consequently, peak currents and i 2 r losses are lower at higher switching frequencies, but core losses, gate charge currents, and switching losses increase. synchronizing output (syncout) syncout is an open-drain output that outputs a 180 n out-of-phase signal relative to the internal oscillator. overtemperature protection thermal-overload protection limits the total power dissipation in the device. when the junction temperature exceeds 175 n c (typ), an internal thermal sensor shuts down the internal bias regulator and the step-down controller, allowing the device to cool. the thermal sensor turns on the device again after the junction temperature cools by 15 n c. applications information setting the output voltage connect fb to bias for a fixed 5v output voltage. to set the output to other voltages between 1v and 10v, connect a resistive divider from output (out) to fb to agnd ( figure 2 ). use the following formula to determine the r fb2 of the resistive divider network: r fb2 = r total x v fb /v out where v fb = 1v, r total = selected total resistance of r fb1 , r fb2 in , and v out is the desired output in volts. calculate r fb1 (out to fb resistor) with the following equation: out fb1 fb2 fb v rr 1 v ?? ?? = ? ?? ?? ?? ?? ?? where v fb = 1v (see the electrical characteristics table). figure 2. adjustable output-voltage setting www.maximintegrated.com maxim integrated 11 max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current r fb2 r fb1 fb v out max16935max16939 downloaded from: http:///
fpwm/skip modes the devices offer a pin-selectable skip mode or fixed- frequency pwm mode option. they have an internal ls mosfet that turns on when the fsync pin is connected to v bias or if there is a clock present on the fsync pin. this enables the fixed-frequency-forced pwm mode operation over the entire load range. this option allows the user to maintain fixed frequency over the entire load range in applications that require tight control on emi. even though the device has an internal ls mosfet for fixed- frequency operation, an external schottky diode is still required to support the entire load range. if the fsync pin is connected to gnd, the skip mode is enabled on the device. in skip mode of operation, the converter?s switching frequency is load dependent. at higher load current, the switching frequency does not change and the operating mode is similar to the fpwm mode. skip mode helps improve efficiency in light-load applications by allowing the converters to turn on the high-side switch only when the output voltage falls below a set threshold. as such, the converters do not switch mosfets on and off as often as is the case in the fpwm mode. consequently, the gate charge and switching losses are much lower in skip mode. inductor selection three key inductor parameters must be specified for operation with the devices: inductance value (l), inductor saturation current (i sat ), and dc resistance (r dcr ). to select inductance value, the ratio of inductor peak-to-peak ac current to dc average current (lir) must be selected first. a good compromise between size and loss is a 30% peak-to-peak ripple current to average current ratio (lir = 0.3). the switching frequency, input voltage, output voltage, and selected lir then determine the inductor value as follows: out sup out sup sw out v (v v ) l v f i lir ? = where v sup , v out , and i out are typical values (so that efficiency is optimum for typical conditions). the switch - ing frequency is set by r fosc (see figure 3 ). input capacitor the input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit?s switching. the input capacitor rms current requirement (i rms ) is defined by the following equation: out sup out rms load(max) sup v (v v ) ii v ? = i rms has a maximum value when the input voltage equals twice the output voltage (v sup = 2v out ), so i rms(max) = i load(max) /2. choose an input capacitor that exhibits less than +10 n c self-heating temperature rise at the rms input current for optimal long-term reliability. the input voltage ripple is composed of d v q (caused by the capacitor discharge) and d v esr (caused by the esr of the capacitor). use low-esr ceramic capacitors with high ripple current capability at the input. assume the contribution from the esr and capacitor discharge equal to 50%. calculate the input capacitance and esr required for a specified input voltage ripple using the fol - lowing equations: esr in l out v esr i i 2 ? = ? + where: sup out out l sup sw (v v ) v i v fl ? ?= and: out out in q sw supsw i d(1 d) v c and d vf v ? = = ? where i out is the maximum output current and d is the duty cycle. figure 3. switching frequency vs. r fosc www.maximintegrated.com maxim integrated 12 max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current switching frequency vs. r fosc r fosc (k ) switching frequency (mhz) 102 72 42 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 0 12 132 downloaded from: http:///
output capacitorthe output filter capacitor must have low enough esr to meet output ripple and load transient requirements. the output capacitance must be high enough to absorb the inductor energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault protection. when using high-capacitance, low-esr capacitors, the filter capacitor?s esr dominates the output voltage ripple. so the size of the output capaci - tor depends on the maximum esr required to meet the output voltage ripple (v ripple(p-p) ) specifications: ripple (p p ) load (max ) v esr i lir ? = the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value. when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent voltage droop and voltage rise from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. however, low capacity filter capacitors typically have high esr zeros that can affect the overall stability. rectiier selection the devices require an external schottky diode rectifier as a freewheeling diode when they are configured for skip-mode operation. connect this rectifier close to the device, using short leads and short pcb traces. in fpwm mode, the schottky diode helps minimize efficiency losses by diverting the inductor current that would other - wise flow through the low-side mosfet. choose a rectifier with a voltage rating greater than the maximum expected input voltage, v supsw . use a low forward-voltage-drop schottky rectifier to limit the negative voltage at lx. avoid higher than necessary reverse-voltage schottky rectifiers that have higher forward-voltage drops. compensation network the devices use an internal transconductance error ampli - fier with its inverting input and its output available to the user for external frequency compensation. the output capacitor and compensation network determine the loop stability. the inductor and the output capacitor are chosen based on performance, size, and cost. additionally, the compensation network optimizes the control-loop stability. the controller uses a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor. the device uses the voltage drop across the high-side mosfet to sense inductor current. current-mode control eliminates the double pole in the feedback loop caused by the inductor and output capacitor, resulting in a smaller phase shift and requiring less elaborate error-amplifier compensation than voltage-mode control. only a simple single-series resistor (r c ) and capacitor (c c ) are required to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for output filtering ( figure 4 ). for other types of capacitors, due to the higher capacitance and esr, the frequency of the zero created by the capacitance and esr is lower than the desired closed-loop crossover frequency. to stabilize a nonceramic output capacitor loop, add another compensation capacitor (c f ) from comp to gnd to cancel this esr zero. the basic regulator loop is modeled as a power modulator, output feedback divider, and an error amplifier. the power modulator has a dc gain set by g m o r load , with a pole and zero pair set by r load , the output capacitor (c out ), and its esr. the following equations allow to approximate the value for the gain of the power modulator (gain mod(dc) ), neglecting the effect of the ramp stabilization. ramp stabilization is necessary when the duty cycle is above 50% and is internally done for the device. mod ( dc ) m load gain g r = where r load = v out /i lout(max) in i and g m = 3s. in a current-mode step-down converter, the output capacitor, its esr, and the load resistance introduce a pole at the following frequency: = pmod out load 1 f 2c r figure 4. compensation network www.maximintegrated.com maxim integrated 13 max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current r2 r1 v ref v out r c c c c f comp g m downloaded from: http:///
the output capacitor and its esr also introduce a zero at: zmod out 1 f 2 esr c = when c out is composed of ?n? identical capacitors in parallel, the resulting c out = n o c out(each) , and esr = esr (each) /n. note that the capacitor zero for a parallel combination of alike capacitors is the same as for an individual capacitor. the feedback voltage-divider has a gain of gain fb = v fb / v out , where v fb is 1v (typ). the transconductance error amplifier has a dc gain of gain ea(dc) = g m , ea o r out,ea , where g m,ea is the error amplifier transconductance, which is 700 f s (typ), and r out,ea is the output resistance of the error amplifier 50m i . a dominant pole (f dpea ) is set by the compensation capacitor (c c ) and the amplifier output resistance (r out,ea ). a zero (f zea ) is set by the compensation resistor (r c ) and the compensation capacitor (c c ). there is an optional pole (f pea ) set by c f and r c to cancel the output capacitor esr zero if it occurs near the crossover frequency (f c ), where the loop gain equals 1 (0db)). thus: dpea c o u t ,e a c zea cc pea fc 1 f 2 c (r r ) 1 f 2c r 1 f 2cr = + = = the loop-gain crossover frequency (f c ) should be set below 1/5th of the switching frequency and much higher than the power-modulator pole (f pmod ): sw pmod c f ff 5 << the total loop gain as the product of the modulator gain, the feedback voltage-divider gain, and the error amplifier gain at f c should be equal to 1. so: fb mod(fc) ea(fc) out v gain gain 1 v = ea(fc) m, ea c pmod mod(fc) mod(dc) c gain g r f gain gain f = = therefore: fb mod(fc) m,ea c out v gain g r 1 v = solving for r c : out c m,ea fb mod(fc) v r g v gain = set the error-amplifier compensation zero formed by r c and c c (f zea ) at the f pmod . calculate the value of c c a follows: c pmod c 1 c 2f r = if f zmod is less than 5 x f c , add a second capacitor, c f , from comp to gnd and set the compensation pole formed by r c and c f (f pea ) at the f zmod . calculate the value of c f as follows: f zmod c 1 c 2f r = as the load current decreases, the modulator pole also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same. www.maximintegrated.com maxim integrated 14 max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current downloaded from: http:///
typical application circuit pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. use a multilayer board whenever possible for better noise immunity and power dissipation. follow these guidelines for good pcb layout: 1) use a large contiguous copper plane under the ic package. ensure that all heat-dissipating compo - nents have adequate cooling. the bottom pad of the ic must be soldered down to this copper plane for effective heat dissipation and for getting the full power out of the ic. use multiple vias or a single large via in this plane for heat dissipation. 2) isolate the power components and high current path from the sensitive analog circuitry. doing so is essential to prevent any noise coupling into the analog signals. 3) keep the high-current paths short, especially at the ground terminals. this practice is essential for stable, jitter-free operation. the high-current path composed of the input capacitor, high-side fet, inductor, and the output capacitor should be as short as possible. 4) keep the power traces and load connections short. this practice is essential for high efficiency. use thick copper pcbs (2oz vs. 1oz) to enhance full-load efficiency. 5) the analog signal lines should be routed away from the high-frequency planes. doing so ensures integrity of sensitive signals feeding back into the ic. 6) the ground connection for the analog and power section should be close to the ic. this keeps the ground current loops to a minimum. in cases where only one ground is used, enough isolation between analog return signals and high power signals must be maintained. www.maximintegrated.com maxim integrated 15 max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current d1 c out 22f c in2 r comp 20k i r pgood 10k i r syncout 100 i r fosc 12k i l1 2.2h v out 5v at 3.5a c bst 0.22f lx bst v out v bias out v bat fb v bias v out pgood syncout fosc c bias 1f c comp2 12pf bias c comp1 1000pf comp fsync osc sync pulse en supsw sup c in1 power-good output 180 out-of-phase output agnd pgnd max16935max16939 r snub* c snub* *r filter = 1 i and c filter = 220pf required for the following operating conditions: v bat r 25v, v out p 5v, f sw r 1.8mhz, fpwm mode enabled downloaded from: http:///
ordering information/selector guide /v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. **future product contact factory for availability. package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos www.maximintegrated.com maxim integrated 16 max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current package type package code outline no. land pattern no. 16 tqfn-ep t1655+4 21-0140 90-0121 16 tssop-ep u16e+3 21-0108 90-0120 part vout spread spectrum temp range pin-package adjustable (fb connected to resistive divider) (v) fixed (fb connected to bias) (v) max16935 rate/v+ 1 to 10 5 off -40c to +125c 16 tqfn-ep* max16935rateb/v+ 1 to 10 3.3 off -40c to +125c 16 tqfn-ep* max16935raue/v+ 1 to 10 5 off -40c to +125c 16 tssop-ep* max16935raueb/v+ 1 to 10 3.3 off -40c to +125c 16 tssop-ep* max16935sate/v+ 1 to 10 5 on -40c to +125c 16 tqfn-ep* max16935sateb/v+ 1 to 10 3.3 on -40c to +125c 16 tqfn-ep* max16935saue/v+ 1 to 10 5 on -40c to +125c 16 tssop-ep* max16935saueb/v+ 1 to 10 3.3 on -40c to +125c 16 tssop-ep* max16939 atera/v+ 1 to 10 5 off -40c to +125c 16 tqfn-ep* max16939aterb/v+ 1 to 10 3.3 off -40c to +125c 16 tqfn-ep* max16939auera/v+** 1 to 10 5 off -40c to +125c 16 tssop-ep* max16939auerb/v+** 1 to 10 3.3 off -40c to +125c 16 tssop-ep* max16939atesa/v+ 1 to 10 5 on -40c to +125c 16 tqfn-ep* max16939atesb/v+ 1 to 10 3.3 on -40c to +125c 16 tqfn-ep* max16939auesa/v+** 1 to 10 5 on -40c to +125c 16 tssop-ep* max16939auesb/v+** 1 to 10 3.3 on -40c to +125c 16 tssop-ep* downloaded from: http:///
revision history maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. ? 2016 maxim integrated products, inc. 17 max16935/max16939 36v, 3.5a, 2.2mhz step-down converters with 28a quiescent current revision number revision date description pages changed 0 12/13 initial release ? 1 2/14 corrected typo for g m value in compensation network section 13 2 3/14 updated pgood pin description and updated spread spectrum , automatic slew- rate control on lx , and internal oscillator (fosc) sections 9, 11 3 1/15 added tqfn options to general description, absolute maximum ratings, package thermal characteristics, pin configurations , pin description , package information, and ordering information 1, 2, 8, 9, 18 4 2/15 updated the benefits and features section 5 3/15 corrected the first equation on the top left side of page 14 6 5/15 added 3.3v output-voltage option; updated general description , absolute maximum ratings , package thermal characteristics , electrical characteristics , and detailed description sections, deleted graph 16 and replaced graphs 01?06, 14, 15, 21 in typical operating characteristics ; added four new /v opns to ordering information/ selector guide 1?7, 9, 16 7 5/15 removed future product designations in ordering information 16 8 6/15 added the max16939 to the data sheet as a future product 1?17 9 6/15 corrected max16939 variants in ordering information/selector guide 16 10 4/16 added bullet to benefits and features section, removed future product references 1, 16 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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