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microwave wideband synthesizer with integrated vco data sheet adf4355 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed b y analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 C 2016 analog devices, in c. all rights reserved. technical support www.analog.com features rf o utput frequency range: 54 mhz to 68 00 mhz fractional - n synthesizer and i nteger - n synthesizer hig h resolution 38 - bit modulus low phase noise , voltage controlled oscillator ( vco ) programmable divide by 1, 2, 4, 8, 16, 32, or 64 output analog and digital power supplies: 3.3 v charge pump and vco power supplies: 5 .0 v typical logic compatibility: 1.8 v programmable dual modulus prescaler of 4/5 or 8/9 programmable output power level rf output mute function 3 - wire serial interface analog and digital lock detect applications wireless infrastructure (w - cdma, td - scdma, wimax, gsm, pcs, dcs, dect) point to point/point to multipoint microwa ve links satellite s /vsat s test equipment/ i nstrumentation clock generation general description the adf4355 allows implementation of fractional - n or integer - n phase - locked loop (pll) frequency synthesizers when used with an external loop filter and an external reference frequency. a series of frequency dividers permits operation from 5 4 mhz to 6800 mhz. the adf4355 has an integrated vco with a fundamental output frequency ranging from 3400 m hz to 6800 mhz . in addition, the vco frequency is connecte d to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate radio frequency ( rf ) output frequencies as low as 5 4 mhz. for applications that require isolation , the rf output stage can be mute d . the mute function is both pin and software controllable. control of all on - chip registers is through a simple 3 - wire interface . the adf4355 operates with ana log and digital power supplies ranging from 3.15 v to 3.45 v, with charge pump and vco supplies from 4.75 v to 5.25 v. t h e adf4355 also conta ins hardware and software power - down modes. functional block dia gram 12910-001 m u x o u t c p o u t c reg 2 v bias r ef i n c l k da t a l e a v c reg 1 d v d d d d v p a gnd c e c p g n d sd g n d a g nd v c o r se t v v c o v t un e v r e f r f o u t a + r f o u t a C r f o u t b + r f o u t b C v c o c o r e p ha se c o mp ara t o r char g e p u mp o u t p u t s t a g e o u t p u t s t a g e p d b r f m u lt i p l exer 10 - b i t r c o un t er 2 d i v i d er 2 d o ub l er f unc t io n l a t c h da t a r e gi s t er i n t e g er r egister n c o un t er f rac t io n t h i rd - o rd er f rac t io na l i n t e r p o l a t o r m o du l u s m u lt i p l exer l o c k d e t e c t 1 / 2 / 4 /8 16/32/64 ad f 4 355 r ef i n a b v rf a g nd rf v r e gvco a v d d r egister r egister figure 1.
adf4355* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? adf4355 evaluation board documentation data sheet ? adf4355: microwave wideband synthesizer with integrated vco data sheet user guides ? ug-805: evaluating the adf4355 microwave wideband synthesizer with integrated vco tools and simulations ? adisimfrequency planner tool ? adisimpll? reference materials press ? analog devices pll with vco synthesizer improves base station performance and wireless service quality technical articles ? replacing yig-tuned oscillators with silicon by using an ultrawideband pll/vco with precise phase control ? wideband phase-locked loops with integrated voltage controlled oscillators design resources ? adf4355 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all adf4355 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
adf4355 data sheet rev. a | page 2 of 35 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specificatio ns ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 transistor count ........................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 circuit description ......................................................................... 12 reference input section ............................................................. 12 rf n divider ............................................................................... 12 phase frequency detector (pfd) and charge pump ............ 13 muxout and lock detect ...................................................... 13 input shift registers ................................................................... 13 program modes .......................................................................... 13 vco .............................................................................................. 14 output stage ................................................................................ 14 register maps .................................................................................. 16 register 0 ..................................................................................... 18 register 1 ..................................................................................... 19 register 2 ..................................................................................... 20 register 3 ..................................................................................... 21 register 4 ..................................................................................... 22 register 5 ..................................................................................... 23 register 6 ..................................................................................... 24 register 7 ..................................................................................... 26 register 8 ..................................................................................... 27 register 9 ..................................................................................... 27 register 10 ................................................................................... 28 register 11 ................................................................................... 28 register 12 ................................................................................... 29 register initialization sequence ............................................... 2 9 frequency update sequence ..................................................... 29 rf synthesizer a worked example ...................................... 30 reference doubler and reference divider ............................. 30 spurious optimization and fast lock ..................................... 30 optimizing jitter ......................................................................... 31 spur mechanisms ....................................................................... 31 lock time .................................................................................... 31 applications information .............................................................. 32 direct conversion modulator .................................................. 32 power supplies ............................................................................ 33 printed circuit board (pcb) design guidelines for a chip - scale package .............................................................................. 33 output matching ........................................................................ 34 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 35 revision history 3 /1 6 rev . 0 to rev. a added doubler enabled parameter, table 1 ................................. 3 changes to table 2 ............................................................................ 5 deleted vp, vvco to avdd parameter, table 3 ........................ 6 changes to table 4 ............................................................................ 7 changes to reference input section and int, frac1, frac2, mod1, mod2, and r counter relationship section title ...... 12 changes to figure 28 ...................................................................... 16 changes to automatic calibration (autocalibration) section and prescaler section ..................................................................... 18 changes to phase resync section ................................................ 21 changes to negative bleed section .............................................. 24 change to figure 36 ....................................................................... 24 change to reserved section .......................................................... 25 changes to loss of lock (lol) mode section ........................... 26 changes to adc clock divider (adc_clk _div ) section ... 28 changes to register initialization sequence section and changes to frequency update s equence section ...................... 29 changes to rf syn thesizer a worked example section ........ 30 change to figure 44 ....................................................................... 3 2 changes to power supplies section and figure 45 .................... 33 4 /1 5 revision 0 : initial version
data sheet adf4355 rev. a | page 3 of 35 specifications av dd = dv dd = v rf = 3.3 v 5%, 4.75 v v p = v vco 5. 2 5 v, a gnd = cp gnd = a gndvco = sd gnd = a gndrf = 0 v, r set = 5.1 k?, dbm referred to 50 ?, t a = t min to t max , unless otherwise noted. table 1 . parameter symbol min typ max unit test conditions/comments ref in a/ref in b characteristics input frequency for f < 10 mhz, ensure slew rate > 21 v/s single - ended mode 10 250 mhz differential mode 10 600 mhz doubler enabled 100 mhz doubler is set in register 4, bit db26 input sensitivity single - ended mode 0.4 av dd v p -p ref in a biased at av dd /2; ac coupling ensures av dd /2 bias differential mode 0.4 1.8 v p -p lvds and lvpecl compatible, ref in a/ref in b biased at 2.1 v; ac coupling ensures 2.1 v bias input capacitance single - ended mode 6.9 pf differential mode 1.4 pf input current 60 a single - ended reference programmed 250 a differential reference programmed phase detector frequency 125 mhz charge pump (cp) charge pump current, sink/source i cp r set = 5.1 k? high value 4.8 ma low value 0.3 ma r set range 5.1 k? fixed current matching 3 % 0.5 v v cp 1 v p ? 0.5 v i cp vs. v cp 1 3 % 0.5 v v cp 1 v p ? 0.5 v i cp vs. temperature 1.5 % v cp 1 = 2.5 v logic inputs input high voltage v inh 1.5 v input low voltage v inl 0.6 v input current i inh /i inl 1 a input capacitance c in 3.0 pf logic outputs output high voltage v oh dv dd ? 0.4 v 1.5 1.8 v 1.8 v output selected output high current i oh 500 a output low voltage v ol 0.4 v i ol 2 = 500 a power supplies analog power av dd 3.15 3.45 v digital power and rf supply voltage dv dd , v rf av dd voltages must equal av dd charge pump and vco voltage v p , v vco 4.75 5.0 5.25 v v p must equal v vco charge pump supply power current i p 8 9 digital power supply current + analog power supply curent 3 di dd , ai dd 62 69 ma output dividers 6 to 36 ma each output divide by 2 consumes 6 ma supply current i vco 70 85 ma rf out a/rf out b supply current x rf out i 16/20/ 42/55 20/35/ 50/70 ma rf output stage is programmable; rf out b+/rf out b? powered off low power sleep mode 500 a hardware power - down 1000 a software power - down
adf4355 data sheet rev. a | page 4 of 35 parameter symbol min typ max unit test conditions/comments rf output characteristics vco frequency range 3400 6800 mhz fundamental vco range rf output frequency 53.125 6800 mhz vco sensitivity k v 15 mhz/v frequency pushing (open - loop) 15 mhz/v frequency pulling (open - loop) 0.5 mhz voltage standing wave ratio (vswr) = 2:1 harmonic content second ?27 dbc fundamental vco output (rf out a+) ?22 dbc divided vco output (rf out a+) third ?20 dbc fundamental vco output (rf out a+) ?12 dbc divided vco output (rf out a+) rf output power 4 +8 dbm rf out a+ = 1 ghz +3 dbm rf out a+/rf out a? = 4.4 ghz rf output power variation 1 db rf out a+/rf out a? = 4.4 ghz rf output power variation (over frequency) 3 db rf out a+/rf out a? = 1 ghz to 4.4 ghz level of signal with rf output disabled ?60 dbm rf out a+/rf out a? = 1 ghz, vco = 4 ghz ?30 dbm rf out a+/rf out a? = 4.4 ghz, vco = 4.4 ghz noise characteristics fundamental vco phase noise performance vco noise in open - loop conditions ?116 dbc/hz 100 khz offset from 3.4 ghz carrier ?136 dbc/hz 800 khz offset from 3.4 ghz carrier ?138 dbc/hz 1 mhz offset from 3.4 ghz carrier ?155 dbc/hz 10 mhz offset from 3.4 ghz carrier ?113 dbc/hz 100 khz offset from 5.0 ghz carrier ?133 dbc/hz 800 khz offset from 5.0 ghz carrier ?135 dbc/hz 1 mhz offset from 5.0 ghz carrier ?153 dbc/hz 10 mhz offset from 5.0 ghz carrier ?110 dbc/hz 100 khz offset from 6.8 ghz carrier ?130 dbc/hz 800 khz offset from 6.8 ghz carrier ?132 dbc/hz 1 mhz offset from 6.8 ghz carrier ?150 dbc/hz 10 mhz offset from 6.8 ghz carrier normalized in - band phase noise floor fractional channel 5 ?221 dbc/hz integer channel 6 ?223 dbc/hz normalized 1/f noise, pn 1_f 7 ?116 dbc/hz 10 khz offset; normalized to 1 ghz integrated rms jitter 150 fs spurious signals due to phase frequency detector (pfd) frequency ?80 dbc 1 v cp is the voltage at the cp out pin. 2 i ol is the output low current. 3 t a = 25c; av dd = dv dd = v rf = 3.3 v; v vco = v p = 5.0 v; prescaler = 4/5; f ref in = 122.88 mhz; f pfd = 61.44 mhz; and f rf = 1650 mhz. 4 rf output power using the ev - adf4355sd1z evaluation board measured into a spectrum analyzer, with board and cable losses de - embedded. the ev - adf4355sd1z rf outputs are pulled up externally using a 4.7 nh inductor. un used rf output pins are terminated in 50 ?. 5 use t his figure to calculate the phase noise for any application. to calculate in - band phase noise performance as seen at the vco output, use the following formula: ?221 + 10log(f pfd ) + 20logn. the value given is the lowest noise mode for the fractional channel. 6 use t his figure to calculate the phase noise for any application. to calculate in - band phase noise performance as seen at the vco output, use the following formula: ?223 + 10log(f pfd ) + 20logn. the value given is the lowest noise mode for the integer channel. 7 the pll phase noise is com posed of 1/f (flicker) noise plus the normalized pll noise floor. the formula for calculating the 1/f noise contribution at a n rf frequency (f rf ) and at a frequency offset (f) is given by pn = p 1_f + 10log(10 khz/f) + 20log(f rf /1 ghz). both the normalized phase noise floor and flicker noise are modeled in the adisimpll design tool.
data sheet adf4355 rev. a | page 5 of 35 timing characteristics av dd = dv dd =v rf = 3.3 v 5%, 4.75 v v p = v vco 5.25 v, a gnd = cp gnd = a gndvco = sd gnd = a gndrf = 0 v, r set = 5.1 k, dbm referred to 50 , t a = t min to t max , unless otherwise noted. table 2. write timing parameter limit unit description f clk 50 mhz max serial peripheral interface clk frequency t 1 10 ns min le setup time t 2 5 ns min data to clk setup time t 3 5 ns min data to clk hold time t 4 10 ns min clk high duration t 5 10 ns min clk low duration t 6 5 ns min clk to le setup time t 7 20 or (2/f pfd ), whichever is longer ns min le pulse width write timing diagram clk data le db31 (msb) db30 db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 db2 (control bit c3) db3 (control bit c4) 12910-002 figure 2. write timing diagram
adf4355 data sheet rev. a | page 6 of 35 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating v rf , dv dd , av dd to gnd 1 ?0.3 v to +3.6 v av dd to dv dd ?0.3 v to +0.3 v v p , v vco to gnd 1 ?0.3 v to +5.8 v cp out to gnd 1 ?0.3 v to v p + 0.3 v digital input/output voltage to gnd 1 ?0.3 v to dv dd + 0.3 v analog input/output voltage to gnd 1 ?0.3 v to av dd + 0.3 v ref in a, ref in b to gnd 1 ?0.3 v to av dd + 0.3 v ref in a to ref in b 2.1 v operating temperature range ?40c to +85c storage temperature range ?65c to +125c maximum junction temperature 150c ja , thermal impedance pad soldered to gnd 1 27.3c/w reflow soldering peak temperature 260c time at peak temperature 40 sec electrostatic discharge (esd) charged device model 1 00 0 v human body model 2500 v 1 gnd = a gnd = sd gnd = a gndrf = a gndvco = cp gnd = 0 v. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. th e adf4355 is a high performance rf integrated circuit with an esd rating of 2500 v and is esd sensitive. take p roper precautions for handling and assembly. transistor count the transistor count for the adf4355 is 103 ,665 (cmos) and 3214 (bipolar). esd caution
data sheet adf4355 rev. a | page 7 of 35 pin configuration and fu nction descriptions 12910-003 clk data le ce v bias v ref c reg 2 ref in a ref in b sd gnd v p cp out cp gnd muxout r set rf out a+ rf out a ? rf out b+ rf out b ? v tune a gndvco a gndvco pdb rf c reg 1 a gndrf v vco notes 1. the exposed pad must be connected to a gnd . dv dd v regvco a gnd av dd v rf av dd 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 adf4355 top view (not to scale) figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 clk serial clock input. data is clocked in to the 32-bit shift register on the clk rising edge. this input is a high impedance cmos input. 2 data serial data input. the serial data is loaded most significan t bit (msb) first with the four least significant bits (lsbs) as the control bits. this input is a high impedance cmos input. 3 le load enable, cmos input. when le goes high, the data stor ed in the shift register is loaded into the register selected by the four lsbs. 4 ce chip enable. a logic low on this pin powers down the devi ce and puts the charge pump into three-state mode. a logic high on this pin powers up the device, depending on the status of the power-down bits. 5, 16 av dd analog power supply. this pin ranges from 3.15 v to 3.45 v. connect decoupling capacitors to the analog ground plane as close to this pin as possible. av dd must have the same value as dv dd . 6 v p charge pump power supply. v p must have the same value as v vco . connect decoupling capacitors to the ground plane as close to v p as possible. 7 cp out charge pump output. when enab led, this output provides i cp to the external loop filter. the output of the loop filter is connected to v tune to drive the internal vco. 8 cp gnd charge pump ground. this output is the ground return pin for cp out . 9 a gnd analog ground. ground return pin for av dd . 10 v rf power supply for the rf output. connect decoupling capacito rs to the analog ground plane as close to this pin as possible. v rf must have the same value as av dd . 11 rf out a+ vco output. the output level is programmable. the vco fundamental output or a divided down version is available. 12 rf out a? complementary vco output. the output level is programma ble. the vco fundamental output or a divided down version is available. 13 a gndrf rf output stage ground. ground return pins for the rf output stage. 14 rf out b+ auxiliary vco output. the output level is programmable. the vco fundamental output or a divided down version is available. 15 rf out b? complementary auxiliary vco output. the output level is programmable. the vco fundamental output or a divided down version is available. 17 v vco power supply for the vco. the voltage on this pin ranges fr om 4.75 v to 5.25 v. connect decoupling capacitors to the analog ground plane as close to this pin as possible. 18, 21 a gndvco vco ground. ground return path for the vco. 19 v regvco vco compensation node. connect decoupling capacitors to the ground plane as close to this pin as possible. connect v regvco directly to v vco . 20 v tune control input to the vco. this voltage determines th e output frequency and is de rived from filtering the cp out output voltage. the capacitance at this pin (v tune input capacitance) is 9 pf. 22 r set bias current resistor. connecting a resistor between this pin and ground sets the ch arge pump output current. 23 v ref internal compensation node. dc biased at half the tuning range. connect de coupling capacitors to the ground plane as close to this pin as possible. 24 v bias reference voltage. connect a 100 nf decoupling capacitor to the ground plane as close to this pin as possible.
adf4355 data sheet rev. a | page 8 of 35 pin no. mnemonic description 25, 32 c reg 1, c reg 2 output s from the ldo r egulator. c reg 1 and c reg 2 are the s upply voltage s to the digital circuits and have a n ominal voltage of 1.8 v. decoupling capacitors of 100 nf connected to a gnd are required for these pins . 26 pdb rf rf power - down. a logic low o n this pin mutes the rf outputs. this mut e function is also software controllable. 27 dv dd digital power supply. this pin must be at the same voltage as av dd . place decoupling capacitors to the ground plane as close to this pin as possible. 28 ref in b complementary reference input. if unused, ac - couple this pin to a gnd . 29 ref in a reference input. 30 muxout multiplexer output. the multiplexer output allows the digital lock detect, the analog lock detect, scaled rf, or the scaled reference frequency t o be externally accessible. 31 sd gnd digital - modulator ground. sd gnd is the g round return path for the - modulator. ep exposed pad. the exposed pad must be connected to a gnd .
data sheet adf4355 rev. a | page 9 of 35 typical performance characteristics C170 C150 C130 C 1 10 C90 C70 C50 1k 10k 100k 1m 10m 100m frequenc y (hz) phase noise (dbc/hz) 12910-004 figure 4 . open - loop vco phase noise, 3.4 ghz 1k 10k 100k 1m 10m 100m frequenc y (hz) phase noise (dbc/hz) C170 C150 C130 C1 10 C90 C70 C50 12910-005 5 - 50 1k 10k 100k 1m 10m 100m frequenc y (hz) phase noise (dbc/hz) C170 C150 C130 C 1 10 C90 C70 C50 12910-006 6 - 68 1k 10k 100k 1m 10m 100m frequenc y (hz) phase noise (dbc/hz) C170 C150 C130 C 1 10 C90 C70 C50 1 2 4 8 16 32 64 12910-007 7 - 34 6144 20 1k 10k 100k 1m 10m 100m frequenc y (hz) phase noise (dbc/hz) C170 C150 C130 C 1 10 C90 C70 C50 1 2 4 8 16 32 64 12910-008 8 - 50 6144 20 1k 10k 100k 1m 10m 100m frequenc y (hz) phase noise (dbc/hz) C170 C150 C130 C 1 10 C90 C70 C50 1 2 4 8 16 32 64 12910-009 9 - 68 6144 20
adf4355 data sheet rev. a | page 10 of 35 1k 10k 100k 1m 10m 100m frequenc y (hz) phase noise (dbc/hz) C170 C150 C130 C1 10 C90 C70 C50 1 2 12910-010 figure 10 . closed - loop phase noise , rf out a+, fundamental vco and divide by 2, vco = 3.4 ghz, pfd = 61.44 mhz, loop bandwidth = 2 khz 1k 10k 100k 1m 10m 100m frequenc y (hz) phase noise (dbc/hz) C170 C150 C130 C1 10 C90 C70 C50 1 2 12910-0 1 1 11 - 2 50 6144 2 1k 10k 100k 1m 10m 100m frequenc y (hz) phase noise (dbc/hz) C170 C150 C130 C 1 10 C90 C70 C50 1 2 12910-012 12 - 2 68 6144 2 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 output power (dbm) frequenc y (ghz) 12910-016 C40c +25c +85c fe 13 . otpt poe s. feenc , rf out a+/rf out a (7.5 nh indctos, 10 pf bpass capactos, boad losses de - emedded) C50 C45 C40 C35 C30 C25 C20 C15 C10 C5 0 1 2 3 4 5 6 7 power (dbc) frequenc y (ghz) 12910-017 second harmonic third harmonic fe 14 . rf out a+/rf out a h amoncs s. feenc (7.5 nh indctos, 10 pf bpass capactos, boad losses de - emedded) frequenc y (ghz) power (dbm) C10 C8 C6 C4 C2 0 2 4 6 8 10 0 1 2 3 4 5 6 7 12910-018 15 100 100
data sheet adf4355 rev. a | page 11 of 35 0.8 1.8 2.8 3.8 4.8 5.8 6.8 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 rms jitter (ps) output frequenc y (ghz) rms jitter (ps) 1khz t o 20mhz rms jitter (ps) 12khz t o 20mhz 12910-021 figure 16 . rms jitter vs. output frequency, pfd frequency = 61.44 mhz, loop filter = 20 khz C 1 10 C100 C90 C80 C70 C60 C50 pfd spur amplitude (dbc) rf out a+/rf out aC output frequenc y (ghz) 12910-022 0 1 2 3 4 5 6 7 pfd = 15.36mhz pfd = 30.72mhz pfd = 61.44mhz fe 17 . pfd sp ampltde s. rf out a+/rf out a otpt feenc, pfd = 15.36 mhz, pfd = 30.72 mhz, pfd = 61.44 mhz, loop flte = 20 khz 1k 10k 100k 1m 10m 100m frequenc y (hz) noise and spur power (dbc/hz) C160 C150 C140 C130 C120 C 1 10 C100 C90 C80 12910-024 18 - 1800 15502 12288 6144 4 2 0 20 1k 10k 100k 1m 10m 100m frequenc y (hz) noise and spur power (dbc/hz) C160 C150 C140 C130 C120 C 1 10 C100 C90 C80 12910-025 19 - - 21135 12288 6144 2 2 0 20 1k 10k 100k 1m 10m 100m frequenc y (hz) noise and spur power (dbc/hz) C160 C150 C140 C130 C120 C 1 10 C100 C90 C80 12910-026 20 - 2591 12288 6144 - - 2 2 0 20 4.65 4.15 C1 0 1 2 3 4 4.20 1 4.25 4.30 4.35 4.40 4.45 4.50 4.55 frequenc y (ghz) time (ms) 4.60 12910-128 21 250 4150 4400 20
adf4355 data sheet rev. a | page 12 of 35 circuit description reference input sect ion figure 22 shows the reference input stage. the reference input can accept both single - ended and differential signals . use t he referenc e mode bit (register 4, bit db9) to select the signal . to use a differential signal on the reference input, program this bit high. in this case , sw 1 and sw2 are open, sw3 and sw4 are closed , and the current source that driv es the d ifferential pair of transistors switche s on. the differential signal buffer s and provide s an emitter - coupled logic ( ecl ) to the cmos converter. when a single - ended signal is used as the reference, program bit db9 in register 4 to 0. connect the single - ended reference signal to ref in a. in this case , sw1 and sw2 are closed, sw3 and sw4 are open , and the current source that driv es the differential pair of transistors switche s off. 2.5k 2.5k ref in a ref in b av dd bias generator buffer 85k ? sw2 sw3 sw1 reference input mode sw4 ecl t o cmos converter t o r counter mul tiplexer 12910- 226 figure 22 . reference input stage rf n divider t he rf n divider allows a division ratio in the pll feedback path. determine t he division ratio by the int, frac1, frac2 , and mod2 values that this divider comprises . third-order fractiona l interpol a t or frac1 int rf n counter from vco output/ output dividers t o pfd n counter frac2 v alue mod2 v alue n = int + frac1 + mod1 frac2 mod2 12910-027 register register figure 23 . rf n divider int, frac 1, frac2 , mod 1, mod2 , and r counter relationship the int, frac1, frac2, mod1, and mod2 values, in conjunction with the r counter, make it possible to generate output frequencies spaced by fractions of the pfd frequency (f pfd ). for more informa tion, see the rf s ynthesizer a worked example section. calculate the rf vco frequency ( vco out ) b y vco out = f pfd n (1) where: vco out is the output frequency of the vco (without using the output divider). f pfd is the frequency of the phase frequency detector. n is the desired value of the feedback counter, n. calculate f pfd by f pfd = ref in [(1 + d )/( r (1 + t ))] (2) where: ref in is the reference input frequency. d is the ref in doubler bit. r is the preset divide ratio of the binary 10 - bit programmable reference counter (1 to 1023). t is the ref in divide by 2 bit (0 or 1) . n comprises mod1 mod2 frac2 frac1 int n () here int is the 16 - bit integer value (23 to 32,767 for the 4/5 prescaler, 75 to 65,535 for the 8/9 prescaler). frac1 is the numerator of the primary modulus (0 to 16,777,215). frac2 is the numerator of the 14 - bit auxiliary modulus (0 to 16,383). mod2 is the programmable, 14 - bit auxiliary fractional modulus (2 to 1 6,383). mod1 is a 24 - bit primary modulus with a fixed value of 2 24 = 16,777,216. equation 3 results in a very fine frequency resolution with no residual frequency error. to apply this formula , take the following steps: 1. calculate n by dividing vco out /f pfd . 2. the integer value of this number forms int. 3. sub tract th e int value from the full n value. 4. multiply the remainder by 2 24 . 5. the integer value of this number forms frac1. 6. calculate mod2 based on the channel spacing (f chsp ) by mod2 = f pfd / gcd ( f pfd , f chsp ) (4) where: gcd(f pfd , f chsp ) is the greatest common divider of the pfd frequency and the channel spacing frequency. f chsp is the desired channel spacing frequency.
data sheet adf4355 rev. a | page 13 of 35 7. calculate frac2 by the following equation: frac2 = [( n ? int ) 2 24 ? frac1 )] mod2 (5) the frac2 and mod2 fraction result s in outputs with zero frequency error for channel spacings when f pfd /gcd( f pfd / f chsp ) < 16,383 ( 6 ) where: f pfd is the frequency of the phase frequency detector. gcd is a greatest c ommon denominator function. f chsp is the desired channel spacing frequency . if zero frequency error is not required, the mod1 and mod2 denominators operate together to create a 38 - bit resolution modulus. int n mode when frac1 and frac2 = 0, the synthesizer operates in integer - n mode. r counter the 10 - bit r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 1023 are allowed. phase frequency dete ctor (pfd) and charge pump the pfd takes inputs from th e r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 24 is a simplified schematic of the pfd . the pfd includes a fixed delay element that sets the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and provides a consistent reference spur level. set t he phase detector polarity to po sitive on th is device because of the positive tuning of the vco. u3 clr2 q2 d2 u2 down up high high cp Cin +in charge pump del a y clr1 q1 d1 u1 12910-028 figure 24 . pfd simplified schematic muxout and lock dete ct the output multiplexer on the adf4355 allows the user to access various internal points on the chip. the m3, m2, and m1 bits in register 4 control the state of muxout. figure 25 shows the muxout section in block diagram form. sd gnd dv dd control mux muxout analog lock detect digi t a l lock detect r divider output n divider output sd gnd rese r ved three-s ta te output dv dd 12910-029 figure 25 . muxout block diagram input shift register s the adf4355 digital section includes a 10 - bit r counter , a 16- bit rf i nteger - n counter, a 24 - bit frac1 counter, a 14 - bit auxiliary fractional counter , and a 14 - bit auxiliary modulus counter . data clock s into the 32 - bit shift register on each rising edge of clk. the data clock s in msb first. data transfer s from the shift register to one of 12 latches on the rising edge of le. the state of the four control bits ( c4 , c3 , c2, and c1 ) in the shift register determines the destination latch. as shown in figure 2 , the four least significant bit s (lsbs) are db3, db2, db1, and db0. the truth table for these bits is shown in table 5 . figure 28 and figure 29 summarize the program ing of the latches. table 5 . truth table for the c4, c3, c2, and c1 control bits control bits register c4 c3 c2 c1 0 0 0 0 register 0 0 0 0 1 register 1 0 0 1 0 register 2 0 0 1 1 register 3 0 1 0 0 register 4 0 1 0 1 register 5 0 1 1 0 register 6 0 1 1 1 register 7 1 0 0 0 register 8 1 0 0 1 register 9 1 0 1 0 register 10 1 0 1 1 register 11 1 1 0 0 register 12 program modes table 5 and figure 28 through figure 42 show the program modes that must be set up in the adf4355 . the following settings in the adf4355 are double buffered: main fractional value (frac1), auxiliary modulus value (mod2), auxiliary fractional value (frac2), reference doubler, reference divide by 2 (rdiv2), r counter value, and charge pump current setting. t wo events must occur before the adf4355 uses a new value for any of the double buffered settings. first, the new value must latch into the device by writing to the appropriate register , and s econd, a new write to register 0 must be performed.
adf4355 data sheet rev. a | page 14 of 35 for example, to ensure that the modulus value loads correctly, every time the modulus value update s , register 0 must be written to. the rf d ivider select in register 6 is also double buffered, but only when bit db14 of register 4 is high. vco the vco core in the adf4355 consists of four separate vcos, each of which uses 256 overlapping bands , which allow s covering a w ide frequency range without a large vco sensitivity (k v ) and wi thout resultant poor phase noise and spurious performance. the correct vco and band are chosen automatically by the vco and band select logic when register 0 is updated and auto - calibration is enabled . the vco v tune is disconnected from the output of the loop filter and is connected to an internal reference voltage. the r counter output is used as the clock for the band select logic. after band selection, normal pll action resumes. the nominal value of k v is 1 5 mhz/v when the n divider is driven from the vco output , or th e k v value is divided by d. d is the output divider value if the n divider is driven from the rf output divider (chosen by programming bits[d23:d21] in register 6). the vco shows variation of k v as the tuning voltage , v tune , varies within the band and from band to band. for wideband applications covering a wide frequency range (and changing output dividers), a value of 1 5 mhz/v provides the most accurate k v , because this value is closest to the average value. figure 26 shows how k v varies with fundamental vco frequency along with an average value for the frequency band. users may prefer this figure when using narrow - band designs. frequenc y (ghz) 0 5 10 15 20 25 30 35 40 45 50 3.3 3.8 4.3 4.8 5.3 5.8 6.3 6.8 vco sensitivit y , k v (mhz/v) a verage vco sensitivit y linear trend line 12910-133 figure 26 . k v vs. frequency output stage the rf out a+ and rf out a? pins of the adf4355 connect to the collectors of an npn differential pair driven by buffered outputs of the vco, as shown in figure 27 . in this scheme , the adf4355 contains internal 50 ? resistors connected to the v rf pin. t o optimize the power dissipation vs. the output power requirements, the tail current of the differential pair is programmable using bits[d2:d1] in register 6. four curre nt levels can be set. these levels give approximate output power levels of ?4 dbm, ?1 dbm, +2 dbm, and +5 dbm, respectively, using a 50 ? resistor to v rf and ac coupling into a 50 ? load . for accurate power levels, refer to the typical performan ce characteristics sec tion . w ith an output power of 5 dbm, a n external shunt inductor is necessary to provide higher power levels ; however, this addition results in less wideband than the internal bias only. terminate t he unused complementary output with a similar circuit to the used output. vco rf out a+ rf out aC v rf v rf 50 50 buffer/ divide b y 1/2/4/8/ 16/32/64 12910-032 figure 27 . output stage another feature of the adf4355 is that the supply current to the output stage s can shut down until the adf4355 achieves lock as measured by the digital lock detect circuitry. the mute till lock detect (mtld) bit (db11) in register 6 enable s this . the rf out b+/ rf out b? pins are duplicate output s that can be used i ndependently or in addition to the rf out a+/rf out a? pins .
data sheet adf4355 rev. a | page 15 of 35 table 6 . total i dd (rf out a r efers to rf out a+/rf out a?) divide by rf out a off rf out a = ?4 dbm rf out a = ?1 dbm rf out a = +2 dbm rf out a = +5 dbm 5 v supply (i vco and i p ) 78 ma 78 ma 78 ma 78 ma 78 ma 3.3 v supply (ai dd , di dd , i rf ) 1 79.8 ma 101.3 ma 111.9 ma 122.7 ma 132.8 ma 2 87.8 ma 110.1 ma 120.6 ma 131.9 ma 141.9 ma 4 97.1 ma 119.3 ma 130.1 ma 141.6 ma 152.1 ma 8 104.9 ma 127.1 ma 137.8 ma 149.2 ma 159.7 ma 16 109.8 ma 131.8 ma 142.7 ma 154.1 ma 164.6 ma 32 113.6 ma 135.5 ma 146.5 ma 157.8 ma 168.4 ma 64 115.9 ma 137.8 ma 148.9 ma 160.1 ma 170.8 ma
adf4355 data sheet rev. a | page 16 of 35 register map s 1 dbr = double buffered registerbuffered b y the write t o register 0. 2 dbb = double buffered bitsbuffered b y a write t o register 0 when bit db14 of register 4 is high. db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 n16 n15 n14 n13 n12 n 1 1 n10 n9 rese r ved 16-bit integer v alue (int) contro l bits n8 n7 n6 n5 n4 n3 n2 n1 c4(0) c3(0) c2(0) prescaler pr1 ac1 0 0 0 0 0 0 0 0 0 0 c1(0) db31 au t oca l db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 f24 f23 f22 f21 rese r ved 24-bit main fractiona l v alue (frac1) contro l bits f20 f19 f18 f17 f16 f15 f14 f13 f12 f 1 1 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 c3(0) c2(0) c1(1) c4(0) 0 0 0 dbr 1 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 14-bit auxilia r y modulus v alue (mod2) contro l bits m14 m13 m12 m 1 1 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 c3(0) c2(1) c1(0) c4(0) dbr 1 f 1 1 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f12 f13 f14 14-bit auxilia r y fractiona l v alue (frac2) dbr 1 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 p a1 p24 p23 p22 p21 24-bit phase v alue (phase) contro l bits p20 p19 p18 p17 p16 p15 p14 p13 p12 p 1 1 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 c3(0) c2(1) c1(1) c4(0) pr1 sd1 0 dbr 1 phase adjust phase resync sd load reset rese r ved db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 10-bit r counter contro l bits d1 cp4 cp3 cp2 cp1 u6 u5 u4 u3 u2 u1 c3(1) c2(0) c1(0) c4(0) dbr 1 dbr 1 muxout rese r ved current setting mux logic pd polarit y power-down c p three- s ta te counter reset ref mode double buff rdiv2 reference doubler dbr 1 dbr 1 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 0 0 0 0 0 0 0 0 c4(0) c3(1) c2(0) contro l bits 0 0 rese r ved db0 c1(1) 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 12910-034 register 0 register 1 register 2 register 3 register 4 register 5 r e g i s t e r 6 0 0 m3 m2 m1 rd 2 rd 1 r1 0 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 r f d i vi de r selec t 2 r f o u t p u t po w e r d b 3 1 d b 3 0 d b 2 9 d b 2 8 d b 2 7 d b 2 6 d b 2 5 d b 2 4 d b 2 3 d b 2 2 d b 2 1 d b 2 0 d b 1 9 d b1 8 d b 1 7 d b 1 6 d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 1 0 d b 9 d b 8 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 db 0 0 1 0 1 0 d 1 3 d 1 2 d 1 1 d 1 0 b l 1 0 d 8 0 d 6 d 5 d 4 d 3 d 2 d 1 c 4 ( 0 ) c3 ( 1 ) c2 ( 1 ) c o n t r o l b i t s c ha r g e p u m p b l ee d c u rr e n t r f o u t p u t e n a b l e a u x r f o u t p u t po w e r aux rf output enable m t l d f eed b a c k se l e c t r e s e r v e d c 1 ( 0 ) r e s e r v e d b l 2 b l 3 b l 4 b l 5 b l 6 b l 7 b l 8 n e g a t i v e b l ee d b l 9 r e s e r v e d b l 1 0 g a t e d b l ee d r e s e r v e d figure 28 . register summary (register 0 to register 6)
data sheet adf4355 rev. a | page 17 of 35 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0le0 0 0000000 0 ld1 c3(1) c2(1) c1(1) control bits reserved c4(0) ld2ld3 frac-n ld precision ldo mode lol mode lol ld4 ld5 ld cycle count 0 00 00 0100 reserved le sync db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 10 0 00 reserved control bits 01 011010 00 1000 10 c3(0) c2(0) c1(0) c4(1) 0 0 0 0 0 0 0 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 vc5 vc4 vc3 vc2 vc1 timeout control bits tl10 tl9 tl8 tl7 tl6 tl5 tl4 tl3 tl2 tl1 al5 al4 al3 al2 al1 sl5 sl4 sl3 sl2 sl1 c3(0) c2(0) c1(1) c4(1) vc6 vc7 vc8 vco band division db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 00 0 00 reserved control bits 110 0000000 c3(0) c2(1) c1(0) c4(1) 000 ae1ae2 ad1ad2ad3 ad4 ad5 ad6 adc enable adc conversion ad7 ad8 adc clock divider db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 000 reserved control bits 011 0000100 1 10 0000000 c3(0) c2(1) c1(1) c4(1) 0 0 0 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 p13 p12 p11 p10 p9 resync clock control bits p8 p7 p6 p5 p4 p3 p2 p1 0 0 0 001000001 c3(1) c2(0) c1(0) c4(1) p14 p15 p16 reserved 12910-035 register 7 register 8 register 9 register 10 register 11 register 12 synthesizer lock timeout automatic level timeout figure 29. register summary (register 7 to register 12)
adf4355 data sheet rev. a | page 18 of 35 n16 n15 ... n5 n4 n3 n2 n1 integer value (int) 00...00000 notallowed 00...00001 notallowed 00...00010 notallowed .......... ... 00...10110 notallowed 00...10111 23 00...11000 24 .......... ... 11...11101 65533 11...11110 65534 11...11111 65535 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 n16 n15 n14 n13 n12 n11 n10 n9 reserved 16-bit integer value (int) control bits n8 n7 n6 n5 n4 n3 n2 n1 c4(0) c3(0) c2(0) int min = 75 with prescaler = 8/9 pr1 prescaler 04/5 18/9 prescaler pr1 ac1 0000000000 c1(0) db31 autocal ac1 vco autocal 0 disabled 1 enabled 12910-036 figure 30. register 0 register 0 control bits with bits[c4:c1] set to 0000, register 0 is programmed. figure 30 shows the input data format for programming this register. reserved bits[db31:db22] are reserved and must be set to 0. automatic calibration (autocalibration) write to register 0 to enact (by default) the vco autocalibration and to choose the appropriate vco and vco subband. write a 1 to the autocal bit (ac1, bit db21) (bit db21) to enable the autocalibration, which is the recommended mode of operation. set the ac1 bit to 0 to disable the autocalibration, leaving the adf4355 in the same band it is already in when register 0 is updated. disable the autocalibration only for fixed frequency applications, phase adjust applications, or very small (<10 khz) frequency jumps. toggling autocal is also required when changing frequency (see the frequency update sequence section for additional details). prescaler the dual modulus prescaler (p/p + 1), along with the int, fracx, and modx counters, determines the overall division ratio from the vco output to the pfd input. the pr1 bit (bit db20) in register 0 sets the prescaler value. operating at current mode logic levels, the prescaler takes the clock from the vco output and divides it down for the counters. it is based on a synchronous 4/5 core. when the prescaler is set to 4/5, the maximum rf frequency allowed is 6.8 ghz. the prescaler limits the int value; therefore, if p is 4/5, n min is 23, and if p is 8/9, n min is 75. 16-bit integer value the 16 int bits (bits[db19:db4]) set the int value, which determines the integer part of the feedback division factor. the int value is used in equation 3 (see the int, frac1, frac2, mod1, mod2, and r counter relationship section). all integer values from 23 to 32,767 are allowed for the 4/5 prescaler. for the 8/9 prescaler, the minimum integer value is 75, and the maximum value is 65,535.
data sheet adf4355 rev. a | page 19 of 35 f24 f23 .......... f2 f1 main fractional value (frac1) 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 16777212 1 1 .......... 0 1 16777213 1 1 .......... 1 0 16777214 1 1 ......... 1 1 16777215 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 f24 f23 f22 f21 reserved 24-bit main fractional value (frac1) control bits f20 f19 f18 f17 f16 f15 f14 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 c3(0) c2(0) c1(1) c4(0) 0 0 0 dbr 1 12910-037 1 dbr = double buffered register?buffered by the write to register 0. figure 31. register 1 register 1 control bits with bits[c4:c1] set to 0001, register 1 is programmed. figure 31 shows the input data format for programming this register. reserved bits[db31:db28] are reserved and must be set to 0. 24-bit main fractional value the 24 frac1 bits (bits[db27:db4]) set the numerator of the fraction that is input to the - modulator. this fraction, along with the int value, specifies the new frequency channel that the synthesizer locks to, as shown in the rf synthesizera worked example section. frac1 values from 0 to (mod1 ? 1) cover channels over a frequency range equal to the pfd reference frequency.
adf4355 data sheet rev. a | page 20 of 35 m14 m13 .......... m2 m1 modulus value (mod2) 0 0 .......... 0 0 not allowed 0 0 .......... 0 1 not allowed 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 16380 1 1 .......... 0 1 16381 1 1 .......... 1 0 16382 1 1 ......... 1 1 16383 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 14-bit auxiliary modulus value (mod2) control bits m14m13m12m11m10m9m8m7m6m5m4m3m2m1 c3(0) c2(1) c1(0) c4(0) dbr 1 dbr 1 f14 f13 .......... f2 f1 frac2 word 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 16381 1 1 .......... 0 1 16382 1 1 .......... 1 0 16382 1 1 ......... 1 1 16383 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f12 f13 f14 14-bit auxiliary fractional value (frac2) 12910-038 1 dbr = double buffered register?buffered by the write to register 0. figure 32. register 2 register 2 control bits with bits[c4:c1] set to 0010, register 2 is programmed. figure 32 shows the input data format for programming this register. 14-bit auxiliary fractional value (frac2) the 14-bit auxiliary fractional value (bits[db31:db18]) controls the auxiliary fractional word. frac2 must be less than the mod2 value programmed in register 2. 14-bit auxiliary modulus value (mod2) the 14-bit auxiliary modulus value (bits[db17:db4]) sets the auxiliary fractional modulus. use mod2 to correct any residual error due to the main fractional modulus.
data sheet adf4355 rev. a | page 21 of 35 p24 p23 .......... p2 p1 phase value (phase) 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 16777212 1 1 .......... 0 1 16777213 1 1 .......... 1 0 16777214 1 1 ......... 1 1 16777215 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 pa1p24 p23p22 p21 24-bit phase value (phase) control bits p20 p19 p18 p17 p16 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 c3(0) c2(1) c1(1) c4(0) pr1 sd1 0 dbr 1 phase adjust phase resync sd load reset reserved pa1 phase adjust 0 disabled 1 enabled pr1 phase resync 0disabled 1 enabled sd1 sd load reset 0on register0 update 1disabled 12910-039 1 dbr = double buffered register?buffered by the write to register 0. figure 33. register 3 register 3 control bits with bits[c4:c1] set to 0011, register 3 is programmed. figure 33 shows the input data format for programming this register. reserved bit db31 is reserved and must be set to 0. sd load reset when writing to register 0, the - modulator resets. for applications when the phase is continually adjusted, this may not be desirable; therefore, in these cases, the - reset can be disabled by writing a 1 to the sd1 bit (bit db30). phase resync to use the phase resynchronization feature, the pr1 bit (bit db29) must be set to 1. if unused, the bit can be programmed to 0. the phase resync timer must also be used in register 12 to ensure that the resynchronization feature is applied after the pll has settled to the final frequency. if the pll has not settled to the final frequency, phase resync may not function correctly. resynchronization is useful in phased array and beam forming applications. it ensures repeatability of output phase when programming the same frequency. in phase critical applications that use frequencies requiring the output divider (<3400 mhz), it is necessary to feed the n divider with the divided vco frequency rather than from the fundamental vco frequency. this is achieved by programming the d13 bit (bit db24) in register 6 to 0, which ensures divided feedback to the n divider. phase resynchronization only operateswhen frac2 = 0. for resync applications, enable the sd load reset in register 3 by setting db30 to 0. phase adjust to adjust the relative output phase of the adf4355 on each register 0 update, set the pa1 bit (bit db28) to 1. this feature differs from the resynchronization feature in that it is useful when adjustments to the phase are made continually in an application. for this function, disable the vco automatic calibration by setting the ac1 bit (bit db21) in register 0 to 1 and disable the sd load reset by setting the sd1 bit (bit db30) in register 3 to 1. note that phase resync and phase adjust cannot be used simultaneously. 24-bit phase value the phase of the rf output frequency can adjust in 24-bit steps; from 0 (0) to 360 (2 24 ? 1). for phase adjust applications, the phase is set by ( phase value /16,777,216) 360 when the phase value is programmed to register 3, each subsequent adjustment of register 0 increments the phase by the value in this equation.
adf4355 data sheet rev. a | page 22 of 35 rd2 reference doubler 0disabled 1enabled rd1 reference divide by 2 0disabled 1enabled cp4cp3cp2cp1 i cp (ma) 5.1k ? 00000.31 00010.63 00100.94 00111.25 01001.56 01011.88 01102.19 01112.50 10002.81 10013.13 10103.44 10113.75 11004.06 11014.38 11104.69 11115.00 r10 r9 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... r2 r1 r divider (r) 00 011 00 102 .. ... .. ... .. ... 1 1 0 0 1020 1 1 0 1 1021 1 1 1 0 1022 1 1 1 1 1023 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 0 0 m3 m2 m1 rd2 rd1 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 d1 cp4 cp3 cp2 cp1 u6 u5 u4 u3 u2 u1 c3(1) c2(0) c1(0) rdiv2 reference doubler current setting 10-bit r counter control bits mux logic pd polarity power-down cp three- state counter reset ref mode muxout double buff u5 ldp 01.8v 13.3v u4 pd polarity 0negative 1positive u3 power down 0disabled 1enabled u2 cp three-state 0disabled 1enabled u1 counter reset 0disabled 1enabled d1 double buffered register 6, bits[db23:db21] 0disabled 1enabled u6 refin 0single 1diff m3 m2 m1 output 0 0 0 three-state output 00 1dv dd 01 0sd gnd 0 1 1 r divider output 1 0 0 n divider output 1 0 1 analog lock detect 1 1 0 digital lock detect 11 1reserved db0 c4(0) reserved dbr 1 dbr 1 dbr 1 dbr 1 12910-040 1 dbr = double buffered register?buffered by the write to register 0. figure 34. register 4 register 4 control bits with bits[c4:c1] set to 0100, register 4 is programmed. figure 34 shows the input data format for programming this register. reserved bits[db31:db30] are reserved and must be set to 0. muxout the on-chip multiplexer (muxout) is controlled by bits[db29:db27]. for additional details, see figure 34. reference doubler setting the rd2 bit (bit db26) to 0 feeds the ref in signal directly to the 10-bit r counter, disabling the doubler. setting this bit to 1 multiplies the reference frequency by a factor of 2 before feeding it into the 10-bit r counter. when the doubler is disabled, the ref in falling edge is the active edge at the pfd input to the fractional synthesizer. when the doubler is enabled, both the rising and falling edges of the reference frequency become active edges at the pfd input. the maximum allowable reference frequency when the doubler is enabled is 100 mhz. rdiv2 setting the rd1 bit (bit db25) to 1 inserts a divide by 2 toggle flip-flop between the r counter and pfd, which extends the maximum reference frequency input rate. this function provides a 50% duty cycle signal at the pfd input. 10-bit r counter the 10-bit r counter divides the input reference frequency (ref in ) to produce the reference clock to the pfd. division ratios range from 1 to 1023. double buffer the d1 bit (bit db14) enables or disables double buffering of the rf divider select bits (bits[db23:db21]) in register 6. the program modes section explains how double buffering works. charge pump current setting the cp4 to cp1 bits (bits[db13:db10]) set the charge pump current. set this value to the charge pump current that the loop filter is designed with (see figure 34). for the lowest spurs, the 0.9 ma setting is recommended.
data sheet adf4355 rev. a | page 23 of 35 reference mode the adf4355 permits use of either differe ntial or single - ended reference sources. for optimum integer boundary spur performance, use the single - ended setting for all references up to 250 mhz (even if using a differential reference signal). use the differential setting for reference frequencies a bove 250 mhz. level select to assist wit h logic compatibility, muxout is programm able to two logic levels. set the u5 bit (bit db8) to 0 to select 1.8 v logic, and set it to 1 to select 3.3 v logic. phase detector (pd) polarity the u4 bit (bit db7) sets the phase detector polarity. when a passive loop filter or a noninverting active loop filter is used, set db7 to 1 (positive). if an active filter with an inverting characteristic is used, set this bit to 0 (negative). power - down the u3 bit (bit db6) sets the programmable power - down mode. setting db6 to 1 performs a power - down. setting db6 to 0 returns the synthesizer to normal operation. in software power - down mode, the adf4355 retains all infor mation in its registers. the register contents are only lost if the supply voltages are removed. when power - down activates, the following events occur: ? the synthesizer counters are forced to their load state conditions. ? the vco powers down. ? the charge pump is forced into three - state mode. ? the digital lock detect circuitry resets. ? the rf out a+/rf out a? and rf out b+/rf out b? output stages are disabled. ? the input registers remain active and capable of loading and latching data. charge pump three - state setting the u2 bit (bit db5) to 1 puts the charge pump into three - state mode. set db5 to 0 for normal operation. counter reset the u1 bit (bit db4) resets the r counter, n counter, and vco band select of the adf4355 . when db4 is set to 1, the rf synthesizer n counter and r counter , and the vco band select , are reset. for normal operation, set db4 to 0. toggling c ounter reset (bit db4) is also required when changing frequency (see the frequency update sequence section for additional details ). register 5 the bits in register 5 are reserved and must be programmed as d escribed in figure 35 , using a hexadecimal wor d of 0x00800025 . db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 0 0 0 0 0 0 0 0 c4(0) c3(1) c2(0) contro l bits 0 0 rese r ved db0 c1(1) 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 12910-041 figure 35 . register 5 ( 0x00800025 )
adf4355 data sheet rev. a | page 24 of 35 12910-042 1 bits[db23:db21] are buffered by a write to register 0 when the double buffer bit is enabled, bit db14 of register 4. d3 rf out 0disabled 1 enabled d2 d1 output power 0 0 ?4dbm 0 1 ?1dbm 10+2dbm 11+5dbm d5 d4 auxiliary output power 0 0 ?4dbm 0 1 ?1dbm 10+2dbm 11+5dbm d6 auxiliary out 0disabled 1 enabled d8 mute till lock detect 0 mute disabled 1 mute enabled d13 feedback select 0 fundamen tal 1 divided d12 d11 rf divider select 00 1 00 2 01 4 01 8 d10 0 1 0 1 1 1 1 0 0 1 16 32 64 0 1 0 bl8 bl7 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... bl2 bl1 bleed current 0 0 0 1 1 (3.75a) 0 0 1 0 2 (7.5a) .. ... .. ... .. ... 1 1 0 0 252 (945a) 1 1 0 1 253 (948.75a) 1 1 1 0 254 (952.5a) 1 1 1 1 255 (956.25a) bl9 bleed current 0 enabled 1 disabled bl10 gated bleed 0 enabled 1 disabled rf divider select 1 rf output power db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 1 0 d13 d12 d11 d10 bl1 0 d8 0 d6 d5 d4 d3 d2 d1 c4(0) c3(1) c2(1) control bits charge pump bleed current rf output enable aux rf output power aux rf output enable mtld feedback select reserved c1(0) reserved bl2 bl3 bl4 bl5 bl6 bl7 bl8 negative bleed bl9 reserved bl10 gated bleed reserved figure 36. register 6 register 6 control bits with bits[c4:c1] set to 0110, register 6 is programmed. figure 36 shows the input data format for programming this register. reserved bit db31 is reserved and must be set to 0. gated bleed bleed currents can improve phase noise and spurs; however, due to a potential impact on lock time, the gated bleed bit, bl10 (bit db30), if set to 1, ensures bleed currents are not switched on until the digital lock detect asserts logic high. note that this function requires digital lock detect to be enabled. negative bleed use of constant negative bleed is recommended for most applications because it improves the linearity of the charge pump leading to lower noise and spurs than leaving negative bleed off. to enable negative bleed, write 1 to bl9 (bit db29), and to disable negative bleed, write 0 to bl9 (bit db29). use negative bleed only when operating in fractional-n mode, that is, frac1 or frac2 is not equal to 0. do not use negative bleed for f pfd greater than 100 mhz. reserved bits[db28:db25] are reserved and must be set to 1010. feedback select d13 (bit db24) selects the feedback from the output of the vco to the n counter. when d13 is set to 1, the signal is taken directly from the vco. when this bit is set to 0, the signal is taken from the output of the output dividers. the dividers enable coverage of the wide frequency band (54 mhz to 6800 mhz). when the divider is enabled and the feedback signal is taken from the output, the rf output signals of two separately configured plls are in phase. divided feedback is useful in some applications where the positive interference of signals is required to increase the power. rf divider select d12 to d10 (bits[db23:db21]) select the value of the rf output divider (see figure 36).
data sheet adf4355 rev. a | page 25 of 35 charge pump bleed current bl8 to bl1 (bits[db20:db13]) control the level of the bleed current added to the charge pump output. this current optimizes the phase noise and spurious levels from the device. te st s have shown that the optimal bleed set is the following: 4/ n < i bleed / i cp < 10/ n where: i bleed is the value of constant negative bleed applied to the charge pump, which is set by the contents of bits [bl8:bl1]. i cp is the value of charge pump current setting, bits[db13:db10] of register 4. n is the value of the feedback counter from the vco to the pfd. reserved bit db12 is reserved and must be set to 0 . mute till lock detect when d8 (bit db11) is set to 1, the supply current to the rf output stage is shut down until the device achieves lock, as determined by the digital lock det ect circuitry. reserved bit db10 is reserved and must be set to 0 . auxiliary rf output enable bit db9 enables or disables the auxiliary frequency rf output (rf out b+/ rf out b? ). when db9 is set to 1, the auxiliary frequency rf output is enabled . when db 9 is set to 0, the auxiliary rf output is disabled. auxiliary rf output power bits[db 8 :db 7 ] set the value of the auxiliary rf output power level (se e figure 36). rf output enable bit db6 enables or disables the primary rf output ( rf out a+/ rf out a? ). when db6 is set to 0, the primary rf output is disabled. when db6 is set to 1, the primary rf output is enabled. output power bits[db5:db4] set the value of the primary rf output power level (s ee figure 36).
adf4355 data sheet rev. a | page 26 of 35 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0le0 0 0000000 0 ld1 c3(1) c2(1) c1(1) control bits reserved ld3 ld2 fractional-n ld precision 005.0ns 016.0ns 108.0ns 1112.0ns ld1 0 fractional-n 1integer-n (2.9ns) c4(0) lock detect mode ld2 ld3 frac-n ld precision ld mode lol 0 disabled 1 enabled loss of lock mode lol mode lol ld5 ld4 lock detect cycle count 0 0 1024 0 1 2048 1 0 4096 1 1 8192 ld4 ld5 ld cycle count 0 00 00 0100 le 0 disabled 1 le synced to refin le synchroniz ation reserved le sync 12910-043 figure 37. register 7 register 7 control bits with bits[c4:c1] set to 0111, register 7 is programmed. figure 37 shows the input data format for programming this register. reserved bits[db31:db29] are reserved and must be set to 0. bit db28 is reserved and must be set to 1. bits[db27:db26] are reserved and must be set to 0. le sync when set to 1, bit db25 ensures that the load enable (le) edge is synchronized internally with the rising edge of reference input frequency. this synchronization prevents the rare event of reference and rf dividers from loading at the same time as a falling edge of reference frequency, which can lead to longer lock times. reserved bits[db24:db10] are reserved and must be set to 0. fractional-n lock detect count (ldc) ld5 and ld4 (bits[db9:db8]) set the number of consecutive cycles counted by the lock detect circuitry before asserting lock detect high. see figure 37 for details. loss of lock (lol) mode set lol (bit db7) to 1 when the application is a fixed frequency application in which the input reference frequency (ref in ) is likely to be removed, such as a clocking application. the standard lock detect circuit assumes that ref in is always present; however, this may not be the case with clocking applications. to enable this functionality, set db7 to 1. loss of lock mode does not function reliably when using a differential ref in mode. fractional-n lock detect precision (ldp) ld3 and ld2 (bits[db6:db5]) set the precision of the lock detect circuitry in fractional-n mode. ldp is available at 5.0 ns, 6.0 ns, 8.0 ns, or 12.0 ns. if bleed currents are used, use 12 ns. lock detect mode (ldm) if ld1 (bit db4) is set to 0, each reference cycle is set by fractional-n lock detect precision as described in the fractional-n lock detect count (ldc) section. if db4 is set to 1, each reference cycle is 2.9 ns long, which is more appropriate for integer-n applications.
data sheet adf4355 rev. a | page 27 of 35 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 1 0000 reserved control bits 01 011010 00 1000 10 c3(0) c2(0) c1(0) c4(1) 0 0 0 0 0 0 0 12910-044 figure 38. register 8 (0x102d0428) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 vc5 vc4 vc3 vc2 vc1 timeout control bits tl10 tl9 tl8 tl7 tl6 tl5 tl4 tl3 tl2 tl1 al5 al4 al3 al2 al1 sl5 sl4 sl3 sl2 sl1 c3(0) c2(0) c1(1) c4(1) vc6 vc7 vc8 tl10 tl9 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... tl2 tl1 timeout 00 011 00 102 .. ... .. ... .. ... 1 1 0 0 1020 1 1 0 1 1021 1 1 1 0 1022 1 1 1 1 1023 al5 al4 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... al2 al1 alc wait 00 011 00 102 .. ... .. ... .. ... 11 0028 11 0129 11 1030 11 1131 vc8 vc7 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... vc2 vc1 vco band div 00 011 00 102 .. ... .. ... .. ... 11 00252 11 01253 11 10254 11 11255 vco band division sl5 sl4 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... sl2 sl1 slc wait 00 011 00 102 .. ... .. ... .. ... 11 0028 11 0129 11 1030 11 1131 12910-045 synthesizer lock timeout automatic level timeout figure 39. register 9 register 8 the bits in this register are reserved and must be programmed as described in figure 38, using a hexadecimal word of 0x102d0428. register 9 control bits with bits[c4:c1] set to 1001, register 9 is programmed. figure 39 shows the input data format for programming this register. vco band division vc8 to vc1 (bits[db31:db24]) set the value of the vco band division clock. determine the value of this clock by pfd/(band division 16) such that the result is <150 khz. timeout tl10 to tl1 (bits[db23:db14]) set the timeout value for the vco band select. use this value as a variable in the other vco calibration settings. automatic level calibration timeout al5 to al1 (bits[db13:db9]) set the timer value used for the automatic level calibration of the vco. this function combines the pfd frequency, the timeout variable, and alc wait variable. choose alc such that the following equation is always greater than 50 s. ( timeout alc wait / pfd frequency ) > 50 s synthesizer lock timeout sl5 to sl1 (bits[db8:db4]) set the synthesizer lock timeout value. use this value to allow the v tune force to settle on the v tune pin. the value must be 20 s. calculate the value using the following equation: ( timeout synthesizer lock timeout / pfd frequency ) > 20 s
adf4355 data sheet rev. a | page 28 of 35 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 00 0 00 reserved control bits 110 0000000 c3(0) c2(1) c1(0) c4(1) 000 ae1 ae2 ad1ad2ad3 ad4 ad5 ad6 adc enable adc conversion ad7 ad8 adc clock divider ad8 ad7 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ad2 ad1 adc clk div 00 011 00 102 .. ... .. ... .. ... 11 00252 11 01253 11 10254 11 11255 ae1 adc 0disabled 1 enabled ae2 adc conversion 0 disabled 1 enabled 12910-047 figure 40. register 10 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 000 reserved control bits 011 0000100 1 10 0000000 c3(0) c2(1) c1(1) c4(1) 0 0 0 12910-048 figure 41. register 11 (0x0061300b) register 10 control bits with bits[c4:c1] set to 1010, register 10 is programmed. figure 40 shows the input data format for programming this register. reserved bits[db31:db14] are reserved. bits[db23:db22] must be set to 11, but all other bits in this range must be set to 0. adc clock divider (adc_clk_div) an on-board analog-to-digital converter (adc) determines the v tune setpoint relative to the ambient temperature of the adf4355 environment. the adc ensures that the initial tuning voltage in any application is chosen correctly to avoid any temperature drift issues. the adc uses a clock that is equal to the output of the r counter (or the pfd frequency) divided by adc_clk_div. ad8 to ad1 (bits[db13:db6]) set the value of this divider. on power-up, the r counter is not programmed; however, in these power-up cases, it defaults to r = 1. choose the adc_clk_div value such that adc_clk_div = ceiling((( f pfd /100,000) ? 2)/4) where ceiling() is a function to round up to the nearest integer. for example, for f pfd = 61.44 mhz, set adc_clk_div = 154 so that the adc clock frequency is 99.417 khz. if adc_clk_div is greater than 255, set it to 255. adc conversion enable ae2 (bit db5) ensures that the adc performs a conversion when a write to register 10 is performed. it is recommended to enable this mode. adc enable ae1 (bit db4), when set to 1, powers up the adc for the temperature dependent v tune calibration. it is recommended to always use this function. register 11 the bits in this register are reserved and must be programmed as described in figure 41, using a hexadecimal word of 0x0061300b.
data sheet adf4355 rev. a | page 29 of 35 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 p13 p12 p11 p10 p9 resync clock control bits p8 p7 p6 p5 p4 p3 p2 p1 0 0 0 001000001 c3(1) c2(0) c1(0) c4(1) p14 p15 p16 p16p15...p5p4p3p2p1 resync clock 00...00000 notallowed 00...00001 1 00...00010 2 .......... ... 00...10110 22 00...10111 23 00...11000 24 .......... ... 11...11101 65533 11...11110 65534 11...11111 65535 reserved 12910-049 figure 42. register 12 register 12 control bits with bits[c4:c1] set to 1100, register 12 is programmed. figure 42 shows the input data format for programming this register. phase resync clock divider value p16 to p1 (bits[db31:db16]) set the timeout counter for activation of phase resync. this value must be set such that a resync happens immediately after (and not before) the pll has achieved lock after reprogramming. calculate the timeout value using the following equation: time out value = phase resync clock / pfd frequency reserved bits[db15:db4] are reserved. bit db10 and bit db4 must be set to 1, but all other bits in this range must be set to 0. register initialization sequence at initial power-up, after the correct application of voltages to the supply pins, registers must be programmed in sequence. for f pfd 75 mhz, use the following sequence: 1. register 12. 2. register 11. 3. register 10. 4. register 9. 5. register 8. 6. register 7. 7. register 6. 8. register 5. 9. register 4. 10. register 3. 11. register 2. 12. register 1. 13. wait >16 adc_clk cycles. for example, if adc_clk = 99.417 khz, wait 16/99,417 sec = 161 s. see the register 10 section for more information. 14. register 0. for f pfd > 75 mhz (initially lock with half f pfd ), use the following sequence: 1. register 12. 2. register 11. 3. register 10. 4. register 9. 5. register 8. 6. register 7. 7. register 6. 8. register 5. 9. register 4 (with the r divider doubled to output half f pfd ). 10. register 3. 11. register 2 (for halved f pfd ). 12. register 1 (for halved f pfd ). 13. wait >16 adc_clk cycles. for example, if adc_clk = 99.417 khz, wait 16/99417 sec = 161 s. see the register 10 section for more information. 14. register 0 (for halved f pfd ; autocalibration enabled). 15. register 4 (with the r divider set for desired f pfd ). 16. register 2 (for desired f pfd ). 17. register 1 (for desired f pfd ). 18. register 0 (for desired f pfd ; autocalibration disabled). frequency update sequence frequency updates require updating the auxiliary modulator (mod2) in register 2, the fractional value (frac1) in register 1, and the integer value (int) in register 0. it is recommended to perform a temperature dependent v tune calibration by updating register 10 first. a counter reset (bit db4) is also required in the frequency update sequence therefore, for f pfd 75 mhz, use the following sequence: 1. register 10. 2. register 4 (counter reset enabled [db4 = 1]). 3. register 2. 4. register 1. 5. register 0 (autocalibration disabled [db21 = 0]). 6. register 4 (counter reset disabled [db4 = 0]).
adf4355 data sheet rev. a | page 30 of 35 7. wait >16 adc_clk_div cycles. for example, if adc_clk_div = 99.417 khz, wait 16/99417 sec = 161 s. see the register 10 section. 8. register 0 (autocalibration enabled [db21 = 1]) . for f pfd > 75 mhz (initially lock with half f pfd ), use the following sequence : 1. register 10. 2. register 4 (counter reset enabled [db4 = 1]) . 3. register 2 (for halved f pfd ). 4. register 1 (for halved f pfd ). 5. register 0 (for halved f pfd ; autocalibration disabled). 6. register 4 (counter reset disabled [db4 = 0]) 7. wait >16 adc_clk cycles. for example, if adc_clk = 99.417 khz, wait 16/99417 sec = 161 s . see the register 10 section for more information. 8. register 0 (for halved f pfd ; autocalibration enabled). 9. register 2 (for desired f pfd ). 10. register 1 (for desired f pfd ). 11. register 0 (for desired f pfd ; autocalibration disabled). the frequency change only occurs when writing to register 0. rf synthesizer a worked example use the following equations to program the adf4355 synthesizer: rf out = mod1 mod2 frac2 frac1 int + + ( f pfd ) /rf divider ( 7 ) where: rf out is the rf frequency output. int is the integer division factor. frac1 is the fractionality. frac2 is the auxiliary fractionality. mod2 is the auxiliary modulus. mod1 is the fixed 24 - bit modulus. rf divider is the output divider that divides down the vco frequency. f pfd = ref in ((1 + d )/( r (1 + t ))) ( 8 ) where: ref in is the reference frequency input. d is the rf ref in doubler bit. r is the rf reference division factor. t is the reference divide by 2 bit (0 or 1). for example, in a universal mobile telecommunication system (umts) where 21 12.8 mhz rf frequency output (rf out ) is required, a 122.88 mhz reference frequency input (ref in ) is available. note that the adf4355 vco operates in the frequency range of 3.4 ghz to 6.8 ghz. therefore, an rf divider of 2 must be used (vco frequency = 4225.6 mhz, rf out = vco frequency/ rf d ivider = 4225.6 mhz/2 = 2112.8 mhz). the feedback path is also im portant. in this example, th e vco output is fed back before the output divider (see figure 43). in this example , di vide the 122.88 mhz reference signal by 2 to generate a f pfd of 61.44 mhz. the desired channel spacing is 200 khz. 12910-148 f p f d p f d v c o n d i v i d er 2 r f o u t figure 43 . loop closed before output divider the w orked example is as follows : ? n = vco out /f pfd = 4225.6 mhz/61.44 mhz = 68.7760416666666667 ? int = int(vco frequency/f pfd ) = 68 ? frac = 0.7760416666666667 ? mod1 = 16,777,216 ? frac1 = int(mod1 frac) = 13019817 ? remainder = 0.6666666667 or 2/3 ? mod2 = f pfd /gcd(f pfd /f chsp ) = 61.44 mhz/ gcd(61.44 mhz/200 khz) = 1536 ? frac2 = r emainder 1536 = 1024 from equation 8 , f pfd = (122.88 mhz (1 + 0)/2) = 61.44 m hz ( 9 ) from e quation 7 , 2112.8 mhz = 61.44 mhz (( in t + ( frac1 + frac2/mod2) / 2 24 ))/2 ( 10) where: int = 68 frac1 = 13,019,817 frac2 = 1024 mod2 = 1536 rf divider = 2 (see equation 7) reference doubler an d reference divider the on - chip reference doubler allows the input reference signal to be doubled. th e doubler is useful for increasing the pfd comparison frequency. to improve the noise performance of the system , increase the pfd frequency. doubling the pfd frequency usually improves noise performance by 3 db. the reference divide by 2 divides the reference signal by 2, resulting in a 50% duty cycle pfd frequency. spurious optimizatio n and fast lock narrow loop bandwidths can filter unwanted spurious signals, but these bandwidths usually have a long lock time. a wider loop bandwidth achieves faster lock times but may lead to increased spurious signals inside the loop bandwidth.
data sheet adf4355 rev. a | page 31 of 35 optimizi ng jitter for lowest jitter applications, use the highest possible pfd frequency to minimize the contribution of in - band noise from the pll. set t he pll filter bandwidth such that the in - band noise of t he pll intersects with the open - loop noise of the vco , minimizing the contribution of both to the overall noise. use t he adisimpll ? design tool for this task. spur mechanisms this section describes the two different spur mechanisms that arise wit h a fractional - n synthesizer and how to minimize them in the adf4355 . integer boundary spurs one mechanism for fractional spur creation is the interactions between the rf vco frequency and the r eference frequency. when these frequencies are not integer related (the purpose of a fractional - n synthesizer), spur sidebands appear on the vco output spectrum at an offset frequency that corresponds to the beat note or the difference in frequency between an integer multiple of the reference and the vco frequency. these spurs are attenuate d by the loop filter and are more noticeable on channels close to integer multiples of the reference where the difference frequency can be inside the loop bandwidth ( thus the name , integer boundary spurs). reference spurs reference spurs are generally not a problem in fractional - n synthesizers because the reference offset is far outside the loop bandwidth. however, any reference feedthrough mechanism that bypasses the loop may cause a problem. feedthrough of low levels of on - chip reference switching noise, through the prescaler back to the vco, can result in reference spur levels as high as ?80 dbc. lock time the pll lock time divide s into a number of settings. all of these are modeled in the adisimpll design tool. faster lock times than those detailed in this data sheet are possible; contact your local analog devices , inc., sales representative for more informa tion . lock time a worked example assum ing f pfd = 61.44 mhz, vco band div = ceiling ( f pfd /2,400,000) = 26 where ceiling () rounds up to the nearest integer. by combining the following two equations: alc wait > (50 s f pfd )/ timeout synthesizer lock timeout > (20 s f pfd )/ timeout the following i s found : alc wait = 2.5 synthesizer lock timeout maximize alc w ait (to reduce t imeout to minimize time) so that alc w ait = 30 and synthesizer lock timeout = 12 . finally, alc wait > (50 s f pfd )/timeout , is rearra nged as timeout = ceiling ((f pfd 50 s)/ alc wait ) timeout = ceiling ((61.44 mhz 50 s)/30) = 103 synth esizer lock timeout the synth esizer lock timeout ensures that the vco calibration dac , which forces v tune , has settled to a steady value for the band se lect circuitry. the timeout and synthesizer lock timeout variables programmed in register 9 select the length of time the dac is allowed to settle to the final voltage before the vco calibration process c ontinue s to the next phase, which is vco band selection. the pfd frequency is used as the clock for this logic, and the duration is set by frequency pfd timeout lock r synthesize timeout vco band selection use t he pfd frequency a gain as the clock for the band selection process. calculate this value by pfd /( vco band selection 16) < 150 khz the band selection takes 11 cycles of the previously calculated value. calculate t he duration by 11 ( vco band selection 16)/ pfd frequency auto matic level calibration timeout use t he auto matic level calibration (alc) function to choose the correct bias current in the adf4355 vco core. calculate t he time taken by 5 11 alc wait t imeout / pfd frequency pll low - pass filter settling time the time taken for the loop to settle is inversely proportional to the low - pass filter bandwidth. the settling time is also modeled in the adisimpll design tool. the total lock time for changing frequencies is the sum of the four separate times (synth esizer lock, vco band selection, alc timeout, and pll settling time) and is all m odeled in the adisimpll design tool.
adf4355 data sheet rev. a | page 32 of 35 applications informa tion direct conversion mo dulator direct conversion architectures are incre asingly being used to implement base station transmitters. figure 44 shows how to use analog devices device s to implement such a system. the circuit block diagram sh ows the ad9761 txdac + ? being used with the adl5375 . the use of a dual integrated dac, such as the ad9761 , ensures minimum error contribution (over temperature) from this portion of the signal chain. the local oscillator (lo) is implemented using the adf4355 . the low - pass filter was designed using the adisimpll design tool for a pfd of 61.44 mhz and a closed - loop bandwidth of 20 khz. the lo ports of the adl5375 can be driven differentially from the complementary rf out a +/rf out a? outputs of the adf4355 . different ial drive gives better second - order distortion performance than a single - ended lo driver and eliminates the use of a balun to convert from a single - ended lo input to the more desirable differential lo input for the adl5375 . the adl5375 accepts lo drive levels from ?6 dbm to +6 dbm. the optimum lo power can be software programmed on the adf4355 , which allows levels from ?4 dbm to + 5 dbm from each output. the rf output is designed to drive a 50 ? load ; however, it must be ac - coupled, as shown in figure 44 . if the i and q inputs are driven in quad rature by 2 v p - p signals, the resulting output power from the adl5375 modulator is approximately 2 dbm. ad9761 txdac refio fsadj modul a ted digi t a l d at a qoutb iou t a ioutb qou t a 2k ? lo w - p ass fi l ter lo w - p ass fi l ter ibb p ibbn qbb p qbbn loi p loin 51? 51? 51 ? 51 ? adl5375 rfout quadr a ture phase splitter dso p 1500pf 390pf 33nf 3.3k ? 1k ? spi-com pa tible seria l bus adf4355 v vco rf out bC rf out b+ c p out 1nf 1nf 4.7k ? r set le d at a clk ref in a ref in b fref in v tune dv dd a v dd a v dd ce 16 27 17 29 1 2 3 22 v vco 14 15 10 20 7 pdb rf 26 6 v p 5 4 rf out aC rf out a+ 12 1 1 7.5nh 7.5nh 1nf 1nf v out v rf 1nf 1nf fref in 28 v dd muxout lock detect 25 30 32 c reg 2 100nf c reg 1 100nf 12910-138 lpf lpf cp gnd a gnd 8 31 9 13 18 21 a gndrf a gndvco 19 23 24 sd gnd 10pf 0.1 f 10pf 0.1 f 10pf 0.1 f v regvco v bias v ref figure 44 . direct conversion modulator
data sheet adf4355 rev. a | page 33 of 35 power supplies the adf4355 -2 contains four multiband vcos that cover an octave range of frequencies. to ensure best performance, it is vital to conne ct a low noise regulator, such as the adm7170 , to the v vco pin. connect the same regulator to pa ckage pins v vco , v regvco , and v p . for the 3.3 v supply pins, use two adm7170 regulators, one for the dv dd and av dd supplies and one for v rf . figure 45 shows t he recommended connections. printed circuit boar d ( pcb ) design guidelines for a chip - scale package the lands on the 32 - lead lead frame chip - scale package are rectangular. the pcb pad for these lands must be 0.1 mm longer than the package land length and 0. 05 mm wider than the package land width. center e ach land on the pad to maximize the solder joint size. the bottom of the chip - scale package has a central exposed thermal pad. the thermal pad on the pcb must be at least as large as the exposed pad. on the pcb, there must be a minimum clearance of 0.25 mm between the thermal pad and the inner edges of the pad pattern. this clearance ensures the avoidance of shorting . to improve the thermal performance of the package, use t hermal vias on the pcb thermal p ad. if vias are used, incorporate them into the thermal pad at the 1.2 mm pitch grid. the via diameter must be between 0.3 mm and 0.33 mm and the via barrel must be plated with 1 oz. of copper to plug the via. for a microwave pll and vco synthesizer , such as the adf4355 , take care with the board stack - up and layout. do not consider using fr4 material because it is too lossy above 3 ghz. instead, rogers 4350, rogers 4003, or rogers 3003 dielectric material is suitable. take c are with the rf output traces to minimize discontinuities and ensure the best signal integrity. via placement and grounding are critical. 1500pf 390pf 33nf 3.3k? 1k? spi-compatible serial bus adf4355 v vco cp gnd a gnd rf out bC rf out b+ cp out 1nf1nf 4.7k? r set le data clk fref in v tune dv dd av dd ce muxout 16 27 17 29 1 2 3 22 8 31 9 13 18 21 lock detect a gndrf a gndvco 14 15 19 23 24 25 30 10 20 7 pdb rf 26 sd gnd 6 32 v p 5 av dd 10pf 0.1f 10pf 0.1f 10pf 0.1f 4 rf out aC rf out a+ 12 11 7.5nh 7.5nh 1nf 1nf c out 10f c in 10f v out = 5.0v v in = 6.0v off on v out v rf 100nf 100nf 1nf1nf fref in 28 c out 10f c in 10f v out = 3.3v v in = 6.0v vout ss vin gnd en off on adm7170 c ss 1nf vout ss vin gnd en adm7170 ref in a ref in b v regvco v bias c reg 2 c reg 1 v ref 12910-050 c out 10f c in 10f v out = 3.3v v in = 6.0v vout ss vin gnd en off on adm7170 c ss 1nf c ss 1nf sense vout vout vout sense sense figure 45 . adf4355 power supplies
adf4355 data sheet rev. a | page 34 of 35 output matching the low frequency output can simply be ac - coupled to the next circuit , if desired ; however, if higher output power is required, use a pull - up i nduct or to increase the output power level. 7.5nh 100pf rf out a+ v rf 50? 12910-051 figure 46 . optimum output stage when differential outputs are not needed, terminate the unused output or combine it with both outputs using a balun. for lower frequencies below 2 ghz , i t is recommended to use a 100 nh indu c tor on the rf out a +/rf out a? pins. the rf out a+/rf out a? pins are a differential circuit . p rovide each output with the same (or similar) components where possible , such as the same shunt inductor value, bypass capacitor , a nd termination. the auxiliary frequency output , rf out b+/rf out b? , can be treated the same as the rf out a+/rf out a? output . if unused, leave both rf out b+/rf out b? pins open .
data sheet adf4355 rev. a | page 35 of 35 outline dimensions 08-16-2010-b 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min * 3.75 3.60 sq 3.55 * compliant to jedec standards mo-220- whhd-5 with the exception of the exposed pad dimension. figure 47 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very, very thin quad (cp - 32 - 12 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adf4355 bcpz ?40c to +85c 32 - lead lead frame chip scale package [lfcsp_wq] cp - 32 - 1 2 adf4355 bcpz - rl7 ?40c to +85c 32- lead lead frame chip scale package [lfcsp_wq] cp -32-1 2 ev - adf4355 sd1z evaluation board 1 z = rohs compliant part. ? 2015 C 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12910 - 0 - 3/16(a)

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