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real-time analog computational unit (acu) AD538 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features v o = v y (v z /v x ) m transfer function wide dynamic range (denominator) ?1000:1 simultaneous multiplication and division resistor-programmable powers and roots no external trims required low input offsets <100 v low error 0.25% of reading (100:1 range) monolithic construction real-time analog multiplication, division and exponentiation high accuracy analog division with a wide input dynamic range on board +2 v or +10 v scaling reference voltage and current (summing) input modes monolithic construction with lower cost and higher reliability than hybrid and modular circuits applications one- or two-quadrant multiply/divide log ratio computation squaring/square rooting trigonometric function approximations linearization via curve fitting precision agc power functions functional block diagram v o a b d v x v z v y +10 v +2v c i i x i z i y 00959-001 100? 100? 25k? 25k? AD538 log ratio 25k? output antilog internal voltage reference log figure 1. general description the AD538 is a monolithic real-time computational circuit that provides precision analog multiplication, division, and exponentiation. the combination of low input and output offset voltages and excellent linearity results in accurate computation over an unusually wide input dynamic range. laser wafer trimming makes multiplication and division with errors as low as 0.25% of reading possible, while typical output offsets of 100 v or less add to the overall off-the-shelf performance level. real-time analog signal processing is further enhanced by the 400 khz bandwidth of the device. the overall transfer function of the AD538 is v o = v y (v z /v x ) m . programming a particular function is via pin strapping. no external components are required for one-quadrant (positive input) multiplication and division. two-quadrant (bipolar numerator) division is possible with the use of external level shifting and scaling resistors. the desired scale factor for both multiplication and division can be set using the on-chip +2 v or +10 v references, or controlled externally to provide simultaneous multiplication and division. exponentiation with an m value from 0.2 to 5 can be implemented with the addition of one or two external resistors. direct log ratio computation is possible by using only the log ratio and output sections of the chip. access to the multiple summing junctions adds further to the flexibility of the AD538. finally, a wide power supply range of 4.5 v to 18 v allows operation from standard 5 v, 12 v and 15 v supplies. the AD538 is available in two accuracy grades (a and b) over the industrial (?25c to +85c) temperature range and one grade (s) over the military (?55c to +125c) temperature range. the device is packaged in an 18-lead to-118 hermetic side-brazed ceramic dip. a-grade chips are also available.
important links for the AD538 * last content update 09/07/2013 05:28 pm parametric selection tables find similar products by operating parameters documentation an-213: low cost, two-chip, voltage -controlled amplifier and video switch an-304: one chip slide-rulerdquo; works with logs, antilogs for real time processing ask the applications engineer-1 space qualified parts list evaluation kits & symbols & footprints symbols and footprints design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy AD538 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
AD538 rev. e | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ........................................................................ 9 re - examination of multiplier/divider accuracy .................... 9 functional description .............................................................. 10 stability precautions ................................................................... 10 using the voltage references .................................................. 10 one - quadrant multiplication/division .................................. 11 two - quadrant division ............................................................ 12 log rat io operation .................................................................. 12 analog computation of powers and roots .......................... 13 square root operation .............................................................. 13 applications information .............................................................. 15 transducer linearization .......................................................... 15 arc - tangent approximation .................................................. 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 6 /11 rev. d to rev. e updated format .................................................................. universal added table 3 .................................................................................... 6 changes to ordering guide .......................................................... 11 5/10 rev. c to rev. d updated outline dimensions ....................................................... 11 changes to ordering guide .......................................................... 11
AD538 rev. e | page 3 of 16 specifications v s = 15 v, t a = 25 c , unless otherwise noted . table 1 . parameter test conditions/ comments AD538ad AD538bd AD538sd unit min typ max min typ max min typ max multiplier divider performance nominal transfer function 10 v v x , v y , v z 0 v o = v y ( v z / v x ) m v o = v y ( v z / v x ) m v o = v y ( v z / v x ) m 400 a i x , i y , i z 0 v o = 25 k i y ( i z / i x ) m v o = 25 k i y ( i z / i x ) m v o = 25 k i y ( i z / i x ) m total error terms 100 mv v x 10 v 0.5 1 0.25 0.5 0.5 1 % of reading + 100:1 input range 1 100 mv v y 10 v 200 500 100 250 200 500 v 100 mv v z 10 v v z 10 v x , m = 1.0 t a = t min to t max 1 2 0.5 1 1.25 2.5 % of reading + 450 750 350 500 750 1000 v wide dynamic range 2 100 mv v x 10 v 1 2 0.5 1 1 2 % of reading + 100 mv v y 10 v 200 500 100 250 200 500 v 100 mv v z 10 v 100 250 750 150 200 250 v (v y + v z )/v x v z 10 v x , m = 1.0 t a = t min to t max 1 3 1 2 2 4 % of reading + 450 750 350 500 750 1000 v + 450 750 350 500 750 1000 v (v y + v z )/v x exponent (m) range t a = t min to t max 0.2 5 0.2 5 0.2 5 output characteristics offset voltage v y = 0, v c = ? 600 mv 200 500 100 250 200 500 v t a = t min to t max 450 750 350 500 750 1000 v output voltage swing r l = 2 k ? 11 +11 ? 11 +11 ? 11 +11 v output current 5 10 5 10 5 10 ma frequency response slew rate 1.4 1.4 1.4 v/s small signal bandwidth 100 mv 10 v y , v z , v x 10 v 400 400 400 khz voltage reference accuracy v re f = 10 v or 2 v 25 50 15 25 25 50 mv additional error t a = t min or t max 20 30 20 30 30 50 mv output current v ref = 10 v to 2 v 1 2.5 1 2.5 1 2.5 ma power supply rejection +2 v = v ref 4.5 v v s 18 v 300 600 300 600 300 600 v/v +10 v = v ref 13 v v s 18 v 200 500 200 500 200 500 v/v power supply rated r l = 2 k 15 15 15 v operating range 3 4.5 18 4.5 18 4.5 18 v psrr 4.5 v< , v s < 18 v 0.5 0.1 0.5 0.1 0.5 0.1 %/v v x = v y = v z = 1 v v o = 1 v quiescent current 4.5 7 4.5 7 4.5 7 ma
AD538 rev. e | page 4 of 16 parameter test conditions/ comments AD538ad AD538bd AD538sd unit min typ max min typ max min typ max temperature range rated ? 25 +85 ? 25 +85 ? 55 +125 c storage ? 65 +150 ? 65 +150 ? 65 +150 c 1 over the 100 mv to 10 v operating range total error is the sum of a percent of reading term and an output offset. with this i nput dynamic range the input offset contribution to total error is negligible compared to the p ercent of reading error. thus, it is specified indirectly as a part of the percent of reading error. 2 the most accurate representation of total error with low level inputs is the summation of a percent of reading term, an outpu t offset and an input offset multiplied by the incremental gain (v y + v z ) v x . 3 when using supplies below 13 v, the 10 v reference pin must be connected to the 2 v pin in order for the AD538 to operate correctly.
AD538 rev. e | page 5 of 16 absolute maximum rat ings table 2 . parameter rating supply voltage 18 v internal power dissipation 250 mw output short circuit - to - ground indefinite input voltages v x , v y , v z (+v s ? 1 v), ? 1 v input currents i x , i y , i z , i o 1 ma operating temperature range ? 25c to +85c stor age temperature range ? 65c to +150c lead temperature, storage 60 sec, +300c thermal resistance jc 35c/w ja 120c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating o nly; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y. esd caution
AD538 rev. e | page 6 of 16 pin configuration an d function descripti ons 00959-002 i z 1 v z 2 b 3 +10v 4 a 18 d 17 i x 16 v x 15 +2v 5 signal gnd 14 +v s 6 pwr gnd 13 ?v s 7 c 12 v o 8 i y 1 1 i 9 v y 10 AD538 t op view (not to scale) figure 2. pin configuration table 3 . pin no. mnemonic description 1 i z current input for the z multiplicand . 2 v z voltage input fo r the z multiplicand . 3 b output of the log ratio differential amplifier. this amplifier subtracts the l og of the z input from the log of the x i nput, or performs the equivalent logarithmic equivalent of long division. 4 +10v +10 v reference voltage outp ut . 5 +2v +2 v reference voltage output . 6 +v s positive supply rail . 7 C v s negative rail . 8 v o output voltage . 9 i current input to the output amplifier . 10 v y voltage input to the y multiplicand . 11 i y current input to the y multiplicand . 12 c cur rent input to the base of the antilog log -to - linear converter . 13 pwr gnd high level power return of the chip . 14 signal gnd low level ground return of the device . 15 v x voltage input of the x multiplicand . 16 i x current input of the x input multiplica nd . 17 d use for log ratio function. 18 a use for log ratio function.
AD538 rev. e | page 7 of 16 typical performance characteristics 5 1000 800 600 400 200 0 4 3 2 1 0 ?55 ?40 ?20 0 20 40 60 80 100 125 temperature (c) total % of reading error output stage offset (v) 00959-003 offset % of reading figure 3 . multiplier error vs. temperature (100 mv < v x , v y , v z 10 v) 5 1000 800 600 400 200 0 4 3 2 1 0 ?55 ?40 ?20 0 20 40 60 80 100 125 temperature (c) total % of reading error output stage offset (v) 00959-004 offset % of reading figure 4 . divider error vs. temperature (100 mv < v x , v y , v z 10 v) 1000 100 10 1 100 1k 10k 100k 1m input frequency (hz) v o (mv p-p) 00959-005 v x = 10v v y = 0v v z = 5v +5v sin t volts figure 5. v z feedthrough vs. frequency 1m 100k 400k 10k 40k 0.01 0.1 1 10 denominator voltage, v x ? v dc small signal bandwidth (hz) 00959-006 v y = 10v dc v z = v x +0.05 v x sin t figure 6 . small signal bandwidth vs. denominator v oltage (one - quadrant mult/div) 5 6 1000 1200 800 600 400 200 0 4 3 2 1 0 ?55 ?40 ?20 0 20 40 60 80 100 125 temperature (c) total % of reading error output stage offset (v) 00959-007 % of reading offset figure 7 . multiplier error vs. temperature (10 mv < v x , v y , v z 100 mv) 5 1000 800 600 400 200 0 4 3 2 1 0 ?55 ?40 ?20 0 20 40 60 80 100 125 temperature (c) total % of reading error output stage offset (v) 00959-008 % of reading offset figure 8 . divider error vs. temperature (10 mv < v x , v y , v z 100 mv)
AD538 rev. e | page 8 of 16 100 150 10 1 0.1 100 1k 10k 100k 1m input frequency (hz) v o (mv p-p) 00959-009 v x = 10v v y = 5v +5v sin t volts v z = 0v figure 9. v y feedthrough vs. frequency 5 4 3 2 1 0 0.01 0.1 1 10 dc output voltage (v) voltage noise (e n ? v/ hz) 00959-010 v x = 0.01v v x = 10v for the frequency range of 10hz to 100khz the total rms output noise, e o , for a given bandwidth bw, is calculated e o = e n bw. figure 10 . 1 khz output noise spectral density vs. dc output voltage
AD538 rev. e | page 9 of 16 theory of operation re-examination of multiplier/divider accuracy traditionally, the accuracy (actually the errors) of analog multipliers and dividers has been specified in terms of percent of full scale. thus specified, a 1% multiplier error with a 10 v full-scale output would mean a worst-case error of +100 mv at any level within its designated output range. while this type of error specification is easy to test evaluate, and interpret, it can leave the user guessing as to how useful the multiplier actually is at low output levels, those approaching the specified error limit (in this case) 100 mv. the error sources of the AD538 do not follow the percent of full-scale approach to specification, thus it more optimally fits the needs of the very wide dynamic range applications for which it is best suited. rather than as a percent of full scale, the AD538s error as a multiplier or divider for a 100:1 (100 mv to 10 v) input range is specified as the sum of two error components: a percent of reading (ideal output) term plus a fixed output offset. following this format, the AD538ad, operating as a multiplier or divider with inputs down to 100 mv, has a maximum error of 1% of reading 500 v. some sample total error calculations for both grades over the 100:1 input range are illustrated in table 4. this error specification format is a familiar one to designers and users of digital voltmeters where error is specified as a percent of reading a certain number of digits on the meter readout. for operation as a multiplier or divider over a wider dynamic range (>100:1), the AD538 has a more detailed error specification that is the sum of three components: a percent of reading term, an output offset term, and an input offset term for the v y /v x log ratio section. a sample application of this specification, taken from table 4, for the AD538ad with v y = 1 v, v z = 100 mv and v x = 10 mv would yield a maximum error of 2.0% of reading 500 v (1 v + 100 mv)/10 mv 250 v or 2.0% of reading 500 v 27.5 mv. this example illustrates that with very low level inputs the AD538s incremental gain (v y + v z )/v x has increased to make the input offset contribution to error substantial. table 4. sample error calculation chart (worst case) v y input (v) v z input (v) v x input (v) ideal output (v) total offset error term (mv) % of reading error term (mv) total error summation (mv) total error summation as a % of the ideal output 100:1 input range total error = % rdg output v os 10 10 10 10 0.5 (ad) 100 (ad) 100.5 (ad) 1.0 (ad) 0.25 (bd) 50 (bd) 50.25 (bd) 0.5 (bd) 10 0.1 0.1 10 0.5 (ad) 100 (ad) 100.5 (ad) 1.0 (ad) 0.25 (bd) 50 (bd) 50.25 (bd) 0.5 (bd) 1 1 1 1 0.5 (ad) 10 ) (ad 10.5 (ad) 1.05 (ad) 0.25 (bd) 5 (bd) 5.25 (bd) 0.5 (bd) 0.1 0.1 0.1 0.1 0.5 (ad) 1 (ad) 1.5 (ad) 1.5 (ad) 0.25 (bd) 0.5 (bd) 0.75 (bd) 0.75 (bd) wide dynamic range total error = % rdg output v os input v os (v y + v z )/v x 1 0.10 0.01 10 28 (ad) 200 (ad) 228 (ad) 2.28 (ad) 16.75 (bd) 100 (bd) 116.75 (bd) 1.17 (bd) 10 0.05 2 0.25 1.76 (ad) 5 (ad) 6.76 (ad) 2.7 (ad) 1 (bd) 2.5 (bd) 3.5 (bd) 1.4 (bd) 5 0.01 0.01 5 125.75 (ad) 100 (ad) 225.75 (ad) 4.52 (ad) 75.4 (bd) 50 (bd) 125.4 (bd) 2.51 (bd) 10 0.01 0.1 1 25.53 (ad) 20 (ad) 45.53 (ad) 4.55 (ad) 15.27 (bd) 10 (bd) 25.27 (bd) 2.53 (bd)
AD538 rev. e | page 10 of 16 functional descripti on as shown in figure 1 and fi gure 11 , the v z and v x inputs connect directly to the input log ratio amplifiers of the AD538 . this subsection provides an output voltage proportional to the natural log of input voltage, v z , minus the natural log of input voltage , v x . the output of the l og ratio subsection at b can be expressed by the transfer function ? ? ? ? ? ? ? ? = x z b v v q kt v ln w here: k is 1.3806 10 ? 23 j/k. q is 1.60219 10 ? 19 c. t is in kelvins. the log ratio configuration may be used alone, if correctly temperature compensated and scaled to the desired output level (see the applications information section). under normal operation, the log - ratio output will be directly connected to a second functional block at input c, the antilog subsection. this section performs the antilog according to the transfer function: ? ? ? ? ? ? = kt q v e v v c y o as with the log - ratio circuit included in the AD538, the user may use the antilog subsection by itself. when both subsections are combined, the output at b is tied to c, the transfer function of the AD538 computational unit is: v o = v y e c b v v kt q q kt v v x z = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; ln which reduces to: ? ? ? ? ? ? ? ? = x z y o v v v v finally, by increasing the gain, or attenuating the output of the log ratio subsection via resistor programming, it is possible to raise the quantity v z /v x to the m th power. without external programming, m is unity. thus , the overall AD538 transfer f unction equals: m x z y o v v v v ? ? ? ? ? ? ? ? = where 0.2 < m < 5. when the AD538 is used as an analog divider, the v y input can be used to multiply the ratio v z /v x by a convenient scale factor. the actual multiplication by the v y input signal is accomplished by ad ding the log of the v y input signal to the signal at c, which is already in the log domain. s tability p recautions at higher frequencies, the multistaged signal path of the AD538 can result in large phase shifts (as illustrated in figure 11) . if a condition of high incremental gain exists along that path (for example , v o = v y v z /v x = 10 v 10 mv/10 mv = 10 v so that v o / v x = 1000), then small amounts of capacitive feedbac k from v o to the current inputs i z or i x can result in instability. appropriate care should be exercised in board layout to prevent capacitive feedback mechanisms under these conditions. 00959-012 log e i y v y ln y log e i z v z ln z log e i x v x ln x buffer + + + ? ln z ? ln x m(ln z ? ln x) m(ln z ? ln x) +ln y antilog e 0.2 ?0? v o = v y v z v x m figure 11 . model circuit u sing t he v oltage r eferences a stable band gap voltage reference for scaling is included in the AD538. it is laser - trimmed to provide a selectable voltage output of +10 v buffered (pin 4), +2 v unbuffered (pin 5) or any voltages between +2 v and +10.2 v buffered as shown in figure 12 . the output impedance at pin 5 is approxima tely 5 k . note that any loading of this pin produce s an error in the +10 v reference voltage. external loads on the +2 v output should be greater than 500 k to maintain errors less than 1%. 25k? 25k? 100? 25k? 25k? antilog log output 100? 50k? +2v to +10.2v buffered 11.5k ? AD538 i y a d i x v x c v y 8 1 1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 2 3 4 5 6 7 8 9 log ratio internal voltage reference signal gnd pwr gnd i z v z v o i +v s ?v s b ref out +2v 00959-013 figure 12 . +2 v to +10.2 v adjustable reference in si tuations not requiring both reference levels, the +2 v outpu t can be converted to a buffered output by tying pin 4 and pin 5 together. if both references are required simult aneously, the +10 v output should be used directly and the +2 v out put should be externally buffered.
AD538 rev. e | page 11 of 16 one - q uadrant m ultiplication /d ivision figure 13 shows how the AD538 may be easily configured as a precision one - quadrant multiplier/divider. the transfer function v o = v y (v z /v x ) allows three ind ependent input variables, a calculation not available with a conventional multipli er. in addition, the 1000:1 (that is, 10 mv to 10 v) input dynamic range of the AD538 greatly exceeds that of analog multipliers computing one - quadrant multiplication and d ivision. 25k? 25k? 100? 25k? 25k? antilog log output 100? AD538 i y a d i x v x c in4148 v y 8 1 1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 2 3 4 5 6 7 8 9 log ra tio interna l volt age reference signa l gnd pwr gnd i z v z v z input v o i +15v ?15v b +10v +2v 00959-014 output v y input v x input v o = v y v z v x figure 13 . one - quadrant combination multiplier/divider by simply connecting the input , v x (pin 15) to the 10 v reference (pin 4), and tying the log - ratio output at b to the antilog input at c, the AD538 can be configured as a one - qua drant analog multiplier with 10 v scaling. if 2 v scaling is desired, v x can be tied to the 2 v reference. when the input v x is tied to the +10 v reference terminal, the multiplier transfer function becomes: v v v v z y o 10 as a multi plier, this circuit provides a typical bandwidth of 400 khz with values of v x , v y , or v z varying over a 100:1 range ( that is , 100 mv to 10 v). the maximum error with a 100 mv to 10 v range for the two input variables will typically be +0.5% of reading. usi ng the optional z offset trim scheme, as shown in figure 14 , this error can be reduced to +0.25% of reading. by using the 10 v reference as the v y input, the circuit of figure 13 is configured as a one - qu adrant divider with a fixed scale factor. as with the one - quadrant multiplier, the inputs accept only single (positive) polarity signals. the output of the one - quadrant divider with a +10 v scale factor is: x z o v v v v 10 the typical bandwidth of this circuit is 370 khz with 1 v to 10 v denominator input levels. at lower amplitudes, the band - width gradually decreases to approximately 200 khz at the 2 mv input level.
AD538 rev. e | page 12 of 16 t wo - q uadrant d ivision the two - quadrant linear divider circuit illustrated in figure 14 uses the same basic connections as the one - quadrant version. however, in this circuit the numerator has been offset in the positive direction by adding the denominator input voltage to it. the offsetting scheme changes the d i viders transfer function from ? ? ? ? ? ? ? ? = x z o v v v v 10 to ( ) ? ? ? ? ? ? ? ? + = ? ? ? ? ? ? ? ? + = + = x z x z x x z o v v v v a v av v v v 10 a 10 1 v 10 v 10 where: ? ? ? ? ? ? ? ? = k 25 k 35 a as long as the magnitude of the denominator input is equal to or greater than the magnitude of the numerator input, the circuit accept s bipolar n umerator voltages. however, under the conditions of a 0 v numerator input, the output would incorrectly equal +14 v. the offset can be removed by connecting the 10 v reference through resistors r1 and r2 to the output sections summing node i at pin 9 thu s providing a gain of 1.4 at the center of the trimming potentiometer. the pot entiometer , r2 , adjusts out or corrects this offset, leaving the desired transfer function of 10 v (v z /v x ). 25k? 35k? r2 10k? r1 12.4k ? 25k? 35k? 100? 25k? 25k? antilog log output zero adjust 100? AD538 i y a d i x v x c in4148 v y 8 1 1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 2 3 4 5 6 7 8 9 log ra tio interna l volt age reference signa l gnd pwr gnd i z v z v o i b +10v +2v output v o = 10 for v x ?9 z v z v x 10m ? v os 3.9m ? 1m ? adj 68k? ?1.2v ad589 ?v s numer a t or v z denomin a t or v x optiona l z offset trim 00959-015 +15v ?15v figure 14 . two - quadrant division with 10 v scaling log r atio o peration figure 15 shows the AD538 configured for computing the log of the ratio of two input voltages (or currents). the output signal from b is connected to the summing junction of the output amplifier via two series resistors. the 90.9 metal film resistor effectively degrades the temperature coefficient of the 3500 ppm/c resistor to produce a 1.09 k +3300 ppm/c equivalent value. in this configuration, the v y input must be tied to some voltage less th an zero ( ? 1.2 v in this case) removing this input from the transfer function. the 5 k potentiometer controls the circuits scale factor adjustment providing a +1 v per decade adjustment. the output offset potentiometer should be set to provide a zero outp ut with v x = v z = 1 v. t h e i n p u t v z adjustment should be set for an output of 3 v with v z = l mv and v x = 1 v. 25k? 1m ? ad589 68k? 5% optiona l input v os adjustment 10m ? ?1.2v ?v s 25k? 100? 90.9 ? 1% 1k +3500 ppm/c 25k? 25k? antilog log output 100? 48.7 ? AD538 i y a d i x v x c in4148 v y 8 1 1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 2 3 4 5 6 7 8 9 log ra tio interna l volt age reference signa l gnd pwr gnd i z v z v o i +15v ?15v b +10v +2v 00959-016 output v x input v z v x 5k? scale f ac t or adjust optiona l output v os adjustment 2k? 1% +v s ?v s 10k? 10m ? v o = 1v log 10 figure 15 . log ratio circuit the log ratio circuit shown achieves 0.5% accuracy in the log domain for input voltages within three decades of input range: 10 mv to 10 v. this error is not defined as a percent of full - s cale output, but as a percent of input. for example, using a 1 v/decade scale factor, a 1% error in the positive direction at the input of the log ratio a mplifier translates into a 4.3 mv deviation from the ideal output ( that is , 1 v log 10 (1.01) = 4.3214 mv). an input error 1% in the negative direction is slightly different, giving an output deviation of 4.3648 mv.
AD538 rev. e | page 13 of 16 analog c omputation of p owers a nd r oots it is often necessary to raise the quotient of two input signals to a power or take a root. this could be squaring, cubing, square rooting or exponentiation to some noninteger power. examples include power series generation. with the AD538, only one or two external resistors are required to set any desired power, over the range of 0.2 to 5. raising the basic quantity v z /v x to a power greater than one requires that the gain of the AD538s log ratio subtractor be increased, via an external resistor between th e a and d pins . similarly, a voltage divider that attenuates the log ratio output between point b and point c will program the power to a value less than one. 00959-017 3 12 18 17 2 10 15 8 r a r b r c v o v o v z v y v z v y v ref v x v ref v x b ca d powers m r a 2 196? 3 97.6 ? 4 64.9 ? 5 48.7 ? 3 12 2 10 15 8 b c roots m r b r c 1/2 100 ? 100? 1/3 100 ? 49.9 ? 1/4 150 ? 49.9 ? 1/5 162 ? 40.2 ? r a = r b = r c 200? 196? m ? 1 v z v ref v y ( ) m v z v ref v y ( ) m = ?1 r b r c 1 m figure 16 . basic configurations and transfer functions for the AD538 s quare root o peration the explicit square root circuit of figure 17 illustrates a precise method for performing a real - time square root computation. for added flexibility and accuracy, this circuit has a scale factor adjustment. the actual square rooting operation is performed in this circuit by raising the quantity v z /v x to the one - half power via the resistor divider network consisting of resistors r b and r c . for maximum linearity, the two resistors should be 1% (or better) ratio - matched metal film types. 1 v scaling is achieved by dividing - down the 2 v reference and applying approximately 1 v to both the v y and v x inputs. in this circuit, the v x input is intentionally set low, to about 0.95 v, so that the v y input can be adjust ed high, permitting a 5% scale factor trim. using this trim scheme, the output voltage will be within 3 mv 0.2% of the ideal value over a 10 v to 1 mv input range (80 db). for a decreased input dynamic range of 10 mv to 10 v (60 db) the error is even less; here the output will be within 2 mv 0.2% of the ideal value. the bandwidth of the AD538 square root circuit is approximately 280 khz with a 1 v p - p sine wave with a +2 v dc offset. t his basic circuit may also be used to compute the cube, fourth or fifth roots of an input waveform. all that is required for a given root is that the correct ratio of resistors, r c and r b , be selected such that their sum is between 150 and 200 . the op tional absolute value circuit shown preceding the AD538 allows the use of bipolar input voltages. only one op amp is required for the absolute value function because the i z input of the AD538 functions as a summing junction. if it is necessary to preserve the sign of the input voltage, the polarity of the op amp output may be sensed and used after the computation to switch the sign bit of a d vm chip.
AD538 rev. e | page 14 of 16 00959-018 25k? 25k? 100? 25k? 25k? antilog log output 100? r b 100? * r c 100? * ra tio m a tch 1% me t al film resis t ors for best accurac y * AD538 i y a d i x v x c d1 in4148 v y 8 1 1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 2 3 4 5 6 7 8 9 log ra tio interna l volt age reference signa l gnd pwr gnd i z v z v o i +15v ?15v b +10v +2v +2v 1k? 100? scale f ac t or trim 1k? v in 20k? 20k? 10k? 5k? optiona l absolute v alue section 20k? +v s v os in4148 ad op-07 or ad8 1 1 (v os t ap t o ?v s ) in4148 ?v s 2 7 1 8 6 4 3 v in 1v v o = 1v v o figure 17 . square root circuit
AD538 rev. e | page 15 of 16 applications information t ransducer l ineariza tion many electronic transducers used in scientific, commercial or industrial equipment monitor the physical properties of a device and/or its environment. sensing (and perhaps compensating for) changes in pressure, temperature, moisture or other physical phenomenon can be an expensive undertaking, particularly where high accuracy and very low nonlinearity are important. in conventional analog systems accuracy may be easily increased by offset and scale factor trims ; however, nonlinearity is usually the abs olute limitation of the sensing device. with the ability to easily program a complex analog function, the AD538 can effectively compensate for the nonlinearities of an inexpensive transducer. the AD538 can be connected between the transducer preamplifier output and the next stage of monitoring or transmitting circuitry. the recommended procedure for linearizing a particular transducer is first to find the closest function which best approximates the nonlinearity of the device and then, to select the appro priate exponent resistor value(s). arc - t angent a pproximation the circuit of figure 18 is typical of those AD538 applications where the quantity v z /v x is raised to powers greater than one. in an approximate arc - tangent function, th e AD538 will accurately compute the angle that is defined by x and y displacements represented by input voltages v x and v z . with accura cy to within one degree (for input voltages between 100 v and 10 v ), the AD538 arc - tangent circuit is more precise than conventional analog circuits and is faster than most digital techniques. the circuit shown is set up for the transfer function: ( ) ( ) ( ) 21 . 1 ? ? ? ? ? ? ? = x z ref v v v v v where: ? ? ? ? ? ? = ? x z tan 1 the (v ref ? v ) function is implemented in this circuit by adding together the output, v , and an externally applied reference voltage, v ref , via an external ad547 op amp. the 1 f c apacitor connected around the ad547s 100 k feedback resistor frequency compensates the loop (formed by the amplifier between v and v y ). 25k? 25k? 100? 25k? 25k? antilog in4148 log output 100? AD538 i y a d i x v x v z 1f 1f v x c v y 8 1 1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 2 3 4 5 6 7 8 9 log ratio internal voltage reference signal gnd pwr gnd i z v z v o i +v s ?v s b +10v +2v 00959-019 v = [v 5() ?v ] v z v x 1.21 t an ?1 z x r a 931 ? v ?15v +15v r1* 100k? r2* 100k? 118k? 1f 0.1f 100k? 10k? full-scale adjust +15v ?15v 7 4 3 6 2 ad547jh ratio match 1% metal film resistors for best accuracy * figure 18 . the arc - tangent function the v b /v a quantity is calculated in the same manner as in the one - quadrant divider circuit, except that the resulting quotient is raised to the 1.21 power. resistor r a (nominally 931 ) sets the power or m factor. for the highest arc - tangent accuracy the r1 and r2 external resistors should be ratio matched; h owever, the offset trim scheme shown in other circuits is not required since nonlinearity effects are the predominant source of error. also note that instability will occur as the output approaches 90 because, by definition, the arc - tangent function is in finite and therefore, the g ain of the AD538 will be extremely high.
AD538 rev. e | page 16 of 16 outline dimensions 18 1 9 10 0.310 (7.87) 0.220 (5.59) pin 1 0.098 (2.49) max 0.005 (0.13) min seating plane 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) max 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.960 (24.38) max 0.100 (2.54) bsc 0.150 (3.81) min 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. figure 19 . 18 - lead side - brazed ceramic dual in - line package [sbdip] (d - 18) dimensions shown in inches and (millimeters) ordering guide mo del 1 temperature range package description package option AD538achips ? 25c to +85c chips AD538ad ? 25c to +85c 18- lead side - brazed ceramic dual in - line package [sbdip] d -18 AD538adz ? 25c to +85c 18- lead side - brazed ceramic dual in - line package [sbdip] d -18 AD538bd ? 25c to +85c 18- lead side - brazed ceramic dual in - line package [sbdip] d -18 AD538bdz ? 25c to +85c 18- lead side - brazed ceramic dual in - line package [sbdip] d -18 AD538sd ? 55c to +125c 18- lead side - brazed cera mic dual in - line package [sbdip] d -18 AD538sd/883b ? 55c to +125c 18- lead side - brazed ceramic dual in - line package [sbdip] d -18 1 z = rohs compliant part. ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00959 - 0- 6/11(e)

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