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? semiconductor components industries, llc, 2008 october, 2008 ? rev. 25 1 publication order number: ncv8509/d ncv8509 series sequenced linear dual-voltage regulator the ncv8509 series are dual voltage regulators whose output voltages power up in such a manner as to protect the integrity of modern day microcontroller i/o and esd input structures. newer generation microcontrollers require two power supplies. one voltage is used for powering the core, while the other powers the i/o. features ? power ? up sequence ? output voltage options: ? v out1 5 v ( 2%) 115 ma, v out2 2.6 v (2%) 100 ma ? v out1 5 v ( 2%) 115 ma, v out2 2.5 v (2%) 100 ma ? v out1 3.3 v ( 2%) 115 ma, v out2 1.8 v (2%) 100 ma ? low 175 a quiescent current ? power shunt ? programmable reset time ? dual drive reset valid ? programmable slew rate control ? thermal shutdown ? 16 lead sow exposed pad ? ncv prefix, for automotive and other applications requiring site and change control ? aec qualified ? ppap capable ? these are pb ? free devices typical applications ? automotive powertrain ? telematics v in1 v in2 gnd v out1 v out2 slew reset delay microprocessor ncv8509 v bat figure 1. application diagram r ex 138 c slew 33 nf c in1 10 f c in2 0.1 f c vout1 10 f c vout2 10 f c delay 33 nf r reset 10 k mra4004t3 http://onsemi.com pin connections marking diagram xx = voltage ratings as indicated below: 26 = 5 v/2.6 v 25 = 5 v/2.5 v 18 = 3.3 v/1.8 v a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free device soic 16 lead wide body exposed pad pdw suffix case 751ag 1 16 1 16 nc nc 1 16 v out2 nc nc reset v in2 nc v in1 nc nc gnd v out1 delay nc slew see detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. ordering information ncv8509xx awlyywwg http://onsemi.com
ncv8509 series http://onsemi.com 2 maximum ratings rating value unit v in1 (dc) ? 0.3 to 50 v v in1 peak transient voltage 50 v v in2 (dc) 50 v v in2 (current out of pin) 10 ma operating voltage 50 v input voltage range (slew, reset , delay) ? 0.3 to 10 v v out1 10 v v out2 10 v electrostatic discharge (human body model) (machine model) 4.0 400 kv v package thermal resistance, sow ? 16 e pad: junction ? to ? case, r jc junction ? to ? ambient, r ja 16 57 c/w c/w lead temperature soldering: reflow: (smd styles only) (note 1) 240 peak (note 2) c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. 60 second maximum above 183 c. 2. ? 5 c/+0 c allowable conditions. electrical characteristics (6.0 v < v in1 < 18 v, i vout1 = 5.0 ma, i vout2 = 5.0 ma, ? 40 c < t j < 125 c, c vout1 = c vout2 = 10 f; unless otherwise noted.) characteristic test conditions min typ max unit v out1 output voltage 5 v option 3.3 v option 1.0 ma < i vout1 < 100 ma 1.0 ma < i vout1 < 100 ma 4.9 3.234 5.0 3.3 5.1 3.366 v v dropout voltage (v in1 ? v out1 ) i out = 100 ma i out = 100 a ? ? 400 100 600 200 mv mv load regulation 1.0 ma < i vout1 < 100 ma ? 10 50 mv line regulation 6.0 v < v in1 < 18 v ? 10 50 mv current limit v out1 = v out1 (typ) ? 500 mv v out1 = 0 v 115 ? 305 105 610 300 ma ma v out2 output voltage 2.6 v option 2.5 v option 1.8 v option 1.0 ma < i vout2 < 100 ma 1.0 ma < i vout2 < 100 ma 1.0 ma < i vout2 < 100 ma 2.548 2.450 1.764 2.6 2.5 1.8 2.652 2.550 1.836 v v v load regulation 1.0 ma < i vout2 < 100 ma ? 5.0 50 mv line regulation 6.0 v < v in1 = v in2 < 18 v ? 10 50 mv current limit v out2 = v out2 (typ) ? 500 mv v out2 = 0 v 105 ? 305 105 610 300 ma ma general quiescent current i out1 = i out2 = 100 a, v in1 = 12 v i out1 = i out2 = 50 ma, v in1 = 14 v ? ? 125 5.0 175 10 a ma thermal shutdown (note 3) (guaranteed by design) 150 180 210 c 3. both outputs will turn off.
ncv8509 series http://onsemi.com 3 electrical characteristics (continued) (6.0 v < v in1 < 18 v, i vout1 = 5.0 ma, i vout2 = 5.0 ma, ? 40 c < t j < 125 c, c vout1 = c vout2 = 10 f; unless otherwise noted.) characteristic test conditions min typ max unit slew slew charging current slew = 1.0 v 4.0 6.0 8.0 a v out1 slew rate (note 4) 5 v option 3.3 v option c slew = 33 nf ? ? 710 469 ? ? v/s v/s v out2 slew rate 2.6 v option 2.5 v option 1.8 v option c slew = 33 nf ? ? ? 370 355 256 ? ? ? v/s v/s v/s slew control threshold (see figure 53) 1.5 1.8 2.1 v reset reset threshold increasing (note 5) ? 94.5 96.5 98.5 % reset threshold decreasing 5 v option 3.3 v option 2.6 v option 2.5 v option 1.8 v option ? 4.5 2.97 2.34 2.25 1.62 4.73 3.12 2.46 2.36 1.70 0.965 v out 0.965 v out 0.965 v out 0.965 v out 0.965 v out v v v v v reset output low i reset = 1.0 ma ? 0.1 0.4 v reset output peak power down (see figure 41) ? 0.6 1.0 v reset threshold hysteresis 5 v option 3.3 v option 2.6 v option 2.5 v option 1.8 v option ? 50 33 26 25 18 100 66 52 50 36 150 99 78 75 54 mv mv mv mv mv delay delay switching threshold ? 1.125 1.5 1.875 v delay charge current delay = 1.0 v 4.0 6.0 8.0 a delay saturation voltage v out1 out of regulation ? ? 0.1 v delay discharge current delay = 5.0 v v out1 out of regulation 10 ? ? ma output tracking delta 1 [v out1 ? v out2 ] 5 v option 3.3 v option c out1 = c out2 , i out1 = i out2 c out1 = c out2 , i out1 = i out2 ? ? ? ? 3.2 2.8 v v delta 2 [v out2 ? v out1 ] c out1 = c out2 , i out1 = i out2 ? ? 100 mv power shunt shunt voltage 1 (v in2 ) v in1 = 6.0 v, i out2 = 100 ma, no r ex 3.3 ? 4.6 v shunt voltage 2 (v in2 ) v in1 = 12 v, 1.0 ma < i out2 < 100 ma, no r ex 3.25 4.5 5.75 v 4. not a tested parameter. 5. reset signal sensitive to v out1 and v out2 .
ncv8509 series http://onsemi.com 4 pin description pin no. symbol description 1 ? 9, 11, 14, 16 2% output voltage) for powering microprocessor core. 2% output voltage) for powering microprocessor i/o. v out1 v in1 + + + ? v in1 v in2 c in2 c in1 power shunt bandgap & bias gnd reset v out1 ? + reset comp v bg v ref c delay delay delay discharge latch + ? ? + slew c slew v ref v out1 c out1 v bg v ref v in1 error amp thermal shutdown + + + ? error amp v out2 c out2 v in2 v ref start ? up current figure 2. block diagram slew control r ex v ref start ? up current
ncv8509 series http://onsemi.com 5 typical performance characteristics ? 40 voltage (v) 2.55 temperature ( c) 2.59 2.60 2.61 2.62 2.63 2.64 2.65 ? 20 2.57 2.58 2.56 0 20 40 60 80 100 120 140 figure 3. 2.6 v output voltage ? 40 voltage (v) 3.23 temperature ( c) 3.31 3.32 3.33 3.34 3.35 3.36 3.37 ? 20 3.29 3.30 3.28 0 20 40 60 80 100 120 140 3.27 3.25 3.26 3.24 figure 4. 3.3 v output voltage ? 40 voltage (v) 2.45 temperature ( c) 2.49 2.50 2.51 2.52 2.53 2.54 2.55 ? 20 2.47 2.48 2.46 0 20 40 60 80 100 120 140 figure 5. 2.5 v output voltage ? 40 voltage (v) 1.76 temperature ( c) 1.81 1.82 1.83 1.84 ? 20 1.79 1.80 1.78 0 20 40 60 80 100 120 140 1.77 figure 6. 1.8 v output voltage ? 40 voltage (v) 4.90 temperature ( c) 4.98 5.00 5.02 5.04 5.06 5.08 5.10 ? 20 4.94 4.96 4.92 0 20 40 60 80 100 120 140 figure 7. 5.0 v output voltage i vout1 = 5 ma i vout2 = 5 ma i vout1 = 5 ma i vout2 = 5 ma i vout1 = 5 ma i vout2 = 5 ma i vout1 = 5 ma i vout2 = 5 ma i vout1 = 5 ma i vout2 = 5 ma 1.8 v 0 v in2 (volts) 0 v in1 (volts) 2 4 6 8 10 12 14 16 figure 8. v in2 versus v in1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 r ex = 2.5 v 2.6 v
ncv8509 series http://onsemi.com 6 typical performance characteristics ? 40 c 0 i q (ma) 0 i out1 (ma) 5101520 0 i q (ma) 0 i out1 (ma) 10 20 30 40 50 60 70 80 90 figure 9. i q versus i out1 figure 10. i q versus i out1 25 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 125 c 25 c 100 2 4 6 8 10 12 ? 40 c 125 c 25 c ? 40 c 0 i q (ma) 0 i out2 (ma) 5101520 0 i q (ma) 0 i out2 (ma) 10 20 30 40 50 60 70 80 90 figure 11. i q versus i out2 figure 12. i q versus i out2 25 0.2 0.4 0.6 0.8 1.0 1.2 125 c 25 c 100 0.5 1.0 1.5 2.0 2.5 3.0 ? 40 c 125 c 25 c ? 40 c 0 i q (ma) 0 i out1 , i out2 (ma) 5101520 0 i q (ma) 0 i out1 , i out2 (ma) 10 20 30 40 50 60 70 80 90 figure 13. i q versus i out (v out1 & v out2 ) figure 14. i q versus i out (v out1 & v out2 ) 25 0.5 1.0 1.5 2.0 2.5 125 c 25 c 100 2 4 6 8 12 ? 40 c 125 c 25 c 10 14
ncv8509 series http://onsemi.com 7 typical performance characteristics ? 40 c 0 v out1 (v) 0 v in1 (v) 2468 0 v out1 (v) 0 v in1 (v) 123456789 figure 15. v out1 (5 v) versus v in1 figure 16. v out1 (3.3 v) versus v in1 10 1 2 3 4 5 6 125 c 25 c 10 0.5 1.0 2.0 2.5 3.0 4.0 ? 40 c 125 c 25 c ? 40 c 0 v out2 (v) 0 v in1 (v) 2468 0 v out2 (v) 0 v in1 (v) 123456789 figure 17. v out2 (2.6 v) versus v in1 figure 18. v out2 (2.5 v) versus v in1 10 0.5 1.0 1.5 2.0 2.5 3.0 125 c 25 c 10 0.5 1.0 1.5 2.0 2.5 3.0 ? 40 c 125 c 25 c ? 40 c 0 v out2 (v) 0 v in1 (v) 2468 figure 19. v out2 (1.8 v) versus v in1 10 0.2 0.6 0.8 1.0 2.0 125 c 25 c 13579 1.5 3.5 13579 0.4 1.4 1.6 1.8 1.2 13579
ncv8509 series http://onsemi.com 8 typical performance characteristics ? 40 reset delay time (ms) 7.5 temperature ( c) ? 20 20 40 60 0 time (ms) 0 c delay (nf) 20 40 60 80 100 120 140 figure 20. reset delay time versus temperature figure 21. reset delay time versus c delay 120 8.0 8.5 9.0 9.5 10 160 5 15 20 25 10 40 0 volts/sec 0 c slew (nf) 10 40 50 60 volts/sec 0 c slew (nf) 30 40 50 60 70 80 90 figure 22. slew rate versus c slew figure 23. slew rate versus c slew 100 500 1000 1500 2000 2500 5 v 100 100 200 300 500 700 800 0 80 100 30 35 20 30 70 80 90 3.3 v 2.6 v 2.5 v 1.8 v 400 600 5 v 3.3 v 2.6 v 2.5 v 1.8 v 0 dropout voltage (mv) 0 output current (ma) 150 300 450 125 25 50 75 3.3 v/1.8 v 5 v/2.6 v 0 quiescent current (ma) 0 output current (ma) 8 16 2 4 6 8 1012141618 figure 24. v out1 dropout voltage figure 25. quiescent current vs. v in1 100 250 400 50 200 350 100 5 v/2.5 v 6 14 4 12 2 10 3.3 v/1.8 v 5 v/2.6 v 5 v/2.5 v i out1 = i out2 = 50 ma
ncv8509 series http://onsemi.com 9 typical performance characteristics stable region 0 esr ( ) 0.01 output current (ma) 10 100 1000 10 100 20 30 40 50 60 70 80 90 unstable region stable region c vout1 = 10 f 3.3 v 5.0 v 0 esr ( ) 0.01 output current (ma) 10 100 10 100 20 30 40 50 60 70 80 90 unstable region stable region c vout2 = 10 f 2.5 v 2.6 v 1.8 v figure 26. v out1 output capacitor esr (10 f) figure 27. v out2 output capacitor esr (10 f) 0.1 1 1 0.1 0 esr ( ) 0.01 output current (ma) 10 100 1000 10 100 20 30 40 50 60 70 80 90 stable region 0 esr ( ) 0.01 output current (ma) 10 100 10 100 20 30 40 50 60 70 80 90 unstable region figure 28. v out1 output capacitor esr (0.1 f / 1 f) figure 29. v out2 (2.6 v) output capacitor esr (0.1 f / 1 f) 0.1 1 1 0.1 0 esr ( ) 0.01 output current (ma) 10 100 10 100 20 30 40 50 60 70 80 90 figure 30. v out2 (2.5 v) output capacitor esr (0.1 f / 1 f) 1 0.1 0 esr ( ) 0.01 output current (ma) 10 100 10 100 20 30 40 50 60 70 80 90 unstable region figure 31. v out2 (1.8 v) output capacitor esr (0.1 f / 1 f) 1 0.1 3.3 v, 0.1 f unstable region 3.3 v, 1.0 f 5.0 v, 1.0 f 5.0 v, 0.1 f unstable region 1 f 0.1 f 1 f stable region unstable region unstable region 1 f 0.1 f 1 f unstable region stable region 1 f 1 f 0.1 f 0.1 f
ncv8509 series http://onsemi.com 10 typical performance characteristics (load transient waveforms shown were measured on the 5 v/2.6 v device) figure 32. v out1 load transient response 100 ma to no load & no load to 100 ma figure 33. v out2 load transient response 100 ma to no load & no load to 100 ma figure 34. v out1 load transient response 100 ma to no load figure 35. v out2 load transient response 100 ma to no load figure 36. v out1 load transient response no load to 100 ma figure 37. v out2 load transient response no load to 100 ma
ncv8509 series http://onsemi.com 11 timing diagrams v in1 v out1 v out2 outputs are not actively discharged. figure 38. response to impulse figure 39. output decay vs. load impedance v in1 v out1 v out2 v in1 v out1 v out2 v in1 v out1 v out2 z(v out1 ) << z(v out2 ) z(v out1 ) >> z(v out2 ) figure 40. v in power shunt max v in delta i(v in2 ) r ex power shunt off power shunt on v in2 v in1 4.5 v
ncv8509 series http://onsemi.com 12 circuit description figure 41. dual drive reset valid v in v out1 reset power up short on v out1 v in1 fast turn off reset output peak reset delay reset delay reset delay reset the reset function gets its drive from both the input (v in1 ) and the output (v out1 ). because of this, it is able to maintain a more reliable reset valid signal. most regulators maintain a valid reset signal down to 1 v on the output voltage. the reset on the ncv8509 is valid down to 0 v on the output voltage v out1 (power is provided via v in1 ) and the reset on the ncv8509 is valid down to 0 v on the input voltage v in1 (power is provided via v out1 ). refer to figure 41 for operation timing diagrams. delay function the reset delay circuit provides a programmable (by external capacitor) delay on the reset output lead. the delay lead provides source current (typically 6.0 a) to the external delay capacitor during the following proceedings: 1. during power up (once the regulation threshold has been verified); 2. after a reset event has occurred and the device is back in regulation. the delay capacitor is discharged when the regulation (reset threshold) has been violated. this is a latched incident. the capacitor will fully discharge and wait for the device to regulate before going through the delay time event again. power shunt r ex routes some of the current used in the v out2 to a second input pin (v in2 ). this is accomplished by using an internal shunt. a simplified version of this shunt is shown in figure 42. this has the effect of reducing the amount of power dissipated on chip. the effects of choosing the external resistor value are shown in figure 43. selection of the optimum rex resistor value can be done using the following equation: (v in(max) 4.5) i out2(max) when not using the power shunt, short v in1 to v in2 .
ncv8509 series http://onsemi.com 13 figure 42. power shunt r ex v in1 v in2 v out2 voltage regulator figure 43. power on chip 0 0 v in 0.2 0.4 0.6 0.8 1.0 1.2 1.8 watts 5 10152025 1.4 1.6 r ex > 138 r ex = 138 r ex < 138 i out2 = 100 ma figure 44. 135 v in1 18 v v in2 4.5 v r load v out2 2.5 v 100 ma 135 v in1 6.0 v v in2 3.1 v r load v out2 2.5 v 21.5 ma 135 v in1 6.0 v v in2 4.5 v r load v out2 2.5 v 100 ma 78.5 ma + 600 mv ? figure 45. figure 46. 21.5 ma 100 ma 21.5 ma why use a power shunt? the power shunt circuitry helps manage and optimize power dissipation on the integrated circuit. figure 44 shows a 100 ma load. a 135 resistor dissipates 1.35 w as shown. without the power shunt, the 135 resistor would run into head room issues at 6.0 v and would only be able to drive 21.5 ma as shown in figure 45 before causing the 2.5 v output to collapse. figure 46 shows the power shunt circuitry adding the current back in at low voltage operation. so the power is moved off chip at high voltage where it is needed most. to further clarify, figure 47 shows the maximum allowed resistor value (29 ) without the power shunt for 6.0 v operation. figure 48 shows the scenario at high voltage. only 290 mw of power is dissipated off chip compared to figure 44 with 1.35 w. figure 47. 29 v in1 18 v v in2 15.1 v r load v out2 2.5 v 100 ma figure 48. 29 v in1 6.0 v v in2 3.1 v r load v out2 2.5 v 100 ma + 600 mv ? 100 ma 100 ma
ncv8509 series http://onsemi.com 14 power dissipation ncv8509 has a power shunt circuit which reduces the power on chip by utilizing an external resistor, r ex . thus the power on chip, p ic , is equal to the total power, p t , minus the power dissipated in the resistor p rex . refer to figure 49. p ic p total p rex (1) where (2) p total (v in1 v out1) i out1 (v in1 v out2 )i out2 (v in1 iq) and p rex (v in1 v in2 )i out2 (3) figure 49. ncv8509 control circuitry i out2 i out1 iq v out1 gnd v out2 q3 q2 q1 r ex v z v in2 v in1 shunt v sat + ? in1 sat v ref v in1 (i out2 r ex ) (4) v in2 for v in1
(v ref v sat ) for (v ref v sat )
v in1
(v ref (i out2 r ex )) for (v ref (i out2 i out ))
v in1 where v ref = v z ? v be when q1 is normally conducting. based on equation 3, the power in r ex is dependent on v in2 . (increasing r ex may require an increase in c in2 . a careful system validation should be performed for stability). the voltage on v in2 is controlled by the shunt circuit, which has three modes of operation, as seen in figure 50. mode 1. at low battery v in2 is equal to v in1 minus the saturation voltage of the shunt output npn. mode 2. once v in1 rises above the reference voltage of the shunt circuit, v in2 will regulate at the v ref . mode 3. v in2 would continue to regulate at v ref , but since i out2 is not infinite, when v in1 rises higher than the reference voltage plus the voltage drop across the external resistor r ex , it will force v in2 to be v in1 ? (i out2 r ex ). equation 4 provides a summary for v in2. combining equations 3 and 4 gives three different equations for power across r ex . p mode1 (v sat i out2 ) (5) p mode2 (v in1 v ref ) i out2 (6) p mode3 i out2 2 r ex (7)
ncv8509 series http://onsemi.com 15 figure 50. v in shunt max v in delta i(v in2 ) r ex shunt off shunt on v in2 v in1 4.5 v mode 1 mode 2 mode 3 v in1
v ref v sat v in2 v in1 v sat v ref v sat
v in1
v ref (i out2 r ex ) v in2 v ref v in1 v ref (i out2 r ex ) v in2 v in1 (i out2 r ex ) figure 51. 16 lead sow (exposed pad), ja as a function of the pad copper area (2 oz. cu thickness), board material = 0.0625 g ? 10/r ? 4 40 70 90 100 thermal resistance, junction to ambient, r ja , ( c/w) 0 copper area (mm 2 ) 200 400 800 80 60 50 600 once the value of p ic(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p ic (8) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (9) where: r jc = the junction ? to ? case thermal resistance, r cs = the case ? to ? heatsink thermal resistance, and r sa = the heatsink ? to ? ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
ncv8509 series http://onsemi.com 16 v out1 v out2 short on v out1 short on v out2 10 s 10 s fast slew rate >> soft start figure 52. fault response. note the high slew rate coming out of fault conditions. soft start only applies to a power up sequence. fast slew rate >> soft start decay time dependent on external load decay time dependent on external load disable time disable time slew rate control figure 53 shows the circuitry associated with slew rate control. the diagram highlights the control of one output for simplicity. v out1 and v out2 are both controlled on the ic. the slew rate capacitor (c slew ) is charged with an on ? chip current source runing at 6.0 a (typ.). charging a capacitor with a current source creates a linear voltage ramp as shown in figure 54. the lowest voltage to the positive terminals of the comparator (error amp) dominates the output voltage (v out ). consequently, when c slew is fully discharged on power up, it is the dominant factor on the positive terminal and disables the output. the output (v out ) follows the linear ramp on the slew pin (after being gained up with r1 and r2) until v bg becomes the dominant voltage. this occurs when slew = v bg + v d1 or approximately 1.8 v. r1 + + ? v out r2 error amp slew c slew 6.0 a internal voltage rail 3.8 v d2 v in1 d1 v bg figure 53. slew control circuitry slew time can be calculated using the standard capacitor equation. i c dv dt ,t c( v) i using a 33 nf capacitor, the slew time is: t (33 nf)(1.8 v) 6 a 9.9 ms the corresponding slew rate for this is 1.8 v/9.9 ms = 182 v/s on the slew pin. to calculate the slew rate on outputs, you must multiply by the gain set up by r1 and r2. a v v out 1.28 v for a 5 v output, the gain would be: a v 5v 1.28 v 3.9 v v assuming v bg = 1.28 v. the resultant slew rate on the output is the slew rate on the slew pin multiplied by the gain, or: (182 v s) (3.9 v v) 710 v s outputs in regulation figure 54. time (ms) slew pin voltage (v) 3.8 1.8 t slew
ncv8509 series http://onsemi.com 17 ordering information device output voltage package shipping ? ncv8509pdw18g 3.3 v/1.8 v soic 16 lead (pb ? free) 47 units/rail ncv8509pdw18r2g soic 16 lead (pb ? free) 1000 tape & reel ncv8509pdw25g 5 v/2.5 v soic 16 lead (pb ? free) 47 units/rail NCV8509PDW25R2G soic 16 lead (pb ? free) 1000 tape & reel ncv8509pdw26g 5 v/2.6 v soic 16 lead (pb ? free) 47 units/rail ncv8509pdw26r2g soic 16 lead (pb ? free) 1000 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv8509 series http://onsemi.com 18 package dimensions soic 16 lead wide body exposed pad pdw suffix case 751ag ? 01 issue a g ? w ? ? u ? p m 0.25 (0.010) w ? t ? seating plane k d 16 pl c m 0.25 (0.010) t uw s s m f detail e detail e r x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable protrusion shall be 0.13 (0.005) total in excess of the d dimension at maximum material condition. 6. 751r-01 obsolete, new standard 751r-02. j m 14 pl pin 1 i.d. 8 1 16 9 top side 0.10 (0.004) t 16 exposed pad 18 back side l h dim a min max min max inches 10.15 10.45 0.400 0.411 millimeters b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc h 3.45 3.66 0.136 0.144 j 0.25 0.32 0.010 0.012 k 0.00 0.10 0.000 0.004 l 4.72 4.93 0.186 0.194 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 a b 9 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.350 0.175 0.050 0.376 0.188 0.200 0.074 dimensions: inches 0.024 0.150 exposed pad c l c l on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncv8509/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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