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? 2016 microchip technology inc. ds20005575a-page 1 MIC4102 features ? drives high- and low-side n-channel mosfets with single input ? adaptive anti-shoot-through protection ? low-side drive disable pin ? bootstrap supply voltage to 118v dc ? supply voltage up to 16v ? ttl input thresholds ? on-chip bootstrap diode ? fast 30 ns propagation times ? drives 1000 pf load with 10 ns rise and fall times ? low power consumption ? supply undervoltage protection ?2.5 ? pull-up, 1.5 ? pull-down output resistance ? space saving soic-8l package ? ?40c to +125c junction temperature range applications ? high voltage buck converters ? networking/telecom power supplies ? automotive power supplies ? current-fed push-pull power topologies ? ultrasonic drivers ? avionic power supplies general description the MIC4102 is a high frequency, 100v half-bridge mosfet driver ic featuring internal anti-shoot-through protection. the low-side and high-side gate drivers are controlled by a single input signal to the pwm pin. the MIC4102 implements adaptive anti-shoot-through circuitry to optimize the switching transitions for maximum efficiency. the single input control also reduces system complexity and greatly si mplifies the overall design. the MIC4102 also features a low-side drive disable pin. this gives the MIC4102 the capability to operate in a non-synchronous buck mode. this feature allows the MIC4102 to start up into applications where a bias voltage may already be present without pulling the output voltage down. undervoltage protection on both the low-side and high-side supplies forces the outputs low. an on-chip bootstrap diode eliminates the discrete diode required with other driver ics. the MIC4102 is available in the soic-8l package with a junction operating range from ?40c to +125c. typical application schematic MIC4102 soic-8l hi MIC4102 pwm controller ls ho hs lo hb vdd 9v to 16v bias 100v supply gnd v out 100v half-bridge mosfet driver with anti-shoot-through protection
MIC4102 ds20005575a-page 2 ? 2016 microchip technology inc. functional block diagram MIC4102 1 5 6 8 4 3 2 v ss driver uvlo uvlo level shift driver hv level shift hb ho hs lo pwm ls 7 v dd
? 2016 microchip technology inc. ds20005575a-page 3 MIC4102 1.0 electrical characteristics absolute maximum ratings ? supply voltage (v dd , v hb ? v hs ) .............................................................................................................. ?0.3v to +18v input voltages (v pwm , v ls )...............................................................................................................?0.3v to v dd + 0.3v voltage on lo (v lo )..........................................................................................................................?0.3 v to v dd + 0.3v voltage on ho (v ho ).................................................................................................................v hs ? 0.3v to v hb + 0.3v voltage on hs (continuous)........... .............. .............. .............. .............. ........... ............ ........... ....................?1v to +110v voltage on hb ............... .............. .............. .............. .............. ............ ........... ........... ......... ....................................... +118v average current in v dd to hb diode ................................................................................................................... .100 ma esd rating ..................................................................................................................... ........................................ note 1 operating ratings ? supply voltage (v dd ) .............................................................................................................................. ...... +9v to +16v voltage on hs ............... .............. .............. .............. .............. ............ ........... ........... ......... ........................... ?1v to +100v voltage on hs (repetitive transien t) .............. .............. .............. .............. .............. ........... .......... ............... ?5v to +105v hs slew rate................................................................................................................... ..................................... 50 v/ns voltage on hb ............... .............. .............. .............. .............. ............ ........... ........... ......... ............ v hs + 8v to v hs + 16v and ............................................................................................................................ ................. v dd ? 1v to v dd + 100v ? notice: stresses above those listed under ?absolute maximu m ratings? may cause permanent damage to the device. this is a stress rating only and functiona l operation of the device at those or an y other conditions above those indicated in the operational sections of this s pecification is not intended. exposure to maximum rating conditions for extended periods may affect device reliability. ? notice: the device is not guaranteed to function outside its operating ratings. note 1: devices are esd sensitive. handling precautions are recommended. human body model, 1.5 k ? in series with 100 pf.
MIC4102 ds20005575a-page 4 ? 2016 microchip technology inc. table 1-1: electrical characteristics electrical characteristics: v dd = v hb = 12v; v ss = v hs = 0v; no load on lo or ho; t a = +25c; unless noted. bold values are valid for ?40c t j +125c. ( note 1 ) . parameters sym. min. typ. max. units conditions supply current v dd quiescent current i dd ?150450 a pwm = 0v ?? 600 v dd operating current i ddo ?33.5 ma f = 500 khz ?? 4.0 total hb quiescent current i hb ?25150 a pwm = 0v ?? 200 total hb operating current i hbo ?1.52.5 ma f = 500 khz ?? 3 hb to v ss quiescent current i hbs ?0.05 1 a v hs = v hb = 110v ?? 30 input pins (ttl) low level input voltage threshold v il 0.8 1.5 ? v ? high level input voltage threshold v ih ?1.5 2.2 v? input pull-down resistance r i 100 200 500 k ? ? undervoltage protection v dd rising threshold v ddr 6.5 7.3 8.0 v? v dd threshold hysteresis v ddh ?0.5? v ? hb rising threshold v hbr 6.0 7.0 8.0 v ? hb threshold hysteresis v hbh ?0.4? v ? bootstrap diode low-current forward voltage v dl ?0.40.55 vi vdd-hb = 100 a ?? 0.70 high-current forward voltage v dh ?0.70.8 vi vdd-hb = 100 ma ?? 1.0 dynamic resistance r d ?1.01.5 ? i vdd-hb = 100 ma ?? 2.0 lo gate driver low level output voltage v oll ? 0.18 0.3 vi lo = 160 ma ?? 0.4 high level output voltage v ohl ? 0.25 0.3 v i lo = ?100 ma, v ohl = v dd ? v lo ?? 0.45 peak sink current i ohl ?3?a v lo = 0v peak source current i oll ?2?a v lo = 12v note 1: specification for packaged product only. 2: all voltages relative to pin 7, v ss , unless otherwise specified. 3: guaranteed by design. not production tested.
? 2016 microchip technology inc. ds20005575a-page 5 MIC4102 ho gate driver low level output voltage v olh ?0.220.3 vi ho = 160 ma ?? 0.4 high level output voltage v ohh ?0.250.3 v i ho = ?100 ma, v ohh = v hb ? v ho ?? 0.45 peak sink current i ohh ?3?a v ho = 0v peak source current i olh ?2?a v ho = 12v switching specifications (anti-shoot-through circuitry) delay between pwm going high to lo going low t looff ?3045 ns ? ?? 60 voltage threshold for lo mosfet to be considered off v looff ?1.7? v ? delay between lo off to ho going high t hoon ?3050 ns ? ?? 60 delay between pwm going low to ho going low t hooff ?4565 ns ? ?? 70 switch node voltage threshold when ho turns off v swth 12.54 v ? delay between ho mosfet being considered off to lo turning on t loon ?3060 ns ? ?? 70 delay between ls going low and lo turning off t lsoff ?3645 ns c l = 1000 pf ?? 70 forced lo on, if v loth is not detected t swto 120 250 450 ns ? switching specifications either output rise time (3v to 9v) t r ?10?ns c l = 1000 pf either output fall time (3v to 9v) t f ?6?ns c l = 1000 pf either output rise time (3v to 9v) t r ?0.330.6 s c l = 0.1 f ?? 0.8 either output fall time (3v to 9v) t f ?0.20.3 s c l = 0.1 f ?? 0.4 minimum input pulse width that changes the output with ls = 5v t pw ?40 60 ns c l = 0, note 3 minimum output pulse width on ho with min pulse width on pwm with ls = 5v t pw ?15?ns c l = 0, note 3 table 1-1: electrical characteristics (continued) electrical characteristics: v dd = v hb = 12v; v ss = v hs = 0v; no load on lo or ho; t a = +25c; unless noted. bold values are valid for ?40c t j +125c. ( note 1 ) . parameters sym. min. ty p. max. units conditions note 1: specification for packaged product only. 2: all voltages relative to pin 7, v ss , unless otherwise specified. 3: guaranteed by design. not production tested.
MIC4102 ds20005575a-page 6 ? 2016 microchip technology inc. minimum input pulse width that changes the output with ls = 0v t pw ?13 20 ns c l = 0, note 3 minimum output pulse width on ho with min pulse width on pwm with ls = 0v ??20?? c l = 0, note 3 bootstrap diode turn-on or turn-off time t bs ?10?ns ? table 1-1: electrical characteristics (continued) electrical characteristics: v dd = v hb = 12v; v ss = v hs = 0v; no load on lo or ho; t a = +25c; unless noted. bold values are valid for ?40c t j +125c. ( note 1 ) . parameters sym. min. typ. max. units conditions note 1: specification for packaged product only. 2: all voltages relative to pin 7, v ss , unless otherwise specified. 3: guaranteed by design. not production tested.
? 2016 microchip technology inc. ds20005575a-page 7 MIC4102 temperature specifications parameters sym. min. typ. max. units conditions temperature ranges max. junction temperature range t j ?55 ? +150 c note 1 storage temperature range t s ?60 ? +150 c ? operating junction temperature range t j ?40 ? +125 c ? package thermal resistances thermal resistance, soic-8l ? ja ?140 ?c/w? note 1: the maximum allowable power dissipation is a functi on of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., t a , t j , ? ja ). exceeding the maximum allowable power dissipation will cause the dev ice operating junction te mperature to exceed the maximum +125c rating. sustained junction temperat ures above +125c can impa ct the device reliability.
MIC4102 ds20005575a-page 8 ? 2016 microchip technology inc. 2.0 typical performance curves figure 2-1: quiescent current vs. supply voltage. figure 2-2: quiescent current vs. temperature. figure 2-3: operating current vs. supply voltage. figure 2-4: supply current vs. supply voltage vs. ls level. figure 2-5: operating current vs. temperature. figure 2-6: supply current vs. frequency. note: the graphs and tables provided following this note ar e a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance char acteristics listed herein are not tested or guaranteed. in some graphs or t ables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range.
? 2016 microchip technology inc. ds20005575a-page 9 MIC4102 figure 2-7: supply current vs. frequency for pin l and h. figure 2-8: high level output voltage vs. temperature. figure 2-9: low level output of low-side driver vs. temperature. figure 2-10: low level output of low-side driver vs. temperature. figure 2-11: uvlo thresholds vs. temperature. figure 2-12: uvlo hysteresis vs. temperature.
MIC4102 ds20005575a-page 10 ? 2016 microchip technology inc. figure 2-13: bootstrap diode i-v characteristics. figure 2-14: bootstrap diode reverse current.
? 2016 microchip technology inc. ds20005575a-page 11 MIC4102 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . package type table 3-1: pin function table pin number pin name description 1v dd positive supply to lower gate drivers. decouple this pin to v ss (pin 7). bootstrap diode connected to hb (pin 2). 2 hb high-side bootstrap supply. external bootstrap capacitor is required. connect positive side of bootstrap capacitor to this pin. bootstrap diode is on-chip. 3 ho high-side output. connect to gate of high-side power mosfet. 4 hs high-side source connection. connect to source of high-side power mosfet. connect negative side of bootstrap capacitor to this pin. 5 pwm control input. pwm high signal makes high-side ho output high and low-side lo output low. pwm low signal makes high-si de ho output low and low-side lo output high. 6 ls low-side disable. when pulled low, this control signal immediately terminates the low-side lo output drive. the low-side lo out put drive will remain low until this signal is removed. hs drive is not affected by the ls signal. the logic table is below (see table 3-2 ). 7v ss chip negative supply. generally, this will be grounded. 8 lo low-side output. connect to gate of low-side power mosfet. MIC4102 soic-8l (m) (top view) 1 vdd hb ho hs 8lo vss ls pwm 7 6 5 2 3 4 table 3-2: ls pin logic table ls pwm lo ho 0000 0101 1010 1101
MIC4102 ds20005575a-page 12 ? 2016 microchip technology inc. 4.0 timing diagram figure 4-1: MIC4102 timing diagram. table 4-1: time points and actions for figure 4-1 time point action 1-2 pwm signal goes high. this initiates the lo signal to go low. the delay between pwm high to (v lo ? 10%) is typically 30 ns (t looff ). 2-4 lo goes low. when lo reaches 1.7v (v looff ) the low-side mosfet is deemed to be off. the high-side output ho then goes high. the delay between 3 and 4 is typically 30 ns (t hoon ); this allows for large turn off delay times of mosfets. 5-7 pwm goes low; ho goes lo w, typically within 45 ns, t hooff . the switch node (hs pin) is then monitored; when the switch node is v dd ? 2.5v (v swth ) the high-side mosfet is deemed to be off and the lo output goes high within typically 30 ns (t loon ). this is controlled by a one shot and remains high until pwm goes high. this is because it is possible to have the sw node oscillate, and could easily bounce through 10v le vel. if the lo high tran sition has not happened within 250 ns, it is forced to happen, unless the ls input is low. 8-10 if at any time after 7 has occurred and ls pin goes low, the lo output will turn off within 36 ns (v lsoff ). ho will remain off. the ls pin overrides all shoot-through control logic. if ls is low at the start of the next cycle when pwm signal goes high then ho shall switch transition 1-4 as normal. (i.e. pwm signal equals ho output, lo = 0v). t looff 30ns 60ns pwm ls switch node (hs pin) lo ho 1 2 3 v looff < 1.7v 4 5 6 7 v swth < (v dd ? 2.5v) 8 9 10 t hoon 30ns 60ns t hooff 45ns 70ns t loon 30ns 70ns t lsoff 36ns 70ns
? 2016 microchip technology inc. ds20005575a-page 13 MIC4102 5.0 functional description the MIC4102 is a high voltage, non-inverting, synchronous mosfet driver that uses a single pwm input signal to alternately drive both high-side and low-side n-channel mosfets. the functional block diagram of the MIC4102 is shown on page two. the MIC4102 input is ttl-compatible. the high-side output buffer includes a high speed level-shifting circuit that is referenced to the hs pin. an internal diode is used as part of a bootstrap circuit to provide the drive voltage for the high-side output. 5.1 startup and uvlo the uvlo circuit forces both driver outputs low until the supply voltage exceeds the uvlo threshold. the low-side uvlo circuit monitors the voltage between the v dd and v ss pins. the high-side uvlo circuit monitors the voltage between the hb and hs pins. hysteresis in the uvlo circuit prevents noise and finite circuit impedance from causing chatter during turn-on. the v dd pin voltage is supplied to the hs pin through the internal bootstrap diode. the hb pin voltage will always be a diode drop less than v dd . 5.2 input stage the MIC4102 utilizes a ttl-compatible input stage. the pwm input pin is referenced to the v ss pin. the voltage state of the input signal does not change the quiescent current draw of the driver. the threshold level is independent of the v dd supply voltage and there is no dependence between i vdd and the input signal amplitude. this f eature makes the MIC4102 an excellent level translator that will drive high threshold mosfets from a low voltage pwm ic. 5.3 low-side driver a block diagram of the low-side driver is shown in figure 5-1 . the low-side driver is designed to drive a ground (v ss pin) referenced n-channel mosfet. low driver impedances allow the external mosfet to be turned on and off quickly. the rail-to-rail drive capability of the output ensures a low r ds(on) from the external mosfet. a low level applied to pwm pin will cause the ho output to go low and the lo output to go high. the upper driver fet turns on and v dd is applied to the gate of the external mosfet. a high level on the pwm pin forces the lo output low by turning off the upper driver and turning on the lower driver which ground the gate of the external mosfet. pulling the ls pin low disables the lo pin. figure 5-1: low-side driver block diagram. 5.4 high-side driver and bootstrap circuit a block diagram of the high-side driver and bootstrap circuit is shown in figure 5-2 . this driver is designed to drive a floating n-channel mosfet, whose source terminal is referenc ed to the hs pin. figure 5-2: high-side driver block diagram. a low-power, high-speed, level-shifting circuit isolates the low-side (v ss pin) referenced circuitry from the high-side (hs pin) referenced driver. power to the high-side driver and uvlo circuit is supplied by the bootstrap circuit while the voltage level of the hs pin is shifted high. the bootstrap circuit consists of an internal diode and external capacitor, c b . in a typical application, such as the synchronous buck converter shown in figure 5-3 , the hs pin is at ground potential while the low-side mosfet is on. the internal diode allows capacitor c b to charge up to v dd ? v d during this time (where v d is the forward voltage drop of the internal diode). after the low-side mosfet is turned off and the ho pin turns on, the voltage across capacitor c b is applied to the v ss v dd lo external fet drive signal ls hs hb ho external fet v dd c b
MIC4102 ds20005575a-page 14 ? 2016 microchip technology inc. gate of the upper external mosfet. as the upper mosfet turns on, voltage on the hs pin rises with the source of the high-side mosfet until it reaches v in . as the hs and hb pin rise, the internal diode is reverse-biased, preventing capacitor c b from discharging. figure 5-3: high-side driver and bootstrap circuit. hs hb ho c b lo level shift pwm v ss v in v out c out l out c vdd q1 q2 q ff _ q v dd v dd
? 2016 microchip technology inc. ds20005575a-page 15 MIC4102 6.0 application information 6.1 power dissipation considerations power dissipation in the driver can be separated into three areas: ? internal diode dissipation in the bootstrap circuit ? internal driver dissipation ? quiescent current dissipation used to supply the internal logic and control functions. 6.2 bootstrap circuit power dissipation power dissipation of the internal bootstrap diode primarily comes from the average charging current of the c b capacitor times the forward voltage drop of the diode. secondary sources of diode power dissipation are the reverse leakage current and reverse recovery effects of the diode. the average current drawn by repeated charging of the high-side mosfet is calculated by: equation 6-1: the average power dissipated by the forward voltage drop of the diode equals: equation 6-2: the value of v f should be taken at the peak current through the diode. however, this current is difficult to calculate because of differences in source impedances. the peak current can either be measured or the value of v f at the average current can be used and will yield a good approximation of diode power dissipation. the reverse leakage current of the internal bootstrap diode is typically 11 a at a reverse voltage of 100v and 125c. power dissipation due to reverse leakage is typically much less than 1 mw and can be ignored. reverse recovery time is the time required for the injected minority carriers to be swept away from the depletion region during turn-off of the diode. power dissipation due to reverse recovery can be calculated by computing the average reverse current due to reverse recovery charge multiplied by the reverse voltage across the diode. the average reverse current and power dissipation due to reverse recovery can be estimated by: equation 6-3: equation 6-4: the total diode power dissipation is: equation 6-5: an optional external bootstrap diode may be used instead of the internal diode ( figure 6-1 ). an external diode may be useful if high gate charge mosfets are being driven and the power dissipation of the internal diode is contributing to excessive die temperatures. the voltage drop of the external diode must be less than the internal diode for this option to work. the reverse voltage across the diode will be equal to the input voltage minus the v dd supply voltage. a 100v schottky diode will work for most 72v input telecom applications. the equations above can be used to calculate power dissipation in the external diode. however, if the external diode has significant reverse leakage current, the power dissipated in that diode due to reverse leakage can be calculated as: equation 6-6: i fave ?? q gate f s ? = where: q gate total gate charge at v hb f s gate drive switching frequency pdiode fwd i fave ?? v f ? = where: v f diode forward voltage drop i rr ave ?? 2 i rrm ? t rr ? f s ? = where: i rrm peak reverse recovery current t rr reverse recovery time pdiode rr i rr ave ?? v rev ? = pdiode total pdiode fwd pdiode rr + = pdiode rev i r v rev ? 1 d ? ?? ? = where: i r reverse current flow at v rev & t j v rev diode reverse voltage d duty cycle = t on /f s f s switching freq. of power supply
MIC4102 ds20005575a-page 16 ? 2016 microchip technology inc. the on-time is the time the high-side switch is conducting. in most power supply topologies, the diode is reverse-biased during th e switching cycle off-time. figure 6-1: optional bootstrap diode. 6.3 gate drive power dissipation power dissipation in the output driver stage is mainly caused by charging and discharging the gate to source and gate to drain capacitanc e of the external mosfet. figure 6-2 shows a simplified equivalent circuit of the MIC4102 driving an external high-side mosfet. figure 6-2: MIC4102 driving an external mosfet. 6.4 dissipation during the external mosfet turn-on energy from capacitor c b is used to charge up the input capacitance of the mosfet (c gd and c gs ). the energy delivered to the mosfet is dissipated in the three resistive components, r on , r g , and r g_fet . r on is the on resistance of the upper driver mosfet in the MIC4102. r g is the series resistor (if any) between the driver ic and the mosfet. r g_fet is the gate resistance of the mosfet. r g_fet is usually listed in the power mosfet?s specifications. the esr of capacitor c b and the resistance of the connecting etch can be ignored because they are much less than r on and r g_fet . the effective capacitance of c gd and c gs is difficult to calculate because they vary non-linearly with i d , v gs , and v ds . fortunately, most power mosfet specifications include a typical graph of total gate charge vs. v gs . figure 6-3 shows a typical gate charge curve for an arbitrary power mosfet. this chart shows that for a gate voltage of 10v, the mosfet requires about 23.5 nc of charge. the energy dissipated by the resistive components of the gate drive circuit during turn-on is calculated as: equation 6-7: but equation 6-8: so equation 6-9: figure 6-3: typical gate charge vs. v gs . c b v in external diode hs hb ho v dd lo level shift pwm v ss q ff _ q hs hb ho external fet v dd c b r g r g_fet r on r off c gd c gs e 1 2 -- - c iss ? v gs 2 ? = where: c iss total gate capacitance of mosfet qcv ? = e 1 2 -- - q g ? v gs ? =
? 2016 microchip technology inc. ds20005575a-page 17 MIC4102 the same energy is dissipated by r off , r g , and r g_fet when the driver ic turns the mosfet off. equation 6-10: and equation 6-11: the power dissipated inside the MIC4102 equals the ratio of r on and r off to the external resistive losses in r g and r g_fet . the power dissipated in the MIC4102 due to driving the external mosfet is: equation 6-12: 6.5 supply current power dissipation power is dissipated in the MIC4102 even if there is nothing being driven. the supply current is drawn by the bias for the internal circuitry, the level shifting circuitry, and shoot-through current in the output drivers. the supply current is proportional to operating frequency and the v dd and v hb voltages. the typical characteristic graphs show how supply current varies with switching frequency and supply voltage. the power dissipated by the MIC4102 due to supply current is: equation 6-13: 6.6 total power dissipation and thermal considerations total power dissipation in the MIC4102 equals the power dissipation caused by driving the external mosfets, the supply current, and the internal bootstrap diode. equation 6-14: the die temperature may be calculated once the total power dissipation is known. equation 6-15: 6.7 anti-shoot-through, propagation delay, and other timing considerations the block diagram on page two illustrates how the MIC4102 drives the power stage of a synchronous buck converter. it is important that only one of the two mosfets is on at any given time. if both mosfets are simultaneously on, they will short v in to ground, causing high current from the v in supply to ?shoot through? the mosfets and into ground. excessive shoot-through causes higher power dissipation in the mosfets, voltage spikes, and ringing in the circuit. the high current and voltage ringing generate conducted and radiated emi. minimizing shoot-through can be done passively, actively, or though a combination of both. passive shoot-through protection uses delays between the high and low gate drivers to prevent both mosfets from being on at the same time. these delays can be adjusted for different applications. although simple, the e driver 1 2 -- - q g ? v gs ? = where: e driver energy dissipated during turn-on or turn-off p driver 1 2 -- - q g ? v gs ? f s ? = where: p driver power dissipated during turn-on or turn-off q g total gate charge at v gs v gs gate-to-source voltage on the mosfet f s switching frequency of the gate drive circuit pdiss drive p driver r on r on r g r g _fet ++ ------------------------------------------------ - p driver r off r off r g r g _fet ++ --------------------------------------------------- - ? + ? = pdiss supply v dd i dd ? v hb + i hb ? = pdiss total pdiss supply pdiss drive pdiode total ++ = t j t a pdiss total + ? ja ? = where: t j junction temperature t a maximum ambient temperature pdiss total power dissipation of the MIC4102 ja thermal resistance from junction to ambient air
MIC4102 ds20005575a-page 18 ? 2016 microchip technology inc. disadvantage of this approach is the long delays required to account for process and temperature variations in the mosfet and the mosfet driver. active shoot-though monitors voltages on the gate drive outputs and switch node to determine when to switch the mosfets on and off. this active approach adjusts the delays to account for some of the variations, but it also has its disadvantages. high currents and fast switching voltages in the gate drive and return paths can cause parasitic ringing that may turn the mosfets back on even though the gate driver output is low. another disadvantage is that the driver cannot monitor the gate voltage inside the mosfet. figure 6-4 shows an equivalent circuit, including parasitics, of the gate driver section. the internal gate resistance (r g_gate ) and any external damping resistor (r g ) isolate the mosfet?s gate from the driver output. there is a delay between when the driver output goes low and the mosfet turns off. this turn-off delay is usually specified in the mosfet data sheet. this delay increases when an external damping resistor is used. figure 6-4: gate drive circuit with parasitics. the MIC4102 uses a combin ation of active sensing and passive delay to ensure that both mosfets are not on at the same time a nd to minimize shoot-through current. the timing diagram helps illustrate how the anti-shoot-through circuitry works. a high level on the pwm pin causes the lo pin to go low. the MIC4102 monitors the lo pin voltage and prevents the ho pin from turning on until the voltage on the lo pin reaches the v looff threshold. after a short delay, the MIC4102 drives the ho pin high. monitoring the lo voltage eliminates any excessive delay due to the mosfet drivers turn-off time and the short delay accounts for the mosfet turn-off delay as well as letting the lo pin voltage settle out. an external resistor between the lo output and the mosfet may affect the performance of the lo pin monitoring circuit and is not recommended. a low on the pwm pin causes the ho pin to go low after a short delay (t hooff ). before the lo pin can go high, the voltage on the switching node (hs pin) must have dropped to 2.5v below the v dd voltage. monitoring the switch voltage instead of th e ho pin voltage eliminates timing variations and excessive delays due to the high side mosfet turn-off. the lo driver turns on after a short delay (t loon ). once the lo driver is turned on, it is latched on until the pwm signal goes high. this prevents any ringing or oscillations on the switch node or hs pin from turning off the lo driver. if the pwm pin goes low and the voltage on the hs pin does not cross the v swth threshold, the lo pin will be forced high after a short delay (t swto ), ensuring proper operation. fast propagation delay between the input and output drive waveform is desirable. it improves overcurrent protection by decreasing the response time between the control signal and the mosfet gate drive. minimizing propagation delay also minimizes phase shift errors in power supplies with wide bandwidth control loops. care must be taken to ensure the input signal pulse width is greater than the minimum specified pulse width. an input signal that is less than the minimum pulse width may result in no output pulse or an output pulse whose width is signif icantly less than the input. the maximum duty cycle (ratio of high-side on-time to switching period) is determin ed by the time required for the c b capacitor to charge during the off-time. adequate time must be allowed for the c b capacitor to charge up before the high-side driver is turned back on. the anti-shoot-through circuit in the MIC4102 prevents the driver from turning both mosfets on at the same time; however, other factors outside of the anti-shoot-through circuit?s control can cause shoot-through. some of these include ringing on the gate drive node and capacitive coupling of the switching node voltage on the gate of the low-side mosfet. 6.8 decoupling and bootstrap capacitor selection decoupling capacitors are required for both the low-side (v dd ) and high-side (hb) supply pins. these capacitors supply the charge necessary to drive the external mosfets as well as minimize the voltage ripple on these pins. the capacitor from hb to hs serves double duty by providing decoupling for the high-side circuitry as well as providing current to the high-side circuit while the high-side external mosfet is on. ceramic capacitors are recommended because of their low impedance and small size. z5u type ceramic capacitor dielectrics are not recommended due to the large change in capacitance over hs hb ho hs fet v dd r g r g_fet r on r off c gd c gs lo r g_fet c gd c gs v in ls fet r on r off v ss switching node
? 2016 microchip technology inc. ds20005575a-page 19 MIC4102 temperature and voltage. a minimum value of 0.1 f is required for each of the capacitors, regardless of the mosfets being driven. larger mosfets may require larger capacitance values for proper operation. the voltage rating of the capacitors depends on the supply voltage, ambient temperature, and the voltage derating used for reliability. 25v rated x5r or x7r ceramic capacitors are recommended for most applications. the minimum capacitance value should be increased if low voltage capacitors are used because even good quality dielectric capacitors, such as x5r, will lose 40% to 70% of their capacitance value at the rated voltage. placement of the decoupling capacitors is critical. the bypass capacitor for v dd should be placed as close as possible between the v dd and v ss pins. the bypass capacitor (c b ) for the hb supply pin must be located as close as possible between the hb and hs pins. the etch connections must be short, wide, and direct. the use of a ground plane to minimize connection impedance is recommended. refer to the section on layout and component placement for more information. the voltage on the bootstrap capacitor drops each time it delivers charge to turn on the mosfet. the voltage drop depends on the gate charge required by the mosfet. most mosfet spec ifications specify gate charge vs. v gs voltage. based on this information and a recommended ? v hb of less than 0.1v, the minimum value of bootstrap capacitance is calculated as: equation 6-16: the decoupling capacitor for the v dd input may be calculated in with the same formula; however, the two capacitors are usually equal in value. 6.9 grounding, component placement, and circuit layout nanosecond switching speeds and ampere peak currents in and around the MIC4102 driver require proper placement and trace routing of all components. improper placement may cause degraded noise immunity, false switching, excessive ringing, or circuit latch-up. figure 6-5 shows the critical current paths when the driver outputs go high and turn on the external mosfets. it also shows the need for a low impedance ground plane. the charge needed to turn-on the mosfet gates comes from the decoupling capacitors c vdd and c b . current in the low-side gate driver flows from c vdd through the internal driver, into the mosfet gate, and out the source. the return connection back to the decoupling capacitor is made through the ground plane. any inductance or resistance in the ground return path causes a voltage spike or ringing to appear on the source of the mosfet. this voltage works against the gate voltage and can either slow down or turn off the mosfet during the period where it should be turned on. current in the high-side driver is sourced from capacitor c b , flows into the hb pin, and out the ho pin, into the gate of the high-side mosfet. the return path for the current is from the source of the mosfet and back to capacitor c b . the high-side circuit return path usually does not have a low impedance ground plane, so the etch connections in th is critical path should be short and wide to minimize parasitic inductance. as with the low-side circuit, impedance between the mosfet source and the decoupling capacitor causes negative voltage feedback that fights the turn-on of the mosfet. it is important to note that capacitor c b must be placed close to the hb and hs pins. this capacitor not only provides all the energy for tu rn-on, but it must also keep hb pin noise and ripple low for proper operation of the high-side drive circuitry. figure 6-5: turn-on current paths. figure 6-6 shows the critical current paths when the driver outputs go low and turn off the external mosfets. short, low impedance connections are important during turn-off for the same reasons given in the turn-on explanation. cu rrent flowing through the internal diode replenishes charge in the bootstrap capacitor, c b . c b q g v hb ? ------------- - ? where: q g total gate charge at v hb ? v hb voltage drop at the hb pin hs hb ho v dd c b ls pwm v ss lo c vdd gnd plane gnd plane low-side drive turn-on current path high-side drive turn-on current path level shift _ q ff q
MIC4102 ds20005575a-page 20 ? 2016 microchip technology inc. figure 6-6: turn-off current paths. the following circuit guidelines should be adhered to for optimum circuit performance: ?the v dd and hb bypass capacitors must be placed close to the supply and ground pins. it is critical that the etch length between the high side decoupling capacitor (c b ) and the hb and hs pins be minimized to reduce lead inductance. ? a ground plane should be used to minimize parasitic inductance and impedance of the return paths. the MIC4102 is capable of greater than 3a peak currents. any impedance between the MIC4102, the decoupling capacitors, and the external mosfet will degrade the performance of the driver. ? trace out the high d i /d t and d v /d t paths, as shown in figure 6-5 and figure 6-6 to minimize the etch length and loop area for these connections. minimizing these parameters decreases the parasitic inductance and the radiated emi generated by fast rise and fall times. a typical layout of a synchronous buck converter power stage using the MIC4102 ( figure 6-7 ) is shown in figure 6-8 . figure 6-7: typical converter power stage. figure 6-8: typical layout of a synchronous buck converter power stage. the circuit is configured as a synchronous buck power stage. the high-side mosfet drain connects to the input supply voltage (drain) and the source connects to the switching node. the low-side mosfet drain connects to the switching node and its source is connected to ground. the buck converter output inductor (not shown) would connect to the switching node. the high-side drive trace, ho, is routed on top of its return trace, hs, to minimize loop area and parasitic inductance. the lo w-side drive trace, lo, is routed over the ground plane and minimizes the impedance of that current path. the decoupling capacitors, c b and c vdd , are placed to minimize etch length between the capacitors and their respective pins. this close placement is necessary to efficiently charge capacitor c b when the hs node is low. all traces are 0.025? wide or greater to reduce impedance. c in is used to decouple the high current path through the mosfets. hs hb ho v dd c b level shift ls pwm v ss lo c vdd low-side drive turn-off current path high-side drive turn-off current path charge c b through internal diode when hs pin is low _ q ff q v v v v v hs hb ho v dd c b lo level shift pwm v ss v in c in c vdd high-side fet low-side fet q ff _ q v dd hs (switch node)
? 2016 microchip technology inc. ds20005575a-page 21 MIC4102 7.0 packaging information 7.1 package marking information xxx xxxxxx yyww 8-lead soic* mic 4102ym 1613 example legend: xx...x product code or cust omer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb -free jedec designator ( ) can be found on the outer packaging for this package. , , pin one index is identified by a dot, delta up, or delta down (triangle mark). note : in the event the full microchip part numbe r cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for customer-specific informa tion. package may or may not include the corporate logo. underbar (_) symbol may not be to scale. 3 e 3 e
MIC4102 ds20005575a-page 22 ? 2016 microchip technology inc. 8-lead soic package outline and recommended land pattern note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging
? 2016 microchip technology inc. ds20005575a-page 23 MIC4102 appendix a: revision history revision a (june 2016) ? converted micrel docu ment MIC4102 to micro- chip data sheet ds20005575a. ? minor text changes throughout.
MIC4102 ds20005575a-page 24 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005575a-page 25 MIC4102 product identification system to order or obtain information, e.g., on pricing or delivery, contact your local microchip representative or sales office . examples: a) MIC4102ym: 100v half-bridge mos- fet driver with anti- shoot-through protection, ?40c to +125c temp. range, soic-8l package, 95/tube b) MIC4102ym-tr: 100v half-bridge mos- fet driver with anti- shoot-through protec- tion, ?40c to +125c temp. range, soic-8l package, 2,500/reel part no. x package device device: MIC4102: 100v half-bridge mosfet driver with anti-shoot-through protection temperature: y = ?40c to +125c package: m= soic-8l media type: (blank) = 95/tube tr = 2,500/reel x temperature xx media type
MIC4102 ds20005575a-page 26 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005575a-page 27 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microc hip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered tradem arks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0717-1 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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