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revision history 1gb sdram-as4c64m16d1a - 66pin tsop ii package revision details date rev 1.0 preliminary datasheet oct 2015 alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 1/62 - rev. 1.0 oct.2015
overview the 1gb ddr sdram is a high-s peed cmos double data rate synchronous dram containing 1024 mbits. it is internally configured as a quad 16m x 16 dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, ck). data outputs occur at both rising edges of ck and ck . read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locatio ns in a programmed sequence. accesses begin with the registration of a bankactivate command which is then followed by a read or write command. the device provides programmable read or write burst lengths of 2, 4, or 8. an auto precharge function may be ena bled to provide a self -t imed row precharge that is initiated at the end of the burst sequence. the refresh functions, either auto or self refresh are easy to use. in addition, 1gb ddr features programmable dll option. by having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. these devices are well suited for applications requiring high memory bandwidth; result in a device particularly well suited to high performance main memory and graphics applications. features fast clock rate: 166mhz differential clock ck & ck bi - directional dqs dll ena ble/disable by emrs fully synchronous operation internal pipeline architecture four internal banks, 16m x 16 - bit for each bank programmable mode and extended mode registers - cas latency: 2, 2.5, 3 - burst length: 2, 4, 8 - burst type: sequential & interleaved individual byte write mask control dm wr ite latency = 0 auto refresh and self refresh 8192 refresh cycles / 64ms precharge & active power down power supplie s: v dd & v ddq = 2.5v 0.2v industrial operating temperature: t a = -4 0~85? interface: sstl_2 i/o interface package: 66 pin tsop ii, 0.65mm pin pitch - pb and halogen free table 1. ordering information product part no org temperature max clock (mhz) as4c64m 16d1a-6tcn commercial 0c to 85c package 66 pin tsopii AS4C64M16D1A-6TIN industrial -40c to 85c 66 pin tsopii 64 x 16 64 x 16 166mhz 166mhz AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 2/62 - rev. 1.0 oct.2015
figure 1. pin assignment (top view) vssq 1 66 vdd vss 2 65 dq0 dq15 3 64 vddq vssq 4 63 dq1 dq14 5 62 dq2 dq13 6 61 vssq vddq 7 60 dq3 dq12 8 59 dq4 dq11 9 58 vddq vssq 10 57 dq5 dq10 11 56 dq6 dq9 12 55 vssq vddq 13 54 dq7 dq8 14 53 nc nc 15 52 vddq 16 51 ldqs udqs 18 49 vdd vref 19 48 nc vss 20 47 ldm udm 22 45 cas ck 23 44 ras cke 24 43 cs nc 25 42 nc a12 26 41 ba0 a11 27 40 ba1 a9 28 39 a10/ap a8 29 38 a0 a7 17 50 a13 nc 21 46 we ck 31 36 a2 a5 32 35 a3 a4 33 34 vdd vss 30 37 a1 a6 AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 3/62 - rev. 1.0 oct.2015
figure 2. block diagram ck cke cs ras cas we dll clock buffer command decoder column counter control signal generator address buffer refresh counter 16m x 16 cell array (bank #0) row decoder 16m x 16 cell array (bank #1) row decoder 16m x 16 cell array (bank #2) row decoder 16m x 16 cell array (bank #3) row decoder column decoder column decoder column decoder column decoder mode register a10/ap a0-a9 a11-a13 ba0 ba1 ck data strobe buffer ldqs udqs dq buffer ldm udm dq15 dq0 ~ AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 4/62 - rev. 1.0 oct.2015
table 2. pin details symbol type description ck, ck input differential clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . input and output data is referenced to the crossing of ck and ck (both directions of the crossing) cke input clock enable: cke activates (high) and deactivates (low) the ck signal. if cke goes low synchronously with clock, the internal clock is s uspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. ba 0, b a1 input bank activate : ba 0 and b a 1 define to which bank the bankactivate, read, write, or bankprecharge command is being applied. a0 - a1 3 input address inputs: a0 - a1 3 are sampled during the bankactivate command (row address a0 - a1 3 ) and read/write command (column address a0 -a9 with a10 defining aut o precharge). cs input chip select: cs enables (sampled low) and disables (sampled high) the command decoder. all commands are masked when cs is sampled high. cs provides for external bank selection on systems with multiple banks. it is considered part of the command code. ras input row address strobe: the ras signal defines the operation commands in conjunction with the cas and we signals and is latched at the positive edges of ck. when ras and cs are asserted "low" and cas is asserted "high," either the bankactivate command or the precharge command is selected by the we signal. when the we is asserted "high," the bankactivate command is selected and the ban k designated by b a is turned on to the active state. when the we is asserted "low," the precharge command is selected and the bank designated by b a is switched to the idle state after the precharge operation. cas input column address strobe: the cas signal defines the operation commands in conjunction with the ras and we signals and is latched at the positive edges of ck. when ras is held "high" and cs is asserted "low," the column access is started by asserting cas "low." then, the read or write command is selected by asserting we "high" or ?ow . we input write enable: the we signal defines the operation commands in conjunction with the ras and cas signals and is latched at the positive edges of ck. the we input is used to select the bankactivate or precharge command and read or write command. ldqs, udqs input / output bidirectional data strobe: specifies timing for input and output data. read data strobe is edge triggered. write data strobe provides a setup and hold time for data and dqm. ldqs is for dq0~7, udqs is for dq8~15. ldm, udm input data input mask: input data is masked when dm is sampled high during a write cycle. ldm masks dq0 - dq7, udm masks dq8 - dq15. dq0 - dq15 input / output data i/o: the dq0 - dq15 input and output data are synchronized with positive and negative edges of ldqs and udqs. the i/os are byte - maskable during writes . v dd supply power supply: 2.5v 0.2v . v ss supply ground v ddq supply dq p ower: 2.5v 0.2v . provide isolated power to dqs for improved noise immunity. v ssq supply dq ground: provide isolated ground to dqs for improved noise immunity. v ref supply reference voltage for inputs: +0.5*v ddq nc - no connect: these pins should be l eft unconnected. pin descriptions AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 5/62 - rev. 1.0 oct.2015
operation mode table 3 shows the truth table for the operation commands. table 3. truth table (note (1), (2)) command state cke n-1 cke n dm ba 0,1 a 10 a 0- 9, 11 -13 cs ras cas we bankactivate idle (3) h x x v row address l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write active (3) h x x v l column address (a0 ~ a 9) l h l l write and autoprecharge active (3) h x x v h l h l l read active (3) h x x v l column address (a0 ~ a 9) l h l h read and autoprecharge active (3) h x x v h l h l h ( extended ) mode register set idle h x x op code l l l l no - operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x autorefresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x (selfrefresh) l h h h precharge power down mode entry idle h l x x x x h x x x l h h h precharge power down mode exit any l h x x x x h x x x (powerdown) l h h h active power down mode entry active h l x x x x h x x x l v v v active power do wn mode exit any l h x x x x h x x x (powerdown) l h h h data in put mask disable active h x l x x x x x x x data input mask enable (5) active h x h x x x x x x x note: 1. v=valid data, x=don't care, l=low level, h=high level 2. cke n signal is i nput level when commands are provided. cke n-1 signal is input level one clock cycle before the commands are provided. 3. these are states of bank designated by b a signal. 4. device state is 2, 4, and 8 burst operation. 5. ldm and udm can be enable d respect ively. AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 6/62 - rev. 1.0 oct.2015
mode register set (mrs) the mode register stores the data for controlling various operating modes of a ddr sdram. it programs cas latency, burst type, and burst length to make the ddr sdram useful for a variety of applications. the default v alue of the mode register is not defined; therefore the mode register must be written by the user. values stored in the register will be retained until the register is reprogrammed. the mode register is written by asserting low on cs , ras , cas , we , ba1 and ba0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and cke should be high). the state of address pins a0~a1 3 and ba0, ba1 in the same cycle in which cs , ras , cas and we are asserted low is written into the mode register. a minimum of two clock cycles, tmr d, are required to complete the write operation in the mode register. the mode register is divided into various fields depending on functionality. the burst length uses a0~a2, burst type uses a3, and cas latency (read latency from column address) uses a4~a 6. a logic 0 should be programmed to all the undefined addresses to ensure future compatibility. reserved states should not be used to avoid unknown device operation or incompatibility with future versions. refer to the table for specific codes for various burst lengths, burst types and cas latencies . table 4. mode register bitmap b a1 b a0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 0 rfu must be set to 0 t.m. cas latency bt burst length mode register a8 a7 test mode a6 a5 a4 cas latency a3 burst type a2 a1 a0 burst length 0 0 normal mode 0 0 0 reserved 0 sequential 0 0 0 reserved 1 0 dll reset 0 0 1 reserved 1 interleave 0 0 1 2 x 1 test mode 0 1 0 2 0 1 0 4 0 1 1 3 0 1 1 8 ba0 mode 1 0 0 reserved 1 0 0 reserved 0 mrs 1 0 1 reserved 1 0 1 reserved 1 emrs 1 1 0 2.5 1 1 0 reserved 1 1 1 reserved 1 1 1 reserved burst length field (a2~a0) this field specifies the data length of column access using the a2~a0 pins and selects the burst length to be 2, 4, 8. table 5. burst length a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 7/62 - rev. 1.0 oct.2015
addressing mode select field (a3) the addressing mode can be one of two modes, either interleave mode or sequential mode. both sequential mode and interleave mode support burst length of 2, 4 and 8. table 6 . addressing mode a3 addressing mode 0 sequential 1 interleave burst definition, addressing sequence of sequential and interleave mode table 7. burst address ordering burst length start address sequential interleave a2 a1 a0 2 x x 0 0, 1 0, 1 x x 1 1, 0 1, 0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 cas latency field (a6~a4) this field specifies the number of clock cycles from the assertion of the read command to the first read data. the minimum whole value of cas latency depends on the frequency of ck. the minimum whole value satisfying the following formula must be programmed into this field. t cac (min) cas latency x t ck table 8. cas latency a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 reserved 1 0 1 reserved 1 1 0 2.5 clocks 1 1 1 reserved test mode field (a8~a7) these two bits are used to enter the test mode and must be programmed to "00" in normal operation. table 9. test mode a8 a7 test mode 0 0 normal mode 1 0 dll reset ( b a 0, b a 1) AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 8/62 - rev. 1.0 oct.2015
table 10. mrs/emrs ba1 ba0 a13 ~ a0 rfu 0 mrs cycle rfu 1 extended functions (emrs) extended mode register set (emrs) the extended mod e register set stores the data for enabling or disabling dll and selecting output driver strength. the default value of the extended mode register is not defined, therefore must be written after power up for proper operation. the extened mode register is w ritten by asserting low on cs , ras , cas , we , ba1 and ba0 (the device should have all banks idle with no bursts in progress prior to writing into the mode regi ster, and cke should be high) . the state of a0 ~ a1 3 , b a 0 and b a 1 is written in the mode register in the same cycle as cs , ras , cas , and we going low . the ddr s dram should be in a ll bank precharge with cke already high prior to writing into the extended mode register. a1 is used for setting driver strength to normal, or weak. two clock cycles are required to complete the write operation in the extended mode regis ter. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. a0 is used for dll enable or disable. "high" on b a 0 is used for emrs. refer to the table for spe cific codes. table 11. extended mode register bitmap b a1 b a0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 rfu must be set to 0 ds1 rfu must be set to 0 ds0 dll extended mode register ba0 mode a6 a1 drive strength comment a0 dll 0 mrs 0 0 full 0 enable 1 emrs 0 1 weak 1 disable 1 0 rfu reserved for future 1 1 matched impedance output driver matches impedance AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 9/62 - rev. 1.0 oct.2015
table 1 2. absolute maximum rating symbo l item values unit v i /o voltage on i/o pins relative to vss - 0. 5 ~ v ddq + 0. 5 v v dd , v ddq voltage on v dd , v ddq supply relative to vss - 1 ~ 3.6 v v in voltage on inputs relative to vss - 1 ~ 3.6 v t a ambient temperature -4 0 ~ + 85 c t stg storage temperature - 5 5 ~ +150 c t solder soldering temperature 2 60 c p d power dissipation 1 .3 w i os short circuit output current 50 ma note: absolute maximum dc requirements contain stress ratings only. functional operation at the absolute maximum limits is not implied or guaranteed. extended exposure to maximum ratings may affect device reliability. table 1 3. recommended d.c. operating conditions (v dd = 2.5 v 0.2v , t a = -40 ~ 85 c) symbol para meter min. max. unit v dd power supply voltage 2.3 2.7 v v ddq power supply voltage (for i/o buffer) 2.3 2.7 v v ref input reference voltage 0.49*v ddq 0.51* v ddq v v ih (dc) input high voltage (dc) v ref + 0.15 v ddq + 0.3 v v il (dc) input low voltage (dc) - 0.3 v ref 0.15 v v tt termination voltage v ref - 0.04 v ref + 0.04 v v in (dc) input voltage level, ck and ck inputs - 0.3 v ddq + 0.3 v v id (dc) input different voltage, ck and ck inputs 0.36 v ddq + 0.6 v i i input leakage current -2 2 a i oz output leakage current -5 5 a i oh output high current (v oh = 1.95v) - 16.2 - ma i ol output low current (v ol = 0.35v) 16.2 - ma note : all voltages are referenced to v ss . table 14. capacitance (v dd = 2. 5 v, f = 1mhz , t a = 25 c) symbol parameter min. max. delta unit c in 1 input capacitance (ck, ck ) 3.5 4.5 0.5 pf c in 2 input capacitance ( all other input - only pins ) 3.5 4.5 0.5 pf c i/o dq, dqs , dm input/output capacitance 4 5 0.5 pf note: th ese parameters are guaranteed by design, periodically sampled and are not 100% tested AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 10/62 - rev. 1.0 oct.2015
table 15. d.c. characteristics (v dd = 2.5 v 0.2v , t a = -40 ~ 85 c) parameter & test condition symbol -6 unit note max . operating current: one bank; active - precharge; t rc =t rc (min); t ck =t ck (min); dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. idd0 160 ma operating current : one bank; bl=4; reads - refer to the following page for detai led test conditions idd1 180 ma precharge power - down standby current: all banks idle; power - down mode; t ck =t ck (min); cke = low idd2p 10 ma p recharge floating standby current: cs = high ; all banks idle; cke = high ; t ck =t ck (min) ; address and o ther control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm idd2f 70 ma p recharge quiet standby current: cs =high ; all banks idle; cke =high ; t ck =t ck (min) address and other control inputs stable at v ih (min) or v il (max); v in = v ref for dq, dqs and dm idd2q 70 ma active power - down standby current : one bank active; power - down mode; cke=low; t ck =t ck (min) idd3p 40 ma active standby current : cs =high;cke=high; o ne bank active ; t rc =t rc (max);t ck =t ck (min);address and control inputs changing once per clock cycle; dq,dqs,and dm inputs changing twice per clock cycle idd3n 130 ma operating current burst read : bl=2; reads; continuous burst; one bank active; addre ss and control inputs changing once per clock cycle; t ck =t ck (min); lout=0ma;50% of data changing on every transfer idd4r 260 ma operating current burst write : bl=2; writes; continuous burst ;one bank active; a ddress and control inputs changing once per clock cycle; t ck =t ck (min); dq,dqs,and dm changing twice per clock cycle; 50% of data changing on every transfer idd4w 260 ma auto refresh current : t rc =t rfc (min); t ck =t ck (min) idd5 280 ma self refresh current: self refresh mode ; cke Q 0.2v; t ck =t ck (min) idd6 12 ma 1 burst operating current 4 bank operation: four bank interleaving reads; bl=4;with auto precharge; t rc =t rc (min); t ck =t ck (min); address and control inputs chang e only during active, read , or write command idd7 420 ma AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 11/62 - rev. 1.0 oct.2015
table 1 6. electrical characteristics and recommended a.c.operating condition (v dd = 2.5 v 0.2v , t a = -40 ~ 85 c) symbol parameter - 6 unit note min. max. t ck clock cycle time cl = 2 7.5 12 ns cl = 2.5 6 12 ns cl = 3 5 12 ns t ch clock high level width 0.45 0.55 t ck t cl clock low level width 0.45 0.55 t ck t hp clock half period t clmin or t chmin - ns 2 t hz data - out - high impedance time from ck, ck - 0.7 ns 3 t lz data - out - low impedance time from ck, ck - 0.7 0.7 ns 3 t dqsck dqs- out access time from ck, ck - 0. 6 0. 6 ns t ac output access time from ck, ck - 0.7 0.7 ns t dqsq dqs- dq skew - 0.4 ns t rpre read preamble 0.9 1.1 t ck t rpst read postamble 0.4 0.6 t ck t dqss ck to valid dqs - in 0.72 1.2 5 t ck t wpres dqs- in setup time 0 - ns 4 t wpre dqs write pream ble 0. 25 - t ck t wpst dqs write postamble 0.4 0.6 t ck 5 t dqsh dqs in high level pulse width 0.35 - t ck t dqsl dqs in low level pulse width 0.35 - t ck t is address and control input setup time 0. 7 - ns 6 t ih address a nd control input hold time 0. 7 - ns 6 t ds dq & dm setup time to dqs 0.4 - ns t dh dq & dm hold time to dqs 0.4 - ns t qh dq/dqs output hold time from dqs t hp - t qhs - ns t rc row cycle time 55 - ns t rfc refresh row cycle time 70 - ns t ras row active time 40 7 0k ns t rcd active to read or write delay 15 - ns t rp row precharge time 15 - ns t rrd row active to row active delay 10 - ns t wr write recovery time 15 - ns t w tr intern al write to read command delay 2 - t ck t mrd mode register set cycle time 10 - ns t ref i average periodic refresh interval - 7.8 s 7 t xsrd self refresh exit to read command delay 200 - t ck t xsnr self refresh exit to non - read com mand delay 75 - ns t d al auto precharge write recovery + precharge time t wr +t rp - ns t dipw dq and dm input puls e width 1.75 - ns t ipw co ntrol and address input pulse width 2.2 - ns t qhs data hold skew factor - 0.5 ns t dss dq s falling edge to ck setup time 0.2 - t ck t dsh dq s falling edge hold time from ck 0.2 - t ck t rap active to autoprecharge delay t rcd or t rasmin - ns AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 12/62 - rev. 1.0 oct.2015
table 1 7. recommended a.c. operating conditions (v dd = 2.5 v 0.2v , t a = -40 ~ 85 c) symbol parameter min. max. unit v ih ( ac ) input high voltage ( a c) v ref + 0. 31 - v v il ( ac ) input low voltage ( a c) - v ref 0.31 v v id (a c) input different voltage, ck and ck inputs 0.7 v ddq + 0.6 v v ix (a c) input crossing point voltage, ck and ck inputs 0.5* v ddq - 0.2 0.5* v ddq +0.2 v note: 1) enables on - chip refresh and address counters. 2) min(t cl , t ch ) refers to the smaller of the actual clock low time and actual clock high time as pr ovided to the device. 3) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving ( hz ), or begins driving ( lz). 4) the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this clk edge. a valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. when no writes wer e previously in progress on the bus, dqs will be transitioning from high - z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 5) the maximum limit for this parameter i s not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 6) for co m mand/address and ck & ck slew rate R 1.0v/ns. 7) a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 8) power - up sequence is described in note 10 9 ) a.c. test conditions tabl e 17. sstl _2 interface reference level of output signals (v r ef ) 0.5 * v ddq output load reference to the test load input signal levels v ref +0.3 1 v / v ref - 0.3 1 v input signals slew rate 1 v/ns reference level of input signals 0.5 * v ddq figure 3. sstl_2 a.c. test load dq, dqs z0=50 50 30pf 0.5 * vddq 10 ) power up sequenc e power u p must be performed in the following sequence. AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 13/62 - rev. 1.0 oct.2015
1) apply p ower to v dd before or at the same time as v ddq, v tt and v ref when all input signals are held "nop" state and maintain cke low. 2) start clock and maintain stable condition for minimum 200 s. 3) issue a nop command and keep cke high 4) issue a precharge all command. 5) issue emrs enable dll. 6) issue mrs reset dll. (an additional 200 clock cycles are required to lock the dll). 7) precharge all banks of the device. 8) issue t wo or more a uto refresh commands. 9) issue mrs with a8 to low to initialize the mode register. AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 14/62 - rev. 1.0 oct.2015
timing waveforms figure 4. activating a specific row in a specific bank ck ck cke cs ras cas we ra address ba ba0,1 don? care high ra=row address ba=bank address AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 15/62 - rev. 1.0 oct.2015
figure 5. trcd and trrd definition ck ck address ba0,ba1 act nop command nop act nop nop rd/wr nop row row col bank a bank b bank b t rrd t rcd don? care figure 6. read command ck ck cke cs ras cas we ca a0 - a9 a10 don? care high en ap dis ap ba ba0,1 ca=column address ba=bank address en ap=enable autoprecharge dis ap=disable autoprecharge AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 16/62 - rev. 1.0 oct.2015
figure 7. read burst required cas latencies (cl=2) ck ck command read nop nop nop nop nop bank a, col n address dqs dq cl=2 don? care do n=data out from column n burst length=4 3 subsequent elements of data out appear in the programmed order following do n do n read burst required cas latencies (cl=2.5) ck ck command read nop nop nop nop nop bank a, col n address dqs dq cl=2.5 don? care do n=data out from column n burst length=4 3 subsequent elements of data out appear in the programmed order following do n do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 17/62 - rev. 1.0 oct.2015
read burst required cas latencies (cl=3) do n ck ck command read nop nop nop nop nop bank a, col n address dqs dq cl=3 don? care do n=data out from column n burst length=4 3 subsequent elements of data out appear in the programmed order following do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 18/62 - rev. 1.0 oct.2015
figure 8. consecutive read bursts required cas latencies (cl=2) ck ck command read nop read nop nop nop bank, col n address dqs dq cl=2 do n don? care bank, col o do o do n (or o)=data out from column n (or column o) burst length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of data out appear in the programmed order following do n 3 (or 7) subsequent elements of data out appear in the programmed order following do o read commands shown must be to the same device AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 19/62 - rev. 1.0 oct.2015
consecutive read bursts required cas latencies (cl=2.5) do o ck ck command read nop read nop nop nop bank, col n address dqs dq cl=2.5 don? care bank, col o do n (or o)=data out from column n (or column o) burst length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of data out appear in the programmed order following do n 3 (or 7) subsequent elements of data out appear in the programmed order following do o read commands shown must be to the same device do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 20/62 - rev. 1.0 oct.2015
consecutive read bursts required cas latencies (cl=3) do o ck ck command read nop read nop nop nop bank, col n address dqs dq cl=3 don? care bank, col o do n (or o)=data out from column n (or column o) burst length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of data out appear in the programmed order following do n 3 (or 7) subsequent elements of data out appear in the programmed order following do o read commands shown must be to the same device do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 21/62 - rev. 1.0 oct.2015
figure 9. non -consecutive read bursts required cas latencies (cl=2) ck ck command read nop nop read nop nop bank, col n address dqs dq cl=2 don? care bank, col o do n (or o)=data out from column n (or column o) burst length=4 3 subsequent elements of data out appear in the programmed order following do n (and following do o) do o do n non -consecutive read bursts required cas latencies (cl=2.5) ck ck command read nop nop read nop nop bank, col n address dqs dq cl=2.5 don? care bank, col o nop do n (or o)=data out from column n (or column o) burst length=4 3 subsequent elements of data out appear in the programmed order following do n (and following do o) do n do o AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 22/62 - rev. 1.0 oct.2015
non -consecutive read bursts required cas latencies (cl=3) ck ck command read nop nop read nop nop bank, col n address dqs dq cl=3 don? care bank, col o nop do n (or o)=data out from column n (or column o) burst length=4 3 subsequent elements of data out appear in the programmed order following do n (and following do o) do o do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 23/62 - rev. 1.0 oct.2015
figure 10. random read accesses required cas latencies (cl=2) do p do n' do o do o' do p' do q ck ck command read read read read nop nop bank, col n address dqs dq cl=2 don? care bank, col o bank, col p bank, col q do n, etc. =data out from column n, etc. n', etc. =the next data out following do n, etc. according to the programmed burst order burst length=2,4 or 8 in cases shown. if burst of 4 or 8, the burst is interrupted reads are to active rows in any banks do n random read accesses required cas latencies (cl=2.5) do p do n' do o do o' do p' ck ck command read read read read nop nop bank, col n address dqs dq cl=2.5 don? care bank, col o bank, col p bank, col q do n, etc. =data out from column n, etc. n' , etc. =the next data out following do n, etc. according to the programmed burst order burst length=2,4 or 8 in cases shown. if burst of 4 or 8, the burst is interrupted reads are to active rows in any banks do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 24/62 - rev. 1.0 oct.2015
random read accesses required cas latencies (cl=3) do p do n' do o do o' ck ck command read read read read nop nop bank, col n address dqs dq cl=3 don? care bank, col o bank, col p bank, col q do n, etc. =data out from column n, etc. n', etc. =the next data out following do n, etc. according to the programmed burst order burst length=2,4 or 8 in cases shown. if burst of 4 or 8, the burst is interrupted reads are to active rows in any banks do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 25/62 - rev. 1.0 oct.2015
figure 1 1. terminating a read burst required cas latencies (cl=2) ck ck command read nop bst nop nop nop bank a, col n address dqs dq cl=2 don? care do n = data out from column n cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of data out appear in the programmed order following do n do n terminating a read burst required cas latencies (cl=2.5) ck ck command read nop bst nop nop nop bank a, col n address dqs dq cl=2.5 don? care do n = data out from column n cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of data out appear in the programmed order following do n do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 26/62 - rev. 1.0 oct.2015
terminating a read burst required cas latencies (cl=3) ck ck command read nop bst nop nop nop bank a, col n address dqs dq cl=3 don? care do n = data out from column n cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of data out appear in the programmed order following do n do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 27/62 - rev. 1.0 oct.2015
figure 12. read to write required cas latencies (cl=2) read bst nop write nop nop bank, col n cl=2 don? care bank, col o di o tdqss min do n (or o)= data out from column n (or column o) burst length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the bst command shown can be nop) 1 subsequent element of data out appears in the programmed order following do n data in elements are applied following di o in the programmed order do n ck ck command address dqs dq dm AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 28/62 - rev. 1.0 oct.2015
read to write required cas latencies (cl=2.5) ck ck command read bst nop nop write nop bank, col n address dqs dq cl=2.5 don? care min tdqss di o dm bank, col o do n (or o)= data out from column n (or column o) burst length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the bst command shown can be nop) 1 subsequent element of data out appears in the programmed order following do n data in elements are applied following di o in the programmed order do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 29/62 - rev. 1.0 oct.2015
read to write required cas latencies (cl=3) ck ck command read bst nop nop write nop bank, col n address dqs dq cl=3 don? care bank, col o min tdqss di o dm do n (or o)= data out from column n (or column o) burst length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the bst command shown can be nop) 1 subsequent element of data out appears in the programmed order following do n data in elements are applied following di o in the programmed order do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 30/62 - rev. 1.0 oct.2015
figure 13. read to precharge required cas latencies (cl=2) ck ck command read nop pre nop nop act bank a, col n address dqs dq cl=2 don? care bank (a or all) bank a, row t rp do n = data out from column n cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of data out appear in the programmed order following do n precharge may be applied at (bl/2) tck after the read command note that precharge may not be issued before tras ns after the active command for applicable banks the active command may be applied if trc has been met do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 31/62 - rev. 1.0 oct.2015
read to precharge required cas latencies (cl=2.5) ck ck command read nop pre nop nop act bank a, col n address dqs dq cl=2.5 don? care bank (a or all) bank a, row t rp do n = data out from column n cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of data out appear in the programmed order following do n precharge may be applied at (bl/2) tck after the read command note that precharge may not be issued before tras ns after the active command for applicable banks the active command may be applied if trc has been met do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 32/62 - rev. 1.0 oct.2015
read to precharge required cas latencies (cl=3) ck ck command read nop pre nop nop act bank a, col n address dqs dq cl=3 don? care bank (a or all) bank a, row t rp do n = data out from column n cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of data out appear in the programmed order following do n precharge may be applied at (bl/2) tck after the read command note that precharge may not be issued before tras ns after the active command for applicable banks the active command may be applied if trc has been met do n AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 33/62 - rev. 1.0 oct.2015
figure 14. write command ck ck cke cs ras cas we ca a0 - a9 a10 don? care high en ap dis ap ba ba0,1 ca=column address ba=bank address en ap=enable autoprecharge dis ap=disable autoprecharge AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 34/62 - rev. 1.0 oct.2015
figure 15. write max dqss ck ck command write nop nop nop bank a, col n address dqs dq tdqss don? care dm t0 t1 t2 t3 t4 t5 t6 t7 max di n di n = data in for column n 3 subsequent elements of data in are applied in the programmed order following di n a non-interrupted burst of 4 is shown a10 is low with the write command (auto precharge disabled) AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 35/62 - rev. 1.0 oct.2015
figure 16. write min dqss ck ck command write nop nop nop bank a, col n address dqs dq tdqss dm t0 t1 t2 t3 t4 t5 t6 min di n don? care di n = data in for column n 3 subsequent elements of data in are applied in the programmed order following di n a non-interrupted burst of 4 is shown a10 is low with the write command (auto precharge disabled) AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 36/62 - rev. 1.0 oct.2015
figure 17. write burst nom, min, and max tdqss ck ck command write nop nop nop bank , col n address dqs dq tdqss (nom) don? care dm t0 t1 t2 t3 t4 t5 t6 t7 di n t8 t9 t10 t11 nop nop dqs dq tdqss (min) dm di n dqs dq tdqss (max) dm di n di n = data in for column n 3 subsequent elements of data are applied in the programmed order following di n a non-interrupted burst of 4 is shown a10 is low with the write command (auto precharge disabled) dm=udm & ldm AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 37/62 - rev. 1.0 oct.2015
figure 18. write to write max tdqss ck ck command write nop write nop bank , col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 nop nop dqs dq tdqss (max) dm di n bank , col o di o don? care di n , etc. = data in for column n,etc. 3 subsequent elements of data in are applied in the programmed order following di n non-interrupted bursts of 4 are shown dm= udm & ldm 3 subsequent elements of data in are applied in the programmed order following di o AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 38/62 - rev. 1.0 oct.2015
figure 19. write to write max tdqss, non consecutive ck ck command write nop nop write bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 nop nop dqs dq tdqss (max) dm di n bank col o di o don? care di n, etc. = data in for column n, etc. 3 subsequent elements of data in are applied in the programmed order following di n non-interrupted bursts of 4 are shown dm= udm & ldm 3 subsequent elements of data in are applied in the programmed order following di o AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 39/62 - rev. 1.0 oct.2015
figure 20. random write cycles max tdqss ck ck command write write write write bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 write dqs dq tdqss (max) dm di n bank col q di o di n' di o' di p di p' di q di q' bank col o bank col p bank col r don? care di n, etc. = data in for column n, etc. n', etc. = the next data in following di n, etc. according to the programmed burst order if burst of 4 or 8, the burst would be truncated dm= udm & ldm programmed burst length 2, 4, or 8 in cases shown each write command may be to any bank and may be to the same or different devices AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 40/62 - rev. 1.0 oct.2015
figure 21. write to read max tdqss non interrupting ck ck command write nop nop read bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n bank col o t10 t11 nop twtr cl=3 don? care di n, etc. = data in for column n, etc. 1 subsequent elements of data in are applied in the programmed order following di n twtr is referenced from the first positive ck edge after the last data in pair dm= udm & ldm a non-interrupted burst of 2 is shown a10 is low with the write command (auto precharge is disabled) the read and write commands are to the same devices but not necessarily to the same bank t12 nop AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 41/62 - rev. 1.0 oct.2015
figure 22. write to read max tdqss interrupting ck ck command write nop nop read bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n bank col o t10 t11 nop twtr cl=3 don? care di n, etc. = data in for column n, etc. 1 subsequent elements of data in are applied in the programmed order following di n twtr is referenced from the first positive ck edge after the last data in pair dm= udm & ldm an interrupted burst of 8 is shown, 2 data elements are written a10 is low with the write command (auto precharge is disabled) the read and write commands are to the same device s but not necessarily to the same bank t12 AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 42/62 - rev. 1.0 oct.2015
figure 23. write to read max tdqss, odd number of data, interrupting ck ck write nop nop read bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n bank col o t10 t11 nop twtr cl=3 don? care di n = data in for column n twtr is referenced from the first positive ck edge after the last data in pair (not the last desired data in element) dm= ldm & udm an interrupted burst of 8 is shown, 1 data elements are written a10 is low with the write command (auto precharge is disabled) the read and write commands are to the same devices but not necessarily to the same bank t12 command AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 43/62 - rev. 1.0 oct.2015
figure 24. write to precharge max tdqss, non- interrupting ck ck command write nop nop nop bank a, col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 pre dqs dq tdqss (max) dm di n bank (a or al) t10 t11 nop twr trp don? care di n = data in for column n 1 subsequent elements of data in are applied in the programmed order following di n twr is referenced from the first positive ck edge after the last data in pair dm= udm & ldm a non-interrupted burst of 2 is shown a10 is low with the write command (auto precharge is disabled) AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 44/62 - rev. 1.0 oct.2015
figure 25. write to precharge max tdqss, interrupting ck ck command write nop nop pre bank a, col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n t10 t11 nop twr trp *1 *2 don? care di n = data in for column n twr is referenced from the first positive ck edge after the last data in pair dm= udm & ldm an interrupted burst of 4 or 8 is shown, 2 data elements are written a10 is low with the write command (auto precharge is disabled) *1 = can be don't care for programmed burst length of 4 *2 = for programmed burst length of 4, dqs becomes don't care at this point *1 *1 *1 bank (a or all) AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 45/62 - rev. 1.0 oct.2015
figure 26. write to precharge max tdqss odd number of data interrupting ck ck command write nop nop bank a, col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n t10 t11 nop twr trp *2 don? care di n = data in for column n twr is referenced from the first positive ck edge after the last data in pair dm= udm & ldm an interrupted burst of 4 or 8 is shown, 1 data element is written a10 is low with the write command (auto precharge is disabled) *1 = can be don't care for programmed burst length of 4 *2 = for programmed burst length of 4, dqs becomes don't care at this point *1 *1 *1 *1 pre bank (a or all) AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 46/62 - rev. 1.0 oct.2015
figure 27. precharge command ck ck cke cs ras cas we address a10 don? care high all banks one bank ba ba0,1 ba= bank address (if a10 is low, otherwise don't care) AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 47/62 - rev. 1.0 oct.2015
figure 28. p ower-down ck ck cke valid command don? care t0 t1 t2 t3 t4 tn tn+1 tn+2 tn+3 tn+4 valid tn+5 tn+6 nop nop no column access in progress enter power-down mode exit power-down mode t is t is figure 29. clock frequency change in precharge ck ck cmd t is t0 t1 t2 t4 tx tx+1 ty ty+1 ty+2 ty+3 ty+4 tz nop nop nop dll reset nop valid nop frequency change occurs here stable new clock before power down exit t rp minmum 2 clocks required before changing frequency 200 clocks cke AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 48/62 - rev. 1.0 oct.2015
figure 30. data input (write) timing dqs dq don? care t ds di n dm t dh t ds t dh t dqsh t dqsl di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following di n figure 31. data output (read) timing ck ck dq t ch t cl t qh t dqsq max t qh max t dqsq burst length = 4 in the case shown dqs AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 49/62 - rev. 1.0 oct.2015
figure 32. initialize and mode register sets t is t ih nop pre emrs mrs pre ar ar mrs act code code code ra tvdt>=0 t ch t cl t ck t is t ih t is t ih code code code ra t is t ih t is t ih all banks t is t ih all banks ba0=h ba1=l ba0=l ba1=l ba0=l ba1=l ba t is t ih high-z high-z lvcmos low level ck ck dm address command vref cke a10 ba0,ba1 dqs dq vdd vddq vtt (system*) *=vtt is not applied directly to the device, however tvtd must be greater than or equal to zero to avoid device latch-up. ** = tmrd is required before any command can be applied, and 200 cycles of ck are required before any executable command can be applied the two auto refresh commands may be moved to follow the first mrs but precede the second precharge all command. don? care power-up: vdd and clk stable extended mode register set load mode register, reset dll (with a8=h) 200 cycles of ck** load mode register, (with a8=l) t=200s **t mrd **t mrd t rfc t rfc **t mrd t rp AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 50/62 - rev. 1.0 oct.2015
figure 33. power down mode ck ck cke valid* command don? care valid t ck nop nop enter power-down mode exit power-down mode t ch t cl t is t is t ih t is t is t ih valid t is t ih address valid dqs dq dm no column accesses are allowed to be in progress at the time power-down is entered *=if this command is a precharge all (or if the device is already in the idle state) then the power-down mode shown is precharge power down. if this command is an active (or if at least one row is already active) then the power-down mode shown is active power down. AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 51/62 - rev. 1.0 oct.2015
figure 34. auto refresh mode ck ck a0-a9 a11-a13 valid nop t is don? care t ih nop ar nop ar nop nop act t is t ih t ch t cl t ck ra cke ra a10 ba0,ba1 dqs dq *bank(s) valid nop pre ra all banks one banks ba t ih t is dm t rp t rfc t rfc * = h don't care i , if a10 is high at this point; a10 must be high if more than one bank is active (i.e., must precharge all active banks) pre = precharge, act = active, ra = row address, ba = bank address, ar = autorefresh nop commands are shown for ease of illustration; other valid commands may be possible after trfc dm, dq and dqs signals are all h don't care i /high-z for operations shown command AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 52/62 - rev. 1.0 oct.2015
figure 35. self refresh mode ck ck cke nop command don? care valid t ck ar nop clock must be stable before exiting self refresh mode enter self refresh mode t ch t cl t is t is t ih t is t is t ih address valid dqs dq dm t is t ih t rp* t xsnr/ t xsrd** exit self refresh mode * = device must be in the h all banks idlei state prior to entering self refresh mode ** = txsnr is required before any non-read command can be applied, and txsrd (200 cycles of ck) is required before a read command can be applied. AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 53/62 - rev. 1.0 oct.2015
figure 36. read without auto precharge ck ck a0-a9 nop t is t ih pre nop nop valid valid valid t is t ih t ch t cl t ck ra cke dm dqs nop read ra t ih t is dq cl=3 t rp act nop nop nop col n t is t ih ra all banks one banks bank x t is t ih dis ap *bank x bank x t rpre t dqsck min t rpst t lz t lz t ac min dqs dq t rpre t rpst t lz t lz max t dqsck t hz max t ih max max min min don? care do n = data out from column n pre = precharge, act = active, ra = row address, ba = bank address, ar = autorefresh burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = h don't care i , if a10 is high at this point nop commands are shown for ease of illustration; other commands may be valid at the se times precharge may not be issued before tras ns after the active command for applicable banks do n do n command a11-a13 a10 ba0,ba1 max t ac case 1: t ac /t dqsck =min case 2: t ac /t dqsck =max AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 54/62 - rev. 1.0 oct.2015
figure 37. read with auto precharge nop t is t ih nop nop nop valid valid valid t is t ih t ch t cl t ck ra nop read ra t ih t is cl=3 t rp act nop nop nop col n t is t ih ra bank x t is t ih en ap bank x t rpre min t rpst t lz t ac min t rpre t rpst t lz t lz max t dqsck t hz max t ih min max max don? care do n = data out from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n en ap = enable autoprecharge act = active, ra = row address nop commands are shown for ease of illustration; other commands may be valid at these times the read command may not be issued until trap has been satisfied. if fast autoprecharge is supported, trap = trcd, else the read may not be issued prior to trasmin - (bl*tck/2) do n do n max t ac min t lz t dqsck ck ck a0-a9 command cke a10 ba0,ba1 dm dqs dq dqs dq a11-a13 case 2: t ac /t dqsck =max case 1: t ac /t dqsck =min AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 55/62 - rev. 1.0 oct.2015
figure 38. bank read acc ess nop t is t ih nop nop read t is t ih t ch t cl t ck nop act ra t ih t is t rc nop pre nop nop ra t is t ih col n all banks one banks dis ap bank x t rpre min t rpst t lz t lz t ac act ra ra ra ra *bank x bank x t is t ih bank x t ras t rcd t rp t dqsck min min t rpre max t lz t ac max max t rpst t dqsck don? care do n = data out from column n pre = precharge, act = active, ra = row address, ba = bank address burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = i don't care i , if a10 is high at this point nop commands are shown for ease of illustration; other commands may be valid at these times note that trcd > trcd min so that the same timing applies if autoprecharge is enabled (in which case tras would be limiting) do n do n min cl=3 max t lz max t hz dq dqs case 2: t ac /t dqsck =max dq dqs case 1: t ac /t dqsck =min dm ba0,ba1 command cke ck ck a10 a11-a13 a0-a9 AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 56/62 - rev. 1.0 oct.2015
figure 39. write without auto precharge ck ck a0-a9 a11-a13 nop command t is t ih nop nop nop valid t is t ih t ch t cl t ck ra cke a10 ba0,ba1 dqs nop write ra t ih t is dq t dsh pre nop nop act col n t is t ih ra all banks one banks bank x t is t ih dis ap *bank x ba t wpres case 1: t dqss =min di n t ih t dqss t dsh t dqsh t dqsl t wpst t wpre dm dqs dq t dss t wpres case 2: t dqss =max di n t dqss t dss dm t wr t rp t dqsh t wpst t dqsl t wpre don? care di n = data in from column n pre = precharge, act = active, ra = row address, ba = bank address, ar = autorefresh burst length = 4 in the case shown 3 subsequent elements of data in are provided in the programmed order following di n dis ap = disable autoprecharge *=i don't care i , if a10 is high at this point nop commands are shown for ease of illustration; other commands may be valid at these times although tdqss is drawn only for the first dqs rising edge, each rising edge of dqs must fall within the + 25% window of the corresponding positive clock edge precharge may not be issued before tras ns after the active command for applicable banks AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 57/62 - rev. 1.0 oct.2015
figure 40. write with auto prechar ge ck ck a0-a9 a11-a13 nop command t is t ih nop nop nop valid t is t ih t ch t cl t ck ra cke a10 ba0,ba1 dqs nop write ra t ih t is dq t dsh nop nop nop act col n t is t ih ra bank x dis ap ba t wpres case 1: t dqss =min di n t dqss t dsh t dqsh t dqsl t wpst t wpre dm dqs dq t dss t wpres case 2: t dqss =max di n t dqss t dss dm t dal t dqsh t wpst t dqsl valid valid t wpre don? care di n = data in from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following di n en ap = enable autoprecharge act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other commands may be valid at these times although tdqss is drawn only for the first dqs rising edge, each rising edge of dqs must fall within the + 25% window of the corresponding positive clock edge AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 58/62 - rev. 1.0 oct.2015
figure 41. bank write access ck ck a0-a9 a11-a13 nop command t is t ih nop write nop t is t ih t ch t cl t ck cke a10 ba0,ba1 dqs nop act all banks t ih t is dq t dsh nop nop nop pre ra t is t ih bank x dis ap *bank x t wpres case 1: t dqss =min di n t dqss t dsh t dqsh t dqsl t wpst dm dqs dq case 2: t dqss =max t dqss t dss dm t ras t dqsh t wpst col n ra ra one bank t is t ih bank x t wr t rcd t wpre t dss t dqsl t wpres t wpre di n don? care di n = data in from column n pre = precharge, act = active, ra = row address, ba = bank address burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following di n dis ap = disable autoprecharge *=i don't care i , if a10 is high at this point nop commands are shown for ease of illustration; other commands may be valid at these times although tdqss is drawn only for the first dqs rising edge, each rising edge of dqs must fall within the + 25% window of the corresponding positive clock edge precharge may not be issued before tras ns after the active command for applicable banks AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 59/62 - rev. 1.0 oct.2015
figure 42. write dm operation ck ck a0-a9 a11-a13 nop command t is t ih nop nop nop valid t is t ih t ch t cl t ck ra cke a10 ba0,ba1 dqs nop write ra t ih t is dq t dsh pre nop nop act col n t is t ih ra all banks one banks bank x t is t ih dis ap *bank x ba t wpres case 1: t dqss =min di n t dqss t dsh t dqsh t dqsl t wpst t wpre dm dqs dq t dss t wpres case 2: t dqss =max di n t dqss t dss dm t wr t rp t dqsh t dqsl t wpre t wpst don? care di n = data in from column n pre = precharge, act = active, ra = row address, ba = bank address burst length = 4 in the case shown 3 subsequent elements of data in are provided in the programmed order following di n dis ap = disable autoprecharge *=i don't care i , if a10 is high at this point nop commands are shown for ease of illustration; other commands may be valid at these times although tdqss is drawn only for the first dqs rising edge, each rising edge of dqs must fall within the + 25% window of the corresponding positive clock edge precharge may not be issued before tras ns after the active command for applicable banks AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 60/62 - rev. 1.0 oct.2015
figure 43. 66 pin tsop ii package outline drawing information units: mm symbol dimension in mm dimension in inch min nom max min nom max a --- --- 1.2 --- --- 0.047 a1 0.05 --- 0. 2 0.002 --- 0.008 a2 0.9 1.0 1.1 0.035 0.039 0.043 b 0.22 --- 0.45 0.009 --- 0.018 e --- 0.65 --- --- 0.026 --- c 0.095 0.125 0.21 0.004 0.005 0.008 d 22.09 22.22 22.35 0.87 0.875 0.88 e 10.03 10.16 10.29 0.395 0.4 0.405 he 11.56 11.76 11.96 0.455 0 .463 0.471 l 0.40 0.5 0.6 0.016 0.02 0.024 l1 --- 0.8 --- --- 0.032 --- f --- 0.25 --- --- 0.01 --- 0 --- 8 0 --- 8 s --- 0.71 --- --- 0.028 --- --- --- 0.10 --- --- 0.004 d y d a1 e l1 l c s b d f (typ) c e a a1 a2 e he l1 l AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 61/62 - rev. 1.0 oct.2015
alliance memory, inc. 511 taylor way, san carlos, ca 94070 tel: 650-610-6800 fax: 650-620-9211 www.alliancememory.com copyright ? alliance memory all rights reserved ? copyright 2007 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. part numbering system as4c 64m16d1a 6 t c/i n dram 64m16=64mx16 d1=ddr1 (a=a die rev.) t = tsop ii c=commercial (0 c- +85 c) i=industrial (-40 c- +85 c) indicates pb and halogen free 6= 166mhz AS4C64M16D1A-6TIN as4c64m16d1a-6tcn confidential - 62/62 - rev. 1.0 oct.2015

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